1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <drm/intel-gtt.h>
40 /* General customization:
43 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
45 #define DRIVER_NAME "i915"
46 #define DRIVER_DESC "Intel Graphics"
47 #define DRIVER_DATE "20080730"
55 #define pipe_name(p) ((p) + 'A')
62 #define plane_name(p) ((p) + 'A')
64 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
66 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
71 * 1.2: Add Power Management
72 * 1.3: Add vblank support
73 * 1.4: Fix cmdbuffer path, add heap destroy
74 * 1.5: Add vblank pipe configuration
75 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
76 * - Support vertical blank on secondary display pipe
78 #define DRIVER_MAJOR 1
79 #define DRIVER_MINOR 6
80 #define DRIVER_PATCHLEVEL 0
82 #define WATCH_COHERENCY 0
85 #define I915_GEM_PHYS_CURSOR_0 1
86 #define I915_GEM_PHYS_CURSOR_1 2
87 #define I915_GEM_PHYS_OVERLAY_REGS 3
88 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
90 struct drm_i915_gem_phys_object {
92 struct page **page_list;
93 drm_dma_handle_t *handle;
94 struct drm_i915_gem_object *cur_obj;
98 struct mem_block *next;
99 struct mem_block *prev;
102 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
105 struct opregion_header;
106 struct opregion_acpi;
107 struct opregion_swsci;
108 struct opregion_asle;
110 struct intel_opregion {
111 struct opregion_header *header;
112 struct opregion_acpi *acpi;
113 struct opregion_swsci *swsci;
114 struct opregion_asle *asle;
116 u32 __iomem *lid_state;
118 #define OPREGION_SIZE (8*1024)
120 struct intel_overlay;
121 struct intel_overlay_error_state;
123 struct drm_i915_master_private {
124 drm_local_map_t *sarea;
125 struct _drm_i915_sarea *sarea_priv;
127 #define I915_FENCE_REG_NONE -1
129 struct drm_i915_fence_reg {
130 struct list_head lru_list;
131 struct drm_i915_gem_object *obj;
132 uint32_t setup_seqno;
135 struct sdvo_device_mapping {
145 struct intel_display_error_state;
147 struct drm_i915_error_state {
150 u32 pipestat[I915_MAX_PIPES];
155 u32 error; /* gen6+ */
156 u32 bcs_acthd; /* gen6+ blt engine */
161 u32 vcs_acthd; /* gen6+ bsd engine */
173 struct drm_i915_error_object {
177 } *ringbuffer[I915_NUM_RINGS], *batchbuffer[I915_NUM_RINGS];
178 struct drm_i915_error_buffer {
192 } *active_bo, *pinned_bo;
193 u32 active_bo_count, pinned_bo_count;
194 struct intel_overlay_error_state *overlay;
195 struct intel_display_error_state *display;
198 struct drm_i915_display_funcs {
199 void (*dpms)(struct drm_crtc *crtc, int mode);
200 bool (*fbc_enabled)(struct drm_device *dev);
201 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
202 void (*disable_fbc)(struct drm_device *dev);
203 int (*get_display_clock_speed)(struct drm_device *dev);
204 int (*get_fifo_size)(struct drm_device *dev, int plane);
205 void (*update_wm)(struct drm_device *dev);
206 int (*crtc_mode_set)(struct drm_crtc *crtc,
207 struct drm_display_mode *mode,
208 struct drm_display_mode *adjusted_mode,
210 struct drm_framebuffer *old_fb);
211 void (*fdi_link_train)(struct drm_crtc *crtc);
212 void (*init_clock_gating)(struct drm_device *dev);
213 void (*init_pch_clock_gating)(struct drm_device *dev);
214 /* clock updates for mode set */
216 /* render clock increase/decrease */
217 /* display clock increase/decrease */
218 /* pll clock increase/decrease */
221 struct intel_device_info {
231 u8 is_broadwater : 1;
235 u8 has_pipe_cxsr : 1;
237 u8 cursor_needs_physical : 1;
239 u8 overlay_needs_physical : 1;
246 FBC_NO_OUTPUT, /* no outputs enabled to compress */
247 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
248 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
249 FBC_MODE_TOO_LARGE, /* mode too large for compression */
250 FBC_BAD_PLANE, /* fbc not supported on plane */
251 FBC_NOT_TILED, /* buffer not tiled */
252 FBC_MULTIPLE_PIPES, /* more than one pipe active */
257 PCH_IBX, /* Ibexpeak PCH */
258 PCH_CPT, /* Cougarpoint PCH */
261 #define QUIRK_PIPEA_FORCE (1<<0)
265 typedef struct drm_i915_private {
266 struct drm_device *dev;
268 const struct intel_device_info *info;
271 int relative_constants_mode;
276 struct i2c_adapter adapter;
277 struct i2c_adapter *force_bit;
281 struct pci_dev *bridge_dev;
282 struct intel_ring_buffer ring[I915_NUM_RINGS];
285 drm_dma_handle_t *status_page_dmah;
287 drm_local_map_t hws_map;
288 struct drm_i915_gem_object *pwrctx;
289 struct drm_i915_gem_object *renderctx;
291 struct resource mch_res;
299 atomic_t irq_received;
301 /* protects the irq masks */
303 /** Cached value of IMR to avoid reads in updating the bitfield */
309 u32 hotplug_supported_mask;
310 struct work_struct hotplug_work;
312 int tex_lru_log_granularity;
313 int allow_batchbuffer;
314 struct mem_block *agp_heap;
315 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
319 /* For hangcheck timer */
320 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
321 struct timer_list hangcheck_timer;
324 uint32_t last_instdone;
325 uint32_t last_instdone1;
327 unsigned long cfb_size;
328 unsigned long cfb_pitch;
329 unsigned long cfb_offset;
334 struct intel_opregion opregion;
337 struct intel_overlay *overlay;
340 int backlight_level; /* restore backlight to this value */
341 bool backlight_enabled;
342 struct drm_display_mode *panel_fixed_mode;
343 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
344 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
346 /* Feature bits from the VBIOS */
347 unsigned int int_tv_support:1;
348 unsigned int lvds_dither:1;
349 unsigned int lvds_vbt:1;
350 unsigned int int_crt_support:1;
351 unsigned int lvds_use_ssc:1;
362 struct edp_power_seq pps;
364 bool no_aux_handshake;
366 struct notifier_block lid_notifier;
369 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
370 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
371 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
373 unsigned int fsb_freq, mem_freq, is_ddr3;
375 spinlock_t error_lock;
376 struct drm_i915_error_state *first_error;
377 struct work_struct error_work;
378 struct completion error_completion;
379 struct workqueue_struct *wq;
381 /* Display functions */
382 struct drm_i915_display_funcs display;
384 /* PCH chipset type */
385 enum intel_pch pch_type;
387 unsigned long quirks;
412 u32 saveTRANS_HTOTAL_A;
413 u32 saveTRANS_HBLANK_A;
414 u32 saveTRANS_HSYNC_A;
415 u32 saveTRANS_VTOTAL_A;
416 u32 saveTRANS_VBLANK_A;
417 u32 saveTRANS_VSYNC_A;
425 u32 savePFIT_PGM_RATIOS;
426 u32 saveBLC_HIST_CTL;
428 u32 saveBLC_PWM_CTL2;
429 u32 saveBLC_CPU_PWM_CTL;
430 u32 saveBLC_CPU_PWM_CTL2;
443 u32 saveTRANS_HTOTAL_B;
444 u32 saveTRANS_HBLANK_B;
445 u32 saveTRANS_HSYNC_B;
446 u32 saveTRANS_VTOTAL_B;
447 u32 saveTRANS_VBLANK_B;
448 u32 saveTRANS_VSYNC_B;
462 u32 savePP_ON_DELAYS;
463 u32 savePP_OFF_DELAYS;
471 u32 savePFIT_CONTROL;
472 u32 save_palette_a[256];
473 u32 save_palette_b[256];
474 u32 saveDPFC_CB_BASE;
475 u32 saveFBC_CFB_BASE;
478 u32 saveFBC_CONTROL2;
488 u32 saveCACHE_MODE_0;
489 u32 saveMI_ARB_STATE;
500 uint64_t saveFENCE[16];
511 u32 savePIPEA_GMCH_DATA_M;
512 u32 savePIPEB_GMCH_DATA_M;
513 u32 savePIPEA_GMCH_DATA_N;
514 u32 savePIPEB_GMCH_DATA_N;
515 u32 savePIPEA_DP_LINK_M;
516 u32 savePIPEB_DP_LINK_M;
517 u32 savePIPEA_DP_LINK_N;
518 u32 savePIPEB_DP_LINK_N;
529 u32 savePCH_DREF_CONTROL;
530 u32 saveDISP_ARB_CTL;
531 u32 savePIPEA_DATA_M1;
532 u32 savePIPEA_DATA_N1;
533 u32 savePIPEA_LINK_M1;
534 u32 savePIPEA_LINK_N1;
535 u32 savePIPEB_DATA_M1;
536 u32 savePIPEB_DATA_N1;
537 u32 savePIPEB_LINK_M1;
538 u32 savePIPEB_LINK_N1;
539 u32 saveMCHBAR_RENDER_STANDBY;
542 /** Bridge to intel-gtt-ko */
543 const struct intel_gtt *gtt;
544 /** Memory allocator for GTT stolen memory */
545 struct drm_mm stolen;
546 /** Memory allocator for GTT */
547 struct drm_mm gtt_space;
548 /** List of all objects in gtt_space. Used to restore gtt
549 * mappings on resume */
550 struct list_head gtt_list;
552 /** Usable portion of the GTT for GEM */
553 unsigned long gtt_start;
554 unsigned long gtt_mappable_end;
555 unsigned long gtt_end;
557 struct io_mapping *gtt_mapping;
560 struct shrinker inactive_shrinker;
563 * List of objects currently involved in rendering.
565 * Includes buffers having the contents of their GPU caches
566 * flushed, not necessarily primitives. last_rendering_seqno
567 * represents when the rendering involved will be completed.
569 * A reference is held on the buffer while on this list.
571 struct list_head active_list;
574 * List of objects which are not in the ringbuffer but which
575 * still have a write_domain which needs to be flushed before
578 * last_rendering_seqno is 0 while an object is in this list.
580 * A reference is held on the buffer while on this list.
582 struct list_head flushing_list;
585 * LRU list of objects which are not in the ringbuffer and
586 * are ready to unbind, but are still in the GTT.
588 * last_rendering_seqno is 0 while an object is in this list.
590 * A reference is not held on the buffer while on this list,
591 * as merely being GTT-bound shouldn't prevent its being
592 * freed, and we'll pull it off the list in the free path.
594 struct list_head inactive_list;
597 * LRU list of objects which are not in the ringbuffer but
598 * are still pinned in the GTT.
600 struct list_head pinned_list;
602 /** LRU list of objects with fence regs on them. */
603 struct list_head fence_list;
606 * List of objects currently pending being freed.
608 * These objects are no longer in use, but due to a signal
609 * we were prevented from freeing them at the appointed time.
611 struct list_head deferred_free_list;
614 * We leave the user IRQ off as much as possible,
615 * but this means that requests will finish and never
616 * be retired once the system goes idle. Set a timer to
617 * fire periodically while the ring is running. When it
618 * fires, go retire requests.
620 struct delayed_work retire_work;
623 * Are we in a non-interruptible section of code like
629 * Flag if the X Server, and thus DRM, is not currently in
630 * control of the device.
632 * This is set between LeaveVT and EnterVT. It needs to be
633 * replaced with a semaphore. It also needs to be
634 * transitioned away from for kernel modesetting.
639 * Flag if the hardware appears to be wedged.
641 * This is set when attempts to idle the device timeout.
642 * It prevents command submission from occurring and makes
643 * every pending request fail
647 /** Bit 6 swizzling required for X tiling */
648 uint32_t bit_6_swizzle_x;
649 /** Bit 6 swizzling required for Y tiling */
650 uint32_t bit_6_swizzle_y;
652 /* storage for physical objects */
653 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
655 /* accounting, useful for userland debugging */
657 size_t mappable_gtt_total;
658 size_t object_memory;
661 struct sdvo_device_mapping sdvo_mappings[2];
662 /* indicate whether the LVDS_BORDER should be enabled or not */
663 unsigned int lvds_border_bits;
664 /* Panel fitter placement and size for Ironlake+ */
665 u32 pch_pf_pos, pch_pf_size;
666 int panel_t3, panel_t12;
668 struct drm_crtc *plane_to_crtc_mapping[2];
669 struct drm_crtc *pipe_to_crtc_mapping[2];
670 wait_queue_head_t pending_flip_queue;
671 bool flip_pending_is_done;
673 /* Reclocking support */
674 bool render_reclock_avail;
675 bool lvds_downclock_avail;
676 /* indicates the reduced downclock for LVDS*/
678 struct work_struct idle_work;
679 struct timer_list idle_timer;
683 struct child_device_config *child_dev;
684 struct drm_connector *int_lvds_connector;
686 bool mchbar_need_disable;
688 struct work_struct rps_work;
699 unsigned long last_time1;
701 struct timespec last_time2;
702 unsigned long gfx_power;
706 spinlock_t *mchdev_lock;
708 enum no_fbc_reason no_fbc_reason;
710 struct drm_mm_node *compressed_fb;
711 struct drm_mm_node *compressed_llb;
713 unsigned long last_gpu_reset;
715 /* list of fbdev register on this device */
716 struct intel_fbdev *fbdev;
718 struct drm_property *broadcast_rgb_property;
719 struct drm_property *force_audio_property;
721 atomic_t forcewake_count;
722 } drm_i915_private_t;
724 enum i915_cache_level {
727 I915_CACHE_LLC_MLC, /* gen6+ */
730 struct drm_i915_gem_object {
731 struct drm_gem_object base;
733 /** Current space allocated to this object in the GTT, if any. */
734 struct drm_mm_node *gtt_space;
735 struct list_head gtt_list;
737 /** This object's place on the active/flushing/inactive lists */
738 struct list_head ring_list;
739 struct list_head mm_list;
740 /** This object's place on GPU write list */
741 struct list_head gpu_write_list;
742 /** This object's place in the batchbuffer or on the eviction list */
743 struct list_head exec_list;
746 * This is set if the object is on the active or flushing lists
747 * (has pending rendering), and is not set if it's on inactive (ready
750 unsigned int active : 1;
753 * This is set if the object has been written to since last bound
756 unsigned int dirty : 1;
759 * This is set if the object has been written to since the last
762 unsigned int pending_gpu_write : 1;
765 * Fence register bits (if any) for this object. Will be set
766 * as needed when mapped into the GTT.
767 * Protected by dev->struct_mutex.
769 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
771 signed int fence_reg : 5;
774 * Advice: are the backing pages purgeable?
776 unsigned int madv : 2;
779 * Current tiling mode for the object.
781 unsigned int tiling_mode : 2;
782 unsigned int tiling_changed : 1;
784 /** How many users have pinned this object in GTT space. The following
785 * users can each hold at most one reference: pwrite/pread, pin_ioctl
786 * (via user_pin_count), execbuffer (objects are not allowed multiple
787 * times for the same batchbuffer), and the framebuffer code. When
788 * switching/pageflipping, the framebuffer code has at most two buffers
791 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
792 * bits with absolutely no headroom. So use 4 bits. */
793 unsigned int pin_count : 4;
794 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
797 * Is the object at the current location in the gtt mappable and
798 * fenceable? Used to avoid costly recalculations.
800 unsigned int map_and_fenceable : 1;
803 * Whether the current gtt mapping needs to be mappable (and isn't just
804 * mappable by accident). Track pin and fault separate for a more
805 * accurate mappable working set.
807 unsigned int fault_mappable : 1;
808 unsigned int pin_mappable : 1;
811 * Is the GPU currently using a fence to access this buffer,
813 unsigned int pending_fenced_gpu_access:1;
814 unsigned int fenced_gpu_access:1;
816 unsigned int cache_level:2;
823 struct scatterlist *sg_list;
827 * Used for performing relocations during execbuffer insertion.
829 struct hlist_node exec_node;
830 unsigned long exec_handle;
831 struct drm_i915_gem_exec_object2 *exec_entry;
834 * Current offset of the object in GTT space.
836 * This is the same as gtt_space->start
840 /** Breadcrumb of last rendering to the buffer. */
841 uint32_t last_rendering_seqno;
842 struct intel_ring_buffer *ring;
844 /** Breadcrumb of last fenced GPU access to the buffer. */
845 uint32_t last_fenced_seqno;
846 struct intel_ring_buffer *last_fenced_ring;
848 /** Current tiling stride for the object, if it's tiled. */
851 /** Record of address bit 17 of each page at last unbind. */
852 unsigned long *bit_17;
856 * If present, while GEM_DOMAIN_CPU is in the read domain this array
857 * flags which individual pages are valid.
859 uint8_t *page_cpu_valid;
861 /** User space pin count and filp owning the pin */
862 uint32_t user_pin_count;
863 struct drm_file *pin_filp;
865 /** for phy allocated objects */
866 struct drm_i915_gem_phys_object *phys_obj;
869 * Number of crtcs where this object is currently the fb, but
870 * will be page flipped away on the next vblank. When it
871 * reaches 0, dev_priv->pending_flip_queue will be woken up.
873 atomic_t pending_flip;
876 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
879 * Request queue structure.
881 * The request queue allows us to note sequence numbers that have been emitted
882 * and may be associated with active buffers to be retired.
884 * By keeping this list, we can avoid having to do questionable
885 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
886 * an emission time with seqnos for tracking how far ahead of the GPU we are.
888 struct drm_i915_gem_request {
889 /** On Which ring this request was generated */
890 struct intel_ring_buffer *ring;
892 /** GEM sequence number associated with this request. */
895 /** Time at which this request was emitted, in jiffies. */
896 unsigned long emitted_jiffies;
898 /** global list entry for this request */
899 struct list_head list;
901 struct drm_i915_file_private *file_priv;
902 /** file_priv list entry for this request */
903 struct list_head client_list;
906 struct drm_i915_file_private {
908 struct spinlock lock;
909 struct list_head request_list;
913 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
915 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
916 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
917 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
918 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
919 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
920 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
921 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
922 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
923 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
924 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
925 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
926 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
927 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
928 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
929 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
930 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
931 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
932 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
933 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
934 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
937 * The genX designation typically refers to the render engine, so render
938 * capability related checks should use IS_GEN, while display and other checks
939 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
942 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
943 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
944 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
945 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
946 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
947 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
949 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
950 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
951 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
953 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
954 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
956 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
957 * rows, which changed the alignment requirements and fence programming.
959 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
961 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
962 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
963 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
964 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
965 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
966 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
967 /* dsparb controlled by hw only */
968 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
970 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
971 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
972 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
974 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
975 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
977 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
978 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
979 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
981 #include "i915_trace.h"
983 extern struct drm_ioctl_desc i915_ioctls[];
984 extern int i915_max_ioctl;
985 extern unsigned int i915_fbpercrtc;
986 extern int i915_panel_ignore_lid;
987 extern unsigned int i915_powersave;
988 extern unsigned int i915_semaphores;
989 extern unsigned int i915_lvds_downclock;
990 extern unsigned int i915_panel_use_ssc;
991 extern int i915_vbt_sdvo_panel_type;
992 extern unsigned int i915_enable_rc6;
993 extern unsigned int i915_enable_fbc;
995 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
996 extern int i915_resume(struct drm_device *dev);
997 extern void i915_save_display(struct drm_device *dev);
998 extern void i915_restore_display(struct drm_device *dev);
999 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1000 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1003 extern void i915_kernel_lost_context(struct drm_device * dev);
1004 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1005 extern int i915_driver_unload(struct drm_device *);
1006 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1007 extern void i915_driver_lastclose(struct drm_device * dev);
1008 extern void i915_driver_preclose(struct drm_device *dev,
1009 struct drm_file *file_priv);
1010 extern void i915_driver_postclose(struct drm_device *dev,
1011 struct drm_file *file_priv);
1012 extern int i915_driver_device_is_agp(struct drm_device * dev);
1013 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1015 extern int i915_emit_box(struct drm_device *dev,
1016 struct drm_clip_rect *box,
1018 extern int i915_reset(struct drm_device *dev, u8 flags);
1019 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1020 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1021 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1022 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1026 void i915_hangcheck_elapsed(unsigned long data);
1027 void i915_handle_error(struct drm_device *dev, bool wedged);
1028 extern int i915_irq_emit(struct drm_device *dev, void *data,
1029 struct drm_file *file_priv);
1030 extern int i915_irq_wait(struct drm_device *dev, void *data,
1031 struct drm_file *file_priv);
1033 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
1034 extern void i915_driver_irq_preinstall(struct drm_device * dev);
1035 extern int i915_driver_irq_postinstall(struct drm_device *dev);
1036 extern void i915_driver_irq_uninstall(struct drm_device * dev);
1038 extern irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS);
1039 extern void ironlake_irq_preinstall(struct drm_device *dev);
1040 extern int ironlake_irq_postinstall(struct drm_device *dev);
1041 extern void ironlake_irq_uninstall(struct drm_device *dev);
1043 extern irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS);
1044 extern void ivybridge_irq_preinstall(struct drm_device *dev);
1045 extern int ivybridge_irq_postinstall(struct drm_device *dev);
1046 extern void ivybridge_irq_uninstall(struct drm_device *dev);
1048 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1049 struct drm_file *file_priv);
1050 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1051 struct drm_file *file_priv);
1052 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
1053 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
1054 extern int ironlake_enable_vblank(struct drm_device *dev, int crtc);
1055 extern void ironlake_disable_vblank(struct drm_device *dev, int crtc);
1056 extern int ivybridge_enable_vblank(struct drm_device *dev, int crtc);
1057 extern void ivybridge_disable_vblank(struct drm_device *dev, int crtc);
1058 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
1059 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
1060 extern int i915_vblank_swap(struct drm_device *dev, void *data,
1061 struct drm_file *file_priv);
1064 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1067 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1069 void intel_enable_asle (struct drm_device *dev);
1070 int i915_get_vblank_timestamp(struct drm_device *dev, int crtc,
1072 struct timeval *vblank_time,
1075 int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
1076 int *vpos, int *hpos);
1078 #ifdef CONFIG_DEBUG_FS
1079 extern void i915_destroy_error_state(struct drm_device *dev);
1081 #define i915_destroy_error_state(x)
1086 extern int i915_mem_alloc(struct drm_device *dev, void *data,
1087 struct drm_file *file_priv);
1088 extern int i915_mem_free(struct drm_device *dev, void *data,
1089 struct drm_file *file_priv);
1090 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
1091 struct drm_file *file_priv);
1092 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
1093 struct drm_file *file_priv);
1094 extern void i915_mem_takedown(struct mem_block **heap);
1095 extern void i915_mem_release(struct drm_device * dev,
1096 struct drm_file *file_priv, struct mem_block *heap);
1098 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1099 struct drm_file *file_priv);
1100 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1101 struct drm_file *file_priv);
1102 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1103 struct drm_file *file_priv);
1104 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1105 struct drm_file *file_priv);
1106 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1107 struct drm_file *file_priv);
1108 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1109 struct drm_file *file_priv);
1110 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1111 struct drm_file *file_priv);
1112 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1113 struct drm_file *file_priv);
1114 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1115 struct drm_file *file_priv);
1116 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1117 struct drm_file *file_priv);
1118 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1119 struct drm_file *file_priv);
1120 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1121 struct drm_file *file_priv);
1122 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1123 struct drm_file *file_priv);
1124 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1125 struct drm_file *file_priv);
1126 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1127 struct drm_file *file_priv);
1128 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1129 struct drm_file *file_priv);
1130 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1131 struct drm_file *file_priv);
1132 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1133 struct drm_file *file_priv);
1134 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1135 struct drm_file *file_priv);
1136 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1137 struct drm_file *file_priv);
1138 void i915_gem_load(struct drm_device *dev);
1139 int i915_gem_init_object(struct drm_gem_object *obj);
1140 int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring,
1141 uint32_t invalidate_domains,
1142 uint32_t flush_domains);
1143 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1145 void i915_gem_free_object(struct drm_gem_object *obj);
1146 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1148 bool map_and_fenceable);
1149 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1150 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1151 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1152 void i915_gem_lastclose(struct drm_device *dev);
1154 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1155 int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj);
1156 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1157 struct intel_ring_buffer *ring,
1160 int i915_gem_dumb_create(struct drm_file *file_priv,
1161 struct drm_device *dev,
1162 struct drm_mode_create_dumb *args);
1163 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1164 uint32_t handle, uint64_t *offset);
1165 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1168 * Returns true if seq1 is later than seq2.
1171 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1173 return (int32_t)(seq1 - seq2) >= 0;
1177 i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
1179 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1180 return ring->outstanding_lazy_request = dev_priv->next_seqno;
1183 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
1184 struct intel_ring_buffer *pipelined);
1185 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1187 void i915_gem_retire_requests(struct drm_device *dev);
1188 void i915_gem_reset(struct drm_device *dev);
1189 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1190 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1191 uint32_t read_domains,
1192 uint32_t write_domain);
1193 int __must_check i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj);
1194 int __must_check i915_gem_init_ringbuffer(struct drm_device *dev);
1195 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1196 void i915_gem_do_init(struct drm_device *dev,
1197 unsigned long start,
1198 unsigned long mappable_end,
1200 int __must_check i915_gpu_idle(struct drm_device *dev);
1201 int __must_check i915_gem_idle(struct drm_device *dev);
1202 int __must_check i915_add_request(struct intel_ring_buffer *ring,
1203 struct drm_file *file,
1204 struct drm_i915_gem_request *request);
1205 int __must_check i915_wait_request(struct intel_ring_buffer *ring,
1207 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1209 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1212 i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
1213 struct intel_ring_buffer *pipelined);
1214 int i915_gem_attach_phys_object(struct drm_device *dev,
1215 struct drm_i915_gem_object *obj,
1218 void i915_gem_detach_phys_object(struct drm_device *dev,
1219 struct drm_i915_gem_object *obj);
1220 void i915_gem_free_all_phys_object(struct drm_device *dev);
1221 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1224 i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj);
1226 /* i915_gem_gtt.c */
1227 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1228 int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
1229 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1231 /* i915_gem_evict.c */
1232 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1233 unsigned alignment, bool mappable);
1234 int __must_check i915_gem_evict_everything(struct drm_device *dev,
1235 bool purgeable_only);
1236 int __must_check i915_gem_evict_inactive(struct drm_device *dev,
1237 bool purgeable_only);
1239 /* i915_gem_tiling.c */
1240 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1241 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1242 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1244 /* i915_gem_debug.c */
1245 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1246 const char *where, uint32_t mark);
1248 int i915_verify_lists(struct drm_device *dev);
1250 #define i915_verify_lists(dev) 0
1252 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1254 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1255 const char *where, uint32_t mark);
1257 /* i915_debugfs.c */
1258 int i915_debugfs_init(struct drm_minor *minor);
1259 void i915_debugfs_cleanup(struct drm_minor *minor);
1261 /* i915_suspend.c */
1262 extern int i915_save_state(struct drm_device *dev);
1263 extern int i915_restore_state(struct drm_device *dev);
1265 /* i915_suspend.c */
1266 extern int i915_save_state(struct drm_device *dev);
1267 extern int i915_restore_state(struct drm_device *dev);
1270 extern int intel_setup_gmbus(struct drm_device *dev);
1271 extern void intel_teardown_gmbus(struct drm_device *dev);
1272 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1273 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1274 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1276 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1278 extern void intel_i2c_reset(struct drm_device *dev);
1280 /* intel_opregion.c */
1281 extern int intel_opregion_setup(struct drm_device *dev);
1283 extern void intel_opregion_init(struct drm_device *dev);
1284 extern void intel_opregion_fini(struct drm_device *dev);
1285 extern void intel_opregion_asle_intr(struct drm_device *dev);
1286 extern void intel_opregion_gse_intr(struct drm_device *dev);
1287 extern void intel_opregion_enable_asle(struct drm_device *dev);
1289 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1290 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1291 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1292 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1293 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1298 extern void intel_register_dsm_handler(void);
1299 extern void intel_unregister_dsm_handler(void);
1301 static inline void intel_register_dsm_handler(void) { return; }
1302 static inline void intel_unregister_dsm_handler(void) { return; }
1303 #endif /* CONFIG_ACPI */
1306 extern void intel_modeset_init(struct drm_device *dev);
1307 extern void intel_modeset_gem_init(struct drm_device *dev);
1308 extern void intel_modeset_cleanup(struct drm_device *dev);
1309 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1310 extern void i8xx_disable_fbc(struct drm_device *dev);
1311 extern void g4x_disable_fbc(struct drm_device *dev);
1312 extern void ironlake_disable_fbc(struct drm_device *dev);
1313 extern void intel_disable_fbc(struct drm_device *dev);
1314 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
1315 extern bool intel_fbc_enabled(struct drm_device *dev);
1316 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1317 extern void ironlake_enable_rc6(struct drm_device *dev);
1318 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1319 extern void intel_detect_pch (struct drm_device *dev);
1320 extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1323 #ifdef CONFIG_DEBUG_FS
1324 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1325 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1327 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1328 extern void intel_display_print_error_state(struct seq_file *m,
1329 struct drm_device *dev,
1330 struct intel_display_error_state *error);
1333 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
1335 #define BEGIN_LP_RING(n) \
1336 intel_ring_begin(LP_RING(dev_priv), (n))
1338 #define OUT_RING(x) \
1339 intel_ring_emit(LP_RING(dev_priv), x)
1341 #define ADVANCE_LP_RING() \
1342 intel_ring_advance(LP_RING(dev_priv))
1345 * Lock test for when it's just for synchronization of ring access.
1347 * In that case, we don't need to do it when GEM is initialized as nobody else
1348 * has access to the ring.
1350 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
1351 if (LP_RING(dev->dev_private)->obj == NULL) \
1352 LOCK_TEST_WITH_RETURN(dev, file); \
1355 /* On SNB platform, before reading ring registers forcewake bit
1356 * must be set to prevent GT core from power down and stale values being
1359 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1360 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1361 void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1363 /* We give fast paths for the really cool registers */
1364 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1365 (((dev_priv)->info->gen >= 6) && \
1366 ((reg) < 0x40000) && \
1367 ((reg) != FORCEWAKE))
1369 #define __i915_read(x, y) \
1370 static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1372 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1373 gen6_gt_force_wake_get(dev_priv); \
1374 val = read##y(dev_priv->regs + reg); \
1375 gen6_gt_force_wake_put(dev_priv); \
1377 val = read##y(dev_priv->regs + reg); \
1379 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1389 #define __i915_write(x, y) \
1390 static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1391 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1392 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1393 __gen6_gt_wait_for_fifo(dev_priv); \
1395 write##y(val, dev_priv->regs + reg); \
1403 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1404 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1406 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1407 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1408 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1409 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1411 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1412 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1413 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1414 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1416 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1417 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1419 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1420 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)