1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <drm/intel-gtt.h>
40 #include <linux/backlight.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
44 /* General customization:
47 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
49 #define DRIVER_NAME "i915"
50 #define DRIVER_DESC "Intel Graphics"
51 #define DRIVER_DATE "20080730"
59 #define pipe_name(p) ((p) + 'A')
66 #define plane_name(p) ((p) + 'A')
76 #define port_name(p) ((p) + 'A')
78 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
80 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
82 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
83 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
84 if ((intel_encoder)->base.crtc == (__crtc))
86 struct intel_pch_pll {
87 int refcount; /* count of number of CRTCs sharing this PLL */
88 int active; /* count of number of active CRTCs (i.e. DPMS on) */
89 bool on; /* is the PLL actually active? Disabled during modeset */
94 #define I915_NUM_PLLS 2
99 * 1.2: Add Power Management
100 * 1.3: Add vblank support
101 * 1.4: Fix cmdbuffer path, add heap destroy
102 * 1.5: Add vblank pipe configuration
103 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
104 * - Support vertical blank on secondary display pipe
106 #define DRIVER_MAJOR 1
107 #define DRIVER_MINOR 6
108 #define DRIVER_PATCHLEVEL 0
110 #define WATCH_COHERENCY 0
111 #define WATCH_LISTS 0
113 #define I915_GEM_PHYS_CURSOR_0 1
114 #define I915_GEM_PHYS_CURSOR_1 2
115 #define I915_GEM_PHYS_OVERLAY_REGS 3
116 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
118 struct drm_i915_gem_phys_object {
120 struct page **page_list;
121 drm_dma_handle_t *handle;
122 struct drm_i915_gem_object *cur_obj;
126 struct mem_block *next;
127 struct mem_block *prev;
130 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
133 struct opregion_header;
134 struct opregion_acpi;
135 struct opregion_swsci;
136 struct opregion_asle;
137 struct drm_i915_private;
139 struct intel_opregion {
140 struct opregion_header __iomem *header;
141 struct opregion_acpi __iomem *acpi;
142 struct opregion_swsci __iomem *swsci;
143 struct opregion_asle __iomem *asle;
145 u32 __iomem *lid_state;
147 #define OPREGION_SIZE (8*1024)
149 struct intel_overlay;
150 struct intel_overlay_error_state;
152 struct drm_i915_master_private {
153 drm_local_map_t *sarea;
154 struct _drm_i915_sarea *sarea_priv;
156 #define I915_FENCE_REG_NONE -1
157 #define I915_MAX_NUM_FENCES 16
158 /* 16 fences + sign bit for FENCE_REG_NONE */
159 #define I915_MAX_NUM_FENCE_BITS 5
161 struct drm_i915_fence_reg {
162 struct list_head lru_list;
163 struct drm_i915_gem_object *obj;
167 struct sdvo_device_mapping {
176 struct intel_display_error_state;
178 struct drm_i915_error_state {
184 bool waiting[I915_NUM_RINGS];
185 u32 pipestat[I915_MAX_PIPES];
186 u32 tail[I915_NUM_RINGS];
187 u32 head[I915_NUM_RINGS];
188 u32 ipeir[I915_NUM_RINGS];
189 u32 ipehr[I915_NUM_RINGS];
190 u32 instdone[I915_NUM_RINGS];
191 u32 acthd[I915_NUM_RINGS];
192 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
193 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
194 /* our own tracking of ring head and tail */
195 u32 cpu_ring_head[I915_NUM_RINGS];
196 u32 cpu_ring_tail[I915_NUM_RINGS];
197 u32 error; /* gen6+ */
198 u32 instpm[I915_NUM_RINGS];
199 u32 instps[I915_NUM_RINGS];
201 u32 seqno[I915_NUM_RINGS];
203 u32 fault_reg[I915_NUM_RINGS];
205 u32 faddr[I915_NUM_RINGS];
206 u64 fence[I915_MAX_NUM_FENCES];
208 struct drm_i915_error_ring {
209 struct drm_i915_error_object {
213 } *ringbuffer, *batchbuffer;
214 struct drm_i915_error_request {
220 } ring[I915_NUM_RINGS];
221 struct drm_i915_error_buffer {
228 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
235 } *active_bo, *pinned_bo;
236 u32 active_bo_count, pinned_bo_count;
237 struct intel_overlay_error_state *overlay;
238 struct intel_display_error_state *display;
241 struct drm_i915_display_funcs {
242 void (*dpms)(struct drm_crtc *crtc, int mode);
243 bool (*fbc_enabled)(struct drm_device *dev);
244 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
245 void (*disable_fbc)(struct drm_device *dev);
246 int (*get_display_clock_speed)(struct drm_device *dev);
247 int (*get_fifo_size)(struct drm_device *dev, int plane);
248 void (*update_wm)(struct drm_device *dev);
249 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
250 uint32_t sprite_width, int pixel_size);
251 void (*sanitize_pm)(struct drm_device *dev);
252 void (*update_linetime_wm)(struct drm_device *dev, int pipe,
253 struct drm_display_mode *mode);
254 int (*crtc_mode_set)(struct drm_crtc *crtc,
255 struct drm_display_mode *mode,
256 struct drm_display_mode *adjusted_mode,
258 struct drm_framebuffer *old_fb);
259 void (*off)(struct drm_crtc *crtc);
260 void (*write_eld)(struct drm_connector *connector,
261 struct drm_crtc *crtc);
262 void (*fdi_link_train)(struct drm_crtc *crtc);
263 void (*init_clock_gating)(struct drm_device *dev);
264 void (*init_pch_clock_gating)(struct drm_device *dev);
265 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
266 struct drm_framebuffer *fb,
267 struct drm_i915_gem_object *obj);
268 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
270 /* clock updates for mode set */
272 /* render clock increase/decrease */
273 /* display clock increase/decrease */
274 /* pll clock increase/decrease */
277 struct drm_i915_gt_funcs {
278 void (*force_wake_get)(struct drm_i915_private *dev_priv);
279 void (*force_wake_put)(struct drm_i915_private *dev_priv);
282 struct intel_device_info {
301 u8 cursor_needs_physical:1;
303 u8 overlay_needs_physical:1;
310 #define I915_PPGTT_PD_ENTRIES 512
311 #define I915_PPGTT_PT_ENTRIES 1024
312 struct i915_hw_ppgtt {
313 unsigned num_pd_entries;
314 struct page **pt_pages;
316 dma_addr_t *pt_dma_addr;
317 dma_addr_t scratch_page_dma_addr;
321 /* This must match up with the value previously used for execbuf2.rsvd1. */
322 #define DEFAULT_CONTEXT_ID 0
323 struct i915_hw_context {
326 struct drm_i915_file_private *file_priv;
327 struct intel_ring_buffer *ring;
328 struct drm_i915_gem_object *obj;
332 FBC_NO_OUTPUT, /* no outputs enabled to compress */
333 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
334 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
335 FBC_MODE_TOO_LARGE, /* mode too large for compression */
336 FBC_BAD_PLANE, /* fbc not supported on plane */
337 FBC_NOT_TILED, /* buffer not tiled */
338 FBC_MULTIPLE_PIPES, /* more than one pipe active */
343 PCH_NONE = 0, /* No PCH present */
344 PCH_IBX, /* Ibexpeak PCH */
345 PCH_CPT, /* Cougarpoint PCH */
346 PCH_LPT, /* Lynxpoint PCH */
349 #define QUIRK_PIPEA_FORCE (1<<0)
350 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
351 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
354 struct intel_fbc_work;
357 struct i2c_adapter adapter;
361 struct i2c_algo_bit_data bit_algo;
362 struct drm_i915_private *dev_priv;
365 typedef struct drm_i915_private {
366 struct drm_device *dev;
368 const struct intel_device_info *info;
370 int relative_constants_mode;
374 struct drm_i915_gt_funcs gt;
375 /** gt_fifo_count and the subsequent register write are synchronized
376 * with dev->struct_mutex. */
377 unsigned gt_fifo_count;
378 /** forcewake_count is protected by gt_lock */
379 unsigned forcewake_count;
380 /** gt_lock is also taken in irq contexts. */
381 struct spinlock gt_lock;
383 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
385 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
386 * controller on different i2c buses. */
387 struct mutex gmbus_mutex;
390 * Base address of the gmbus and gpio block.
392 uint32_t gpio_mmio_base;
394 struct pci_dev *bridge_dev;
395 struct intel_ring_buffer ring[I915_NUM_RINGS];
398 drm_dma_handle_t *status_page_dmah;
400 struct drm_i915_gem_object *pwrctx;
401 struct drm_i915_gem_object *renderctx;
403 struct resource mch_res;
411 atomic_t irq_received;
413 /* protects the irq masks */
416 /* DPIO indirect register protection */
417 spinlock_t dpio_lock;
419 /** Cached value of IMR to avoid reads in updating the bitfield */
425 u32 hotplug_supported_mask;
426 struct work_struct hotplug_work;
428 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
432 /* For hangcheck timer */
433 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
434 struct timer_list hangcheck_timer;
436 uint32_t last_acthd[I915_NUM_RINGS];
437 uint32_t last_instdone;
438 uint32_t last_instdone1;
440 unsigned int stop_rings;
442 unsigned long cfb_size;
444 enum plane cfb_plane;
446 struct intel_fbc_work *fbc_work;
448 struct intel_opregion opregion;
451 struct intel_overlay *overlay;
452 bool sprite_scaling_enabled;
455 int backlight_level; /* restore backlight to this value */
456 bool backlight_enabled;
457 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
458 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
460 /* Feature bits from the VBIOS */
461 unsigned int int_tv_support:1;
462 unsigned int lvds_dither:1;
463 unsigned int lvds_vbt:1;
464 unsigned int int_crt_support:1;
465 unsigned int lvds_use_ssc:1;
466 unsigned int display_clock_mode:1;
468 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
469 unsigned int lvds_val; /* used for checking LVDS channel mode */
479 struct edp_power_seq pps;
481 bool no_aux_handshake;
483 struct notifier_block lid_notifier;
486 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
487 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
488 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
490 unsigned int fsb_freq, mem_freq, is_ddr3;
492 spinlock_t error_lock;
493 /* Protected by dev->error_lock. */
494 struct drm_i915_error_state *first_error;
495 struct work_struct error_work;
496 struct completion error_completion;
497 struct workqueue_struct *wq;
499 /* Display functions */
500 struct drm_i915_display_funcs display;
502 /* PCH chipset type */
503 enum intel_pch pch_type;
505 unsigned long quirks;
530 u32 saveTRANS_HTOTAL_A;
531 u32 saveTRANS_HBLANK_A;
532 u32 saveTRANS_HSYNC_A;
533 u32 saveTRANS_VTOTAL_A;
534 u32 saveTRANS_VBLANK_A;
535 u32 saveTRANS_VSYNC_A;
543 u32 savePFIT_PGM_RATIOS;
544 u32 saveBLC_HIST_CTL;
546 u32 saveBLC_PWM_CTL2;
547 u32 saveBLC_CPU_PWM_CTL;
548 u32 saveBLC_CPU_PWM_CTL2;
561 u32 saveTRANS_HTOTAL_B;
562 u32 saveTRANS_HBLANK_B;
563 u32 saveTRANS_HSYNC_B;
564 u32 saveTRANS_VTOTAL_B;
565 u32 saveTRANS_VBLANK_B;
566 u32 saveTRANS_VSYNC_B;
580 u32 savePP_ON_DELAYS;
581 u32 savePP_OFF_DELAYS;
589 u32 savePFIT_CONTROL;
590 u32 save_palette_a[256];
591 u32 save_palette_b[256];
592 u32 saveDPFC_CB_BASE;
593 u32 saveFBC_CFB_BASE;
596 u32 saveFBC_CONTROL2;
606 u32 saveCACHE_MODE_0;
607 u32 saveMI_ARB_STATE;
618 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
629 u32 savePIPEA_GMCH_DATA_M;
630 u32 savePIPEB_GMCH_DATA_M;
631 u32 savePIPEA_GMCH_DATA_N;
632 u32 savePIPEB_GMCH_DATA_N;
633 u32 savePIPEA_DP_LINK_M;
634 u32 savePIPEB_DP_LINK_M;
635 u32 savePIPEA_DP_LINK_N;
636 u32 savePIPEB_DP_LINK_N;
647 u32 savePCH_DREF_CONTROL;
648 u32 saveDISP_ARB_CTL;
649 u32 savePIPEA_DATA_M1;
650 u32 savePIPEA_DATA_N1;
651 u32 savePIPEA_LINK_M1;
652 u32 savePIPEA_LINK_N1;
653 u32 savePIPEB_DATA_M1;
654 u32 savePIPEB_DATA_N1;
655 u32 savePIPEB_LINK_M1;
656 u32 savePIPEB_LINK_N1;
657 u32 saveMCHBAR_RENDER_STANDBY;
658 u32 savePCH_PORT_HOTPLUG;
661 /** Bridge to intel-gtt-ko */
662 const struct intel_gtt *gtt;
663 /** Memory allocator for GTT stolen memory */
664 struct drm_mm stolen;
665 /** Memory allocator for GTT */
666 struct drm_mm gtt_space;
667 /** List of all objects in gtt_space. Used to restore gtt
668 * mappings on resume */
669 struct list_head gtt_list;
671 /** Usable portion of the GTT for GEM */
672 unsigned long gtt_start;
673 unsigned long gtt_mappable_end;
674 unsigned long gtt_end;
676 struct io_mapping *gtt_mapping;
677 phys_addr_t gtt_base_addr;
680 /** PPGTT used for aliasing the PPGTT with the GTT */
681 struct i915_hw_ppgtt *aliasing_ppgtt;
685 struct shrinker inactive_shrinker;
688 * List of objects currently involved in rendering.
690 * Includes buffers having the contents of their GPU caches
691 * flushed, not necessarily primitives. last_rendering_seqno
692 * represents when the rendering involved will be completed.
694 * A reference is held on the buffer while on this list.
696 struct list_head active_list;
699 * LRU list of objects which are not in the ringbuffer and
700 * are ready to unbind, but are still in the GTT.
702 * last_rendering_seqno is 0 while an object is in this list.
704 * A reference is not held on the buffer while on this list,
705 * as merely being GTT-bound shouldn't prevent its being
706 * freed, and we'll pull it off the list in the free path.
708 struct list_head inactive_list;
710 /** LRU list of objects with fence regs on them. */
711 struct list_head fence_list;
714 * We leave the user IRQ off as much as possible,
715 * but this means that requests will finish and never
716 * be retired once the system goes idle. Set a timer to
717 * fire periodically while the ring is running. When it
718 * fires, go retire requests.
720 struct delayed_work retire_work;
723 * Are we in a non-interruptible section of code like
729 * Flag if the X Server, and thus DRM, is not currently in
730 * control of the device.
732 * This is set between LeaveVT and EnterVT. It needs to be
733 * replaced with a semaphore. It also needs to be
734 * transitioned away from for kernel modesetting.
739 * Flag if the hardware appears to be wedged.
741 * This is set when attempts to idle the device timeout.
742 * It prevents command submission from occurring and makes
743 * every pending request fail
747 /** Bit 6 swizzling required for X tiling */
748 uint32_t bit_6_swizzle_x;
749 /** Bit 6 swizzling required for Y tiling */
750 uint32_t bit_6_swizzle_y;
752 /* storage for physical objects */
753 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
755 /* accounting, useful for userland debugging */
757 size_t mappable_gtt_total;
758 size_t object_memory;
762 /* Old dri1 support infrastructure, beware the dragons ya fools entering
765 unsigned allow_batchbuffer : 1;
766 u32 __iomem *gfx_hws_cpu_addr;
769 /* Kernel Modesetting */
771 struct sdvo_device_mapping sdvo_mappings[2];
772 /* indicate whether the LVDS_BORDER should be enabled or not */
773 unsigned int lvds_border_bits;
774 /* Panel fitter placement and size for Ironlake+ */
775 u32 pch_pf_pos, pch_pf_size;
777 struct drm_crtc *plane_to_crtc_mapping[3];
778 struct drm_crtc *pipe_to_crtc_mapping[3];
779 wait_queue_head_t pending_flip_queue;
781 struct intel_pch_pll pch_plls[I915_NUM_PLLS];
783 /* Reclocking support */
784 bool render_reclock_avail;
785 bool lvds_downclock_avail;
786 /* indicates the reduced downclock for LVDS*/
788 struct work_struct idle_work;
789 struct timer_list idle_timer;
793 struct child_device_config *child_dev;
794 struct drm_connector *int_lvds_connector;
795 struct drm_connector *int_edp_connector;
797 bool mchbar_need_disable;
799 struct work_struct rps_work;
810 unsigned long last_time1;
811 unsigned long chipset_power;
813 struct timespec last_time2;
814 unsigned long gfx_power;
818 spinlock_t *mchdev_lock;
820 enum no_fbc_reason no_fbc_reason;
822 struct drm_mm_node *compressed_fb;
823 struct drm_mm_node *compressed_llb;
825 unsigned long last_gpu_reset;
827 /* list of fbdev register on this device */
828 struct intel_fbdev *fbdev;
830 struct backlight_device *backlight;
832 struct drm_property *broadcast_rgb_property;
833 struct drm_property *force_audio_property;
835 struct work_struct parity_error_work;
836 bool hw_contexts_disabled;
837 uint32_t hw_context_size;
838 } drm_i915_private_t;
840 /* Iterate over initialised rings */
841 #define for_each_ring(ring__, dev_priv__, i__) \
842 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
843 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
845 enum hdmi_force_audio {
846 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
847 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
848 HDMI_AUDIO_AUTO, /* trust EDID */
849 HDMI_AUDIO_ON, /* force turn on HDMI audio */
852 enum i915_cache_level {
855 I915_CACHE_LLC_MLC, /* gen6+ */
858 struct drm_i915_gem_object {
859 struct drm_gem_object base;
861 /** Current space allocated to this object in the GTT, if any. */
862 struct drm_mm_node *gtt_space;
863 struct list_head gtt_list;
865 /** This object's place on the active/inactive lists */
866 struct list_head ring_list;
867 struct list_head mm_list;
868 /** This object's place on GPU write list */
869 struct list_head gpu_write_list;
870 /** This object's place in the batchbuffer or on the eviction list */
871 struct list_head exec_list;
874 * This is set if the object is on the active lists (has pending
875 * rendering and so a non-zero seqno), and is not set if it i s on
876 * inactive (ready to be unbound) list.
878 unsigned int active:1;
881 * This is set if the object has been written to since last bound
884 unsigned int dirty:1;
887 * Fence register bits (if any) for this object. Will be set
888 * as needed when mapped into the GTT.
889 * Protected by dev->struct_mutex.
891 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
894 * Advice: are the backing pages purgeable?
899 * Current tiling mode for the object.
901 unsigned int tiling_mode:2;
903 * Whether the tiling parameters for the currently associated fence
904 * register have changed. Note that for the purposes of tracking
905 * tiling changes we also treat the unfenced register, the register
906 * slot that the object occupies whilst it executes a fenced
907 * command (such as BLT on gen2/3), as a "fence".
909 unsigned int fence_dirty:1;
911 /** How many users have pinned this object in GTT space. The following
912 * users can each hold at most one reference: pwrite/pread, pin_ioctl
913 * (via user_pin_count), execbuffer (objects are not allowed multiple
914 * times for the same batchbuffer), and the framebuffer code. When
915 * switching/pageflipping, the framebuffer code has at most two buffers
918 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
919 * bits with absolutely no headroom. So use 4 bits. */
920 unsigned int pin_count:4;
921 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
924 * Is the object at the current location in the gtt mappable and
925 * fenceable? Used to avoid costly recalculations.
927 unsigned int map_and_fenceable:1;
930 * Whether the current gtt mapping needs to be mappable (and isn't just
931 * mappable by accident). Track pin and fault separate for a more
932 * accurate mappable working set.
934 unsigned int fault_mappable:1;
935 unsigned int pin_mappable:1;
938 * Is the GPU currently using a fence to access this buffer,
940 unsigned int pending_fenced_gpu_access:1;
941 unsigned int fenced_gpu_access:1;
943 unsigned int cache_level:2;
945 unsigned int has_aliasing_ppgtt_mapping:1;
946 unsigned int has_global_gtt_mapping:1;
953 struct scatterlist *sg_list;
956 /* prime dma-buf support */
957 struct sg_table *sg_table;
958 void *dma_buf_vmapping;
962 * Used for performing relocations during execbuffer insertion.
964 struct hlist_node exec_node;
965 unsigned long exec_handle;
966 struct drm_i915_gem_exec_object2 *exec_entry;
969 * Current offset of the object in GTT space.
971 * This is the same as gtt_space->start
975 struct intel_ring_buffer *ring;
977 /** Breadcrumb of last rendering to the buffer. */
978 uint32_t last_read_seqno;
979 uint32_t last_write_seqno;
980 /** Breadcrumb of last fenced GPU access to the buffer. */
981 uint32_t last_fenced_seqno;
983 /** Current tiling stride for the object, if it's tiled. */
986 /** Record of address bit 17 of each page at last unbind. */
987 unsigned long *bit_17;
989 /** User space pin count and filp owning the pin */
990 uint32_t user_pin_count;
991 struct drm_file *pin_filp;
993 /** for phy allocated objects */
994 struct drm_i915_gem_phys_object *phys_obj;
997 * Number of crtcs where this object is currently the fb, but
998 * will be page flipped away on the next vblank. When it
999 * reaches 0, dev_priv->pending_flip_queue will be woken up.
1001 atomic_t pending_flip;
1004 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1007 * Request queue structure.
1009 * The request queue allows us to note sequence numbers that have been emitted
1010 * and may be associated with active buffers to be retired.
1012 * By keeping this list, we can avoid having to do questionable
1013 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1014 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1016 struct drm_i915_gem_request {
1017 /** On Which ring this request was generated */
1018 struct intel_ring_buffer *ring;
1020 /** GEM sequence number associated with this request. */
1023 /** Postion in the ringbuffer of the end of the request */
1026 /** Time at which this request was emitted, in jiffies. */
1027 unsigned long emitted_jiffies;
1029 /** global list entry for this request */
1030 struct list_head list;
1032 struct drm_i915_file_private *file_priv;
1033 /** file_priv list entry for this request */
1034 struct list_head client_list;
1037 struct drm_i915_file_private {
1039 struct spinlock lock;
1040 struct list_head request_list;
1042 struct idr context_idr;
1045 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1047 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1048 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1049 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1050 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1051 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1052 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1053 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1054 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1055 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1056 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1057 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1058 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1059 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1060 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1061 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1062 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1063 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1064 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1065 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1066 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1067 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1068 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1071 * The genX designation typically refers to the render engine, so render
1072 * capability related checks should use IS_GEN, while display and other checks
1073 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1076 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1077 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1078 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1079 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1080 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1081 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1083 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1084 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1085 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1086 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1088 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1089 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1091 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1092 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1094 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1095 * rows, which changed the alignment requirements and fence programming.
1097 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1099 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1100 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1101 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1102 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1103 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1104 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1105 /* dsparb controlled by hw only */
1106 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1108 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1109 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1110 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1112 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1114 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1115 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1116 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1117 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1118 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1120 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1122 #include "i915_trace.h"
1125 * RC6 is a special power stage which allows the GPU to enter an very
1126 * low-voltage mode when idle, using down to 0V while at this stage. This
1127 * stage is entered automatically when the GPU is idle when RC6 support is
1128 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1130 * There are different RC6 modes available in Intel GPU, which differentiate
1131 * among each other with the latency required to enter and leave RC6 and
1132 * voltage consumed by the GPU in different states.
1134 * The combination of the following flags define which states GPU is allowed
1135 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1136 * RC6pp is deepest RC6. Their support by hardware varies according to the
1137 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1138 * which brings the most power savings; deeper states save more power, but
1139 * require higher latency to switch to and wake up.
1141 #define INTEL_RC6_ENABLE (1<<0)
1142 #define INTEL_RC6p_ENABLE (1<<1)
1143 #define INTEL_RC6pp_ENABLE (1<<2)
1145 extern struct drm_ioctl_desc i915_ioctls[];
1146 extern int i915_max_ioctl;
1147 extern unsigned int i915_fbpercrtc __always_unused;
1148 extern int i915_panel_ignore_lid __read_mostly;
1149 extern unsigned int i915_powersave __read_mostly;
1150 extern int i915_semaphores __read_mostly;
1151 extern unsigned int i915_lvds_downclock __read_mostly;
1152 extern int i915_lvds_channel_mode __read_mostly;
1153 extern int i915_panel_use_ssc __read_mostly;
1154 extern int i915_vbt_sdvo_panel_type __read_mostly;
1155 extern int i915_enable_rc6 __read_mostly;
1156 extern int i915_enable_fbc __read_mostly;
1157 extern bool i915_enable_hangcheck __read_mostly;
1158 extern int i915_enable_ppgtt __read_mostly;
1160 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1161 extern int i915_resume(struct drm_device *dev);
1162 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1163 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1166 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1167 extern void i915_kernel_lost_context(struct drm_device * dev);
1168 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1169 extern int i915_driver_unload(struct drm_device *);
1170 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1171 extern void i915_driver_lastclose(struct drm_device * dev);
1172 extern void i915_driver_preclose(struct drm_device *dev,
1173 struct drm_file *file_priv);
1174 extern void i915_driver_postclose(struct drm_device *dev,
1175 struct drm_file *file_priv);
1176 extern int i915_driver_device_is_agp(struct drm_device * dev);
1177 #ifdef CONFIG_COMPAT
1178 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1181 extern int i915_emit_box(struct drm_device *dev,
1182 struct drm_clip_rect *box,
1184 extern int intel_gpu_reset(struct drm_device *dev);
1185 extern int i915_reset(struct drm_device *dev);
1186 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1187 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1188 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1189 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1193 void i915_hangcheck_elapsed(unsigned long data);
1194 void i915_handle_error(struct drm_device *dev, bool wedged);
1196 extern void intel_irq_init(struct drm_device *dev);
1197 extern void intel_gt_init(struct drm_device *dev);
1199 void i915_error_state_free(struct kref *error_ref);
1202 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1205 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1207 void intel_enable_asle(struct drm_device *dev);
1209 #ifdef CONFIG_DEBUG_FS
1210 extern void i915_destroy_error_state(struct drm_device *dev);
1212 #define i915_destroy_error_state(x)
1217 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1218 struct drm_file *file_priv);
1219 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1220 struct drm_file *file_priv);
1221 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1222 struct drm_file *file_priv);
1223 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1224 struct drm_file *file_priv);
1225 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1226 struct drm_file *file_priv);
1227 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1228 struct drm_file *file_priv);
1229 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1230 struct drm_file *file_priv);
1231 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1232 struct drm_file *file_priv);
1233 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1234 struct drm_file *file_priv);
1235 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1236 struct drm_file *file_priv);
1237 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1238 struct drm_file *file_priv);
1239 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1240 struct drm_file *file_priv);
1241 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1242 struct drm_file *file_priv);
1243 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1244 struct drm_file *file_priv);
1245 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1246 struct drm_file *file_priv);
1247 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1248 struct drm_file *file_priv);
1249 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1250 struct drm_file *file_priv);
1251 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1252 struct drm_file *file_priv);
1253 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1254 struct drm_file *file_priv);
1255 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1256 struct drm_file *file_priv);
1257 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1258 struct drm_file *file_priv);
1259 void i915_gem_load(struct drm_device *dev);
1260 int i915_gem_init_object(struct drm_gem_object *obj);
1261 int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring,
1262 uint32_t invalidate_domains,
1263 uint32_t flush_domains);
1264 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1266 void i915_gem_free_object(struct drm_gem_object *obj);
1267 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1269 bool map_and_fenceable);
1270 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1271 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1272 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1273 void i915_gem_lastclose(struct drm_device *dev);
1275 int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
1277 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1278 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1279 struct intel_ring_buffer *to);
1280 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1281 struct intel_ring_buffer *ring,
1284 int i915_gem_dumb_create(struct drm_file *file_priv,
1285 struct drm_device *dev,
1286 struct drm_mode_create_dumb *args);
1287 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1288 uint32_t handle, uint64_t *offset);
1289 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1292 * Returns true if seq1 is later than seq2.
1295 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1297 return (int32_t)(seq1 - seq2) >= 0;
1300 u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring);
1302 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1303 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1306 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1308 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1309 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1310 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1317 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1319 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1320 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1321 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1325 void i915_gem_retire_requests(struct drm_device *dev);
1326 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1327 int __must_check i915_gem_check_wedge(struct drm_i915_private *dev_priv,
1328 bool interruptible);
1330 void i915_gem_reset(struct drm_device *dev);
1331 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1332 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1333 uint32_t read_domains,
1334 uint32_t write_domain);
1335 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1336 int __must_check i915_gem_init(struct drm_device *dev);
1337 int __must_check i915_gem_init_hw(struct drm_device *dev);
1338 void i915_gem_l3_remap(struct drm_device *dev);
1339 void i915_gem_init_swizzling(struct drm_device *dev);
1340 void i915_gem_init_ppgtt(struct drm_device *dev);
1341 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1342 int __must_check i915_gpu_idle(struct drm_device *dev);
1343 int __must_check i915_gem_idle(struct drm_device *dev);
1344 int i915_add_request(struct intel_ring_buffer *ring,
1345 struct drm_file *file,
1346 struct drm_i915_gem_request *request);
1347 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1349 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1351 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1354 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1356 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1358 struct intel_ring_buffer *pipelined);
1359 int i915_gem_attach_phys_object(struct drm_device *dev,
1360 struct drm_i915_gem_object *obj,
1363 void i915_gem_detach_phys_object(struct drm_device *dev,
1364 struct drm_i915_gem_object *obj);
1365 void i915_gem_free_all_phys_object(struct drm_device *dev);
1366 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1369 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1373 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1374 enum i915_cache_level cache_level);
1376 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1377 struct dma_buf *dma_buf);
1379 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
1380 struct drm_gem_object *gem_obj, int flags);
1382 /* i915_gem_context.c */
1383 void i915_gem_context_init(struct drm_device *dev);
1384 void i915_gem_context_fini(struct drm_device *dev);
1385 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
1386 int i915_switch_context(struct intel_ring_buffer *ring,
1387 struct drm_file *file, int to_id);
1388 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
1389 struct drm_file *file);
1390 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
1391 struct drm_file *file);
1393 /* i915_gem_gtt.c */
1394 int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
1395 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1396 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1397 struct drm_i915_gem_object *obj,
1398 enum i915_cache_level cache_level);
1399 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1400 struct drm_i915_gem_object *obj);
1402 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1403 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1404 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1405 enum i915_cache_level cache_level);
1406 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1407 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1408 void i915_gem_init_global_gtt(struct drm_device *dev,
1409 unsigned long start,
1410 unsigned long mappable_end,
1413 /* i915_gem_evict.c */
1414 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1415 unsigned alignment, bool mappable);
1416 int i915_gem_evict_everything(struct drm_device *dev, bool purgeable_only);
1418 /* i915_gem_stolen.c */
1419 int i915_gem_init_stolen(struct drm_device *dev);
1420 void i915_gem_cleanup_stolen(struct drm_device *dev);
1422 /* i915_gem_tiling.c */
1423 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1424 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1425 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1427 /* i915_gem_debug.c */
1428 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1429 const char *where, uint32_t mark);
1431 int i915_verify_lists(struct drm_device *dev);
1433 #define i915_verify_lists(dev) 0
1435 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1437 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1438 const char *where, uint32_t mark);
1440 /* i915_debugfs.c */
1441 int i915_debugfs_init(struct drm_minor *minor);
1442 void i915_debugfs_cleanup(struct drm_minor *minor);
1444 /* i915_suspend.c */
1445 extern int i915_save_state(struct drm_device *dev);
1446 extern int i915_restore_state(struct drm_device *dev);
1448 /* i915_suspend.c */
1449 extern int i915_save_state(struct drm_device *dev);
1450 extern int i915_restore_state(struct drm_device *dev);
1453 void i915_setup_sysfs(struct drm_device *dev_priv);
1454 void i915_teardown_sysfs(struct drm_device *dev_priv);
1457 extern int intel_setup_gmbus(struct drm_device *dev);
1458 extern void intel_teardown_gmbus(struct drm_device *dev);
1459 extern inline bool intel_gmbus_is_port_valid(unsigned port)
1461 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1464 extern struct i2c_adapter *intel_gmbus_get_adapter(
1465 struct drm_i915_private *dev_priv, unsigned port);
1466 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1467 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1468 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1470 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1472 extern void intel_i2c_reset(struct drm_device *dev);
1474 /* intel_opregion.c */
1475 extern int intel_opregion_setup(struct drm_device *dev);
1477 extern void intel_opregion_init(struct drm_device *dev);
1478 extern void intel_opregion_fini(struct drm_device *dev);
1479 extern void intel_opregion_asle_intr(struct drm_device *dev);
1480 extern void intel_opregion_gse_intr(struct drm_device *dev);
1481 extern void intel_opregion_enable_asle(struct drm_device *dev);
1483 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1484 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1485 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1486 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1487 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1492 extern void intel_register_dsm_handler(void);
1493 extern void intel_unregister_dsm_handler(void);
1495 static inline void intel_register_dsm_handler(void) { return; }
1496 static inline void intel_unregister_dsm_handler(void) { return; }
1497 #endif /* CONFIG_ACPI */
1500 extern void intel_modeset_init_hw(struct drm_device *dev);
1501 extern void intel_modeset_init(struct drm_device *dev);
1502 extern void intel_modeset_gem_init(struct drm_device *dev);
1503 extern void intel_modeset_cleanup(struct drm_device *dev);
1504 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1505 extern bool intel_fbc_enabled(struct drm_device *dev);
1506 extern void intel_disable_fbc(struct drm_device *dev);
1507 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1508 extern void ironlake_init_pch_refclk(struct drm_device *dev);
1509 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1510 extern void intel_detect_pch(struct drm_device *dev);
1511 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1512 extern int intel_enable_rc6(const struct drm_device *dev);
1514 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1515 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1516 struct drm_file *file);
1519 #ifdef CONFIG_DEBUG_FS
1520 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1521 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1523 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1524 extern void intel_display_print_error_state(struct seq_file *m,
1525 struct drm_device *dev,
1526 struct intel_display_error_state *error);
1529 /* On SNB platform, before reading ring registers forcewake bit
1530 * must be set to prevent GT core from power down and stale values being
1533 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1534 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1535 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1537 #define __i915_read(x, y) \
1538 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1546 #define __i915_write(x, y) \
1547 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1555 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1556 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1558 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1559 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1560 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1561 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1563 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1564 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1565 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1566 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1568 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1569 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1571 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1572 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)