1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include <linux/io-mapping.h>
37 /* General customization:
40 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
42 #define DRIVER_NAME "i915"
43 #define DRIVER_DESC "Intel Graphics"
44 #define DRIVER_DATE "20080730"
51 #define I915_NUM_PIPE 2
56 * 1.2: Add Power Management
57 * 1.3: Add vblank support
58 * 1.4: Fix cmdbuffer path, add heap destroy
59 * 1.5: Add vblank pipe configuration
60 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
61 * - Support vertical blank on secondary display pipe
63 #define DRIVER_MAJOR 1
64 #define DRIVER_MINOR 6
65 #define DRIVER_PATCHLEVEL 0
67 #define WATCH_COHERENCY 0
72 #define WATCH_INACTIVE 0
73 #define WATCH_PWRITE 0
75 #define I915_GEM_PHYS_CURSOR_0 1
76 #define I915_GEM_PHYS_CURSOR_1 2
77 #define I915_GEM_PHYS_OVERLAY_REGS 3
78 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
80 struct drm_i915_gem_phys_object {
82 struct page **page_list;
83 drm_dma_handle_t *handle;
84 struct drm_gem_object *cur_obj;
87 typedef struct _drm_i915_ring_buffer {
95 struct drm_gem_object *ring_obj;
96 } drm_i915_ring_buffer_t;
99 struct mem_block *next;
100 struct mem_block *prev;
103 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
106 struct opregion_header;
107 struct opregion_acpi;
108 struct opregion_swsci;
109 struct opregion_asle;
111 struct intel_opregion {
112 struct opregion_header *header;
113 struct opregion_acpi *acpi;
114 struct opregion_swsci *swsci;
115 struct opregion_asle *asle;
119 struct drm_i915_master_private {
120 drm_local_map_t *sarea;
121 struct _drm_i915_sarea *sarea_priv;
123 #define I915_FENCE_REG_NONE -1
125 struct drm_i915_fence_reg {
126 struct drm_gem_object *obj;
129 struct sdvo_device_mapping {
136 struct drm_i915_error_state {
152 typedef struct drm_i915_private {
153 struct drm_device *dev;
159 drm_i915_ring_buffer_t ring;
161 drm_dma_handle_t *status_page_dmah;
162 void *hw_status_page;
163 dma_addr_t dma_status_page;
165 unsigned int status_gfx_addr;
166 drm_local_map_t hws_map;
167 struct drm_gem_object *hws_obj;
169 struct resource mch_res;
177 wait_queue_head_t irq_queue;
178 atomic_t irq_received;
179 /** Protects user_irq_refcount and irq_mask_reg */
180 spinlock_t user_irq_lock;
181 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
182 int user_irq_refcount;
183 /** Cached value of IMR to avoid reads in updating the bitfield */
186 /** splitted irq regs for graphics and display engine on IGDNG,
187 irq_mask_reg is still used for display irq. */
189 u32 gt_irq_enable_reg;
190 u32 de_irq_enable_reg;
192 u32 hotplug_supported_mask;
193 struct work_struct hotplug_work;
195 int tex_lru_log_granularity;
196 int allow_batchbuffer;
197 struct mem_block *agp_heap;
198 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
201 bool cursor_needs_physical;
207 struct intel_opregion opregion;
210 int backlight_duty_cycle; /* restore backlight to this value */
211 bool panel_wants_dither;
212 struct drm_display_mode *panel_fixed_mode;
213 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
214 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
216 /* Feature bits from the VBIOS */
217 unsigned int int_tv_support:1;
218 unsigned int lvds_dither:1;
219 unsigned int lvds_vbt:1;
220 unsigned int int_crt_support:1;
221 unsigned int lvds_use_ssc:1;
222 unsigned int edp_support:1;
225 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
226 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
227 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
229 unsigned int fsb_freq, mem_freq;
231 spinlock_t error_lock;
232 struct drm_i915_error_state *first_error;
233 struct work_struct error_work;
240 u32 saveRENDERSTANDBY;
264 u32 savePFIT_PGM_RATIOS;
266 u32 saveBLC_PWM_CTL2;
291 u32 savePP_ON_DELAYS;
292 u32 savePP_OFF_DELAYS;
300 u32 savePFIT_CONTROL;
301 u32 save_palette_a[256];
302 u32 save_palette_b[256];
303 u32 saveFBC_CFB_BASE;
306 u32 saveFBC_CONTROL2;
310 u32 saveCACHE_MODE_0;
313 u32 saveMI_ARB_STATE;
324 uint64_t saveFENCE[16];
335 u32 savePIPEA_GMCH_DATA_M;
336 u32 savePIPEB_GMCH_DATA_M;
337 u32 savePIPEA_GMCH_DATA_N;
338 u32 savePIPEB_GMCH_DATA_N;
339 u32 savePIPEA_DP_LINK_M;
340 u32 savePIPEB_DP_LINK_M;
341 u32 savePIPEA_DP_LINK_N;
342 u32 savePIPEB_DP_LINK_N;
345 struct drm_mm gtt_space;
347 struct io_mapping *gtt_mapping;
351 * List of objects currently involved in rendering from the
354 * Includes buffers having the contents of their GPU caches
355 * flushed, not necessarily primitives. last_rendering_seqno
356 * represents when the rendering involved will be completed.
358 * A reference is held on the buffer while on this list.
360 spinlock_t active_list_lock;
361 struct list_head active_list;
364 * List of objects which are not in the ringbuffer but which
365 * still have a write_domain which needs to be flushed before
368 * last_rendering_seqno is 0 while an object is in this list.
370 * A reference is held on the buffer while on this list.
372 struct list_head flushing_list;
375 * LRU list of objects which are not in the ringbuffer and
376 * are ready to unbind, but are still in the GTT.
378 * last_rendering_seqno is 0 while an object is in this list.
380 * A reference is not held on the buffer while on this list,
381 * as merely being GTT-bound shouldn't prevent its being
382 * freed, and we'll pull it off the list in the free path.
384 struct list_head inactive_list;
387 * List of breadcrumbs associated with GPU requests currently
390 struct list_head request_list;
393 * We leave the user IRQ off as much as possible,
394 * but this means that requests will finish and never
395 * be retired once the system goes idle. Set a timer to
396 * fire periodically while the ring is running. When it
397 * fires, go retire requests.
399 struct delayed_work retire_work;
401 uint32_t next_gem_seqno;
404 * Waiting sequence number, if any
406 uint32_t waiting_gem_seqno;
409 * Last seq seen at irq time
411 uint32_t irq_gem_seqno;
414 * Flag if the X Server, and thus DRM, is not currently in
415 * control of the device.
417 * This is set between LeaveVT and EnterVT. It needs to be
418 * replaced with a semaphore. It also needs to be
419 * transitioned away from for kernel modesetting.
424 * Flag if the hardware appears to be wedged.
426 * This is set when attempts to idle the device timeout.
427 * It prevents command submission from occuring and makes
428 * every pending request fail
432 /** Bit 6 swizzling required for X tiling */
433 uint32_t bit_6_swizzle_x;
434 /** Bit 6 swizzling required for Y tiling */
435 uint32_t bit_6_swizzle_y;
437 /* storage for physical objects */
438 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
440 struct sdvo_device_mapping sdvo_mappings[2];
441 } drm_i915_private_t;
443 /** driver private structure attached to each drm_gem_object */
444 struct drm_i915_gem_object {
445 struct drm_gem_object *obj;
447 /** Current space allocated to this object in the GTT, if any. */
448 struct drm_mm_node *gtt_space;
450 /** This object's place on the active/flushing/inactive lists */
451 struct list_head list;
454 * This is set if the object is on the active or flushing lists
455 * (has pending rendering), and is not set if it's on inactive (ready
461 * This is set if the object has been written to since last bound
466 /** AGP memory structure for our GTT binding. */
467 DRM_AGP_MEM *agp_mem;
473 * Current offset of the object in GTT space.
475 * This is the same as gtt_space->start
479 * Required alignment for the object
481 uint32_t gtt_alignment;
483 * Fake offset for use by mmap(2)
485 uint64_t mmap_offset;
488 * Fence register bits (if any) for this object. Will be set
489 * as needed when mapped into the GTT.
490 * Protected by dev->struct_mutex.
494 /** How many users have pinned this object in GTT space */
497 /** Breadcrumb of last rendering to the buffer. */
498 uint32_t last_rendering_seqno;
500 /** Current tiling mode for the object. */
501 uint32_t tiling_mode;
504 /** Record of address bit 17 of each page at last unbind. */
507 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
511 * If present, while GEM_DOMAIN_CPU is in the read domain this array
512 * flags which individual pages are valid.
514 uint8_t *page_cpu_valid;
516 /** User space pin count and filp owning the pin */
517 uint32_t user_pin_count;
518 struct drm_file *pin_filp;
520 /** for phy allocated objects */
521 struct drm_i915_gem_phys_object *phys_obj;
524 * Used for checking the object doesn't appear more than once
525 * in an execbuffer object list.
531 * Request queue structure.
533 * The request queue allows us to note sequence numbers that have been emitted
534 * and may be associated with active buffers to be retired.
536 * By keeping this list, we can avoid having to do questionable
537 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
538 * an emission time with seqnos for tracking how far ahead of the GPU we are.
540 struct drm_i915_gem_request {
541 /** GEM sequence number associated with this request. */
544 /** Time at which this request was emitted, in jiffies. */
545 unsigned long emitted_jiffies;
547 /** global list entry for this request */
548 struct list_head list;
550 /** file_priv list entry for this request */
551 struct list_head client_list;
554 struct drm_i915_file_private {
556 struct list_head request_list;
560 enum intel_chip_family {
567 extern struct drm_ioctl_desc i915_ioctls[];
568 extern int i915_max_ioctl;
569 extern unsigned int i915_fbpercrtc;
571 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
572 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
575 extern void i915_kernel_lost_context(struct drm_device * dev);
576 extern int i915_driver_load(struct drm_device *, unsigned long flags);
577 extern int i915_driver_unload(struct drm_device *);
578 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
579 extern void i915_driver_lastclose(struct drm_device * dev);
580 extern void i915_driver_preclose(struct drm_device *dev,
581 struct drm_file *file_priv);
582 extern void i915_driver_postclose(struct drm_device *dev,
583 struct drm_file *file_priv);
584 extern int i915_driver_device_is_agp(struct drm_device * dev);
585 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
587 extern int i915_emit_box(struct drm_device *dev,
588 struct drm_clip_rect *boxes,
589 int i, int DR1, int DR4);
592 extern int i915_irq_emit(struct drm_device *dev, void *data,
593 struct drm_file *file_priv);
594 extern int i915_irq_wait(struct drm_device *dev, void *data,
595 struct drm_file *file_priv);
596 void i915_user_irq_get(struct drm_device *dev);
597 void i915_user_irq_put(struct drm_device *dev);
598 extern void i915_enable_interrupt (struct drm_device *dev);
600 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
601 extern void i915_driver_irq_preinstall(struct drm_device * dev);
602 extern int i915_driver_irq_postinstall(struct drm_device *dev);
603 extern void i915_driver_irq_uninstall(struct drm_device * dev);
604 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
605 struct drm_file *file_priv);
606 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
607 struct drm_file *file_priv);
608 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
609 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
610 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
611 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
612 extern int i915_vblank_swap(struct drm_device *dev, void *data,
613 struct drm_file *file_priv);
614 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
617 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
620 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
624 extern int i915_mem_alloc(struct drm_device *dev, void *data,
625 struct drm_file *file_priv);
626 extern int i915_mem_free(struct drm_device *dev, void *data,
627 struct drm_file *file_priv);
628 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
629 struct drm_file *file_priv);
630 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
631 struct drm_file *file_priv);
632 extern void i915_mem_takedown(struct mem_block **heap);
633 extern void i915_mem_release(struct drm_device * dev,
634 struct drm_file *file_priv, struct mem_block *heap);
636 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
637 struct drm_file *file_priv);
638 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
639 struct drm_file *file_priv);
640 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
641 struct drm_file *file_priv);
642 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
643 struct drm_file *file_priv);
644 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
645 struct drm_file *file_priv);
646 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
647 struct drm_file *file_priv);
648 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
649 struct drm_file *file_priv);
650 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
651 struct drm_file *file_priv);
652 int i915_gem_execbuffer(struct drm_device *dev, void *data,
653 struct drm_file *file_priv);
654 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
655 struct drm_file *file_priv);
656 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
657 struct drm_file *file_priv);
658 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
659 struct drm_file *file_priv);
660 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
661 struct drm_file *file_priv);
662 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
663 struct drm_file *file_priv);
664 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
665 struct drm_file *file_priv);
666 int i915_gem_set_tiling(struct drm_device *dev, void *data,
667 struct drm_file *file_priv);
668 int i915_gem_get_tiling(struct drm_device *dev, void *data,
669 struct drm_file *file_priv);
670 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
671 struct drm_file *file_priv);
672 void i915_gem_load(struct drm_device *dev);
673 int i915_gem_init_object(struct drm_gem_object *obj);
674 void i915_gem_free_object(struct drm_gem_object *obj);
675 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
676 void i915_gem_object_unpin(struct drm_gem_object *obj);
677 int i915_gem_object_unbind(struct drm_gem_object *obj);
678 void i915_gem_release_mmap(struct drm_gem_object *obj);
679 void i915_gem_lastclose(struct drm_device *dev);
680 uint32_t i915_get_gem_seqno(struct drm_device *dev);
681 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
682 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
683 void i915_gem_retire_requests(struct drm_device *dev);
684 void i915_gem_retire_work_handler(struct work_struct *work);
685 void i915_gem_clflush_object(struct drm_gem_object *obj);
686 int i915_gem_object_set_domain(struct drm_gem_object *obj,
687 uint32_t read_domains,
688 uint32_t write_domain);
689 int i915_gem_init_ringbuffer(struct drm_device *dev);
690 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
691 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
693 int i915_gem_idle(struct drm_device *dev);
694 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
695 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
697 int i915_gem_attach_phys_object(struct drm_device *dev,
698 struct drm_gem_object *obj, int id);
699 void i915_gem_detach_phys_object(struct drm_device *dev,
700 struct drm_gem_object *obj);
701 void i915_gem_free_all_phys_object(struct drm_device *dev);
702 int i915_gem_object_get_pages(struct drm_gem_object *obj);
703 void i915_gem_object_put_pages(struct drm_gem_object *obj);
704 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
706 /* i915_gem_tiling.c */
707 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
708 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
709 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
711 /* i915_gem_debug.c */
712 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
713 const char *where, uint32_t mark);
715 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
717 #define i915_verify_inactive(dev, file, line)
719 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
720 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
721 const char *where, uint32_t mark);
722 void i915_dump_lru(struct drm_device *dev, const char *where);
725 int i915_gem_debugfs_init(struct drm_minor *minor);
726 void i915_gem_debugfs_cleanup(struct drm_minor *minor);
729 extern int i915_save_state(struct drm_device *dev);
730 extern int i915_restore_state(struct drm_device *dev);
733 extern int i915_save_state(struct drm_device *dev);
734 extern int i915_restore_state(struct drm_device *dev);
737 /* i915_opregion.c */
738 extern int intel_opregion_init(struct drm_device *dev, int resume);
739 extern void intel_opregion_free(struct drm_device *dev, int suspend);
740 extern void opregion_asle_intr(struct drm_device *dev);
741 extern void opregion_enable_asle(struct drm_device *dev);
743 static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
744 static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
745 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
746 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
750 extern void intel_modeset_init(struct drm_device *dev);
751 extern void intel_modeset_cleanup(struct drm_device *dev);
754 * Lock test for when it's just for synchronization of ring access.
756 * In that case, we don't need to do it when GEM is initialized as nobody else
757 * has access to the ring.
759 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
760 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
761 LOCK_TEST_WITH_RETURN(dev, file_priv); \
764 #define I915_READ(reg) readl(dev_priv->regs + (reg))
765 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
766 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
767 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
768 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
769 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
770 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
771 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
772 #define POSTING_READ(reg) (void)I915_READ(reg)
774 #define I915_VERBOSE 0
776 #define RING_LOCALS unsigned int outring, ringmask, outcount; \
779 #define BEGIN_LP_RING(n) do { \
781 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
782 if (dev_priv->ring.space < (n)*4) \
783 i915_wait_ring(dev, (n)*4, __func__); \
785 outring = dev_priv->ring.tail; \
786 ringmask = dev_priv->ring.tail_mask; \
787 virt = dev_priv->ring.virtual_start; \
790 #define OUT_RING(n) do { \
791 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
792 *(volatile unsigned int *)(virt + outring) = (n); \
795 outring &= ringmask; \
798 #define ADVANCE_LP_RING() do { \
799 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
800 dev_priv->ring.tail = outring; \
801 dev_priv->ring.space -= outcount * 4; \
802 I915_WRITE(PRB0_TAIL, outring); \
806 * Reads a dword out of the status page, which is written to from the command
807 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
810 * The following dwords have a reserved meaning:
811 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
812 * 0x04: ring 0 head pointer
813 * 0x05: ring 1 head pointer (915-class)
814 * 0x06: ring 2 head pointer (915-class)
815 * 0x10-0x1b: Context status DWords (GM45)
816 * 0x1f: Last written status offset. (GM45)
818 * The area from dword 0x20 to 0x3ff is available for driver usage.
820 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
821 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
822 #define I915_GEM_HWS_INDEX 0x20
823 #define I915_BREADCRUMB_INDEX 0x21
825 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
827 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
828 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
829 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
830 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
831 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
833 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
834 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
835 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
836 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
837 (dev)->pci_device == 0x27AE)
838 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
839 (dev)->pci_device == 0x2982 || \
840 (dev)->pci_device == 0x2992 || \
841 (dev)->pci_device == 0x29A2 || \
842 (dev)->pci_device == 0x2A02 || \
843 (dev)->pci_device == 0x2A12 || \
844 (dev)->pci_device == 0x2A42 || \
845 (dev)->pci_device == 0x2E02 || \
846 (dev)->pci_device == 0x2E12 || \
847 (dev)->pci_device == 0x2E22 || \
848 (dev)->pci_device == 0x2E32 || \
849 (dev)->pci_device == 0x0042 || \
850 (dev)->pci_device == 0x0046)
852 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
853 (dev)->pci_device == 0x2A12)
855 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
857 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
858 (dev)->pci_device == 0x2E12 || \
859 (dev)->pci_device == 0x2E22 || \
860 (dev)->pci_device == 0x2E32 || \
863 #define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
864 #define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)
865 #define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))
867 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
868 (dev)->pci_device == 0x29B2 || \
869 (dev)->pci_device == 0x29D2 || \
872 #define IS_IGDNG_D(dev) ((dev)->pci_device == 0x0042)
873 #define IS_IGDNG_M(dev) ((dev)->pci_device == 0x0046)
874 #define IS_IGDNG(dev) (IS_IGDNG_D(dev) || IS_IGDNG_M(dev))
876 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
877 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
880 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
881 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
882 IS_IGD(dev) || IS_IGDNG_M(dev))
884 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
886 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
887 * rows, which changed the alignment requirements and fence programming.
889 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
891 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev))
892 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IGDNG(dev))
893 #define SUPPORTS_EDP(dev) (IS_IGDNG_M(dev))
894 #define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_I965G(dev))
895 /* dsparb controlled by hw only */
896 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev))
898 #define PRIMARY_RINGBUFFER_SIZE (128*1024)