1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
38 /* General customization:
41 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
43 #define DRIVER_NAME "i915"
44 #define DRIVER_DESC "Intel Graphics"
45 #define DRIVER_DATE "20080730"
57 #define I915_NUM_PIPE 2
59 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
64 * 1.2: Add Power Management
65 * 1.3: Add vblank support
66 * 1.4: Fix cmdbuffer path, add heap destroy
67 * 1.5: Add vblank pipe configuration
68 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
69 * - Support vertical blank on secondary display pipe
71 #define DRIVER_MAJOR 1
72 #define DRIVER_MINOR 6
73 #define DRIVER_PATCHLEVEL 0
75 #define WATCH_COHERENCY 0
80 #define WATCH_INACTIVE 0
81 #define WATCH_PWRITE 0
83 #define I915_GEM_PHYS_CURSOR_0 1
84 #define I915_GEM_PHYS_CURSOR_1 2
85 #define I915_GEM_PHYS_OVERLAY_REGS 3
86 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
88 struct drm_i915_gem_phys_object {
90 struct page **page_list;
91 drm_dma_handle_t *handle;
92 struct drm_gem_object *cur_obj;
96 struct mem_block *next;
97 struct mem_block *prev;
100 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
103 struct opregion_header;
104 struct opregion_acpi;
105 struct opregion_swsci;
106 struct opregion_asle;
108 struct intel_opregion {
109 struct opregion_header *header;
110 struct opregion_acpi *acpi;
111 struct opregion_swsci *swsci;
112 struct opregion_asle *asle;
116 struct drm_i915_master_private {
117 drm_local_map_t *sarea;
118 struct _drm_i915_sarea *sarea_priv;
120 #define I915_FENCE_REG_NONE -1
122 struct drm_i915_fence_reg {
123 struct drm_gem_object *obj;
124 struct list_head lru_list;
127 struct sdvo_device_mapping {
135 struct drm_i915_error_state {
150 struct drm_i915_error_object {
154 } *ringbuffer, *batchbuffer[2];
155 struct drm_i915_error_buffer {
171 struct drm_i915_display_funcs {
172 void (*dpms)(struct drm_crtc *crtc, int mode);
173 bool (*fbc_enabled)(struct drm_device *dev);
174 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
175 void (*disable_fbc)(struct drm_device *dev);
176 int (*get_display_clock_speed)(struct drm_device *dev);
177 int (*get_fifo_size)(struct drm_device *dev, int plane);
178 void (*update_wm)(struct drm_device *dev, int planea_clock,
179 int planeb_clock, int sr_hdisplay, int pixel_size);
180 /* clock updates for mode set */
182 /* render clock increase/decrease */
183 /* display clock increase/decrease */
184 /* pll clock increase/decrease */
185 /* clock gating init */
188 struct intel_overlay;
190 struct intel_device_info {
207 u8 has_pipe_cxsr : 1;
209 u8 cursor_needs_physical : 1;
213 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
214 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
215 FBC_MODE_TOO_LARGE, /* mode too large for compression */
216 FBC_BAD_PLANE, /* fbc not supported on plane */
217 FBC_NOT_TILED, /* buffer not tiled */
218 FBC_MULTIPLE_PIPES, /* more than one pipe active */
222 PCH_IBX, /* Ibexpeak PCH */
223 PCH_CPT, /* Cougarpoint PCH */
228 typedef struct drm_i915_private {
229 struct drm_device *dev;
231 const struct intel_device_info *info;
237 struct pci_dev *bridge_dev;
238 struct intel_ring_buffer render_ring;
239 struct intel_ring_buffer bsd_ring;
241 drm_dma_handle_t *status_page_dmah;
243 dma_addr_t dma_status_page;
245 unsigned int seqno_gfx_addr;
246 drm_local_map_t hws_map;
247 struct drm_gem_object *seqno_obj;
248 struct drm_gem_object *pwrctx;
250 struct resource mch_res;
258 wait_queue_head_t irq_queue;
259 atomic_t irq_received;
260 /** Protects user_irq_refcount and irq_mask_reg */
261 spinlock_t user_irq_lock;
263 /** Cached value of IMR to avoid reads in updating the bitfield */
266 /** splitted irq regs for graphics and display engine on Ironlake,
267 irq_mask_reg is still used for display irq. */
269 u32 gt_irq_enable_reg;
270 u32 de_irq_enable_reg;
271 u32 pch_irq_mask_reg;
272 u32 pch_irq_enable_reg;
274 u32 hotplug_supported_mask;
275 struct work_struct hotplug_work;
277 int tex_lru_log_granularity;
278 int allow_batchbuffer;
279 struct mem_block *agp_heap;
280 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
284 /* For hangcheck timer */
285 #define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */
286 struct timer_list hangcheck_timer;
292 unsigned long cfb_size;
293 unsigned long cfb_pitch;
299 struct intel_opregion opregion;
302 struct intel_overlay *overlay;
305 int backlight_duty_cycle; /* restore backlight to this value */
306 bool panel_wants_dither;
307 struct drm_display_mode *panel_fixed_mode;
308 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
309 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
311 /* Feature bits from the VBIOS */
312 unsigned int int_tv_support:1;
313 unsigned int lvds_dither:1;
314 unsigned int lvds_vbt:1;
315 unsigned int int_crt_support:1;
316 unsigned int lvds_use_ssc:1;
317 unsigned int edp_support:1;
321 struct notifier_block lid_notifier;
323 int crt_ddc_bus; /* 0 = unknown, else GPIO to use for CRT DDC */
324 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
325 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
326 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
328 unsigned int fsb_freq, mem_freq, is_ddr3;
330 spinlock_t error_lock;
331 struct drm_i915_error_state *first_error;
332 struct work_struct error_work;
333 struct workqueue_struct *wq;
335 /* Display functions */
336 struct drm_i915_display_funcs display;
338 /* PCH chipset type */
339 enum intel_pch pch_type;
364 u32 saveTRANS_HTOTAL_A;
365 u32 saveTRANS_HBLANK_A;
366 u32 saveTRANS_HSYNC_A;
367 u32 saveTRANS_VTOTAL_A;
368 u32 saveTRANS_VBLANK_A;
369 u32 saveTRANS_VSYNC_A;
377 u32 savePFIT_PGM_RATIOS;
378 u32 saveBLC_HIST_CTL;
380 u32 saveBLC_PWM_CTL2;
381 u32 saveBLC_CPU_PWM_CTL;
382 u32 saveBLC_CPU_PWM_CTL2;
395 u32 saveTRANS_HTOTAL_B;
396 u32 saveTRANS_HBLANK_B;
397 u32 saveTRANS_HSYNC_B;
398 u32 saveTRANS_VTOTAL_B;
399 u32 saveTRANS_VBLANK_B;
400 u32 saveTRANS_VSYNC_B;
414 u32 savePP_ON_DELAYS;
415 u32 savePP_OFF_DELAYS;
423 u32 savePFIT_CONTROL;
424 u32 save_palette_a[256];
425 u32 save_palette_b[256];
426 u32 saveDPFC_CB_BASE;
427 u32 saveFBC_CFB_BASE;
430 u32 saveFBC_CONTROL2;
440 u32 saveCACHE_MODE_0;
441 u32 saveMI_ARB_STATE;
452 uint64_t saveFENCE[16];
463 u32 savePIPEA_GMCH_DATA_M;
464 u32 savePIPEB_GMCH_DATA_M;
465 u32 savePIPEA_GMCH_DATA_N;
466 u32 savePIPEB_GMCH_DATA_N;
467 u32 savePIPEA_DP_LINK_M;
468 u32 savePIPEB_DP_LINK_M;
469 u32 savePIPEA_DP_LINK_N;
470 u32 savePIPEB_DP_LINK_N;
481 u32 savePCH_DREF_CONTROL;
482 u32 saveDISP_ARB_CTL;
483 u32 savePIPEA_DATA_M1;
484 u32 savePIPEA_DATA_N1;
485 u32 savePIPEA_LINK_M1;
486 u32 savePIPEA_LINK_N1;
487 u32 savePIPEB_DATA_M1;
488 u32 savePIPEB_DATA_N1;
489 u32 savePIPEB_LINK_M1;
490 u32 savePIPEB_LINK_N1;
491 u32 saveMCHBAR_RENDER_STANDBY;
494 struct drm_mm gtt_space;
496 struct io_mapping *gtt_mapping;
500 * Membership on list of all loaded devices, used to evict
501 * inactive buffers under memory pressure.
503 * Modifications should only be done whilst holding the
504 * shrink_list_lock spinlock.
506 struct list_head shrink_list;
508 spinlock_t active_list_lock;
511 * List of objects which are not in the ringbuffer but which
512 * still have a write_domain which needs to be flushed before
515 * last_rendering_seqno is 0 while an object is in this list.
517 * A reference is held on the buffer while on this list.
519 struct list_head flushing_list;
522 * List of objects currently pending a GPU write flush.
524 * All elements on this list will belong to either the
525 * active_list or flushing_list, last_rendering_seqno can
526 * be used to differentiate between the two elements.
528 struct list_head gpu_write_list;
531 * LRU list of objects which are not in the ringbuffer and
532 * are ready to unbind, but are still in the GTT.
534 * last_rendering_seqno is 0 while an object is in this list.
536 * A reference is not held on the buffer while on this list,
537 * as merely being GTT-bound shouldn't prevent its being
538 * freed, and we'll pull it off the list in the free path.
540 struct list_head inactive_list;
542 /** LRU list of objects with fence regs on them. */
543 struct list_head fence_list;
546 * We leave the user IRQ off as much as possible,
547 * but this means that requests will finish and never
548 * be retired once the system goes idle. Set a timer to
549 * fire periodically while the ring is running. When it
550 * fires, go retire requests.
552 struct delayed_work retire_work;
554 uint32_t next_gem_seqno;
557 * Waiting sequence number, if any
559 uint32_t waiting_gem_seqno;
562 * Last seq seen at irq time
564 uint32_t irq_gem_seqno;
567 * Flag if the X Server, and thus DRM, is not currently in
568 * control of the device.
570 * This is set between LeaveVT and EnterVT. It needs to be
571 * replaced with a semaphore. It also needs to be
572 * transitioned away from for kernel modesetting.
577 * Flag if the hardware appears to be wedged.
579 * This is set when attempts to idle the device timeout.
580 * It prevents command submission from occuring and makes
581 * every pending request fail
585 /** Bit 6 swizzling required for X tiling */
586 uint32_t bit_6_swizzle_x;
587 /** Bit 6 swizzling required for Y tiling */
588 uint32_t bit_6_swizzle_y;
590 /* storage for physical objects */
591 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
593 struct sdvo_device_mapping sdvo_mappings[2];
594 /* indicate whether the LVDS_BORDER should be enabled or not */
595 unsigned int lvds_border_bits;
597 struct drm_crtc *plane_to_crtc_mapping[2];
598 struct drm_crtc *pipe_to_crtc_mapping[2];
599 wait_queue_head_t pending_flip_queue;
600 bool flip_pending_is_done;
602 /* Reclocking support */
603 bool render_reclock_avail;
604 bool lvds_downclock_avail;
605 /* indicate whether the LVDS EDID is OK */
607 /* indicates the reduced downclock for LVDS*/
609 struct work_struct idle_work;
610 struct timer_list idle_timer;
614 struct child_device_config *child_dev;
615 struct drm_connector *int_lvds_connector;
617 bool mchbar_need_disable;
626 unsigned long last_time1;
628 struct timespec last_time2;
629 unsigned long gfx_power;
633 spinlock_t *mchdev_lock;
635 enum no_fbc_reason no_fbc_reason;
637 struct drm_mm_node *compressed_fb;
638 struct drm_mm_node *compressed_llb;
640 /* list of fbdev register on this device */
641 struct intel_fbdev *fbdev;
642 } drm_i915_private_t;
644 /** driver private structure attached to each drm_gem_object */
645 struct drm_i915_gem_object {
646 struct drm_gem_object base;
648 /** Current space allocated to this object in the GTT, if any. */
649 struct drm_mm_node *gtt_space;
651 /** This object's place on the active/flushing/inactive lists */
652 struct list_head list;
653 /** This object's place on GPU write list */
654 struct list_head gpu_write_list;
657 * This is set if the object is on the active or flushing lists
658 * (has pending rendering), and is not set if it's on inactive (ready
661 unsigned int active : 1;
664 * This is set if the object has been written to since last bound
667 unsigned int dirty : 1;
670 * Fence register bits (if any) for this object. Will be set
671 * as needed when mapped into the GTT.
672 * Protected by dev->struct_mutex.
674 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
679 * Used for checking the object doesn't appear more than once
680 * in an execbuffer object list.
682 unsigned int in_execbuffer : 1;
685 * Advice: are the backing pages purgeable?
687 unsigned int madv : 2;
690 * Refcount for the pages array. With the current locking scheme, there
691 * are at most two concurrent users: Binding a bo to the gtt and
692 * pwrite/pread using physical addresses. So two bits for a maximum
693 * of two users are enough.
695 unsigned int pages_refcount : 2;
696 #define DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT 0x3
699 * Current tiling mode for the object.
701 unsigned int tiling_mode : 2;
703 /** How many users have pinned this object in GTT space. The following
704 * users can each hold at most one reference: pwrite/pread, pin_ioctl
705 * (via user_pin_count), execbuffer (objects are not allowed multiple
706 * times for the same batchbuffer), and the framebuffer code. When
707 * switching/pageflipping, the framebuffer code has at most two buffers
710 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
711 * bits with absolutely no headroom. So use 4 bits. */
713 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
715 /** AGP memory structure for our GTT binding. */
716 DRM_AGP_MEM *agp_mem;
721 * Current offset of the object in GTT space.
723 * This is the same as gtt_space->start
727 /* Which ring is refering to is this object */
728 struct intel_ring_buffer *ring;
731 * Fake offset for use by mmap(2)
733 uint64_t mmap_offset;
735 /** Breadcrumb of last rendering to the buffer. */
736 uint32_t last_rendering_seqno;
738 /** Current tiling stride for the object, if it's tiled. */
741 /** Record of address bit 17 of each page at last unbind. */
744 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
748 * If present, while GEM_DOMAIN_CPU is in the read domain this array
749 * flags which individual pages are valid.
751 uint8_t *page_cpu_valid;
753 /** User space pin count and filp owning the pin */
754 uint32_t user_pin_count;
755 struct drm_file *pin_filp;
757 /** for phy allocated objects */
758 struct drm_i915_gem_phys_object *phys_obj;
761 * Number of crtcs where this object is currently the fb, but
762 * will be page flipped away on the next vblank. When it
763 * reaches 0, dev_priv->pending_flip_queue will be woken up.
765 atomic_t pending_flip;
768 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
771 * Request queue structure.
773 * The request queue allows us to note sequence numbers that have been emitted
774 * and may be associated with active buffers to be retired.
776 * By keeping this list, we can avoid having to do questionable
777 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
778 * an emission time with seqnos for tracking how far ahead of the GPU we are.
780 struct drm_i915_gem_request {
781 /** On Which ring this request was generated */
782 struct intel_ring_buffer *ring;
784 /** GEM sequence number associated with this request. */
787 /** Time at which this request was emitted, in jiffies. */
788 unsigned long emitted_jiffies;
790 /** global list entry for this request */
791 struct list_head list;
793 /** file_priv list entry for this request */
794 struct list_head client_list;
797 struct drm_i915_file_private {
799 struct list_head request_list;
803 enum intel_chip_family {
810 extern struct drm_ioctl_desc i915_ioctls[];
811 extern int i915_max_ioctl;
812 extern unsigned int i915_fbpercrtc;
813 extern unsigned int i915_powersave;
814 extern unsigned int i915_lvds_downclock;
816 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
817 extern int i915_resume(struct drm_device *dev);
818 extern void i915_save_display(struct drm_device *dev);
819 extern void i915_restore_display(struct drm_device *dev);
820 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
821 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
824 extern void i915_kernel_lost_context(struct drm_device * dev);
825 extern int i915_driver_load(struct drm_device *, unsigned long flags);
826 extern int i915_driver_unload(struct drm_device *);
827 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
828 extern void i915_driver_lastclose(struct drm_device * dev);
829 extern void i915_driver_preclose(struct drm_device *dev,
830 struct drm_file *file_priv);
831 extern void i915_driver_postclose(struct drm_device *dev,
832 struct drm_file *file_priv);
833 extern int i915_driver_device_is_agp(struct drm_device * dev);
834 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
836 extern int i915_emit_box(struct drm_device *dev,
837 struct drm_clip_rect *boxes,
838 int i, int DR1, int DR4);
839 extern int i965_reset(struct drm_device *dev, u8 flags);
840 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
841 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
842 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
843 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
847 void i915_hangcheck_elapsed(unsigned long data);
848 void i915_destroy_error_state(struct drm_device *dev);
849 extern int i915_irq_emit(struct drm_device *dev, void *data,
850 struct drm_file *file_priv);
851 extern int i915_irq_wait(struct drm_device *dev, void *data,
852 struct drm_file *file_priv);
853 void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
854 extern void i915_enable_interrupt (struct drm_device *dev);
856 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
857 extern void i915_driver_irq_preinstall(struct drm_device * dev);
858 extern int i915_driver_irq_postinstall(struct drm_device *dev);
859 extern void i915_driver_irq_uninstall(struct drm_device * dev);
860 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
861 struct drm_file *file_priv);
862 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
863 struct drm_file *file_priv);
864 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
865 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
866 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
867 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
868 extern int i915_vblank_swap(struct drm_device *dev, void *data,
869 struct drm_file *file_priv);
870 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
871 extern void i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask);
872 extern void ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv,
874 extern void ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv,
878 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
881 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
883 void intel_enable_asle (struct drm_device *dev);
887 extern int i915_mem_alloc(struct drm_device *dev, void *data,
888 struct drm_file *file_priv);
889 extern int i915_mem_free(struct drm_device *dev, void *data,
890 struct drm_file *file_priv);
891 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
892 struct drm_file *file_priv);
893 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
894 struct drm_file *file_priv);
895 extern void i915_mem_takedown(struct mem_block **heap);
896 extern void i915_mem_release(struct drm_device * dev,
897 struct drm_file *file_priv, struct mem_block *heap);
899 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
900 struct drm_file *file_priv);
901 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
902 struct drm_file *file_priv);
903 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
904 struct drm_file *file_priv);
905 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
906 struct drm_file *file_priv);
907 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
908 struct drm_file *file_priv);
909 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
910 struct drm_file *file_priv);
911 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
912 struct drm_file *file_priv);
913 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
914 struct drm_file *file_priv);
915 int i915_gem_execbuffer(struct drm_device *dev, void *data,
916 struct drm_file *file_priv);
917 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
918 struct drm_file *file_priv);
919 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
920 struct drm_file *file_priv);
921 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
922 struct drm_file *file_priv);
923 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
924 struct drm_file *file_priv);
925 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
926 struct drm_file *file_priv);
927 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
928 struct drm_file *file_priv);
929 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
930 struct drm_file *file_priv);
931 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
932 struct drm_file *file_priv);
933 int i915_gem_set_tiling(struct drm_device *dev, void *data,
934 struct drm_file *file_priv);
935 int i915_gem_get_tiling(struct drm_device *dev, void *data,
936 struct drm_file *file_priv);
937 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
938 struct drm_file *file_priv);
939 void i915_gem_load(struct drm_device *dev);
940 int i915_gem_init_object(struct drm_gem_object *obj);
941 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
943 void i915_gem_free_object(struct drm_gem_object *obj);
944 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
945 void i915_gem_object_unpin(struct drm_gem_object *obj);
946 int i915_gem_object_unbind(struct drm_gem_object *obj);
947 void i915_gem_release_mmap(struct drm_gem_object *obj);
948 void i915_gem_lastclose(struct drm_device *dev);
949 uint32_t i915_get_gem_seqno(struct drm_device *dev,
950 struct intel_ring_buffer *ring);
951 bool i915_seqno_passed(uint32_t seq1, uint32_t seq2);
952 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
953 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
954 void i915_gem_retire_requests(struct drm_device *dev,
955 struct intel_ring_buffer *ring);
956 void i915_gem_retire_work_handler(struct work_struct *work);
957 void i915_gem_clflush_object(struct drm_gem_object *obj);
958 int i915_gem_object_set_domain(struct drm_gem_object *obj,
959 uint32_t read_domains,
960 uint32_t write_domain);
961 int i915_gem_init_ringbuffer(struct drm_device *dev);
962 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
963 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
965 int i915_gem_idle(struct drm_device *dev);
966 uint32_t i915_add_request(struct drm_device *dev,
967 struct drm_file *file_priv,
968 uint32_t flush_domains,
969 struct intel_ring_buffer *ring);
970 int i915_do_wait_request(struct drm_device *dev,
971 uint32_t seqno, int interruptible,
972 struct intel_ring_buffer *ring);
973 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
974 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
976 int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj);
977 int i915_gem_attach_phys_object(struct drm_device *dev,
978 struct drm_gem_object *obj, int id);
979 void i915_gem_detach_phys_object(struct drm_device *dev,
980 struct drm_gem_object *obj);
981 void i915_gem_free_all_phys_object(struct drm_device *dev);
982 int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask);
983 void i915_gem_object_put_pages(struct drm_gem_object *obj);
984 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
985 void i915_gem_object_flush_write_domain(struct drm_gem_object *obj);
987 void i915_gem_shrinker_init(void);
988 void i915_gem_shrinker_exit(void);
990 /* i915_gem_tiling.c */
991 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
992 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
993 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
994 bool i915_tiling_ok(struct drm_device *dev, int stride, int size,
996 bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj,
999 /* i915_gem_debug.c */
1000 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
1001 const char *where, uint32_t mark);
1003 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
1005 #define i915_verify_inactive(dev, file, line)
1007 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
1008 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
1009 const char *where, uint32_t mark);
1010 void i915_dump_lru(struct drm_device *dev, const char *where);
1012 /* i915_debugfs.c */
1013 int i915_debugfs_init(struct drm_minor *minor);
1014 void i915_debugfs_cleanup(struct drm_minor *minor);
1016 /* i915_suspend.c */
1017 extern int i915_save_state(struct drm_device *dev);
1018 extern int i915_restore_state(struct drm_device *dev);
1020 /* i915_suspend.c */
1021 extern int i915_save_state(struct drm_device *dev);
1022 extern int i915_restore_state(struct drm_device *dev);
1025 /* i915_opregion.c */
1026 extern int intel_opregion_init(struct drm_device *dev, int resume);
1027 extern void intel_opregion_free(struct drm_device *dev, int suspend);
1028 extern void opregion_asle_intr(struct drm_device *dev);
1029 extern void ironlake_opregion_gse_intr(struct drm_device *dev);
1030 extern void opregion_enable_asle(struct drm_device *dev);
1032 static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
1033 static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
1034 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
1035 static inline void ironlake_opregion_gse_intr(struct drm_device *dev) { return; }
1036 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
1040 extern void intel_modeset_init(struct drm_device *dev);
1041 extern void intel_modeset_cleanup(struct drm_device *dev);
1042 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1043 extern void i8xx_disable_fbc(struct drm_device *dev);
1044 extern void g4x_disable_fbc(struct drm_device *dev);
1045 extern void intel_disable_fbc(struct drm_device *dev);
1046 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
1047 extern bool intel_fbc_enabled(struct drm_device *dev);
1048 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1049 extern void intel_detect_pch (struct drm_device *dev);
1050 extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1053 * Lock test for when it's just for synchronization of ring access.
1055 * In that case, we don't need to do it when GEM is initialized as nobody else
1056 * has access to the ring.
1058 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
1059 if (((drm_i915_private_t *)dev->dev_private)->render_ring.gem_object \
1061 LOCK_TEST_WITH_RETURN(dev, file_priv); \
1064 #define I915_READ(reg) readl(dev_priv->regs + (reg))
1065 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
1066 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
1067 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
1068 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
1069 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
1070 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
1071 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
1072 #define POSTING_READ(reg) (void)I915_READ(reg)
1073 #define POSTING_READ16(reg) (void)I915_READ16(reg)
1075 #define I915_VERBOSE 0
1077 #define BEGIN_LP_RING(n) do { \
1078 drm_i915_private_t *dev_priv = dev->dev_private; \
1080 DRM_DEBUG(" BEGIN_LP_RING %x\n", (int)(n)); \
1081 intel_ring_begin(dev, &dev_priv->render_ring, (n)); \
1085 #define OUT_RING(x) do { \
1086 drm_i915_private_t *dev_priv = dev->dev_private; \
1088 DRM_DEBUG(" OUT_RING %x\n", (int)(x)); \
1089 intel_ring_emit(dev, &dev_priv->render_ring, x); \
1092 #define ADVANCE_LP_RING() do { \
1093 drm_i915_private_t *dev_priv = dev->dev_private; \
1095 DRM_DEBUG("ADVANCE_LP_RING %x\n", \
1096 dev_priv->render_ring.tail); \
1097 intel_ring_advance(dev, &dev_priv->render_ring); \
1101 * Reads a dword out of the status page, which is written to from the command
1102 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
1103 * MI_STORE_DATA_IMM.
1105 * The following dwords have a reserved meaning:
1106 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
1107 * 0x04: ring 0 head pointer
1108 * 0x05: ring 1 head pointer (915-class)
1109 * 0x06: ring 2 head pointer (915-class)
1110 * 0x10-0x1b: Context status DWords (GM45)
1111 * 0x1f: Last written status offset. (GM45)
1113 * The area from dword 0x20 to 0x3ff is available for driver usage.
1115 #define READ_HWSP(dev_priv, reg) (((volatile u32 *)\
1116 (dev_priv->render_ring.status_page.page_addr))[reg])
1117 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1118 #define I915_GEM_HWS_INDEX 0x20
1119 #define I915_BREADCRUMB_INDEX 0x21
1121 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1123 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1124 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1125 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1126 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1127 #define IS_GEN2(dev) (INTEL_INFO(dev)->is_i8xx)
1128 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1129 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1130 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1131 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1132 #define IS_I965G(dev) (INTEL_INFO(dev)->is_i965g)
1133 #define IS_I965GM(dev) (INTEL_INFO(dev)->is_i965gm)
1134 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1135 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1136 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1137 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1138 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1139 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1140 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1141 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1142 #define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake)
1143 #define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx)
1144 #define IS_GEN6(dev) (INTEL_INFO(dev)->is_gen6)
1145 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1147 #define IS_GEN3(dev) (IS_I915G(dev) || \
1153 #define IS_GEN4(dev) ((dev)->pci_device == 0x2972 || \
1154 (dev)->pci_device == 0x2982 || \
1155 (dev)->pci_device == 0x2992 || \
1156 (dev)->pci_device == 0x29A2 || \
1157 (dev)->pci_device == 0x2A02 || \
1158 (dev)->pci_device == 0x2A12 || \
1159 (dev)->pci_device == 0x2E02 || \
1160 (dev)->pci_device == 0x2E12 || \
1161 (dev)->pci_device == 0x2E22 || \
1162 (dev)->pci_device == 0x2E32 || \
1163 (dev)->pci_device == 0x2A42 || \
1164 (dev)->pci_device == 0x2E42)
1166 #define HAS_BSD(dev) (IS_IRONLAKE(dev) || IS_G4X(dev))
1167 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1169 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1170 * rows, which changed the alignment requirements and fence programming.
1172 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
1174 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_PINEVIEW(dev))
1175 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1176 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1177 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1178 #define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \
1179 !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev) && \
1181 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1182 /* dsparb controlled by hw only */
1183 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1185 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev))
1186 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1187 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1188 #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
1190 #define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) || \
1192 #define HAS_PIPE_CONTROL(dev) (IS_IRONLAKE(dev) || IS_GEN6(dev))
1194 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1195 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1197 #define PRIMARY_RINGBUFFER_SIZE (128*1024)