1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
32 #include <drm/i915_drm.h>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
37 #include <linux/console.h>
38 #include <linux/module.h>
39 #include <drm/drm_crtc_helper.h>
41 static int i915_modeset __read_mostly = -1;
42 module_param_named(modeset, i915_modeset, int, 0400);
43 MODULE_PARM_DESC(modeset,
44 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
45 "1=on, -1=force vga console preference [default])");
47 unsigned int i915_fbpercrtc __always_unused = 0;
48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
50 int i915_panel_ignore_lid __read_mostly = 1;
51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
52 MODULE_PARM_DESC(panel_ignore_lid,
53 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
54 "-1=force lid closed, -2=force lid open)");
56 unsigned int i915_powersave __read_mostly = 1;
57 module_param_named(powersave, i915_powersave, int, 0600);
58 MODULE_PARM_DESC(powersave,
59 "Enable powersavings, fbc, downclocking, etc. (default: true)");
61 int i915_semaphores __read_mostly = -1;
62 module_param_named(semaphores, i915_semaphores, int, 0600);
63 MODULE_PARM_DESC(semaphores,
64 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
66 int i915_enable_rc6 __read_mostly = -1;
67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
68 MODULE_PARM_DESC(i915_enable_rc6,
69 "Enable power-saving render C-state 6. "
70 "Different stages can be selected via bitmask values "
71 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
72 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
73 "default: -1 (use per-chip default)");
75 int i915_enable_fbc __read_mostly = -1;
76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
77 MODULE_PARM_DESC(i915_enable_fbc,
78 "Enable frame buffer compression for power savings "
79 "(default: -1 (use per-chip default))");
81 unsigned int i915_lvds_downclock __read_mostly = 0;
82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
83 MODULE_PARM_DESC(lvds_downclock,
84 "Use panel (LVDS/eDP) downclocking for power savings "
87 int i915_lvds_channel_mode __read_mostly;
88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
89 MODULE_PARM_DESC(lvds_channel_mode,
90 "Specify LVDS channel mode "
91 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
93 int i915_panel_use_ssc __read_mostly = -1;
94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
95 MODULE_PARM_DESC(lvds_use_ssc,
96 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
97 "(default: auto from VBT)");
99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
102 "Override/Ignore selection of SDVO panel mode in the VBT "
103 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
105 static bool i915_try_reset __read_mostly = true;
106 module_param_named(reset, i915_try_reset, bool, 0600);
107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
109 bool i915_enable_hangcheck __read_mostly = true;
110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
111 MODULE_PARM_DESC(enable_hangcheck,
112 "Periodically check GPU activity for detecting hangs. "
113 "WARNING: Disabling this can cause system wide hangs. "
116 int i915_enable_ppgtt __read_mostly = -1;
117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
118 MODULE_PARM_DESC(i915_enable_ppgtt,
119 "Enable PPGTT (default: true)");
121 unsigned int i915_preliminary_hw_support __read_mostly = 0;
122 module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
123 MODULE_PARM_DESC(preliminary_hw_support,
124 "Enable preliminary hardware support. (default: false)");
126 static struct drm_driver driver;
127 extern int intel_agp_enabled;
129 #define INTEL_VGA_DEVICE(id, info) { \
130 .class = PCI_BASE_CLASS_DISPLAY << 16, \
131 .class_mask = 0xff0000, \
134 .subvendor = PCI_ANY_ID, \
135 .subdevice = PCI_ANY_ID, \
136 .driver_data = (unsigned long) info }
138 static const struct intel_device_info intel_i830_info = {
139 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
140 .has_overlay = 1, .overlay_needs_physical = 1,
143 static const struct intel_device_info intel_845g_info = {
145 .has_overlay = 1, .overlay_needs_physical = 1,
148 static const struct intel_device_info intel_i85x_info = {
149 .gen = 2, .is_i85x = 1, .is_mobile = 1,
150 .cursor_needs_physical = 1,
151 .has_overlay = 1, .overlay_needs_physical = 1,
154 static const struct intel_device_info intel_i865g_info = {
156 .has_overlay = 1, .overlay_needs_physical = 1,
159 static const struct intel_device_info intel_i915g_info = {
160 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
161 .has_overlay = 1, .overlay_needs_physical = 1,
163 static const struct intel_device_info intel_i915gm_info = {
164 .gen = 3, .is_mobile = 1,
165 .cursor_needs_physical = 1,
166 .has_overlay = 1, .overlay_needs_physical = 1,
169 static const struct intel_device_info intel_i945g_info = {
170 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
171 .has_overlay = 1, .overlay_needs_physical = 1,
173 static const struct intel_device_info intel_i945gm_info = {
174 .gen = 3, .is_i945gm = 1, .is_mobile = 1,
175 .has_hotplug = 1, .cursor_needs_physical = 1,
176 .has_overlay = 1, .overlay_needs_physical = 1,
180 static const struct intel_device_info intel_i965g_info = {
181 .gen = 4, .is_broadwater = 1,
186 static const struct intel_device_info intel_i965gm_info = {
187 .gen = 4, .is_crestline = 1,
188 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
193 static const struct intel_device_info intel_g33_info = {
194 .gen = 3, .is_g33 = 1,
195 .need_gfx_hws = 1, .has_hotplug = 1,
199 static const struct intel_device_info intel_g45_info = {
200 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
201 .has_pipe_cxsr = 1, .has_hotplug = 1,
205 static const struct intel_device_info intel_gm45_info = {
206 .gen = 4, .is_g4x = 1,
207 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
208 .has_pipe_cxsr = 1, .has_hotplug = 1,
213 static const struct intel_device_info intel_pineview_info = {
214 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
215 .need_gfx_hws = 1, .has_hotplug = 1,
219 static const struct intel_device_info intel_ironlake_d_info = {
221 .need_gfx_hws = 1, .has_hotplug = 1,
225 static const struct intel_device_info intel_ironlake_m_info = {
226 .gen = 5, .is_mobile = 1,
227 .need_gfx_hws = 1, .has_hotplug = 1,
232 static const struct intel_device_info intel_sandybridge_d_info = {
234 .need_gfx_hws = 1, .has_hotplug = 1,
241 static const struct intel_device_info intel_sandybridge_m_info = {
242 .gen = 6, .is_mobile = 1,
243 .need_gfx_hws = 1, .has_hotplug = 1,
251 static const struct intel_device_info intel_ivybridge_d_info = {
252 .is_ivybridge = 1, .gen = 7,
253 .need_gfx_hws = 1, .has_hotplug = 1,
260 static const struct intel_device_info intel_ivybridge_m_info = {
261 .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
262 .need_gfx_hws = 1, .has_hotplug = 1,
263 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
270 static const struct intel_device_info intel_valleyview_m_info = {
271 .gen = 7, .is_mobile = 1,
272 .need_gfx_hws = 1, .has_hotplug = 1,
277 .display_mmio_offset = VLV_DISPLAY_BASE,
281 static const struct intel_device_info intel_valleyview_d_info = {
283 .need_gfx_hws = 1, .has_hotplug = 1,
288 .display_mmio_offset = VLV_DISPLAY_BASE,
292 static const struct intel_device_info intel_haswell_d_info = {
293 .is_haswell = 1, .gen = 7,
294 .need_gfx_hws = 1, .has_hotplug = 1,
301 static const struct intel_device_info intel_haswell_m_info = {
302 .is_haswell = 1, .gen = 7, .is_mobile = 1,
303 .need_gfx_hws = 1, .has_hotplug = 1,
310 static const struct pci_device_id pciidlist[] = { /* aka */
311 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
312 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
313 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
314 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
315 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
316 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
317 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
318 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
319 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
320 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
321 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
322 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
323 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
324 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
325 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
326 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
327 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
328 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
329 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
330 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
331 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
332 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
333 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
334 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
335 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
336 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
337 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
338 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
339 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
340 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
341 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
342 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
343 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
344 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
345 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
346 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
347 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
348 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
349 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
350 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
351 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
352 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
353 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
354 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
355 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
356 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
357 INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
358 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
359 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
360 INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
361 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
362 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
363 INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
364 INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
365 INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
366 INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
367 INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
368 INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
369 INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
370 INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
371 INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
372 INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
373 INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
374 INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
375 INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
376 INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
377 INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
378 INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
379 INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
380 INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
381 INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
382 INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
383 INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
384 INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
385 INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
386 INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
387 INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
388 INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
389 INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
390 INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
391 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
392 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
393 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
397 #if defined(CONFIG_DRM_I915_KMS)
398 MODULE_DEVICE_TABLE(pci, pciidlist);
401 void intel_detect_pch(struct drm_device *dev)
403 struct drm_i915_private *dev_priv = dev->dev_private;
407 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
408 * make graphics device passthrough work easy for VMM, that only
409 * need to expose ISA bridge to let driver know the real hardware
410 * underneath. This is a requirement from virtualization team.
412 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
414 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
416 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
417 dev_priv->pch_id = id;
419 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
420 dev_priv->pch_type = PCH_IBX;
421 dev_priv->num_pch_pll = 2;
422 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
423 WARN_ON(!IS_GEN5(dev));
424 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
425 dev_priv->pch_type = PCH_CPT;
426 dev_priv->num_pch_pll = 2;
427 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
428 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
429 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
430 /* PantherPoint is CPT compatible */
431 dev_priv->pch_type = PCH_CPT;
432 dev_priv->num_pch_pll = 2;
433 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
434 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
435 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
436 dev_priv->pch_type = PCH_LPT;
437 dev_priv->num_pch_pll = 0;
438 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
439 WARN_ON(!IS_HASWELL(dev));
440 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
441 dev_priv->pch_type = PCH_LPT;
442 dev_priv->num_pch_pll = 0;
443 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
444 WARN_ON(!IS_HASWELL(dev));
446 BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
452 bool i915_semaphore_is_enabled(struct drm_device *dev)
454 if (INTEL_INFO(dev)->gen < 6)
457 if (i915_semaphores >= 0)
458 return i915_semaphores;
460 #ifdef CONFIG_INTEL_IOMMU
461 /* Enable semaphores on SNB when IO remapping is off */
462 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
469 static int i915_drm_freeze(struct drm_device *dev)
471 struct drm_i915_private *dev_priv = dev->dev_private;
473 /* ignore lid events during suspend */
474 mutex_lock(&dev_priv->modeset_restore_lock);
475 dev_priv->modeset_restore = MODESET_SUSPENDED;
476 mutex_unlock(&dev_priv->modeset_restore_lock);
478 intel_set_power_well(dev, true);
480 drm_kms_helper_poll_disable(dev);
482 pci_save_state(dev->pdev);
484 /* If KMS is active, we do the leavevt stuff here */
485 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
486 int error = i915_gem_idle(dev);
488 dev_err(&dev->pdev->dev,
489 "GEM idle failed, resume might fail\n");
493 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
495 intel_modeset_disable(dev);
497 drm_irq_uninstall(dev);
498 dev_priv->enable_hotplug_processing = false;
501 i915_save_state(dev);
503 intel_opregion_fini(dev);
506 intel_fbdev_set_suspend(dev, 1);
512 int i915_suspend(struct drm_device *dev, pm_message_t state)
516 if (!dev || !dev->dev_private) {
517 DRM_ERROR("dev: %p\n", dev);
518 DRM_ERROR("DRM not initialized, aborting suspend.\n");
522 if (state.event == PM_EVENT_PRETHAW)
526 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
529 error = i915_drm_freeze(dev);
533 if (state.event == PM_EVENT_SUSPEND) {
534 /* Shut down the device */
535 pci_disable_device(dev->pdev);
536 pci_set_power_state(dev->pdev, PCI_D3hot);
542 void intel_console_resume(struct work_struct *work)
544 struct drm_i915_private *dev_priv =
545 container_of(work, struct drm_i915_private,
546 console_resume_work);
547 struct drm_device *dev = dev_priv->dev;
550 intel_fbdev_set_suspend(dev, 0);
554 static int __i915_drm_thaw(struct drm_device *dev)
556 struct drm_i915_private *dev_priv = dev->dev_private;
559 i915_restore_state(dev);
560 intel_opregion_setup(dev);
562 /* KMS EnterVT equivalent */
563 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
564 intel_init_pch_refclk(dev);
566 mutex_lock(&dev->struct_mutex);
567 dev_priv->mm.suspended = 0;
569 error = i915_gem_init_hw(dev);
570 mutex_unlock(&dev->struct_mutex);
572 /* We need working interrupts for modeset enabling ... */
573 drm_irq_install(dev);
575 intel_modeset_init_hw(dev);
576 intel_modeset_setup_hw_state(dev, false);
579 * ... but also need to make sure that hotplug processing
580 * doesn't cause havoc. Like in the driver load code we don't
581 * bother with the tiny race here where we might loose hotplug
585 dev_priv->enable_hotplug_processing = true;
588 intel_opregion_init(dev);
591 * The console lock can be pretty contented on resume due
592 * to all the printk activity. Try to keep it out of the hot
593 * path of resume if possible.
595 if (console_trylock()) {
596 intel_fbdev_set_suspend(dev, 0);
599 schedule_work(&dev_priv->console_resume_work);
602 mutex_lock(&dev_priv->modeset_restore_lock);
603 dev_priv->modeset_restore = MODESET_DONE;
604 mutex_unlock(&dev_priv->modeset_restore_lock);
608 static int i915_drm_thaw(struct drm_device *dev)
614 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
615 mutex_lock(&dev->struct_mutex);
616 i915_gem_restore_gtt_mappings(dev);
617 mutex_unlock(&dev->struct_mutex);
620 __i915_drm_thaw(dev);
625 int i915_resume(struct drm_device *dev)
627 struct drm_i915_private *dev_priv = dev->dev_private;
630 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
633 if (pci_enable_device(dev->pdev))
636 pci_set_master(dev->pdev);
641 * Platforms with opregion should have sane BIOS, older ones (gen3 and
642 * earlier) need this since the BIOS might clear all our scratch PTEs.
644 if (drm_core_check_feature(dev, DRIVER_MODESET) &&
645 !dev_priv->opregion.header) {
646 mutex_lock(&dev->struct_mutex);
647 i915_gem_restore_gtt_mappings(dev);
648 mutex_unlock(&dev->struct_mutex);
651 ret = __i915_drm_thaw(dev);
655 drm_kms_helper_poll_enable(dev);
659 static int i8xx_do_reset(struct drm_device *dev)
661 struct drm_i915_private *dev_priv = dev->dev_private;
666 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
667 POSTING_READ(D_STATE);
669 if (IS_I830(dev) || IS_845G(dev)) {
670 I915_WRITE(DEBUG_RESET_I830,
671 DEBUG_RESET_DISPLAY |
674 POSTING_READ(DEBUG_RESET_I830);
677 I915_WRITE(DEBUG_RESET_I830, 0);
678 POSTING_READ(DEBUG_RESET_I830);
683 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
684 POSTING_READ(D_STATE);
689 static int i965_reset_complete(struct drm_device *dev)
692 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
693 return (gdrst & GRDOM_RESET_ENABLE) == 0;
696 static int i965_do_reset(struct drm_device *dev)
702 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
703 * well as the reset bit (GR/bit 0). Setting the GR bit
704 * triggers the reset; when done, the hardware will clear it.
706 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
707 pci_write_config_byte(dev->pdev, I965_GDRST,
708 gdrst | GRDOM_RENDER |
710 ret = wait_for(i965_reset_complete(dev), 500);
714 /* We can't reset render&media without also resetting display ... */
715 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
716 pci_write_config_byte(dev->pdev, I965_GDRST,
717 gdrst | GRDOM_MEDIA |
720 return wait_for(i965_reset_complete(dev), 500);
723 static int ironlake_do_reset(struct drm_device *dev)
725 struct drm_i915_private *dev_priv = dev->dev_private;
729 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
730 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
731 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
732 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
736 /* We can't reset render&media without also resetting display ... */
737 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
738 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
739 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
740 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
743 static int gen6_do_reset(struct drm_device *dev)
745 struct drm_i915_private *dev_priv = dev->dev_private;
747 unsigned long irqflags;
749 /* Hold gt_lock across reset to prevent any register access
750 * with forcewake not set correctly
752 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
756 /* GEN6_GDRST is not in the gt power well, no need to check
757 * for fifo space for the write or forcewake the chip for
760 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
762 /* Spin waiting for the device to ack the reset request */
763 ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
765 /* If reset with a user forcewake, try to restore, otherwise turn it off */
766 if (dev_priv->forcewake_count)
767 dev_priv->gt.force_wake_get(dev_priv);
769 dev_priv->gt.force_wake_put(dev_priv);
771 /* Restore fifo count */
772 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
774 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
778 int intel_gpu_reset(struct drm_device *dev)
780 struct drm_i915_private *dev_priv = dev->dev_private;
783 switch (INTEL_INFO(dev)->gen) {
786 ret = gen6_do_reset(dev);
789 ret = ironlake_do_reset(dev);
792 ret = i965_do_reset(dev);
795 ret = i8xx_do_reset(dev);
799 /* Also reset the gpu hangman. */
800 if (dev_priv->gpu_error.stop_rings) {
801 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
802 dev_priv->gpu_error.stop_rings = 0;
803 if (ret == -ENODEV) {
804 DRM_ERROR("Reset not implemented, but ignoring "
805 "error for simulated gpu hangs\n");
814 * i915_reset - reset chip after a hang
815 * @dev: drm device to reset
817 * Reset the chip. Useful if a hang is detected. Returns zero on successful
818 * reset or otherwise an error code.
820 * Procedure is fairly simple:
821 * - reset the chip using the reset reg
822 * - re-init context state
823 * - re-init hardware status page
824 * - re-init ring buffer
825 * - re-init interrupt state
828 int i915_reset(struct drm_device *dev)
830 drm_i915_private_t *dev_priv = dev->dev_private;
836 mutex_lock(&dev->struct_mutex);
841 if (get_seconds() - dev_priv->gpu_error.last_reset < 5)
842 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
844 ret = intel_gpu_reset(dev);
846 dev_priv->gpu_error.last_reset = get_seconds();
848 DRM_ERROR("Failed to reset chip.\n");
849 mutex_unlock(&dev->struct_mutex);
853 /* Ok, now get things going again... */
856 * Everything depends on having the GTT running, so we need to start
857 * there. Fortunately we don't need to do this unless we reset the
858 * chip at a PCI level.
860 * Next we need to restore the context, but we don't use those
863 * Ring buffer needs to be re-initialized in the KMS case, or if X
864 * was running at the time of the reset (i.e. we weren't VT
867 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
868 !dev_priv->mm.suspended) {
869 struct intel_ring_buffer *ring;
872 dev_priv->mm.suspended = 0;
874 i915_gem_init_swizzling(dev);
876 for_each_ring(ring, dev_priv, i)
879 i915_gem_context_init(dev);
880 i915_gem_init_ppgtt(dev);
883 * It would make sense to re-init all the other hw state, at
884 * least the rps/rc6/emon init done within modeset_init_hw. For
885 * some unknown reason, this blows up my ilk, so don't.
888 mutex_unlock(&dev->struct_mutex);
890 drm_irq_uninstall(dev);
891 drm_irq_install(dev);
894 mutex_unlock(&dev->struct_mutex);
900 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
902 struct intel_device_info *intel_info =
903 (struct intel_device_info *) ent->driver_data;
905 if (intel_info->is_valleyview)
906 if(!i915_preliminary_hw_support) {
907 DRM_ERROR("Preliminary hardware support disabled\n");
911 /* Only bind to function 0 of the device. Early generations
912 * used function 1 as a placeholder for multi-head. This causes
913 * us confusion instead, especially on the systems where both
914 * functions have the same PCI-ID!
916 if (PCI_FUNC(pdev->devfn))
919 /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
920 * implementation for gen3 (and only gen3) that used legacy drm maps
921 * (gasp!) to share buffers between X and the client. Hence we need to
922 * keep around the fake agp stuff for gen3, even when kms is enabled. */
923 if (intel_info->gen != 3) {
924 driver.driver_features &=
925 ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
926 } else if (!intel_agp_enabled) {
927 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
931 return drm_get_pci_dev(pdev, ent, &driver);
935 i915_pci_remove(struct pci_dev *pdev)
937 struct drm_device *dev = pci_get_drvdata(pdev);
942 static int i915_pm_suspend(struct device *dev)
944 struct pci_dev *pdev = to_pci_dev(dev);
945 struct drm_device *drm_dev = pci_get_drvdata(pdev);
948 if (!drm_dev || !drm_dev->dev_private) {
949 dev_err(dev, "DRM not initialized, aborting suspend.\n");
953 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
956 error = i915_drm_freeze(drm_dev);
960 pci_disable_device(pdev);
961 pci_set_power_state(pdev, PCI_D3hot);
966 static int i915_pm_resume(struct device *dev)
968 struct pci_dev *pdev = to_pci_dev(dev);
969 struct drm_device *drm_dev = pci_get_drvdata(pdev);
971 return i915_resume(drm_dev);
974 static int i915_pm_freeze(struct device *dev)
976 struct pci_dev *pdev = to_pci_dev(dev);
977 struct drm_device *drm_dev = pci_get_drvdata(pdev);
979 if (!drm_dev || !drm_dev->dev_private) {
980 dev_err(dev, "DRM not initialized, aborting suspend.\n");
984 return i915_drm_freeze(drm_dev);
987 static int i915_pm_thaw(struct device *dev)
989 struct pci_dev *pdev = to_pci_dev(dev);
990 struct drm_device *drm_dev = pci_get_drvdata(pdev);
992 return i915_drm_thaw(drm_dev);
995 static int i915_pm_poweroff(struct device *dev)
997 struct pci_dev *pdev = to_pci_dev(dev);
998 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1000 return i915_drm_freeze(drm_dev);
1003 static const struct dev_pm_ops i915_pm_ops = {
1004 .suspend = i915_pm_suspend,
1005 .resume = i915_pm_resume,
1006 .freeze = i915_pm_freeze,
1007 .thaw = i915_pm_thaw,
1008 .poweroff = i915_pm_poweroff,
1009 .restore = i915_pm_resume,
1012 static const struct vm_operations_struct i915_gem_vm_ops = {
1013 .fault = i915_gem_fault,
1014 .open = drm_gem_vm_open,
1015 .close = drm_gem_vm_close,
1018 static const struct file_operations i915_driver_fops = {
1019 .owner = THIS_MODULE,
1021 .release = drm_release,
1022 .unlocked_ioctl = drm_ioctl,
1023 .mmap = drm_gem_mmap,
1025 .fasync = drm_fasync,
1027 #ifdef CONFIG_COMPAT
1028 .compat_ioctl = i915_compat_ioctl,
1030 .llseek = noop_llseek,
1033 static struct drm_driver driver = {
1034 /* Don't use MTRRs here; the Xserver or userspace app should
1035 * deal with them for Intel hardware.
1038 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
1039 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
1040 .load = i915_driver_load,
1041 .unload = i915_driver_unload,
1042 .open = i915_driver_open,
1043 .lastclose = i915_driver_lastclose,
1044 .preclose = i915_driver_preclose,
1045 .postclose = i915_driver_postclose,
1047 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1048 .suspend = i915_suspend,
1049 .resume = i915_resume,
1051 .device_is_agp = i915_driver_device_is_agp,
1052 .master_create = i915_master_create,
1053 .master_destroy = i915_master_destroy,
1054 #if defined(CONFIG_DEBUG_FS)
1055 .debugfs_init = i915_debugfs_init,
1056 .debugfs_cleanup = i915_debugfs_cleanup,
1058 .gem_init_object = i915_gem_init_object,
1059 .gem_free_object = i915_gem_free_object,
1060 .gem_vm_ops = &i915_gem_vm_ops,
1062 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1063 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1064 .gem_prime_export = i915_gem_prime_export,
1065 .gem_prime_import = i915_gem_prime_import,
1067 .dumb_create = i915_gem_dumb_create,
1068 .dumb_map_offset = i915_gem_mmap_gtt,
1069 .dumb_destroy = i915_gem_dumb_destroy,
1070 .ioctls = i915_ioctls,
1071 .fops = &i915_driver_fops,
1072 .name = DRIVER_NAME,
1073 .desc = DRIVER_DESC,
1074 .date = DRIVER_DATE,
1075 .major = DRIVER_MAJOR,
1076 .minor = DRIVER_MINOR,
1077 .patchlevel = DRIVER_PATCHLEVEL,
1080 static struct pci_driver i915_pci_driver = {
1081 .name = DRIVER_NAME,
1082 .id_table = pciidlist,
1083 .probe = i915_pci_probe,
1084 .remove = i915_pci_remove,
1085 .driver.pm = &i915_pm_ops,
1088 static int __init i915_init(void)
1090 driver.num_ioctls = i915_max_ioctl;
1093 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1094 * explicitly disabled with the module pararmeter.
1096 * Otherwise, just follow the parameter (defaulting to off).
1098 * Allow optional vga_text_mode_force boot option to override
1099 * the default behavior.
1101 #if defined(CONFIG_DRM_I915_KMS)
1102 if (i915_modeset != 0)
1103 driver.driver_features |= DRIVER_MODESET;
1105 if (i915_modeset == 1)
1106 driver.driver_features |= DRIVER_MODESET;
1108 #ifdef CONFIG_VGA_CONSOLE
1109 if (vgacon_text_force() && i915_modeset == -1)
1110 driver.driver_features &= ~DRIVER_MODESET;
1113 if (!(driver.driver_features & DRIVER_MODESET))
1114 driver.get_vblank_timestamp = NULL;
1116 return drm_pci_init(&driver, &i915_pci_driver);
1119 static void __exit i915_exit(void)
1121 drm_pci_exit(&driver, &i915_pci_driver);
1124 module_init(i915_init);
1125 module_exit(i915_exit);
1127 MODULE_AUTHOR(DRIVER_AUTHOR);
1128 MODULE_DESCRIPTION(DRIVER_DESC);
1129 MODULE_LICENSE("GPL and additional rights");
1131 /* We give fast paths for the really cool registers */
1132 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1133 ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1134 ((reg) < 0x40000) && \
1135 ((reg) != FORCEWAKE))
1137 ilk_dummy_write(struct drm_i915_private *dev_priv)
1139 /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
1140 * chip from rc6 before touching it for real. MI_MODE is masked, hence
1141 * harmless to write 0 into. */
1142 I915_WRITE_NOTRACE(MI_MODE, 0);
1146 hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
1148 if (IS_HASWELL(dev_priv->dev) &&
1149 (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1150 DRM_ERROR("Unknown unclaimed register before writing to %x\n",
1152 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1157 hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
1159 if (IS_HASWELL(dev_priv->dev) &&
1160 (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1161 DRM_ERROR("Unclaimed write to %x\n", reg);
1162 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1166 #define __i915_read(x, y) \
1167 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1169 if (IS_GEN5(dev_priv->dev)) \
1170 ilk_dummy_write(dev_priv); \
1171 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1172 unsigned long irqflags; \
1173 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1174 if (dev_priv->forcewake_count == 0) \
1175 dev_priv->gt.force_wake_get(dev_priv); \
1176 val = read##y(dev_priv->regs + reg); \
1177 if (dev_priv->forcewake_count == 0) \
1178 dev_priv->gt.force_wake_put(dev_priv); \
1179 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1181 val = read##y(dev_priv->regs + reg); \
1183 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1193 #define __i915_write(x, y) \
1194 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1195 u32 __fifo_ret = 0; \
1196 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1197 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1198 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1200 if (IS_GEN5(dev_priv->dev)) \
1201 ilk_dummy_write(dev_priv); \
1202 hsw_unclaimed_reg_clear(dev_priv, reg); \
1203 write##y(val, dev_priv->regs + reg); \
1204 if (unlikely(__fifo_ret)) { \
1205 gen6_gt_check_fifodbg(dev_priv); \
1207 hsw_unclaimed_reg_check(dev_priv, reg); \
1215 static const struct register_whitelist {
1218 uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1220 { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
1223 int i915_reg_read_ioctl(struct drm_device *dev,
1224 void *data, struct drm_file *file)
1226 struct drm_i915_private *dev_priv = dev->dev_private;
1227 struct drm_i915_reg_read *reg = data;
1228 struct register_whitelist const *entry = whitelist;
1231 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1232 if (entry->offset == reg->offset &&
1233 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1237 if (i == ARRAY_SIZE(whitelist))
1240 switch (entry->size) {
1242 reg->val = I915_READ64(reg->offset);
1245 reg->val = I915_READ(reg->offset);
1248 reg->val = I915_READ16(reg->offset);
1251 reg->val = I915_READ8(reg->offset);