drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include "drm_crtc_helper.h"
  40
  41 static int i915_modeset __read_mostly = -1;
  42 module_param_named(modeset, i915_modeset, int, 0400);
  43 MODULE_PARM_DESC(modeset,
  44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  45                 "1=on, -1=force vga console preference [default])");
  46
  47 unsigned int i915_fbpercrtc __always_unused = 0;
  48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  49
  50 int i915_panel_ignore_lid __read_mostly = 0;
  51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  52 MODULE_PARM_DESC(panel_ignore_lid,
  53                 "Override lid status (0=autodetect [default], 1=lid open, "
  54                 "-1=lid closed)");
  55
  56 unsigned int i915_powersave __read_mostly = 1;
  57 module_param_named(powersave, i915_powersave, int, 0600);
  58 MODULE_PARM_DESC(powersave,
  59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  60
  61 int i915_semaphores __read_mostly = -1;
  62 module_param_named(semaphores, i915_semaphores, int, 0600);
  63 MODULE_PARM_DESC(semaphores,
  64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  65
  66 int i915_enable_rc6 __read_mostly = -1;
  67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
  68 MODULE_PARM_DESC(i915_enable_rc6,
  69                 "Enable power-saving render C-state 6 (default: -1 (use per-chip default)");
  70
  71 int i915_enable_fbc __read_mostly = -1;
  72 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  73 MODULE_PARM_DESC(i915_enable_fbc,
  74                 "Enable frame buffer compression for power savings "
  75                 "(default: -1 (use per-chip default))");
  76
  77 unsigned int i915_lvds_downclock __read_mostly = 0;
  78 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  79 MODULE_PARM_DESC(lvds_downclock,
  80                 "Use panel (LVDS/eDP) downclocking for power savings "
  81                 "(default: false)");
  82
  83 int i915_panel_use_ssc __read_mostly = -1;
  84 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  85 MODULE_PARM_DESC(lvds_use_ssc,
  86                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  87                 "(default: auto from VBT)");
  88
  89 int i915_vbt_sdvo_panel_type __read_mostly = -1;
  90 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
  91 MODULE_PARM_DESC(vbt_sdvo_panel_type,
  92                 "Override selection of SDVO panel mode in the VBT "
  93                 "(default: auto)");
  94
  95 static bool i915_try_reset __read_mostly = true;
  96 module_param_named(reset, i915_try_reset, bool, 0600);
  97 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
  98
  99 bool i915_enable_hangcheck __read_mostly = true;
 100 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 101 MODULE_PARM_DESC(enable_hangcheck,
 102                 "Periodically check GPU activity for detecting hangs. "
 103                 "WARNING: Disabling this can cause system wide hangs. "
 104                 "(default: true)");
 105
 106 static struct drm_driver driver;
 107 extern int intel_agp_enabled;
 108
 109 #define INTEL_VGA_DEVICE(id, info) {            \
 110         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
 111         .class_mask = 0xff0000,                 \
 112         .vendor = 0x8086,                       \
 113         .device = id,                           \
 114         .subvendor = PCI_ANY_ID,                \
 115         .subdevice = PCI_ANY_ID,                \
 116         .driver_data = (unsigned long) info }
 117
 118 static const struct intel_device_info intel_i830_info = {
 119         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
 120         .has_overlay = 1, .overlay_needs_physical = 1,
 121 };
 122
 123 static const struct intel_device_info intel_845g_info = {
 124         .gen = 2,
 125         .has_overlay = 1, .overlay_needs_physical = 1,
 126 };
 127
 128 static const struct intel_device_info intel_i85x_info = {
 129         .gen = 2, .is_i85x = 1, .is_mobile = 1,
 130         .cursor_needs_physical = 1,
 131         .has_overlay = 1, .overlay_needs_physical = 1,
 132 };
 133
 134 static const struct intel_device_info intel_i865g_info = {
 135         .gen = 2,
 136         .has_overlay = 1, .overlay_needs_physical = 1,
 137 };
 138
 139 static const struct intel_device_info intel_i915g_info = {
 140         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
 141         .has_overlay = 1, .overlay_needs_physical = 1,
 142 };
 143 static const struct intel_device_info intel_i915gm_info = {
 144         .gen = 3, .is_mobile = 1,
 145         .cursor_needs_physical = 1,
 146         .has_overlay = 1, .overlay_needs_physical = 1,
 147         .supports_tv = 1,
 148 };
 149 static const struct intel_device_info intel_i945g_info = {
 150         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
 151         .has_overlay = 1, .overlay_needs_physical = 1,
 152 };
 153 static const struct intel_device_info intel_i945gm_info = {
 154         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
 155         .has_hotplug = 1, .cursor_needs_physical = 1,
 156         .has_overlay = 1, .overlay_needs_physical = 1,
 157         .supports_tv = 1,
 158 };
 159
 160 static const struct intel_device_info intel_i965g_info = {
 161         .gen = 4, .is_broadwater = 1,
 162         .has_hotplug = 1,
 163         .has_overlay = 1,
 164 };
 165
 166 static const struct intel_device_info intel_i965gm_info = {
 167         .gen = 4, .is_crestline = 1,
 168         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 169         .has_overlay = 1,
 170         .supports_tv = 1,
 171 };
 172
 173 static const struct intel_device_info intel_g33_info = {
 174         .gen = 3, .is_g33 = 1,
 175         .need_gfx_hws = 1, .has_hotplug = 1,
 176         .has_overlay = 1,
 177 };
 178
 179 static const struct intel_device_info intel_g45_info = {
 180         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 181         .has_pipe_cxsr = 1, .has_hotplug = 1,
 182         .has_bsd_ring = 1,
 183 };
 184
 185 static const struct intel_device_info intel_gm45_info = {
 186         .gen = 4, .is_g4x = 1,
 187         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 188         .has_pipe_cxsr = 1, .has_hotplug = 1,
 189         .supports_tv = 1,
 190         .has_bsd_ring = 1,
 191 };
 192
 193 static const struct intel_device_info intel_pineview_info = {
 194         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 195         .need_gfx_hws = 1, .has_hotplug = 1,
 196         .has_overlay = 1,
 197 };
 198
 199 static const struct intel_device_info intel_ironlake_d_info = {
 200         .gen = 5,
 201         .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,
 202         .has_bsd_ring = 1,
 203 };
 204
 205 static const struct intel_device_info intel_ironlake_m_info = {
 206         .gen = 5, .is_mobile = 1,
 207         .need_gfx_hws = 1, .has_hotplug = 1,
 208         .has_fbc = 1,
 209         .has_bsd_ring = 1,
 210 };
 211
 212 static const struct intel_device_info intel_sandybridge_d_info = {
 213         .gen = 6,
 214         .need_gfx_hws = 1, .has_hotplug = 1,
 215         .has_bsd_ring = 1,
 216         .has_blt_ring = 1,
 217         .has_force_wake = 1,
 218 };
 219
 220 static const struct intel_device_info intel_sandybridge_m_info = {
 221         .gen = 6, .is_mobile = 1,
 222         .need_gfx_hws = 1, .has_hotplug = 1,
 223         .has_fbc = 1,
 224         .has_bsd_ring = 1,
 225         .has_blt_ring = 1,
 226         .has_force_wake = 1,
 227 };
 228
 229 static const struct intel_device_info intel_ivybridge_d_info = {
 230         .is_ivybridge = 1, .gen = 7,
 231         .need_gfx_hws = 1, .has_hotplug = 1,
 232         .has_bsd_ring = 1,
 233         .has_blt_ring = 1,
 234         .has_force_wake = 1,
 235 };
 236
 237 static const struct intel_device_info intel_ivybridge_m_info = {
 238         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
 239         .need_gfx_hws = 1, .has_hotplug = 1,
 240         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
 241         .has_bsd_ring = 1,
 242         .has_blt_ring = 1,
 243         .has_force_wake = 1,
 244 };
 245
 246 static const struct pci_device_id pciidlist[] = {               /* aka */
 247         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 248         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 249         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 250         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 251         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 252         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 253         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 254         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 255         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 256         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 257         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 258         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 259         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 260         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 261         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 262         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 263         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 264         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 265         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 266         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 267         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 268         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 269         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 270         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 271         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 272         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 273         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 274         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 275         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 276         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 277         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 278         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 279         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 280         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 281         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 282         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 283         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 284         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 285         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 286         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 287         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 288         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 289         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 290         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
 291         {0, 0, 0}
 292 };
 293
 294 #if defined(CONFIG_DRM_I915_KMS)
 295 MODULE_DEVICE_TABLE(pci, pciidlist);
 296 #endif
 297
 298 #define INTEL_PCH_DEVICE_ID_MASK        0xff00
 299 #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
 300 #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
 301 #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
 302
 303 void intel_detect_pch(struct drm_device *dev)
 304 {
 305         struct drm_i915_private *dev_priv = dev->dev_private;
 306         struct pci_dev *pch;
 307
 308         /*
 309          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 310          * make graphics device passthrough work easy for VMM, that only
 311          * need to expose ISA bridge to let driver know the real hardware
 312          * underneath. This is a requirement from virtualization team.
 313          */
 314         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 315         if (pch) {
 316                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 317                         int id;
 318                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 319
 320                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 321                                 dev_priv->pch_type = PCH_IBX;
 322                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 323                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 324                                 dev_priv->pch_type = PCH_CPT;
 325                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 326                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 327                                 /* PantherPoint is CPT compatible */
 328                                 dev_priv->pch_type = PCH_CPT;
 329                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 330                         }
 331                 }
 332                 pci_dev_put(pch);
 333         }
 334 }
 335
 336 void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 337 {
 338         int count;
 339
 340         count = 0;
 341         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
 342                 udelay(10);
 343
 344         I915_WRITE_NOTRACE(FORCEWAKE, 1);
 345         POSTING_READ(FORCEWAKE);
 346
 347         count = 0;
 348         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
 349                 udelay(10);
 350 }
 351
 352 void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
 353 {
 354         int count;
 355
 356         count = 0;
 357         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
 358                 udelay(10);
 359
 360         I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1);
 361         POSTING_READ(FORCEWAKE_MT);
 362
 363         count = 0;
 364         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
 365                 udelay(10);
 366 }
 367
 368 /*
 369  * Generally this is called implicitly by the register read function. However,
 370  * if some sequence requires the GT to not power down then this function should
 371  * be called at the beginning of the sequence followed by a call to
 372  * gen6_gt_force_wake_put() at the end of the sequence.
 373  */
 374 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 375 {
 376         unsigned long irqflags;
 377
 378         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 379         if (dev_priv->forcewake_count++ == 0)
 380                 dev_priv->display.force_wake_get(dev_priv);
 381         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 382 }
 383
 384 void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 385 {
 386         I915_WRITE_NOTRACE(FORCEWAKE, 0);
 387         POSTING_READ(FORCEWAKE);
 388 }
 389
 390 void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
 391 {
 392         I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0);
 393         POSTING_READ(FORCEWAKE_MT);
 394 }
 395
 396 /*
 397  * see gen6_gt_force_wake_get()
 398  */
 399 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 400 {
 401         unsigned long irqflags;
 402
 403         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 404         if (--dev_priv->forcewake_count == 0)
 405                 dev_priv->display.force_wake_put(dev_priv);
 406         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 407 }
 408
 409 void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 410 {
 411         if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 412                 int loop = 500;
 413                 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 414                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 415                         udelay(10);
 416                         fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 417                 }
 418                 WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES);
 419                 dev_priv->gt_fifo_count = fifo;
 420         }
 421         dev_priv->gt_fifo_count--;
 422 }
 423
 424 static int i915_drm_freeze(struct drm_device *dev)
 425 {
 426         struct drm_i915_private *dev_priv = dev->dev_private;
 427
 428         drm_kms_helper_poll_disable(dev);
 429
 430         pci_save_state(dev->pdev);
 431
 432         /* If KMS is active, we do the leavevt stuff here */
 433         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 434                 int error = i915_gem_idle(dev);
 435                 if (error) {
 436                         dev_err(&dev->pdev->dev,
 437                                 "GEM idle failed, resume might fail\n");
 438                         return error;
 439                 }
 440                 drm_irq_uninstall(dev);
 441         }
 442
 443         i915_save_state(dev);
 444
 445         intel_opregion_fini(dev);
 446
 447         /* Modeset on resume, not lid events */
 448         dev_priv->modeset_on_lid = 0;
 449
 450         console_lock();
 451         intel_fbdev_set_suspend(dev, 1);
 452         console_unlock();
 453
 454         return 0;
 455 }
 456
 457 int i915_suspend(struct drm_device *dev, pm_message_t state)
 458 {
 459         int error;
 460
 461         if (!dev || !dev->dev_private) {
 462                 DRM_ERROR("dev: %p\n", dev);
 463                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 464                 return -ENODEV;
 465         }
 466
 467         if (state.event == PM_EVENT_PRETHAW)
 468                 return 0;
 469
 470
 471         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 472                 return 0;
 473
 474         error = i915_drm_freeze(dev);
 475         if (error)
 476                 return error;
 477
 478         if (state.event == PM_EVENT_SUSPEND) {
 479                 /* Shut down the device */
 480                 pci_disable_device(dev->pdev);
 481                 pci_set_power_state(dev->pdev, PCI_D3hot);
 482         }
 483
 484         return 0;
 485 }
 486
 487 static int i915_drm_thaw(struct drm_device *dev)
 488 {
 489         struct drm_i915_private *dev_priv = dev->dev_private;
 490         int error = 0;
 491
 492         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 493                 mutex_lock(&dev->struct_mutex);
 494                 i915_gem_restore_gtt_mappings(dev);
 495                 mutex_unlock(&dev->struct_mutex);
 496         }
 497
 498         i915_restore_state(dev);
 499         intel_opregion_setup(dev);
 500
 501         /* KMS EnterVT equivalent */
 502         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 503                 mutex_lock(&dev->struct_mutex);
 504                 dev_priv->mm.suspended = 0;
 505
 506                 error = i915_gem_init_ringbuffer(dev);
 507                 mutex_unlock(&dev->struct_mutex);
 508
 509                 if (HAS_PCH_SPLIT(dev))
 510                         ironlake_init_pch_refclk(dev);
 511
 512                 drm_mode_config_reset(dev);
 513                 drm_irq_install(dev);
 514
 515                 /* Resume the modeset for every activated CRTC */
 516                 mutex_lock(&dev->mode_config.mutex);
 517                 drm_helper_resume_force_mode(dev);
 518                 mutex_unlock(&dev->mode_config.mutex);
 519
 520                 if (IS_IRONLAKE_M(dev))
 521                         ironlake_enable_rc6(dev);
 522         }
 523
 524         intel_opregion_init(dev);
 525
 526         dev_priv->modeset_on_lid = 0;
 527
 528         console_lock();
 529         intel_fbdev_set_suspend(dev, 0);
 530         console_unlock();
 531         return error;
 532 }
 533
 534 int i915_resume(struct drm_device *dev)
 535 {
 536         int ret;
 537
 538         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 539                 return 0;
 540
 541         if (pci_enable_device(dev->pdev))
 542                 return -EIO;
 543
 544         pci_set_master(dev->pdev);
 545
 546         ret = i915_drm_thaw(dev);
 547         if (ret)
 548                 return ret;
 549
 550         drm_kms_helper_poll_enable(dev);
 551         return 0;
 552 }
 553
 554 static int i8xx_do_reset(struct drm_device *dev, u8 flags)
 555 {
 556         struct drm_i915_private *dev_priv = dev->dev_private;
 557
 558         if (IS_I85X(dev))
 559                 return -ENODEV;
 560
 561         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 562         POSTING_READ(D_STATE);
 563
 564         if (IS_I830(dev) || IS_845G(dev)) {
 565                 I915_WRITE(DEBUG_RESET_I830,
 566                            DEBUG_RESET_DISPLAY |
 567                            DEBUG_RESET_RENDER |
 568                            DEBUG_RESET_FULL);
 569                 POSTING_READ(DEBUG_RESET_I830);
 570                 msleep(1);
 571
 572                 I915_WRITE(DEBUG_RESET_I830, 0);
 573                 POSTING_READ(DEBUG_RESET_I830);
 574         }
 575
 576         msleep(1);
 577
 578         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 579         POSTING_READ(D_STATE);
 580
 581         return 0;
 582 }
 583
 584 static int i965_reset_complete(struct drm_device *dev)
 585 {
 586         u8 gdrst;
 587         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 588         return gdrst & 0x1;
 589 }
 590
 591 static int i965_do_reset(struct drm_device *dev, u8 flags)
 592 {
 593         u8 gdrst;
 594
 595         /*
 596          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 597          * well as the reset bit (GR/bit 0).  Setting the GR bit
 598          * triggers the reset; when done, the hardware will clear it.
 599          */
 600         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 601         pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
 602
 603         return wait_for(i965_reset_complete(dev), 500);
 604 }
 605
 606 static int ironlake_do_reset(struct drm_device *dev, u8 flags)
 607 {
 608         struct drm_i915_private *dev_priv = dev->dev_private;
 609         u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 610         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
 611         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 612 }
 613
 614 static int gen6_do_reset(struct drm_device *dev, u8 flags)
 615 {
 616         struct drm_i915_private *dev_priv = dev->dev_private;
 617
 618         I915_WRITE(GEN6_GDRST, GEN6_GRDOM_FULL);
 619         return wait_for((I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 620 }
 621
 622 /**
 623  * i965_reset - reset chip after a hang
 624  * @dev: drm device to reset
 625  * @flags: reset domains
 626  *
 627  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 628  * reset or otherwise an error code.
 629  *
 630  * Procedure is fairly simple:
 631  *   - reset the chip using the reset reg
 632  *   - re-init context state
 633  *   - re-init hardware status page
 634  *   - re-init ring buffer
 635  *   - re-init interrupt state
 636  *   - re-init display
 637  */
 638 int i915_reset(struct drm_device *dev, u8 flags)
 639 {
 640         drm_i915_private_t *dev_priv = dev->dev_private;
 641         /*
 642          * We really should only reset the display subsystem if we actually
 643          * need to
 644          */
 645         bool need_display = true;
 646         unsigned long irqflags;
 647         int ret;
 648
 649         if (!i915_try_reset)
 650                 return 0;
 651
 652         if (!mutex_trylock(&dev->struct_mutex))
 653                 return -EBUSY;
 654
 655         i915_gem_reset(dev);
 656
 657         ret = -ENODEV;
 658         if (get_seconds() - dev_priv->last_gpu_reset < 5) {
 659                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 660         } else switch (INTEL_INFO(dev)->gen) {
 661         case 7:
 662         case 6:
 663                 ret = gen6_do_reset(dev, flags);
 664                 /* If reset with a user forcewake, try to restore */
 665                 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 666                 if (dev_priv->forcewake_count)
 667                         dev_priv->display.force_wake_get(dev_priv);
 668                 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 669                 break;
 670         case 5:
 671                 ret = ironlake_do_reset(dev, flags);
 672                 break;
 673         case 4:
 674                 ret = i965_do_reset(dev, flags);
 675                 break;
 676         case 2:
 677                 ret = i8xx_do_reset(dev, flags);
 678                 break;
 679         }
 680         dev_priv->last_gpu_reset = get_seconds();
 681         if (ret) {
 682                 DRM_ERROR("Failed to reset chip.\n");
 683                 mutex_unlock(&dev->struct_mutex);
 684                 return ret;
 685         }
 686
 687         /* Ok, now get things going again... */
 688
 689         /*
 690          * Everything depends on having the GTT running, so we need to start
 691          * there.  Fortunately we don't need to do this unless we reset the
 692          * chip at a PCI level.
 693          *
 694          * Next we need to restore the context, but we don't use those
 695          * yet either...
 696          *
 697          * Ring buffer needs to be re-initialized in the KMS case, or if X
 698          * was running at the time of the reset (i.e. we weren't VT
 699          * switched away).
 700          */
 701         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 702                         !dev_priv->mm.suspended) {
 703                 dev_priv->mm.suspended = 0;
 704
 705                 dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
 706                 if (HAS_BSD(dev))
 707                     dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
 708                 if (HAS_BLT(dev))
 709                     dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
 710
 711                 mutex_unlock(&dev->struct_mutex);
 712                 drm_irq_uninstall(dev);
 713                 drm_mode_config_reset(dev);
 714                 drm_irq_install(dev);
 715                 mutex_lock(&dev->struct_mutex);
 716         }
 717
 718         mutex_unlock(&dev->struct_mutex);
 719
 720         /*
 721          * Perform a full modeset as on later generations, e.g. Ironlake, we may
 722          * need to retrain the display link and cannot just restore the register
 723          * values.
 724          */
 725         if (need_display) {
 726                 mutex_lock(&dev->mode_config.mutex);
 727                 drm_helper_resume_force_mode(dev);
 728                 mutex_unlock(&dev->mode_config.mutex);
 729         }
 730
 731         return 0;
 732 }
 733
 734
 735 static int __devinit
 736 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 737 {
 738         /* Only bind to function 0 of the device. Early generations
 739          * used function 1 as a placeholder for multi-head. This causes
 740          * us confusion instead, especially on the systems where both
 741          * functions have the same PCI-ID!
 742          */
 743         if (PCI_FUNC(pdev->devfn))
 744                 return -ENODEV;
 745
 746         return drm_get_pci_dev(pdev, ent, &driver);
 747 }
 748
 749 static void
 750 i915_pci_remove(struct pci_dev *pdev)
 751 {
 752         struct drm_device *dev = pci_get_drvdata(pdev);
 753
 754         drm_put_dev(dev);
 755 }
 756
 757 static int i915_pm_suspend(struct device *dev)
 758 {
 759         struct pci_dev *pdev = to_pci_dev(dev);
 760         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 761         int error;
 762
 763         if (!drm_dev || !drm_dev->dev_private) {
 764                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 765                 return -ENODEV;
 766         }
 767
 768         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 769                 return 0;
 770
 771         error = i915_drm_freeze(drm_dev);
 772         if (error)
 773                 return error;
 774
 775         pci_disable_device(pdev);
 776         pci_set_power_state(pdev, PCI_D3hot);
 777
 778         return 0;
 779 }
 780
 781 static int i915_pm_resume(struct device *dev)
 782 {
 783         struct pci_dev *pdev = to_pci_dev(dev);
 784         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 785
 786         return i915_resume(drm_dev);
 787 }
 788
 789 static int i915_pm_freeze(struct device *dev)
 790 {
 791         struct pci_dev *pdev = to_pci_dev(dev);
 792         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 793
 794         if (!drm_dev || !drm_dev->dev_private) {
 795                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 796                 return -ENODEV;
 797         }
 798
 799         return i915_drm_freeze(drm_dev);
 800 }
 801
 802 static int i915_pm_thaw(struct device *dev)
 803 {
 804         struct pci_dev *pdev = to_pci_dev(dev);
 805         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 806
 807         return i915_drm_thaw(drm_dev);
 808 }
 809
 810 static int i915_pm_poweroff(struct device *dev)
 811 {
 812         struct pci_dev *pdev = to_pci_dev(dev);
 813         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 814
 815         return i915_drm_freeze(drm_dev);
 816 }
 817
 818 static const struct dev_pm_ops i915_pm_ops = {
 819         .suspend = i915_pm_suspend,
 820         .resume = i915_pm_resume,
 821         .freeze = i915_pm_freeze,
 822         .thaw = i915_pm_thaw,
 823         .poweroff = i915_pm_poweroff,
 824         .restore = i915_pm_resume,
 825 };
 826
 827 static struct vm_operations_struct i915_gem_vm_ops = {
 828         .fault = i915_gem_fault,
 829         .open = drm_gem_vm_open,
 830         .close = drm_gem_vm_close,
 831 };
 832
 833 static struct drm_driver driver = {
 834         /* Don't use MTRRs here; the Xserver or userspace app should
 835          * deal with them for Intel hardware.
 836          */
 837         .driver_features =
 838             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
 839             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
 840         .load = i915_driver_load,
 841         .unload = i915_driver_unload,
 842         .open = i915_driver_open,
 843         .lastclose = i915_driver_lastclose,
 844         .preclose = i915_driver_preclose,
 845         .postclose = i915_driver_postclose,
 846
 847         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 848         .suspend = i915_suspend,
 849         .resume = i915_resume,
 850
 851         .device_is_agp = i915_driver_device_is_agp,
 852         .reclaim_buffers = drm_core_reclaim_buffers,
 853         .master_create = i915_master_create,
 854         .master_destroy = i915_master_destroy,
 855 #if defined(CONFIG_DEBUG_FS)
 856         .debugfs_init = i915_debugfs_init,
 857         .debugfs_cleanup = i915_debugfs_cleanup,
 858 #endif
 859         .gem_init_object = i915_gem_init_object,
 860         .gem_free_object = i915_gem_free_object,
 861         .gem_vm_ops = &i915_gem_vm_ops,
 862         .dumb_create = i915_gem_dumb_create,
 863         .dumb_map_offset = i915_gem_mmap_gtt,
 864         .dumb_destroy = i915_gem_dumb_destroy,
 865         .ioctls = i915_ioctls,
 866         .fops = {
 867                  .owner = THIS_MODULE,
 868                  .open = drm_open,
 869                  .release = drm_release,
 870                  .unlocked_ioctl = drm_ioctl,
 871                  .mmap = drm_gem_mmap,
 872                  .poll = drm_poll,
 873                  .fasync = drm_fasync,
 874                  .read = drm_read,
 875 #ifdef CONFIG_COMPAT
 876                  .compat_ioctl = i915_compat_ioctl,
 877 #endif
 878                  .llseek = noop_llseek,
 879         },
 880
 881         .name = DRIVER_NAME,
 882         .desc = DRIVER_DESC,
 883         .date = DRIVER_DATE,
 884         .major = DRIVER_MAJOR,
 885         .minor = DRIVER_MINOR,
 886         .patchlevel = DRIVER_PATCHLEVEL,
 887 };
 888
 889 static struct pci_driver i915_pci_driver = {
 890         .name = DRIVER_NAME,
 891         .id_table = pciidlist,
 892         .probe = i915_pci_probe,
 893         .remove = i915_pci_remove,
 894         .driver.pm = &i915_pm_ops,
 895 };
 896
 897 static int __init i915_init(void)
 898 {
 899         if (!intel_agp_enabled) {
 900                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 901                 return -ENODEV;
 902         }
 903
 904         driver.num_ioctls = i915_max_ioctl;
 905
 906         /*
 907          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
 908          * explicitly disabled with the module pararmeter.
 909          *
 910          * Otherwise, just follow the parameter (defaulting to off).
 911          *
 912          * Allow optional vga_text_mode_force boot option to override
 913          * the default behavior.
 914          */
 915 #if defined(CONFIG_DRM_I915_KMS)
 916         if (i915_modeset != 0)
 917                 driver.driver_features |= DRIVER_MODESET;
 918 #endif
 919         if (i915_modeset == 1)
 920                 driver.driver_features |= DRIVER_MODESET;
 921
 922 #ifdef CONFIG_VGA_CONSOLE
 923         if (vgacon_text_force() && i915_modeset == -1)
 924                 driver.driver_features &= ~DRIVER_MODESET;
 925 #endif
 926
 927         if (!(driver.driver_features & DRIVER_MODESET))
 928                 driver.get_vblank_timestamp = NULL;
 929
 930         return drm_pci_init(&driver, &i915_pci_driver);
 931 }
 932
 933 static void __exit i915_exit(void)
 934 {
 935         drm_pci_exit(&driver, &i915_pci_driver);
 936 }
 937
 938 module_init(i915_init);
 939 module_exit(i915_exit);
 940
 941 MODULE_AUTHOR(DRIVER_AUTHOR);
 942 MODULE_DESCRIPTION(DRIVER_DESC);
 943 MODULE_LICENSE("GPL and additional rights");
 944
 945 /* We give fast paths for the really cool registers */
 946 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
 947         ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
 948          ((reg) < 0x40000) &&            \
 949          ((reg) != FORCEWAKE) &&         \
 950          ((reg) != ECOBUS))
 951
 952 #define __i915_read(x, y) \
 953 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
 954         u##x val = 0; \
 955         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 956                 gen6_gt_force_wake_get(dev_priv); \
 957                 val = read##y(dev_priv->regs + reg); \
 958                 gen6_gt_force_wake_put(dev_priv); \
 959         } else { \
 960                 val = read##y(dev_priv->regs + reg); \
 961         } \
 962         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
 963         return val; \
 964 }
 965
 966 __i915_read(8, b)
 967 __i915_read(16, w)
 968 __i915_read(32, l)
 969 __i915_read(64, q)
 970 #undef __i915_read
 971
 972 #define __i915_write(x, y) \
 973 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
 974         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
 975         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 976                 __gen6_gt_wait_for_fifo(dev_priv); \
 977         } \
 978         write##y(val, dev_priv->regs + reg); \
 979 }
 980 __i915_write(8, b)
 981 __i915_write(16, w)
 982 __i915_write(32, l)
 983 __i915_write(64, q)
 984 #undef __i915_write