drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include "drm_crtc_helper.h"
  40
  41 static int i915_modeset __read_mostly = -1;
  42 module_param_named(modeset, i915_modeset, int, 0400);
  43 MODULE_PARM_DESC(modeset,
  44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  45                 "1=on, -1=force vga console preference [default])");
  46
  47 unsigned int i915_fbpercrtc __always_unused = 0;
  48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  49
  50 int i915_panel_ignore_lid __read_mostly = 0;
  51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  52 MODULE_PARM_DESC(panel_ignore_lid,
  53                 "Override lid status (0=autodetect [default], 1=lid open, "
  54                 "-1=lid closed)");
  55
  56 unsigned int i915_powersave __read_mostly = 1;
  57 module_param_named(powersave, i915_powersave, int, 0600);
  58 MODULE_PARM_DESC(powersave,
  59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  60
  61 int i915_semaphores __read_mostly = -1;
  62 module_param_named(semaphores, i915_semaphores, int, 0600);
  63 MODULE_PARM_DESC(semaphores,
  64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  65
  66 int i915_enable_rc6 __read_mostly = -1;
  67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
  68 MODULE_PARM_DESC(i915_enable_rc6,
  69                 "Enable power-saving render C-state 6. "
  70                 "Different stages can be selected via bitmask values "
  71                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
  72                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
  73                 "default: -1 (use per-chip default)");
  74
  75 int i915_enable_fbc __read_mostly = -1;
  76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  77 MODULE_PARM_DESC(i915_enable_fbc,
  78                 "Enable frame buffer compression for power savings "
  79                 "(default: -1 (use per-chip default))");
  80
  81 unsigned int i915_lvds_downclock __read_mostly = 0;
  82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  83 MODULE_PARM_DESC(lvds_downclock,
  84                 "Use panel (LVDS/eDP) downclocking for power savings "
  85                 "(default: false)");
  86
  87 int i915_lvds_channel_mode __read_mostly;
  88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
  89 MODULE_PARM_DESC(lvds_channel_mode,
  90                  "Specify LVDS channel mode "
  91                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  92
  93 int i915_panel_use_ssc __read_mostly = -1;
  94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  95 MODULE_PARM_DESC(lvds_use_ssc,
  96                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  97                 "(default: auto from VBT)");
  98
  99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
 100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
 101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
 102                 "Override/Ignore selection of SDVO panel mode in the VBT "
 103                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 104
 105 static bool i915_try_reset __read_mostly = true;
 106 module_param_named(reset, i915_try_reset, bool, 0600);
 107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
 108
 109 bool i915_enable_hangcheck __read_mostly = true;
 110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 111 MODULE_PARM_DESC(enable_hangcheck,
 112                 "Periodically check GPU activity for detecting hangs. "
 113                 "WARNING: Disabling this can cause system wide hangs. "
 114                 "(default: true)");
 115
 116 int i915_enable_ppgtt __read_mostly = -1;
 117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
 118 MODULE_PARM_DESC(i915_enable_ppgtt,
 119                 "Enable PPGTT (default: true)");
 120
 121 static struct drm_driver driver;
 122 extern int intel_agp_enabled;
 123
 124 #define INTEL_VGA_DEVICE(id, info) {            \
 125         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
 126         .class_mask = 0xff0000,                 \
 127         .vendor = 0x8086,                       \
 128         .device = id,                           \
 129         .subvendor = PCI_ANY_ID,                \
 130         .subdevice = PCI_ANY_ID,                \
 131         .driver_data = (unsigned long) info }
 132
 133 static const struct intel_device_info intel_i830_info = {
 134         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
 135         .has_overlay = 1, .overlay_needs_physical = 1,
 136 };
 137
 138 static const struct intel_device_info intel_845g_info = {
 139         .gen = 2,
 140         .has_overlay = 1, .overlay_needs_physical = 1,
 141 };
 142
 143 static const struct intel_device_info intel_i85x_info = {
 144         .gen = 2, .is_i85x = 1, .is_mobile = 1,
 145         .cursor_needs_physical = 1,
 146         .has_overlay = 1, .overlay_needs_physical = 1,
 147 };
 148
 149 static const struct intel_device_info intel_i865g_info = {
 150         .gen = 2,
 151         .has_overlay = 1, .overlay_needs_physical = 1,
 152 };
 153
 154 static const struct intel_device_info intel_i915g_info = {
 155         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
 156         .has_overlay = 1, .overlay_needs_physical = 1,
 157 };
 158 static const struct intel_device_info intel_i915gm_info = {
 159         .gen = 3, .is_mobile = 1,
 160         .cursor_needs_physical = 1,
 161         .has_overlay = 1, .overlay_needs_physical = 1,
 162         .supports_tv = 1,
 163 };
 164 static const struct intel_device_info intel_i945g_info = {
 165         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
 166         .has_overlay = 1, .overlay_needs_physical = 1,
 167 };
 168 static const struct intel_device_info intel_i945gm_info = {
 169         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
 170         .has_hotplug = 1, .cursor_needs_physical = 1,
 171         .has_overlay = 1, .overlay_needs_physical = 1,
 172         .supports_tv = 1,
 173 };
 174
 175 static const struct intel_device_info intel_i965g_info = {
 176         .gen = 4, .is_broadwater = 1,
 177         .has_hotplug = 1,
 178         .has_overlay = 1,
 179 };
 180
 181 static const struct intel_device_info intel_i965gm_info = {
 182         .gen = 4, .is_crestline = 1,
 183         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 184         .has_overlay = 1,
 185         .supports_tv = 1,
 186 };
 187
 188 static const struct intel_device_info intel_g33_info = {
 189         .gen = 3, .is_g33 = 1,
 190         .need_gfx_hws = 1, .has_hotplug = 1,
 191         .has_overlay = 1,
 192 };
 193
 194 static const struct intel_device_info intel_g45_info = {
 195         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 196         .has_pipe_cxsr = 1, .has_hotplug = 1,
 197         .has_bsd_ring = 1,
 198 };
 199
 200 static const struct intel_device_info intel_gm45_info = {
 201         .gen = 4, .is_g4x = 1,
 202         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 203         .has_pipe_cxsr = 1, .has_hotplug = 1,
 204         .supports_tv = 1,
 205         .has_bsd_ring = 1,
 206 };
 207
 208 static const struct intel_device_info intel_pineview_info = {
 209         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 210         .need_gfx_hws = 1, .has_hotplug = 1,
 211         .has_overlay = 1,
 212 };
 213
 214 static const struct intel_device_info intel_ironlake_d_info = {
 215         .gen = 5,
 216         .need_gfx_hws = 1, .has_hotplug = 1,
 217         .has_bsd_ring = 1,
 218         .has_pch_split = 1,
 219 };
 220
 221 static const struct intel_device_info intel_ironlake_m_info = {
 222         .gen = 5, .is_mobile = 1,
 223         .need_gfx_hws = 1, .has_hotplug = 1,
 224         .has_fbc = 1,
 225         .has_bsd_ring = 1,
 226         .has_pch_split = 1,
 227 };
 228
 229 static const struct intel_device_info intel_sandybridge_d_info = {
 230         .gen = 6,
 231         .need_gfx_hws = 1, .has_hotplug = 1,
 232         .has_bsd_ring = 1,
 233         .has_blt_ring = 1,
 234         .has_llc = 1,
 235         .has_pch_split = 1,
 236 };
 237
 238 static const struct intel_device_info intel_sandybridge_m_info = {
 239         .gen = 6, .is_mobile = 1,
 240         .need_gfx_hws = 1, .has_hotplug = 1,
 241         .has_fbc = 1,
 242         .has_bsd_ring = 1,
 243         .has_blt_ring = 1,
 244         .has_llc = 1,
 245         .has_pch_split = 1,
 246 };
 247
 248 static const struct intel_device_info intel_ivybridge_d_info = {
 249         .is_ivybridge = 1, .gen = 7,
 250         .need_gfx_hws = 1, .has_hotplug = 1,
 251         .has_bsd_ring = 1,
 252         .has_blt_ring = 1,
 253         .has_llc = 1,
 254         .has_pch_split = 1,
 255 };
 256
 257 static const struct intel_device_info intel_ivybridge_m_info = {
 258         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
 259         .need_gfx_hws = 1, .has_hotplug = 1,
 260         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
 261         .has_bsd_ring = 1,
 262         .has_blt_ring = 1,
 263         .has_llc = 1,
 264         .has_pch_split = 1,
 265 };
 266
 267 static const struct intel_device_info intel_valleyview_m_info = {
 268         .gen = 7, .is_mobile = 1,
 269         .need_gfx_hws = 1, .has_hotplug = 1,
 270         .has_fbc = 0,
 271         .has_bsd_ring = 1,
 272         .has_blt_ring = 1,
 273         .is_valleyview = 1,
 274 };
 275
 276 static const struct intel_device_info intel_valleyview_d_info = {
 277         .gen = 7,
 278         .need_gfx_hws = 1, .has_hotplug = 1,
 279         .has_fbc = 0,
 280         .has_bsd_ring = 1,
 281         .has_blt_ring = 1,
 282         .is_valleyview = 1,
 283 };
 284
 285 static const struct intel_device_info intel_haswell_d_info = {
 286         .is_haswell = 1, .gen = 7,
 287         .need_gfx_hws = 1, .has_hotplug = 1,
 288         .has_bsd_ring = 1,
 289         .has_blt_ring = 1,
 290         .has_llc = 1,
 291         .has_pch_split = 1,
 292 };
 293
 294 static const struct intel_device_info intel_haswell_m_info = {
 295         .is_haswell = 1, .gen = 7, .is_mobile = 1,
 296         .need_gfx_hws = 1, .has_hotplug = 1,
 297         .has_bsd_ring = 1,
 298         .has_blt_ring = 1,
 299         .has_llc = 1,
 300         .has_pch_split = 1,
 301 };
 302
 303 static const struct pci_device_id pciidlist[] = {               /* aka */
 304         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 305         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 306         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 307         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 308         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 309         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 310         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 311         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 312         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 313         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 314         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 315         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 316         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 317         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 318         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 319         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 320         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 321         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 322         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 323         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 324         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 325         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 326         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 327         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 328         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 329         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 330         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 331         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 332         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 333         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 334         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 335         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 336         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 337         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 338         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 339         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 340         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 341         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 342         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 343         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 344         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 345         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 346         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 347         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
 348         {0, 0, 0}
 349 };
 350
 351 #if defined(CONFIG_DRM_I915_KMS)
 352 MODULE_DEVICE_TABLE(pci, pciidlist);
 353 #endif
 354
 355 #define INTEL_PCH_DEVICE_ID_MASK        0xff00
 356 #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
 357 #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
 358 #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
 359 #define INTEL_PCH_LPT_DEVICE_ID_TYPE    0x8c00
 360
 361 void intel_detect_pch(struct drm_device *dev)
 362 {
 363         struct drm_i915_private *dev_priv = dev->dev_private;
 364         struct pci_dev *pch;
 365
 366         /*
 367          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 368          * make graphics device passthrough work easy for VMM, that only
 369          * need to expose ISA bridge to let driver know the real hardware
 370          * underneath. This is a requirement from virtualization team.
 371          */
 372         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 373         if (pch) {
 374                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 375                         int id;
 376                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 377
 378                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 379                                 dev_priv->pch_type = PCH_IBX;
 380                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 381                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 382                                 dev_priv->pch_type = PCH_CPT;
 383                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 384                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 385                                 /* PantherPoint is CPT compatible */
 386                                 dev_priv->pch_type = PCH_CPT;
 387                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 388                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 389                                 dev_priv->pch_type = PCH_LPT;
 390                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 391                         }
 392                 }
 393                 pci_dev_put(pch);
 394         }
 395 }
 396
 397 bool i915_semaphore_is_enabled(struct drm_device *dev)
 398 {
 399         if (INTEL_INFO(dev)->gen < 6)
 400                 return 0;
 401
 402         if (i915_semaphores >= 0)
 403                 return i915_semaphores;
 404
 405         /* Enable semaphores on SNB when IO remapping is off */
 406         if (INTEL_INFO(dev)->gen == 6)
 407                 return !intel_iommu_enabled;
 408
 409         return 1;
 410 }
 411
 412 void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 413 {
 414         int count;
 415
 416         count = 0;
 417         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
 418                 udelay(10);
 419
 420         I915_WRITE_NOTRACE(FORCEWAKE, 1);
 421         POSTING_READ(FORCEWAKE);
 422
 423         count = 0;
 424         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
 425                 udelay(10);
 426 }
 427
 428 void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
 429 {
 430         int count;
 431
 432         count = 0;
 433         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
 434                 udelay(10);
 435
 436         I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1);
 437         POSTING_READ(FORCEWAKE_MT);
 438
 439         count = 0;
 440         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
 441                 udelay(10);
 442 }
 443
 444 /*
 445  * Generally this is called implicitly by the register read function. However,
 446  * if some sequence requires the GT to not power down then this function should
 447  * be called at the beginning of the sequence followed by a call to
 448  * gen6_gt_force_wake_put() at the end of the sequence.
 449  */
 450 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 451 {
 452         unsigned long irqflags;
 453
 454         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 455         if (dev_priv->forcewake_count++ == 0)
 456                 dev_priv->display.force_wake_get(dev_priv);
 457         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 458 }
 459
 460 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 461 {
 462         u32 gtfifodbg;
 463         gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
 464         if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
 465              "MMIO read or write has been dropped %x\n", gtfifodbg))
 466                 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
 467 }
 468
 469 void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 470 {
 471         I915_WRITE_NOTRACE(FORCEWAKE, 0);
 472         /* The below doubles as a POSTING_READ */
 473         gen6_gt_check_fifodbg(dev_priv);
 474 }
 475
 476 void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
 477 {
 478         I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0);
 479         /* The below doubles as a POSTING_READ */
 480         gen6_gt_check_fifodbg(dev_priv);
 481 }
 482
 483 /*
 484  * see gen6_gt_force_wake_get()
 485  */
 486 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 487 {
 488         unsigned long irqflags;
 489
 490         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 491         if (--dev_priv->forcewake_count == 0)
 492                 dev_priv->display.force_wake_put(dev_priv);
 493         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 494 }
 495
 496 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 497 {
 498         int ret = 0;
 499
 500         if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 501                 int loop = 500;
 502                 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 503                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 504                         udelay(10);
 505                         fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 506                 }
 507                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 508                         ++ret;
 509                 dev_priv->gt_fifo_count = fifo;
 510         }
 511         dev_priv->gt_fifo_count--;
 512
 513         return ret;
 514 }
 515
 516 void vlv_force_wake_get(struct drm_i915_private *dev_priv)
 517 {
 518         int count;
 519
 520         count = 0;
 521
 522         /* Already awake? */
 523         if ((I915_READ(0x130094) & 0xa1) == 0xa1)
 524                 return;
 525
 526         I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff);
 527         POSTING_READ(FORCEWAKE_VLV);
 528
 529         count = 0;
 530         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0)
 531                 udelay(10);
 532 }
 533
 534 void vlv_force_wake_put(struct drm_i915_private *dev_priv)
 535 {
 536         I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000);
 537         /* FIXME: confirm VLV behavior with Punit folks */
 538         POSTING_READ(FORCEWAKE_VLV);
 539 }
 540
 541 static int i915_drm_freeze(struct drm_device *dev)
 542 {
 543         struct drm_i915_private *dev_priv = dev->dev_private;
 544
 545         drm_kms_helper_poll_disable(dev);
 546
 547         pci_save_state(dev->pdev);
 548
 549         /* If KMS is active, we do the leavevt stuff here */
 550         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 551                 int error = i915_gem_idle(dev);
 552                 if (error) {
 553                         dev_err(&dev->pdev->dev,
 554                                 "GEM idle failed, resume might fail\n");
 555                         return error;
 556                 }
 557                 drm_irq_uninstall(dev);
 558         }
 559
 560         i915_save_state(dev);
 561
 562         intel_opregion_fini(dev);
 563
 564         /* Modeset on resume, not lid events */
 565         dev_priv->modeset_on_lid = 0;
 566
 567         console_lock();
 568         intel_fbdev_set_suspend(dev, 1);
 569         console_unlock();
 570
 571         return 0;
 572 }
 573
 574 int i915_suspend(struct drm_device *dev, pm_message_t state)
 575 {
 576         int error;
 577
 578         if (!dev || !dev->dev_private) {
 579                 DRM_ERROR("dev: %p\n", dev);
 580                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 581                 return -ENODEV;
 582         }
 583
 584         if (state.event == PM_EVENT_PRETHAW)
 585                 return 0;
 586
 587
 588         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 589                 return 0;
 590
 591         error = i915_drm_freeze(dev);
 592         if (error)
 593                 return error;
 594
 595         if (state.event == PM_EVENT_SUSPEND) {
 596                 /* Shut down the device */
 597                 pci_disable_device(dev->pdev);
 598                 pci_set_power_state(dev->pdev, PCI_D3hot);
 599         }
 600
 601         return 0;
 602 }
 603
 604 static int i915_drm_thaw(struct drm_device *dev)
 605 {
 606         struct drm_i915_private *dev_priv = dev->dev_private;
 607         int error = 0;
 608
 609         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 610                 mutex_lock(&dev->struct_mutex);
 611                 i915_gem_restore_gtt_mappings(dev);
 612                 mutex_unlock(&dev->struct_mutex);
 613         }
 614
 615         i915_restore_state(dev);
 616         intel_opregion_setup(dev);
 617
 618         /* KMS EnterVT equivalent */
 619         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 620                 mutex_lock(&dev->struct_mutex);
 621                 dev_priv->mm.suspended = 0;
 622
 623                 error = i915_gem_init_hw(dev);
 624                 mutex_unlock(&dev->struct_mutex);
 625
 626                 if (HAS_PCH_SPLIT(dev))
 627                         ironlake_init_pch_refclk(dev);
 628
 629                 drm_mode_config_reset(dev);
 630                 drm_irq_install(dev);
 631
 632                 /* Resume the modeset for every activated CRTC */
 633                 mutex_lock(&dev->mode_config.mutex);
 634                 drm_helper_resume_force_mode(dev);
 635                 mutex_unlock(&dev->mode_config.mutex);
 636
 637                 if (IS_IRONLAKE_M(dev))
 638                         ironlake_enable_rc6(dev);
 639         }
 640
 641         intel_opregion_init(dev);
 642
 643         dev_priv->modeset_on_lid = 0;
 644
 645         console_lock();
 646         intel_fbdev_set_suspend(dev, 0);
 647         console_unlock();
 648         return error;
 649 }
 650
 651 int i915_resume(struct drm_device *dev)
 652 {
 653         int ret;
 654
 655         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 656                 return 0;
 657
 658         if (pci_enable_device(dev->pdev))
 659                 return -EIO;
 660
 661         pci_set_master(dev->pdev);
 662
 663         ret = i915_drm_thaw(dev);
 664         if (ret)
 665                 return ret;
 666
 667         drm_kms_helper_poll_enable(dev);
 668         return 0;
 669 }
 670
 671 static int i8xx_do_reset(struct drm_device *dev, u8 flags)
 672 {
 673         struct drm_i915_private *dev_priv = dev->dev_private;
 674
 675         if (IS_I85X(dev))
 676                 return -ENODEV;
 677
 678         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 679         POSTING_READ(D_STATE);
 680
 681         if (IS_I830(dev) || IS_845G(dev)) {
 682                 I915_WRITE(DEBUG_RESET_I830,
 683                            DEBUG_RESET_DISPLAY |
 684                            DEBUG_RESET_RENDER |
 685                            DEBUG_RESET_FULL);
 686                 POSTING_READ(DEBUG_RESET_I830);
 687                 msleep(1);
 688
 689                 I915_WRITE(DEBUG_RESET_I830, 0);
 690                 POSTING_READ(DEBUG_RESET_I830);
 691         }
 692
 693         msleep(1);
 694
 695         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 696         POSTING_READ(D_STATE);
 697
 698         return 0;
 699 }
 700
 701 static int i965_reset_complete(struct drm_device *dev)
 702 {
 703         u8 gdrst;
 704         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 705         return gdrst & 0x1;
 706 }
 707
 708 static int i965_do_reset(struct drm_device *dev, u8 flags)
 709 {
 710         u8 gdrst;
 711
 712         /*
 713          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 714          * well as the reset bit (GR/bit 0).  Setting the GR bit
 715          * triggers the reset; when done, the hardware will clear it.
 716          */
 717         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 718         pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
 719
 720         return wait_for(i965_reset_complete(dev), 500);
 721 }
 722
 723 static int ironlake_do_reset(struct drm_device *dev, u8 flags)
 724 {
 725         struct drm_i915_private *dev_priv = dev->dev_private;
 726         u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 727         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
 728         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 729 }
 730
 731 static int gen6_do_reset(struct drm_device *dev, u8 flags)
 732 {
 733         struct drm_i915_private *dev_priv = dev->dev_private;
 734         int     ret;
 735         unsigned long irqflags;
 736
 737         /* Hold gt_lock across reset to prevent any register access
 738          * with forcewake not set correctly
 739          */
 740         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 741
 742         /* Reset the chip */
 743
 744         /* GEN6_GDRST is not in the gt power well, no need to check
 745          * for fifo space for the write or forcewake the chip for
 746          * the read
 747          */
 748         I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
 749
 750         /* Spin waiting for the device to ack the reset request */
 751         ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 752
 753         /* If reset with a user forcewake, try to restore, otherwise turn it off */
 754         if (dev_priv->forcewake_count)
 755                 dev_priv->display.force_wake_get(dev_priv);
 756         else
 757                 dev_priv->display.force_wake_put(dev_priv);
 758
 759         /* Restore fifo count */
 760         dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 761
 762         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 763         return ret;
 764 }
 765
 766 /**
 767  * i915_reset - reset chip after a hang
 768  * @dev: drm device to reset
 769  * @flags: reset domains
 770  *
 771  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 772  * reset or otherwise an error code.
 773  *
 774  * Procedure is fairly simple:
 775  *   - reset the chip using the reset reg
 776  *   - re-init context state
 777  *   - re-init hardware status page
 778  *   - re-init ring buffer
 779  *   - re-init interrupt state
 780  *   - re-init display
 781  */
 782 int i915_reset(struct drm_device *dev, u8 flags)
 783 {
 784         drm_i915_private_t *dev_priv = dev->dev_private;
 785         /*
 786          * We really should only reset the display subsystem if we actually
 787          * need to
 788          */
 789         bool need_display = true;
 790         int ret;
 791
 792         if (!i915_try_reset)
 793                 return 0;
 794
 795         if (!mutex_trylock(&dev->struct_mutex))
 796                 return -EBUSY;
 797
 798         i915_gem_reset(dev);
 799
 800         ret = -ENODEV;
 801         if (get_seconds() - dev_priv->last_gpu_reset < 5) {
 802                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 803         } else switch (INTEL_INFO(dev)->gen) {
 804         case 7:
 805         case 6:
 806                 ret = gen6_do_reset(dev, flags);
 807                 break;
 808         case 5:
 809                 ret = ironlake_do_reset(dev, flags);
 810                 break;
 811         case 4:
 812                 ret = i965_do_reset(dev, flags);
 813                 break;
 814         case 2:
 815                 ret = i8xx_do_reset(dev, flags);
 816                 break;
 817         }
 818         dev_priv->last_gpu_reset = get_seconds();
 819         if (ret) {
 820                 DRM_ERROR("Failed to reset chip.\n");
 821                 mutex_unlock(&dev->struct_mutex);
 822                 return ret;
 823         }
 824
 825         /* Ok, now get things going again... */
 826
 827         /*
 828          * Everything depends on having the GTT running, so we need to start
 829          * there.  Fortunately we don't need to do this unless we reset the
 830          * chip at a PCI level.
 831          *
 832          * Next we need to restore the context, but we don't use those
 833          * yet either...
 834          *
 835          * Ring buffer needs to be re-initialized in the KMS case, or if X
 836          * was running at the time of the reset (i.e. we weren't VT
 837          * switched away).
 838          */
 839         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 840                         !dev_priv->mm.suspended) {
 841                 dev_priv->mm.suspended = 0;
 842
 843                 i915_gem_init_swizzling(dev);
 844
 845                 dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
 846                 if (HAS_BSD(dev))
 847                     dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
 848                 if (HAS_BLT(dev))
 849                     dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
 850
 851                 i915_gem_init_ppgtt(dev);
 852
 853                 mutex_unlock(&dev->struct_mutex);
 854
 855                 if (drm_core_check_feature(dev, DRIVER_MODESET))
 856                         intel_modeset_init_hw(dev);
 857
 858                 drm_irq_uninstall(dev);
 859                 drm_mode_config_reset(dev);
 860                 drm_irq_install(dev);
 861
 862                 mutex_lock(&dev->struct_mutex);
 863         }
 864
 865         mutex_unlock(&dev->struct_mutex);
 866
 867         /*
 868          * Perform a full modeset as on later generations, e.g. Ironlake, we may
 869          * need to retrain the display link and cannot just restore the register
 870          * values.
 871          */
 872         if (need_display) {
 873                 mutex_lock(&dev->mode_config.mutex);
 874                 drm_helper_resume_force_mode(dev);
 875                 mutex_unlock(&dev->mode_config.mutex);
 876         }
 877
 878         return 0;
 879 }
 880
 881
 882 static int __devinit
 883 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 884 {
 885         /* Only bind to function 0 of the device. Early generations
 886          * used function 1 as a placeholder for multi-head. This causes
 887          * us confusion instead, especially on the systems where both
 888          * functions have the same PCI-ID!
 889          */
 890         if (PCI_FUNC(pdev->devfn))
 891                 return -ENODEV;
 892
 893         return drm_get_pci_dev(pdev, ent, &driver);
 894 }
 895
 896 static void
 897 i915_pci_remove(struct pci_dev *pdev)
 898 {
 899         struct drm_device *dev = pci_get_drvdata(pdev);
 900
 901         drm_put_dev(dev);
 902 }
 903
 904 static int i915_pm_suspend(struct device *dev)
 905 {
 906         struct pci_dev *pdev = to_pci_dev(dev);
 907         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 908         int error;
 909
 910         if (!drm_dev || !drm_dev->dev_private) {
 911                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 912                 return -ENODEV;
 913         }
 914
 915         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 916                 return 0;
 917
 918         error = i915_drm_freeze(drm_dev);
 919         if (error)
 920                 return error;
 921
 922         pci_disable_device(pdev);
 923         pci_set_power_state(pdev, PCI_D3hot);
 924
 925         return 0;
 926 }
 927
 928 static int i915_pm_resume(struct device *dev)
 929 {
 930         struct pci_dev *pdev = to_pci_dev(dev);
 931         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 932
 933         return i915_resume(drm_dev);
 934 }
 935
 936 static int i915_pm_freeze(struct device *dev)
 937 {
 938         struct pci_dev *pdev = to_pci_dev(dev);
 939         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 940
 941         if (!drm_dev || !drm_dev->dev_private) {
 942                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 943                 return -ENODEV;
 944         }
 945
 946         return i915_drm_freeze(drm_dev);
 947 }
 948
 949 static int i915_pm_thaw(struct device *dev)
 950 {
 951         struct pci_dev *pdev = to_pci_dev(dev);
 952         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 953
 954         return i915_drm_thaw(drm_dev);
 955 }
 956
 957 static int i915_pm_poweroff(struct device *dev)
 958 {
 959         struct pci_dev *pdev = to_pci_dev(dev);
 960         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 961
 962         return i915_drm_freeze(drm_dev);
 963 }
 964
 965 static const struct dev_pm_ops i915_pm_ops = {
 966         .suspend = i915_pm_suspend,
 967         .resume = i915_pm_resume,
 968         .freeze = i915_pm_freeze,
 969         .thaw = i915_pm_thaw,
 970         .poweroff = i915_pm_poweroff,
 971         .restore = i915_pm_resume,
 972 };
 973
 974 static struct vm_operations_struct i915_gem_vm_ops = {
 975         .fault = i915_gem_fault,
 976         .open = drm_gem_vm_open,
 977         .close = drm_gem_vm_close,
 978 };
 979
 980 static const struct file_operations i915_driver_fops = {
 981         .owner = THIS_MODULE,
 982         .open = drm_open,
 983         .release = drm_release,
 984         .unlocked_ioctl = drm_ioctl,
 985         .mmap = drm_gem_mmap,
 986         .poll = drm_poll,
 987         .fasync = drm_fasync,
 988         .read = drm_read,
 989 #ifdef CONFIG_COMPAT
 990         .compat_ioctl = i915_compat_ioctl,
 991 #endif
 992         .llseek = noop_llseek,
 993 };
 994
 995 static struct drm_driver driver = {
 996         /* Don't use MTRRs here; the Xserver or userspace app should
 997          * deal with them for Intel hardware.
 998          */
 999         .driver_features =
1000             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
1001             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
1002         .load = i915_driver_load,
1003         .unload = i915_driver_unload,
1004         .open = i915_driver_open,
1005         .lastclose = i915_driver_lastclose,
1006         .preclose = i915_driver_preclose,
1007         .postclose = i915_driver_postclose,
1008
1009         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1010         .suspend = i915_suspend,
1011         .resume = i915_resume,
1012
1013         .device_is_agp = i915_driver_device_is_agp,
1014         .reclaim_buffers = drm_core_reclaim_buffers,
1015         .master_create = i915_master_create,
1016         .master_destroy = i915_master_destroy,
1017 #if defined(CONFIG_DEBUG_FS)
1018         .debugfs_init = i915_debugfs_init,
1019         .debugfs_cleanup = i915_debugfs_cleanup,
1020 #endif
1021         .gem_init_object = i915_gem_init_object,
1022         .gem_free_object = i915_gem_free_object,
1023         .gem_vm_ops = &i915_gem_vm_ops,
1024         .dumb_create = i915_gem_dumb_create,
1025         .dumb_map_offset = i915_gem_mmap_gtt,
1026         .dumb_destroy = i915_gem_dumb_destroy,
1027         .ioctls = i915_ioctls,
1028         .fops = &i915_driver_fops,
1029         .name = DRIVER_NAME,
1030         .desc = DRIVER_DESC,
1031         .date = DRIVER_DATE,
1032         .major = DRIVER_MAJOR,
1033         .minor = DRIVER_MINOR,
1034         .patchlevel = DRIVER_PATCHLEVEL,
1035 };
1036
1037 static struct pci_driver i915_pci_driver = {
1038         .name = DRIVER_NAME,
1039         .id_table = pciidlist,
1040         .probe = i915_pci_probe,
1041         .remove = i915_pci_remove,
1042         .driver.pm = &i915_pm_ops,
1043 };
1044
1045 static int __init i915_init(void)
1046 {
1047         if (!intel_agp_enabled) {
1048                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
1049                 return -ENODEV;
1050         }
1051
1052         driver.num_ioctls = i915_max_ioctl;
1053
1054         /*
1055          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1056          * explicitly disabled with the module pararmeter.
1057          *
1058          * Otherwise, just follow the parameter (defaulting to off).
1059          *
1060          * Allow optional vga_text_mode_force boot option to override
1061          * the default behavior.
1062          */
1063 #if defined(CONFIG_DRM_I915_KMS)
1064         if (i915_modeset != 0)
1065                 driver.driver_features |= DRIVER_MODESET;
1066 #endif
1067         if (i915_modeset == 1)
1068                 driver.driver_features |= DRIVER_MODESET;
1069
1070 #ifdef CONFIG_VGA_CONSOLE
1071         if (vgacon_text_force() && i915_modeset == -1)
1072                 driver.driver_features &= ~DRIVER_MODESET;
1073 #endif
1074
1075         if (!(driver.driver_features & DRIVER_MODESET))
1076                 driver.get_vblank_timestamp = NULL;
1077
1078         return drm_pci_init(&driver, &i915_pci_driver);
1079 }
1080
1081 static void __exit i915_exit(void)
1082 {
1083         drm_pci_exit(&driver, &i915_pci_driver);
1084 }
1085
1086 module_init(i915_init);
1087 module_exit(i915_exit);
1088
1089 MODULE_AUTHOR(DRIVER_AUTHOR);
1090 MODULE_DESCRIPTION(DRIVER_DESC);
1091 MODULE_LICENSE("GPL and additional rights");
1092
1093 /* We give fast paths for the really cool registers */
1094 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1095        (((dev_priv)->info->gen >= 6) && \
1096         ((reg) < 0x40000) &&            \
1097         ((reg) != FORCEWAKE)) && \
1098        (!IS_VALLEYVIEW((dev_priv)->dev))
1099
1100 #define __i915_read(x, y) \
1101 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1102         u##x val = 0; \
1103         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1104                 unsigned long irqflags; \
1105                 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1106                 if (dev_priv->forcewake_count == 0) \
1107                         dev_priv->display.force_wake_get(dev_priv); \
1108                 val = read##y(dev_priv->regs + reg); \
1109                 if (dev_priv->forcewake_count == 0) \
1110                         dev_priv->display.force_wake_put(dev_priv); \
1111                 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1112         } else { \
1113                 val = read##y(dev_priv->regs + reg); \
1114         } \
1115         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1116         return val; \
1117 }
1118
1119 __i915_read(8, b)
1120 __i915_read(16, w)
1121 __i915_read(32, l)
1122 __i915_read(64, q)
1123 #undef __i915_read
1124
1125 #define __i915_write(x, y) \
1126 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1127         u32 __fifo_ret = 0; \
1128         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1129         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1130                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1131         } \
1132         write##y(val, dev_priv->regs + reg); \
1133         if (unlikely(__fifo_ret)) { \
1134                 gen6_gt_check_fifodbg(dev_priv); \
1135         } \
1136 }
1137 __i915_write(8, b)
1138 __i915_write(16, w)
1139 __i915_write(32, l)
1140 __i915_write(64, q)
1141 #undef __i915_write