drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include "drm_crtc_helper.h"
  40
  41 static int i915_modeset __read_mostly = -1;
  42 module_param_named(modeset, i915_modeset, int, 0400);
  43 MODULE_PARM_DESC(modeset,
  44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  45                 "1=on, -1=force vga console preference [default])");
  46
  47 unsigned int i915_fbpercrtc __always_unused = 0;
  48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  49
  50 int i915_panel_ignore_lid __read_mostly = 0;
  51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  52 MODULE_PARM_DESC(panel_ignore_lid,
  53                 "Override lid status (0=autodetect [default], 1=lid open, "
  54                 "-1=lid closed)");
  55
  56 unsigned int i915_powersave __read_mostly = 1;
  57 module_param_named(powersave, i915_powersave, int, 0600);
  58 MODULE_PARM_DESC(powersave,
  59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  60
  61 int i915_semaphores __read_mostly = -1;
  62 module_param_named(semaphores, i915_semaphores, int, 0600);
  63 MODULE_PARM_DESC(semaphores,
  64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  65
  66 int i915_enable_rc6 __read_mostly = -1;
  67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
  68 MODULE_PARM_DESC(i915_enable_rc6,
  69                 "Enable power-saving render C-state 6. "
  70                 "Different stages can be selected via bitmask values "
  71                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
  72                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
  73                 "default: -1 (use per-chip default)");
  74
  75 int i915_enable_fbc __read_mostly = -1;
  76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  77 MODULE_PARM_DESC(i915_enable_fbc,
  78                 "Enable frame buffer compression for power savings "
  79                 "(default: -1 (use per-chip default))");
  80
  81 unsigned int i915_lvds_downclock __read_mostly = 0;
  82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  83 MODULE_PARM_DESC(lvds_downclock,
  84                 "Use panel (LVDS/eDP) downclocking for power savings "
  85                 "(default: false)");
  86
  87 int i915_lvds_channel_mode __read_mostly;
  88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
  89 MODULE_PARM_DESC(lvds_channel_mode,
  90                  "Specify LVDS channel mode "
  91                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  92
  93 int i915_panel_use_ssc __read_mostly = -1;
  94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  95 MODULE_PARM_DESC(lvds_use_ssc,
  96                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  97                 "(default: auto from VBT)");
  98
  99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
 100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
 101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
 102                 "Override/Ignore selection of SDVO panel mode in the VBT "
 103                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 104
 105 static bool i915_try_reset __read_mostly = true;
 106 module_param_named(reset, i915_try_reset, bool, 0600);
 107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
 108
 109 bool i915_enable_hangcheck __read_mostly = true;
 110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 111 MODULE_PARM_DESC(enable_hangcheck,
 112                 "Periodically check GPU activity for detecting hangs. "
 113                 "WARNING: Disabling this can cause system wide hangs. "
 114                 "(default: true)");
 115
 116 int i915_enable_ppgtt __read_mostly = -1;
 117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
 118 MODULE_PARM_DESC(i915_enable_ppgtt,
 119                 "Enable PPGTT (default: true)");
 120
 121 static struct drm_driver driver;
 122 extern int intel_agp_enabled;
 123
 124 #define INTEL_VGA_DEVICE(id, info) {            \
 125         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
 126         .class_mask = 0xff0000,                 \
 127         .vendor = 0x8086,                       \
 128         .device = id,                           \
 129         .subvendor = PCI_ANY_ID,                \
 130         .subdevice = PCI_ANY_ID,                \
 131         .driver_data = (unsigned long) info }
 132
 133 static const struct intel_device_info intel_i830_info = {
 134         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
 135         .has_overlay = 1, .overlay_needs_physical = 1,
 136 };
 137
 138 static const struct intel_device_info intel_845g_info = {
 139         .gen = 2,
 140         .has_overlay = 1, .overlay_needs_physical = 1,
 141 };
 142
 143 static const struct intel_device_info intel_i85x_info = {
 144         .gen = 2, .is_i85x = 1, .is_mobile = 1,
 145         .cursor_needs_physical = 1,
 146         .has_overlay = 1, .overlay_needs_physical = 1,
 147 };
 148
 149 static const struct intel_device_info intel_i865g_info = {
 150         .gen = 2,
 151         .has_overlay = 1, .overlay_needs_physical = 1,
 152 };
 153
 154 static const struct intel_device_info intel_i915g_info = {
 155         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
 156         .has_overlay = 1, .overlay_needs_physical = 1,
 157 };
 158 static const struct intel_device_info intel_i915gm_info = {
 159         .gen = 3, .is_mobile = 1,
 160         .cursor_needs_physical = 1,
 161         .has_overlay = 1, .overlay_needs_physical = 1,
 162         .supports_tv = 1,
 163 };
 164 static const struct intel_device_info intel_i945g_info = {
 165         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
 166         .has_overlay = 1, .overlay_needs_physical = 1,
 167 };
 168 static const struct intel_device_info intel_i945gm_info = {
 169         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
 170         .has_hotplug = 1, .cursor_needs_physical = 1,
 171         .has_overlay = 1, .overlay_needs_physical = 1,
 172         .supports_tv = 1,
 173 };
 174
 175 static const struct intel_device_info intel_i965g_info = {
 176         .gen = 4, .is_broadwater = 1,
 177         .has_hotplug = 1,
 178         .has_overlay = 1,
 179 };
 180
 181 static const struct intel_device_info intel_i965gm_info = {
 182         .gen = 4, .is_crestline = 1,
 183         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 184         .has_overlay = 1,
 185         .supports_tv = 1,
 186 };
 187
 188 static const struct intel_device_info intel_g33_info = {
 189         .gen = 3, .is_g33 = 1,
 190         .need_gfx_hws = 1, .has_hotplug = 1,
 191         .has_overlay = 1,
 192 };
 193
 194 static const struct intel_device_info intel_g45_info = {
 195         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 196         .has_pipe_cxsr = 1, .has_hotplug = 1,
 197         .has_bsd_ring = 1,
 198 };
 199
 200 static const struct intel_device_info intel_gm45_info = {
 201         .gen = 4, .is_g4x = 1,
 202         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 203         .has_pipe_cxsr = 1, .has_hotplug = 1,
 204         .supports_tv = 1,
 205         .has_bsd_ring = 1,
 206 };
 207
 208 static const struct intel_device_info intel_pineview_info = {
 209         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 210         .need_gfx_hws = 1, .has_hotplug = 1,
 211         .has_overlay = 1,
 212 };
 213
 214 static const struct intel_device_info intel_ironlake_d_info = {
 215         .gen = 5,
 216         .need_gfx_hws = 1, .has_hotplug = 1,
 217         .has_bsd_ring = 1,
 218         .has_pch_split = 1,
 219 };
 220
 221 static const struct intel_device_info intel_ironlake_m_info = {
 222         .gen = 5, .is_mobile = 1,
 223         .need_gfx_hws = 1, .has_hotplug = 1,
 224         .has_fbc = 1,
 225         .has_bsd_ring = 1,
 226         .has_pch_split = 1,
 227 };
 228
 229 static const struct intel_device_info intel_sandybridge_d_info = {
 230         .gen = 6,
 231         .need_gfx_hws = 1, .has_hotplug = 1,
 232         .has_bsd_ring = 1,
 233         .has_blt_ring = 1,
 234         .has_llc = 1,
 235         .has_pch_split = 1,
 236 };
 237
 238 static const struct intel_device_info intel_sandybridge_m_info = {
 239         .gen = 6, .is_mobile = 1,
 240         .need_gfx_hws = 1, .has_hotplug = 1,
 241         .has_fbc = 1,
 242         .has_bsd_ring = 1,
 243         .has_blt_ring = 1,
 244         .has_llc = 1,
 245         .has_pch_split = 1,
 246 };
 247
 248 static const struct intel_device_info intel_ivybridge_d_info = {
 249         .is_ivybridge = 1, .gen = 7,
 250         .need_gfx_hws = 1, .has_hotplug = 1,
 251         .has_bsd_ring = 1,
 252         .has_blt_ring = 1,
 253         .has_llc = 1,
 254         .has_pch_split = 1,
 255 };
 256
 257 static const struct intel_device_info intel_ivybridge_m_info = {
 258         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
 259         .need_gfx_hws = 1, .has_hotplug = 1,
 260         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
 261         .has_bsd_ring = 1,
 262         .has_blt_ring = 1,
 263         .has_llc = 1,
 264         .has_pch_split = 1,
 265 };
 266
 267 static const struct intel_device_info intel_valleyview_m_info = {
 268         .gen = 7, .is_mobile = 1,
 269         .need_gfx_hws = 1, .has_hotplug = 1,
 270         .has_fbc = 0,
 271         .has_bsd_ring = 1,
 272         .has_blt_ring = 1,
 273         .is_valleyview = 1,
 274 };
 275
 276 static const struct intel_device_info intel_valleyview_d_info = {
 277         .gen = 7,
 278         .need_gfx_hws = 1, .has_hotplug = 1,
 279         .has_fbc = 0,
 280         .has_bsd_ring = 1,
 281         .has_blt_ring = 1,
 282         .is_valleyview = 1,
 283 };
 284
 285 static const struct intel_device_info intel_haswell_d_info = {
 286         .is_haswell = 1, .gen = 7,
 287         .need_gfx_hws = 1, .has_hotplug = 1,
 288         .has_bsd_ring = 1,
 289         .has_blt_ring = 1,
 290         .has_llc = 1,
 291         .has_pch_split = 1,
 292 };
 293
 294 static const struct intel_device_info intel_haswell_m_info = {
 295         .is_haswell = 1, .gen = 7, .is_mobile = 1,
 296         .need_gfx_hws = 1, .has_hotplug = 1,
 297         .has_bsd_ring = 1,
 298         .has_blt_ring = 1,
 299         .has_llc = 1,
 300         .has_pch_split = 1,
 301 };
 302
 303 static const struct pci_device_id pciidlist[] = {               /* aka */
 304         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 305         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 306         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 307         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 308         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 309         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 310         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 311         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 312         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 313         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 314         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 315         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 316         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 317         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 318         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 319         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 320         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 321         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 322         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 323         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 324         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 325         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 326         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 327         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 328         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 329         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 330         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 331         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 332         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 333         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 334         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 335         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 336         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 337         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 338         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 339         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 340         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 341         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 342         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 343         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 344         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 345         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 346         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 347         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
 348         INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
 349         INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
 350         INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
 351         INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
 352         INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
 353         INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
 354         INTEL_VGA_DEVICE(0x0c16, &intel_haswell_d_info), /* SDV */
 355         {0, 0, 0}
 356 };
 357
 358 #if defined(CONFIG_DRM_I915_KMS)
 359 MODULE_DEVICE_TABLE(pci, pciidlist);
 360 #endif
 361
 362 #define INTEL_PCH_DEVICE_ID_MASK        0xff00
 363 #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
 364 #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
 365 #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
 366 #define INTEL_PCH_LPT_DEVICE_ID_TYPE    0x8c00
 367
 368 void intel_detect_pch(struct drm_device *dev)
 369 {
 370         struct drm_i915_private *dev_priv = dev->dev_private;
 371         struct pci_dev *pch;
 372
 373         /*
 374          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 375          * make graphics device passthrough work easy for VMM, that only
 376          * need to expose ISA bridge to let driver know the real hardware
 377          * underneath. This is a requirement from virtualization team.
 378          */
 379         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 380         if (pch) {
 381                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 382                         int id;
 383                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 384
 385                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 386                                 dev_priv->pch_type = PCH_IBX;
 387                                 dev_priv->num_pch_pll = 2;
 388                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 389                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 390                                 dev_priv->pch_type = PCH_CPT;
 391                                 dev_priv->num_pch_pll = 2;
 392                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 393                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 394                                 /* PantherPoint is CPT compatible */
 395                                 dev_priv->pch_type = PCH_CPT;
 396                                 dev_priv->num_pch_pll = 2;
 397                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 398                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 399                                 dev_priv->pch_type = PCH_LPT;
 400                                 dev_priv->num_pch_pll = 0;
 401                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 402                         }
 403                         BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
 404                 }
 405                 pci_dev_put(pch);
 406         }
 407 }
 408
 409 bool i915_semaphore_is_enabled(struct drm_device *dev)
 410 {
 411         if (INTEL_INFO(dev)->gen < 6)
 412                 return 0;
 413
 414         if (i915_semaphores >= 0)
 415                 return i915_semaphores;
 416
 417 #ifdef CONFIG_INTEL_IOMMU
 418         /* Enable semaphores on SNB when IO remapping is off */
 419         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 420                 return false;
 421 #endif
 422
 423         return 1;
 424 }
 425
 426 void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 427 {
 428         int count;
 429
 430         count = 0;
 431         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
 432                 udelay(10);
 433
 434         I915_WRITE_NOTRACE(FORCEWAKE, 1);
 435         POSTING_READ(FORCEWAKE);
 436
 437         count = 0;
 438         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
 439                 udelay(10);
 440 }
 441
 442 void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
 443 {
 444         int count;
 445
 446         count = 0;
 447         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
 448                 udelay(10);
 449
 450         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1));
 451         POSTING_READ(FORCEWAKE_MT);
 452
 453         count = 0;
 454         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
 455                 udelay(10);
 456 }
 457
 458 /*
 459  * Generally this is called implicitly by the register read function. However,
 460  * if some sequence requires the GT to not power down then this function should
 461  * be called at the beginning of the sequence followed by a call to
 462  * gen6_gt_force_wake_put() at the end of the sequence.
 463  */
 464 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 465 {
 466         unsigned long irqflags;
 467
 468         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 469         if (dev_priv->forcewake_count++ == 0)
 470                 dev_priv->display.force_wake_get(dev_priv);
 471         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 472 }
 473
 474 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 475 {
 476         u32 gtfifodbg;
 477         gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
 478         if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
 479              "MMIO read or write has been dropped %x\n", gtfifodbg))
 480                 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
 481 }
 482
 483 void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 484 {
 485         I915_WRITE_NOTRACE(FORCEWAKE, 0);
 486         /* The below doubles as a POSTING_READ */
 487         gen6_gt_check_fifodbg(dev_priv);
 488 }
 489
 490 void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
 491 {
 492         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1));
 493         /* The below doubles as a POSTING_READ */
 494         gen6_gt_check_fifodbg(dev_priv);
 495 }
 496
 497 /*
 498  * see gen6_gt_force_wake_get()
 499  */
 500 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 501 {
 502         unsigned long irqflags;
 503
 504         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 505         if (--dev_priv->forcewake_count == 0)
 506                 dev_priv->display.force_wake_put(dev_priv);
 507         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 508 }
 509
 510 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 511 {
 512         int ret = 0;
 513
 514         if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 515                 int loop = 500;
 516                 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 517                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 518                         udelay(10);
 519                         fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 520                 }
 521                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 522                         ++ret;
 523                 dev_priv->gt_fifo_count = fifo;
 524         }
 525         dev_priv->gt_fifo_count--;
 526
 527         return ret;
 528 }
 529
 530 void vlv_force_wake_get(struct drm_i915_private *dev_priv)
 531 {
 532         int count;
 533
 534         count = 0;
 535
 536         /* Already awake? */
 537         if ((I915_READ(0x130094) & 0xa1) == 0xa1)
 538                 return;
 539
 540         I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff);
 541         POSTING_READ(FORCEWAKE_VLV);
 542
 543         count = 0;
 544         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0)
 545                 udelay(10);
 546 }
 547
 548 void vlv_force_wake_put(struct drm_i915_private *dev_priv)
 549 {
 550         I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000);
 551         /* FIXME: confirm VLV behavior with Punit folks */
 552         POSTING_READ(FORCEWAKE_VLV);
 553 }
 554
 555 static int i915_drm_freeze(struct drm_device *dev)
 556 {
 557         struct drm_i915_private *dev_priv = dev->dev_private;
 558
 559         drm_kms_helper_poll_disable(dev);
 560
 561         pci_save_state(dev->pdev);
 562
 563         /* If KMS is active, we do the leavevt stuff here */
 564         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 565                 int error = i915_gem_idle(dev);
 566                 if (error) {
 567                         dev_err(&dev->pdev->dev,
 568                                 "GEM idle failed, resume might fail\n");
 569                         return error;
 570                 }
 571                 drm_irq_uninstall(dev);
 572         }
 573
 574         i915_save_state(dev);
 575
 576         intel_opregion_fini(dev);
 577
 578         /* Modeset on resume, not lid events */
 579         dev_priv->modeset_on_lid = 0;
 580
 581         console_lock();
 582         intel_fbdev_set_suspend(dev, 1);
 583         console_unlock();
 584
 585         return 0;
 586 }
 587
 588 int i915_suspend(struct drm_device *dev, pm_message_t state)
 589 {
 590         int error;
 591
 592         if (!dev || !dev->dev_private) {
 593                 DRM_ERROR("dev: %p\n", dev);
 594                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 595                 return -ENODEV;
 596         }
 597
 598         if (state.event == PM_EVENT_PRETHAW)
 599                 return 0;
 600
 601
 602         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 603                 return 0;
 604
 605         error = i915_drm_freeze(dev);
 606         if (error)
 607                 return error;
 608
 609         if (state.event == PM_EVENT_SUSPEND) {
 610                 /* Shut down the device */
 611                 pci_disable_device(dev->pdev);
 612                 pci_set_power_state(dev->pdev, PCI_D3hot);
 613         }
 614
 615         return 0;
 616 }
 617
 618 static int i915_drm_thaw(struct drm_device *dev)
 619 {
 620         struct drm_i915_private *dev_priv = dev->dev_private;
 621         int error = 0;
 622
 623         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 624                 mutex_lock(&dev->struct_mutex);
 625                 i915_gem_restore_gtt_mappings(dev);
 626                 mutex_unlock(&dev->struct_mutex);
 627         }
 628
 629         i915_restore_state(dev);
 630         intel_opregion_setup(dev);
 631
 632         /* KMS EnterVT equivalent */
 633         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 634                 if (HAS_PCH_SPLIT(dev))
 635                         ironlake_init_pch_refclk(dev);
 636
 637                 mutex_lock(&dev->struct_mutex);
 638                 dev_priv->mm.suspended = 0;
 639
 640                 error = i915_gem_init_hw(dev);
 641                 mutex_unlock(&dev->struct_mutex);
 642
 643                 intel_modeset_init_hw(dev);
 644                 drm_mode_config_reset(dev);
 645                 drm_irq_install(dev);
 646
 647                 /* Resume the modeset for every activated CRTC */
 648                 mutex_lock(&dev->mode_config.mutex);
 649                 drm_helper_resume_force_mode(dev);
 650                 mutex_unlock(&dev->mode_config.mutex);
 651         }
 652
 653         intel_opregion_init(dev);
 654
 655         dev_priv->modeset_on_lid = 0;
 656
 657         console_lock();
 658         intel_fbdev_set_suspend(dev, 0);
 659         console_unlock();
 660         return error;
 661 }
 662
 663 int i915_resume(struct drm_device *dev)
 664 {
 665         int ret;
 666
 667         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 668                 return 0;
 669
 670         if (pci_enable_device(dev->pdev))
 671                 return -EIO;
 672
 673         pci_set_master(dev->pdev);
 674
 675         ret = i915_drm_thaw(dev);
 676         if (ret)
 677                 return ret;
 678
 679         drm_kms_helper_poll_enable(dev);
 680         return 0;
 681 }
 682
 683 static int i8xx_do_reset(struct drm_device *dev)
 684 {
 685         struct drm_i915_private *dev_priv = dev->dev_private;
 686
 687         if (IS_I85X(dev))
 688                 return -ENODEV;
 689
 690         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 691         POSTING_READ(D_STATE);
 692
 693         if (IS_I830(dev) || IS_845G(dev)) {
 694                 I915_WRITE(DEBUG_RESET_I830,
 695                            DEBUG_RESET_DISPLAY |
 696                            DEBUG_RESET_RENDER |
 697                            DEBUG_RESET_FULL);
 698                 POSTING_READ(DEBUG_RESET_I830);
 699                 msleep(1);
 700
 701                 I915_WRITE(DEBUG_RESET_I830, 0);
 702                 POSTING_READ(DEBUG_RESET_I830);
 703         }
 704
 705         msleep(1);
 706
 707         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 708         POSTING_READ(D_STATE);
 709
 710         return 0;
 711 }
 712
 713 static int i965_reset_complete(struct drm_device *dev)
 714 {
 715         u8 gdrst;
 716         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 717         return (gdrst & GRDOM_RESET_ENABLE) == 0;
 718 }
 719
 720 static int i965_do_reset(struct drm_device *dev)
 721 {
 722         int ret;
 723         u8 gdrst;
 724
 725         /*
 726          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 727          * well as the reset bit (GR/bit 0).  Setting the GR bit
 728          * triggers the reset; when done, the hardware will clear it.
 729          */
 730         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 731         pci_write_config_byte(dev->pdev, I965_GDRST,
 732                               gdrst | GRDOM_RENDER |
 733                               GRDOM_RESET_ENABLE);
 734         ret =  wait_for(i965_reset_complete(dev), 500);
 735         if (ret)
 736                 return ret;
 737
 738         /* We can't reset render&media without also resetting display ... */
 739         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 740         pci_write_config_byte(dev->pdev, I965_GDRST,
 741                               gdrst | GRDOM_MEDIA |
 742                               GRDOM_RESET_ENABLE);
 743
 744         return wait_for(i965_reset_complete(dev), 500);
 745 }
 746
 747 static int ironlake_do_reset(struct drm_device *dev)
 748 {
 749         struct drm_i915_private *dev_priv = dev->dev_private;
 750         u32 gdrst;
 751         int ret;
 752
 753         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 754         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 755                    gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
 756         ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 757         if (ret)
 758                 return ret;
 759
 760         /* We can't reset render&media without also resetting display ... */
 761         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 762         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 763                    gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
 764         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 765 }
 766
 767 static int gen6_do_reset(struct drm_device *dev)
 768 {
 769         struct drm_i915_private *dev_priv = dev->dev_private;
 770         int     ret;
 771         unsigned long irqflags;
 772
 773         /* Hold gt_lock across reset to prevent any register access
 774          * with forcewake not set correctly
 775          */
 776         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 777
 778         /* Reset the chip */
 779
 780         /* GEN6_GDRST is not in the gt power well, no need to check
 781          * for fifo space for the write or forcewake the chip for
 782          * the read
 783          */
 784         I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
 785
 786         /* Spin waiting for the device to ack the reset request */
 787         ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 788
 789         /* If reset with a user forcewake, try to restore, otherwise turn it off */
 790         if (dev_priv->forcewake_count)
 791                 dev_priv->display.force_wake_get(dev_priv);
 792         else
 793                 dev_priv->display.force_wake_put(dev_priv);
 794
 795         /* Restore fifo count */
 796         dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 797
 798         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 799         return ret;
 800 }
 801
 802 static int intel_gpu_reset(struct drm_device *dev)
 803 {
 804         struct drm_i915_private *dev_priv = dev->dev_private;
 805         int ret = -ENODEV;
 806
 807         switch (INTEL_INFO(dev)->gen) {
 808         case 7:
 809         case 6:
 810                 ret = gen6_do_reset(dev);
 811                 break;
 812         case 5:
 813                 ret = ironlake_do_reset(dev);
 814                 break;
 815         case 4:
 816                 ret = i965_do_reset(dev);
 817                 break;
 818         case 2:
 819                 ret = i8xx_do_reset(dev);
 820                 break;
 821         }
 822
 823         /* Also reset the gpu hangman. */
 824         if (dev_priv->stop_rings) {
 825                 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
 826                 dev_priv->stop_rings = 0;
 827                 if (ret == -ENODEV) {
 828                         DRM_ERROR("Reset not implemented, but ignoring "
 829                                   "error for simulated gpu hangs\n");
 830                         ret = 0;
 831                 }
 832         }
 833
 834         return ret;
 835 }
 836
 837 /**
 838  * i915_reset - reset chip after a hang
 839  * @dev: drm device to reset
 840  *
 841  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 842  * reset or otherwise an error code.
 843  *
 844  * Procedure is fairly simple:
 845  *   - reset the chip using the reset reg
 846  *   - re-init context state
 847  *   - re-init hardware status page
 848  *   - re-init ring buffer
 849  *   - re-init interrupt state
 850  *   - re-init display
 851  */
 852 int i915_reset(struct drm_device *dev)
 853 {
 854         drm_i915_private_t *dev_priv = dev->dev_private;
 855         int ret;
 856
 857         if (!i915_try_reset)
 858                 return 0;
 859
 860         if (!mutex_trylock(&dev->struct_mutex))
 861                 return -EBUSY;
 862
 863         dev_priv->stop_rings = 0;
 864
 865         i915_gem_reset(dev);
 866
 867         ret = -ENODEV;
 868         if (get_seconds() - dev_priv->last_gpu_reset < 5)
 869                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 870         else
 871                 ret = intel_gpu_reset(dev);
 872
 873         dev_priv->last_gpu_reset = get_seconds();
 874         if (ret) {
 875                 DRM_ERROR("Failed to reset chip.\n");
 876                 mutex_unlock(&dev->struct_mutex);
 877                 return ret;
 878         }
 879
 880         /* Ok, now get things going again... */
 881
 882         /*
 883          * Everything depends on having the GTT running, so we need to start
 884          * there.  Fortunately we don't need to do this unless we reset the
 885          * chip at a PCI level.
 886          *
 887          * Next we need to restore the context, but we don't use those
 888          * yet either...
 889          *
 890          * Ring buffer needs to be re-initialized in the KMS case, or if X
 891          * was running at the time of the reset (i.e. we weren't VT
 892          * switched away).
 893          */
 894         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 895                         !dev_priv->mm.suspended) {
 896                 struct intel_ring_buffer *ring;
 897                 int i;
 898
 899                 dev_priv->mm.suspended = 0;
 900
 901                 i915_gem_init_swizzling(dev);
 902
 903                 for_each_ring(ring, dev_priv, i)
 904                         ring->init(ring);
 905
 906                 i915_gem_init_ppgtt(dev);
 907
 908                 mutex_unlock(&dev->struct_mutex);
 909
 910                 if (drm_core_check_feature(dev, DRIVER_MODESET))
 911                         intel_modeset_init_hw(dev);
 912
 913                 drm_irq_uninstall(dev);
 914                 drm_irq_install(dev);
 915         } else {
 916                 mutex_unlock(&dev->struct_mutex);
 917         }
 918
 919         return 0;
 920 }
 921
 922
 923 static int __devinit
 924 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 925 {
 926         /* Only bind to function 0 of the device. Early generations
 927          * used function 1 as a placeholder for multi-head. This causes
 928          * us confusion instead, especially on the systems where both
 929          * functions have the same PCI-ID!
 930          */
 931         if (PCI_FUNC(pdev->devfn))
 932                 return -ENODEV;
 933
 934         return drm_get_pci_dev(pdev, ent, &driver);
 935 }
 936
 937 static void
 938 i915_pci_remove(struct pci_dev *pdev)
 939 {
 940         struct drm_device *dev = pci_get_drvdata(pdev);
 941
 942         drm_put_dev(dev);
 943 }
 944
 945 static int i915_pm_suspend(struct device *dev)
 946 {
 947         struct pci_dev *pdev = to_pci_dev(dev);
 948         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 949         int error;
 950
 951         if (!drm_dev || !drm_dev->dev_private) {
 952                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 953                 return -ENODEV;
 954         }
 955
 956         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 957                 return 0;
 958
 959         error = i915_drm_freeze(drm_dev);
 960         if (error)
 961                 return error;
 962
 963         pci_disable_device(pdev);
 964         pci_set_power_state(pdev, PCI_D3hot);
 965
 966         return 0;
 967 }
 968
 969 static int i915_pm_resume(struct device *dev)
 970 {
 971         struct pci_dev *pdev = to_pci_dev(dev);
 972         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 973
 974         return i915_resume(drm_dev);
 975 }
 976
 977 static int i915_pm_freeze(struct device *dev)
 978 {
 979         struct pci_dev *pdev = to_pci_dev(dev);
 980         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 981
 982         if (!drm_dev || !drm_dev->dev_private) {
 983                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 984                 return -ENODEV;
 985         }
 986
 987         return i915_drm_freeze(drm_dev);
 988 }
 989
 990 static int i915_pm_thaw(struct device *dev)
 991 {
 992         struct pci_dev *pdev = to_pci_dev(dev);
 993         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 994
 995         return i915_drm_thaw(drm_dev);
 996 }
 997
 998 static int i915_pm_poweroff(struct device *dev)
 999 {
1000         struct pci_dev *pdev = to_pci_dev(dev);
1001         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1002
1003         return i915_drm_freeze(drm_dev);
1004 }
1005
1006 static const struct dev_pm_ops i915_pm_ops = {
1007         .suspend = i915_pm_suspend,
1008         .resume = i915_pm_resume,
1009         .freeze = i915_pm_freeze,
1010         .thaw = i915_pm_thaw,
1011         .poweroff = i915_pm_poweroff,
1012         .restore = i915_pm_resume,
1013 };
1014
1015 static const struct vm_operations_struct i915_gem_vm_ops = {
1016         .fault = i915_gem_fault,
1017         .open = drm_gem_vm_open,
1018         .close = drm_gem_vm_close,
1019 };
1020
1021 static const struct file_operations i915_driver_fops = {
1022         .owner = THIS_MODULE,
1023         .open = drm_open,
1024         .release = drm_release,
1025         .unlocked_ioctl = drm_ioctl,
1026         .mmap = drm_gem_mmap,
1027         .poll = drm_poll,
1028         .fasync = drm_fasync,
1029         .read = drm_read,
1030 #ifdef CONFIG_COMPAT
1031         .compat_ioctl = i915_compat_ioctl,
1032 #endif
1033         .llseek = noop_llseek,
1034 };
1035
1036 static struct drm_driver driver = {
1037         /* Don't use MTRRs here; the Xserver or userspace app should
1038          * deal with them for Intel hardware.
1039          */
1040         .driver_features =
1041             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
1042             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
1043         .load = i915_driver_load,
1044         .unload = i915_driver_unload,
1045         .open = i915_driver_open,
1046         .lastclose = i915_driver_lastclose,
1047         .preclose = i915_driver_preclose,
1048         .postclose = i915_driver_postclose,
1049
1050         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1051         .suspend = i915_suspend,
1052         .resume = i915_resume,
1053
1054         .device_is_agp = i915_driver_device_is_agp,
1055         .reclaim_buffers = drm_core_reclaim_buffers,
1056         .master_create = i915_master_create,
1057         .master_destroy = i915_master_destroy,
1058 #if defined(CONFIG_DEBUG_FS)
1059         .debugfs_init = i915_debugfs_init,
1060         .debugfs_cleanup = i915_debugfs_cleanup,
1061 #endif
1062         .gem_init_object = i915_gem_init_object,
1063         .gem_free_object = i915_gem_free_object,
1064         .gem_vm_ops = &i915_gem_vm_ops,
1065
1066         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1067         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1068         .gem_prime_export = i915_gem_prime_export,
1069         .gem_prime_import = i915_gem_prime_import,
1070
1071         .dumb_create = i915_gem_dumb_create,
1072         .dumb_map_offset = i915_gem_mmap_gtt,
1073         .dumb_destroy = i915_gem_dumb_destroy,
1074         .ioctls = i915_ioctls,
1075         .fops = &i915_driver_fops,
1076         .name = DRIVER_NAME,
1077         .desc = DRIVER_DESC,
1078         .date = DRIVER_DATE,
1079         .major = DRIVER_MAJOR,
1080         .minor = DRIVER_MINOR,
1081         .patchlevel = DRIVER_PATCHLEVEL,
1082 };
1083
1084 static struct pci_driver i915_pci_driver = {
1085         .name = DRIVER_NAME,
1086         .id_table = pciidlist,
1087         .probe = i915_pci_probe,
1088         .remove = i915_pci_remove,
1089         .driver.pm = &i915_pm_ops,
1090 };
1091
1092 static int __init i915_init(void)
1093 {
1094         if (!intel_agp_enabled) {
1095                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
1096                 return -ENODEV;
1097         }
1098
1099         driver.num_ioctls = i915_max_ioctl;
1100
1101         /*
1102          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1103          * explicitly disabled with the module pararmeter.
1104          *
1105          * Otherwise, just follow the parameter (defaulting to off).
1106          *
1107          * Allow optional vga_text_mode_force boot option to override
1108          * the default behavior.
1109          */
1110 #if defined(CONFIG_DRM_I915_KMS)
1111         if (i915_modeset != 0)
1112                 driver.driver_features |= DRIVER_MODESET;
1113 #endif
1114         if (i915_modeset == 1)
1115                 driver.driver_features |= DRIVER_MODESET;
1116
1117 #ifdef CONFIG_VGA_CONSOLE
1118         if (vgacon_text_force() && i915_modeset == -1)
1119                 driver.driver_features &= ~DRIVER_MODESET;
1120 #endif
1121
1122         if (!(driver.driver_features & DRIVER_MODESET))
1123                 driver.get_vblank_timestamp = NULL;
1124
1125         return drm_pci_init(&driver, &i915_pci_driver);
1126 }
1127
1128 static void __exit i915_exit(void)
1129 {
1130         drm_pci_exit(&driver, &i915_pci_driver);
1131 }
1132
1133 module_init(i915_init);
1134 module_exit(i915_exit);
1135
1136 MODULE_AUTHOR(DRIVER_AUTHOR);
1137 MODULE_DESCRIPTION(DRIVER_DESC);
1138 MODULE_LICENSE("GPL and additional rights");
1139
1140 /* We give fast paths for the really cool registers */
1141 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1142        (((dev_priv)->info->gen >= 6) && \
1143         ((reg) < 0x40000) &&            \
1144         ((reg) != FORCEWAKE)) && \
1145        (!IS_VALLEYVIEW((dev_priv)->dev))
1146
1147 #define __i915_read(x, y) \
1148 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1149         u##x val = 0; \
1150         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1151                 unsigned long irqflags; \
1152                 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1153                 if (dev_priv->forcewake_count == 0) \
1154                         dev_priv->display.force_wake_get(dev_priv); \
1155                 val = read##y(dev_priv->regs + reg); \
1156                 if (dev_priv->forcewake_count == 0) \
1157                         dev_priv->display.force_wake_put(dev_priv); \
1158                 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1159         } else { \
1160                 val = read##y(dev_priv->regs + reg); \
1161         } \
1162         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1163         return val; \
1164 }
1165
1166 __i915_read(8, b)
1167 __i915_read(16, w)
1168 __i915_read(32, l)
1169 __i915_read(64, q)
1170 #undef __i915_read
1171
1172 #define __i915_write(x, y) \
1173 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1174         u32 __fifo_ret = 0; \
1175         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1176         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1177                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1178         } \
1179         write##y(val, dev_priv->regs + reg); \
1180         if (unlikely(__fifo_ret)) { \
1181                 gen6_gt_check_fifodbg(dev_priv); \
1182         } \
1183 }
1184 __i915_write(8, b)
1185 __i915_write(16, w)
1186 __i915_write(32, l)
1187 __i915_write(64, q)
1188 #undef __i915_write