drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <drm/drmP.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include <drm/drm_crtc_helper.h>
  40
  41 static int i915_modeset __read_mostly = -1;
  42 module_param_named(modeset, i915_modeset, int, 0400);
  43 MODULE_PARM_DESC(modeset,
  44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  45                 "1=on, -1=force vga console preference [default])");
  46
  47 unsigned int i915_fbpercrtc __always_unused = 0;
  48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  49
  50 int i915_panel_ignore_lid __read_mostly = 1;
  51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  52 MODULE_PARM_DESC(panel_ignore_lid,
  53                 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
  54                 "-1=force lid closed, -2=force lid open)");
  55
  56 unsigned int i915_powersave __read_mostly = 1;
  57 module_param_named(powersave, i915_powersave, int, 0600);
  58 MODULE_PARM_DESC(powersave,
  59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  60
  61 int i915_semaphores __read_mostly = -1;
  62 module_param_named(semaphores, i915_semaphores, int, 0600);
  63 MODULE_PARM_DESC(semaphores,
  64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  65
  66 int i915_enable_rc6 __read_mostly = -1;
  67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
  68 MODULE_PARM_DESC(i915_enable_rc6,
  69                 "Enable power-saving render C-state 6. "
  70                 "Different stages can be selected via bitmask values "
  71                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
  72                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
  73                 "default: -1 (use per-chip default)");
  74
  75 int i915_enable_fbc __read_mostly = -1;
  76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  77 MODULE_PARM_DESC(i915_enable_fbc,
  78                 "Enable frame buffer compression for power savings "
  79                 "(default: -1 (use per-chip default))");
  80
  81 unsigned int i915_lvds_downclock __read_mostly = 0;
  82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  83 MODULE_PARM_DESC(lvds_downclock,
  84                 "Use panel (LVDS/eDP) downclocking for power savings "
  85                 "(default: false)");
  86
  87 int i915_lvds_channel_mode __read_mostly;
  88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
  89 MODULE_PARM_DESC(lvds_channel_mode,
  90                  "Specify LVDS channel mode "
  91                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  92
  93 int i915_panel_use_ssc __read_mostly = -1;
  94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  95 MODULE_PARM_DESC(lvds_use_ssc,
  96                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  97                 "(default: auto from VBT)");
  98
  99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
 100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
 101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
 102                 "Override/Ignore selection of SDVO panel mode in the VBT "
 103                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 104
 105 static bool i915_try_reset __read_mostly = true;
 106 module_param_named(reset, i915_try_reset, bool, 0600);
 107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
 108
 109 bool i915_enable_hangcheck __read_mostly = true;
 110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 111 MODULE_PARM_DESC(enable_hangcheck,
 112                 "Periodically check GPU activity for detecting hangs. "
 113                 "WARNING: Disabling this can cause system wide hangs. "
 114                 "(default: true)");
 115
 116 int i915_enable_ppgtt __read_mostly = -1;
 117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
 118 MODULE_PARM_DESC(i915_enable_ppgtt,
 119                 "Enable PPGTT (default: true)");
 120
 121 unsigned int i915_preliminary_hw_support __read_mostly = 0;
 122 module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
 123 MODULE_PARM_DESC(preliminary_hw_support,
 124                 "Enable preliminary hardware support. (default: false)");
 125
 126 int i915_disable_power_well __read_mostly = 0;
 127 module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
 128 MODULE_PARM_DESC(disable_power_well,
 129                  "Disable the power well when possible (default: false)");
 130
 131 static struct drm_driver driver;
 132 extern int intel_agp_enabled;
 133
 134 #define INTEL_VGA_DEVICE(id, info) {            \
 135         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
 136         .class_mask = 0xff0000,                 \
 137         .vendor = 0x8086,                       \
 138         .device = id,                           \
 139         .subvendor = PCI_ANY_ID,                \
 140         .subdevice = PCI_ANY_ID,                \
 141         .driver_data = (unsigned long) info }
 142
 143 static const struct intel_device_info intel_i830_info = {
 144         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 145         .has_overlay = 1, .overlay_needs_physical = 1,
 146 };
 147
 148 static const struct intel_device_info intel_845g_info = {
 149         .gen = 2, .num_pipes = 1,
 150         .has_overlay = 1, .overlay_needs_physical = 1,
 151 };
 152
 153 static const struct intel_device_info intel_i85x_info = {
 154         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
 155         .cursor_needs_physical = 1,
 156         .has_overlay = 1, .overlay_needs_physical = 1,
 157 };
 158
 159 static const struct intel_device_info intel_i865g_info = {
 160         .gen = 2, .num_pipes = 1,
 161         .has_overlay = 1, .overlay_needs_physical = 1,
 162 };
 163
 164 static const struct intel_device_info intel_i915g_info = {
 165         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 166         .has_overlay = 1, .overlay_needs_physical = 1,
 167 };
 168 static const struct intel_device_info intel_i915gm_info = {
 169         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 170         .cursor_needs_physical = 1,
 171         .has_overlay = 1, .overlay_needs_physical = 1,
 172         .supports_tv = 1,
 173 };
 174 static const struct intel_device_info intel_i945g_info = {
 175         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 176         .has_overlay = 1, .overlay_needs_physical = 1,
 177 };
 178 static const struct intel_device_info intel_i945gm_info = {
 179         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 180         .has_hotplug = 1, .cursor_needs_physical = 1,
 181         .has_overlay = 1, .overlay_needs_physical = 1,
 182         .supports_tv = 1,
 183 };
 184
 185 static const struct intel_device_info intel_i965g_info = {
 186         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 187         .has_hotplug = 1,
 188         .has_overlay = 1,
 189 };
 190
 191 static const struct intel_device_info intel_i965gm_info = {
 192         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 193         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 194         .has_overlay = 1,
 195         .supports_tv = 1,
 196 };
 197
 198 static const struct intel_device_info intel_g33_info = {
 199         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 200         .need_gfx_hws = 1, .has_hotplug = 1,
 201         .has_overlay = 1,
 202 };
 203
 204 static const struct intel_device_info intel_g45_info = {
 205         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 206         .has_pipe_cxsr = 1, .has_hotplug = 1,
 207         .has_bsd_ring = 1,
 208 };
 209
 210 static const struct intel_device_info intel_gm45_info = {
 211         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 212         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 213         .has_pipe_cxsr = 1, .has_hotplug = 1,
 214         .supports_tv = 1,
 215         .has_bsd_ring = 1,
 216 };
 217
 218 static const struct intel_device_info intel_pineview_info = {
 219         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 220         .need_gfx_hws = 1, .has_hotplug = 1,
 221         .has_overlay = 1,
 222 };
 223
 224 static const struct intel_device_info intel_ironlake_d_info = {
 225         .gen = 5, .num_pipes = 2,
 226         .need_gfx_hws = 1, .has_hotplug = 1,
 227         .has_bsd_ring = 1,
 228 };
 229
 230 static const struct intel_device_info intel_ironlake_m_info = {
 231         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 232         .need_gfx_hws = 1, .has_hotplug = 1,
 233         .has_fbc = 1,
 234         .has_bsd_ring = 1,
 235 };
 236
 237 static const struct intel_device_info intel_sandybridge_d_info = {
 238         .gen = 6, .num_pipes = 2,
 239         .need_gfx_hws = 1, .has_hotplug = 1,
 240         .has_bsd_ring = 1,
 241         .has_blt_ring = 1,
 242         .has_llc = 1,
 243         .has_force_wake = 1,
 244 };
 245
 246 static const struct intel_device_info intel_sandybridge_m_info = {
 247         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 248         .need_gfx_hws = 1, .has_hotplug = 1,
 249         .has_fbc = 1,
 250         .has_bsd_ring = 1,
 251         .has_blt_ring = 1,
 252         .has_llc = 1,
 253         .has_force_wake = 1,
 254 };
 255
 256 #define GEN7_FEATURES  \
 257         .gen = 7, .num_pipes = 3, \
 258         .need_gfx_hws = 1, .has_hotplug = 1, \
 259         .has_bsd_ring = 1, \
 260         .has_blt_ring = 1, \
 261         .has_llc = 1, \
 262         .has_force_wake = 1
 263
 264 static const struct intel_device_info intel_ivybridge_d_info = {
 265         GEN7_FEATURES,
 266         .is_ivybridge = 1,
 267 };
 268
 269 static const struct intel_device_info intel_ivybridge_m_info = {
 270         GEN7_FEATURES,
 271         .is_ivybridge = 1,
 272         .is_mobile = 1,
 273 };
 274
 275 static const struct intel_device_info intel_valleyview_m_info = {
 276         GEN7_FEATURES,
 277         .is_mobile = 1,
 278         .num_pipes = 2,
 279         .is_valleyview = 1,
 280         .display_mmio_offset = VLV_DISPLAY_BASE,
 281 };
 282
 283 static const struct intel_device_info intel_valleyview_d_info = {
 284         GEN7_FEATURES,
 285         .num_pipes = 2,
 286         .is_valleyview = 1,
 287         .display_mmio_offset = VLV_DISPLAY_BASE,
 288 };
 289
 290 static const struct intel_device_info intel_haswell_d_info = {
 291         GEN7_FEATURES,
 292         .is_haswell = 1,
 293 };
 294
 295 static const struct intel_device_info intel_haswell_m_info = {
 296         GEN7_FEATURES,
 297         .is_haswell = 1,
 298         .is_mobile = 1,
 299 };
 300
 301 static const struct pci_device_id pciidlist[] = {               /* aka */
 302         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 303         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 304         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 305         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 306         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 307         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 308         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 309         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 310         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 311         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 312         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 313         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 314         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 315         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 316         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 317         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 318         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 319         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 320         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 321         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 322         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 323         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 324         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 325         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 326         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 327         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 328         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 329         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 330         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 331         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 332         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 333         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 334         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 335         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 336         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 337         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 338         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 339         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 340         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 341         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 342         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 343         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 344         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 345         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
 346         INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
 347         INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
 348         INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
 349         INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
 350         INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
 351         INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
 352         INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
 353         INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
 354         INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
 355         INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
 356         INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
 357         INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
 358         INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
 359         INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
 360         INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
 361         INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
 362         INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
 363         INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
 364         INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
 365         INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
 366         INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
 367         INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
 368         INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
 369         INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
 370         INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
 371         INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
 372         INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
 373         INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
 374         INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
 375         INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
 376         INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
 377         INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
 378         INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
 379         INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
 380         INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
 381         INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
 382         INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
 383         INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
 384         INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
 385         INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info),
 386         INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
 387         INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
 388         {0, 0, 0}
 389 };
 390
 391 #if defined(CONFIG_DRM_I915_KMS)
 392 MODULE_DEVICE_TABLE(pci, pciidlist);
 393 #endif
 394
 395 void intel_detect_pch(struct drm_device *dev)
 396 {
 397         struct drm_i915_private *dev_priv = dev->dev_private;
 398         struct pci_dev *pch;
 399
 400         /*
 401          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 402          * make graphics device passthrough work easy for VMM, that only
 403          * need to expose ISA bridge to let driver know the real hardware
 404          * underneath. This is a requirement from virtualization team.
 405          */
 406         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 407         if (pch) {
 408                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 409                         unsigned short id;
 410                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 411                         dev_priv->pch_id = id;
 412
 413                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 414                                 dev_priv->pch_type = PCH_IBX;
 415                                 dev_priv->num_pch_pll = 2;
 416                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 417                                 WARN_ON(!IS_GEN5(dev));
 418                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 419                                 dev_priv->pch_type = PCH_CPT;
 420                                 dev_priv->num_pch_pll = 2;
 421                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 422                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 423                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 424                                 /* PantherPoint is CPT compatible */
 425                                 dev_priv->pch_type = PCH_CPT;
 426                                 dev_priv->num_pch_pll = 2;
 427                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 428                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 429                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 430                                 dev_priv->pch_type = PCH_LPT;
 431                                 dev_priv->num_pch_pll = 0;
 432                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 433                                 WARN_ON(!IS_HASWELL(dev));
 434                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 435                                 dev_priv->pch_type = PCH_LPT;
 436                                 dev_priv->num_pch_pll = 0;
 437                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 438                                 WARN_ON(!IS_HASWELL(dev));
 439                         }
 440                         BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
 441                 }
 442                 pci_dev_put(pch);
 443         }
 444 }
 445
 446 bool i915_semaphore_is_enabled(struct drm_device *dev)
 447 {
 448         if (INTEL_INFO(dev)->gen < 6)
 449                 return 0;
 450
 451         if (i915_semaphores >= 0)
 452                 return i915_semaphores;
 453
 454 #ifdef CONFIG_INTEL_IOMMU
 455         /* Enable semaphores on SNB when IO remapping is off */
 456         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 457                 return false;
 458 #endif
 459
 460         return 1;
 461 }
 462
 463 static int i915_drm_freeze(struct drm_device *dev)
 464 {
 465         struct drm_i915_private *dev_priv = dev->dev_private;
 466
 467         /* ignore lid events during suspend */
 468         mutex_lock(&dev_priv->modeset_restore_lock);
 469         dev_priv->modeset_restore = MODESET_SUSPENDED;
 470         mutex_unlock(&dev_priv->modeset_restore_lock);
 471
 472         intel_set_power_well(dev, true);
 473
 474         drm_kms_helper_poll_disable(dev);
 475
 476         pci_save_state(dev->pdev);
 477
 478         /* If KMS is active, we do the leavevt stuff here */
 479         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 480                 int error = i915_gem_idle(dev);
 481                 if (error) {
 482                         dev_err(&dev->pdev->dev,
 483                                 "GEM idle failed, resume might fail\n");
 484                         return error;
 485                 }
 486
 487                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
 488
 489                 intel_modeset_disable(dev);
 490
 491                 drm_irq_uninstall(dev);
 492                 dev_priv->enable_hotplug_processing = false;
 493         }
 494
 495         i915_save_state(dev);
 496
 497         intel_opregion_fini(dev);
 498
 499         console_lock();
 500         intel_fbdev_set_suspend(dev, 1);
 501         console_unlock();
 502
 503         return 0;
 504 }
 505
 506 int i915_suspend(struct drm_device *dev, pm_message_t state)
 507 {
 508         int error;
 509
 510         if (!dev || !dev->dev_private) {
 511                 DRM_ERROR("dev: %p\n", dev);
 512                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 513                 return -ENODEV;
 514         }
 515
 516         if (state.event == PM_EVENT_PRETHAW)
 517                 return 0;
 518
 519
 520         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 521                 return 0;
 522
 523         error = i915_drm_freeze(dev);
 524         if (error)
 525                 return error;
 526
 527         if (state.event == PM_EVENT_SUSPEND) {
 528                 /* Shut down the device */
 529                 pci_disable_device(dev->pdev);
 530                 pci_set_power_state(dev->pdev, PCI_D3hot);
 531         }
 532
 533         return 0;
 534 }
 535
 536 void intel_console_resume(struct work_struct *work)
 537 {
 538         struct drm_i915_private *dev_priv =
 539                 container_of(work, struct drm_i915_private,
 540                              console_resume_work);
 541         struct drm_device *dev = dev_priv->dev;
 542
 543         console_lock();
 544         intel_fbdev_set_suspend(dev, 0);
 545         console_unlock();
 546 }
 547
 548 static int __i915_drm_thaw(struct drm_device *dev)
 549 {
 550         struct drm_i915_private *dev_priv = dev->dev_private;
 551         int error = 0;
 552
 553         i915_restore_state(dev);
 554         intel_opregion_setup(dev);
 555
 556         /* KMS EnterVT equivalent */
 557         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 558                 intel_init_pch_refclk(dev);
 559
 560                 mutex_lock(&dev->struct_mutex);
 561                 dev_priv->mm.suspended = 0;
 562
 563                 error = i915_gem_init_hw(dev);
 564                 mutex_unlock(&dev->struct_mutex);
 565
 566                 /* We need working interrupts for modeset enabling ... */
 567                 drm_irq_install(dev);
 568
 569                 intel_modeset_init_hw(dev);
 570                 intel_modeset_setup_hw_state(dev, false);
 571
 572                 /*
 573                  * ... but also need to make sure that hotplug processing
 574                  * doesn't cause havoc. Like in the driver load code we don't
 575                  * bother with the tiny race here where we might loose hotplug
 576                  * notifications.
 577                  * */
 578                 intel_hpd_init(dev);
 579                 dev_priv->enable_hotplug_processing = true;
 580         }
 581
 582         intel_opregion_init(dev);
 583
 584         /*
 585          * The console lock can be pretty contented on resume due
 586          * to all the printk activity.  Try to keep it out of the hot
 587          * path of resume if possible.
 588          */
 589         if (console_trylock()) {
 590                 intel_fbdev_set_suspend(dev, 0);
 591                 console_unlock();
 592         } else {
 593                 schedule_work(&dev_priv->console_resume_work);
 594         }
 595
 596         mutex_lock(&dev_priv->modeset_restore_lock);
 597         dev_priv->modeset_restore = MODESET_DONE;
 598         mutex_unlock(&dev_priv->modeset_restore_lock);
 599         return error;
 600 }
 601
 602 static int i915_drm_thaw(struct drm_device *dev)
 603 {
 604         int error = 0;
 605
 606         intel_gt_reset(dev);
 607
 608         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 609                 mutex_lock(&dev->struct_mutex);
 610                 i915_gem_restore_gtt_mappings(dev);
 611                 mutex_unlock(&dev->struct_mutex);
 612         }
 613
 614         __i915_drm_thaw(dev);
 615
 616         return error;
 617 }
 618
 619 int i915_resume(struct drm_device *dev)
 620 {
 621         struct drm_i915_private *dev_priv = dev->dev_private;
 622         int ret;
 623
 624         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 625                 return 0;
 626
 627         if (pci_enable_device(dev->pdev))
 628                 return -EIO;
 629
 630         pci_set_master(dev->pdev);
 631
 632         intel_gt_reset(dev);
 633
 634         /*
 635          * Platforms with opregion should have sane BIOS, older ones (gen3 and
 636          * earlier) need this since the BIOS might clear all our scratch PTEs.
 637          */
 638         if (drm_core_check_feature(dev, DRIVER_MODESET) &&
 639             !dev_priv->opregion.header) {
 640                 mutex_lock(&dev->struct_mutex);
 641                 i915_gem_restore_gtt_mappings(dev);
 642                 mutex_unlock(&dev->struct_mutex);
 643         }
 644
 645         ret = __i915_drm_thaw(dev);
 646         if (ret)
 647                 return ret;
 648
 649         drm_kms_helper_poll_enable(dev);
 650         return 0;
 651 }
 652
 653 static int i8xx_do_reset(struct drm_device *dev)
 654 {
 655         struct drm_i915_private *dev_priv = dev->dev_private;
 656
 657         if (IS_I85X(dev))
 658                 return -ENODEV;
 659
 660         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 661         POSTING_READ(D_STATE);
 662
 663         if (IS_I830(dev) || IS_845G(dev)) {
 664                 I915_WRITE(DEBUG_RESET_I830,
 665                            DEBUG_RESET_DISPLAY |
 666                            DEBUG_RESET_RENDER |
 667                            DEBUG_RESET_FULL);
 668                 POSTING_READ(DEBUG_RESET_I830);
 669                 msleep(1);
 670
 671                 I915_WRITE(DEBUG_RESET_I830, 0);
 672                 POSTING_READ(DEBUG_RESET_I830);
 673         }
 674
 675         msleep(1);
 676
 677         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 678         POSTING_READ(D_STATE);
 679
 680         return 0;
 681 }
 682
 683 static int i965_reset_complete(struct drm_device *dev)
 684 {
 685         u8 gdrst;
 686         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 687         return (gdrst & GRDOM_RESET_ENABLE) == 0;
 688 }
 689
 690 static int i965_do_reset(struct drm_device *dev)
 691 {
 692         int ret;
 693         u8 gdrst;
 694
 695         /*
 696          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 697          * well as the reset bit (GR/bit 0).  Setting the GR bit
 698          * triggers the reset; when done, the hardware will clear it.
 699          */
 700         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 701         pci_write_config_byte(dev->pdev, I965_GDRST,
 702                               gdrst | GRDOM_RENDER |
 703                               GRDOM_RESET_ENABLE);
 704         ret =  wait_for(i965_reset_complete(dev), 500);
 705         if (ret)
 706                 return ret;
 707
 708         /* We can't reset render&media without also resetting display ... */
 709         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 710         pci_write_config_byte(dev->pdev, I965_GDRST,
 711                               gdrst | GRDOM_MEDIA |
 712                               GRDOM_RESET_ENABLE);
 713
 714         return wait_for(i965_reset_complete(dev), 500);
 715 }
 716
 717 static int ironlake_do_reset(struct drm_device *dev)
 718 {
 719         struct drm_i915_private *dev_priv = dev->dev_private;
 720         u32 gdrst;
 721         int ret;
 722
 723         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 724         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 725                    gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
 726         ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 727         if (ret)
 728                 return ret;
 729
 730         /* We can't reset render&media without also resetting display ... */
 731         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 732         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 733                    gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
 734         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 735 }
 736
 737 static int gen6_do_reset(struct drm_device *dev)
 738 {
 739         struct drm_i915_private *dev_priv = dev->dev_private;
 740         int     ret;
 741         unsigned long irqflags;
 742
 743         /* Hold gt_lock across reset to prevent any register access
 744          * with forcewake not set correctly
 745          */
 746         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 747
 748         /* Reset the chip */
 749
 750         /* GEN6_GDRST is not in the gt power well, no need to check
 751          * for fifo space for the write or forcewake the chip for
 752          * the read
 753          */
 754         I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
 755
 756         /* Spin waiting for the device to ack the reset request */
 757         ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 758
 759         /* If reset with a user forcewake, try to restore, otherwise turn it off */
 760         if (dev_priv->forcewake_count)
 761                 dev_priv->gt.force_wake_get(dev_priv);
 762         else
 763                 dev_priv->gt.force_wake_put(dev_priv);
 764
 765         /* Restore fifo count */
 766         dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 767
 768         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 769         return ret;
 770 }
 771
 772 int intel_gpu_reset(struct drm_device *dev)
 773 {
 774         struct drm_i915_private *dev_priv = dev->dev_private;
 775         int ret = -ENODEV;
 776
 777         switch (INTEL_INFO(dev)->gen) {
 778         case 7:
 779         case 6:
 780                 ret = gen6_do_reset(dev);
 781                 break;
 782         case 5:
 783                 ret = ironlake_do_reset(dev);
 784                 break;
 785         case 4:
 786                 ret = i965_do_reset(dev);
 787                 break;
 788         case 2:
 789                 ret = i8xx_do_reset(dev);
 790                 break;
 791         }
 792
 793         /* Also reset the gpu hangman. */
 794         if (dev_priv->gpu_error.stop_rings) {
 795                 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
 796                 dev_priv->gpu_error.stop_rings = 0;
 797                 if (ret == -ENODEV) {
 798                         DRM_ERROR("Reset not implemented, but ignoring "
 799                                   "error for simulated gpu hangs\n");
 800                         ret = 0;
 801                 }
 802         }
 803
 804         return ret;
 805 }
 806
 807 /**
 808  * i915_reset - reset chip after a hang
 809  * @dev: drm device to reset
 810  *
 811  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 812  * reset or otherwise an error code.
 813  *
 814  * Procedure is fairly simple:
 815  *   - reset the chip using the reset reg
 816  *   - re-init context state
 817  *   - re-init hardware status page
 818  *   - re-init ring buffer
 819  *   - re-init interrupt state
 820  *   - re-init display
 821  */
 822 int i915_reset(struct drm_device *dev)
 823 {
 824         drm_i915_private_t *dev_priv = dev->dev_private;
 825         int ret;
 826
 827         if (!i915_try_reset)
 828                 return 0;
 829
 830         mutex_lock(&dev->struct_mutex);
 831
 832         i915_gem_reset(dev);
 833
 834         ret = -ENODEV;
 835         if (get_seconds() - dev_priv->gpu_error.last_reset < 5)
 836                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 837         else
 838                 ret = intel_gpu_reset(dev);
 839
 840         dev_priv->gpu_error.last_reset = get_seconds();
 841         if (ret) {
 842                 DRM_ERROR("Failed to reset chip.\n");
 843                 mutex_unlock(&dev->struct_mutex);
 844                 return ret;
 845         }
 846
 847         /* Ok, now get things going again... */
 848
 849         /*
 850          * Everything depends on having the GTT running, so we need to start
 851          * there.  Fortunately we don't need to do this unless we reset the
 852          * chip at a PCI level.
 853          *
 854          * Next we need to restore the context, but we don't use those
 855          * yet either...
 856          *
 857          * Ring buffer needs to be re-initialized in the KMS case, or if X
 858          * was running at the time of the reset (i.e. we weren't VT
 859          * switched away).
 860          */
 861         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 862                         !dev_priv->mm.suspended) {
 863                 struct intel_ring_buffer *ring;
 864                 int i;
 865
 866                 dev_priv->mm.suspended = 0;
 867
 868                 i915_gem_init_swizzling(dev);
 869
 870                 for_each_ring(ring, dev_priv, i)
 871                         ring->init(ring);
 872
 873                 i915_gem_context_init(dev);
 874                 i915_gem_init_ppgtt(dev);
 875
 876                 /*
 877                  * It would make sense to re-init all the other hw state, at
 878                  * least the rps/rc6/emon init done within modeset_init_hw. For
 879                  * some unknown reason, this blows up my ilk, so don't.
 880                  */
 881
 882                 mutex_unlock(&dev->struct_mutex);
 883
 884                 drm_irq_uninstall(dev);
 885                 drm_irq_install(dev);
 886                 intel_hpd_init(dev);
 887         } else {
 888                 mutex_unlock(&dev->struct_mutex);
 889         }
 890
 891         return 0;
 892 }
 893
 894 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 895 {
 896         struct intel_device_info *intel_info =
 897                 (struct intel_device_info *) ent->driver_data;
 898
 899         if (intel_info->is_valleyview)
 900                 if(!i915_preliminary_hw_support) {
 901                         DRM_ERROR("Preliminary hardware support disabled\n");
 902                         return -ENODEV;
 903                 }
 904
 905         /* Only bind to function 0 of the device. Early generations
 906          * used function 1 as a placeholder for multi-head. This causes
 907          * us confusion instead, especially on the systems where both
 908          * functions have the same PCI-ID!
 909          */
 910         if (PCI_FUNC(pdev->devfn))
 911                 return -ENODEV;
 912
 913         /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
 914          * implementation for gen3 (and only gen3) that used legacy drm maps
 915          * (gasp!) to share buffers between X and the client. Hence we need to
 916          * keep around the fake agp stuff for gen3, even when kms is enabled. */
 917         if (intel_info->gen != 3) {
 918                 driver.driver_features &=
 919                         ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
 920         } else if (!intel_agp_enabled) {
 921                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 922                 return -ENODEV;
 923         }
 924
 925         return drm_get_pci_dev(pdev, ent, &driver);
 926 }
 927
 928 static void
 929 i915_pci_remove(struct pci_dev *pdev)
 930 {
 931         struct drm_device *dev = pci_get_drvdata(pdev);
 932
 933         drm_put_dev(dev);
 934 }
 935
 936 static int i915_pm_suspend(struct device *dev)
 937 {
 938         struct pci_dev *pdev = to_pci_dev(dev);
 939         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 940         int error;
 941
 942         if (!drm_dev || !drm_dev->dev_private) {
 943                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 944                 return -ENODEV;
 945         }
 946
 947         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 948                 return 0;
 949
 950         error = i915_drm_freeze(drm_dev);
 951         if (error)
 952                 return error;
 953
 954         pci_disable_device(pdev);
 955         pci_set_power_state(pdev, PCI_D3hot);
 956
 957         return 0;
 958 }
 959
 960 static int i915_pm_resume(struct device *dev)
 961 {
 962         struct pci_dev *pdev = to_pci_dev(dev);
 963         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 964
 965         return i915_resume(drm_dev);
 966 }
 967
 968 static int i915_pm_freeze(struct device *dev)
 969 {
 970         struct pci_dev *pdev = to_pci_dev(dev);
 971         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 972
 973         if (!drm_dev || !drm_dev->dev_private) {
 974                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 975                 return -ENODEV;
 976         }
 977
 978         return i915_drm_freeze(drm_dev);
 979 }
 980
 981 static int i915_pm_thaw(struct device *dev)
 982 {
 983         struct pci_dev *pdev = to_pci_dev(dev);
 984         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 985
 986         return i915_drm_thaw(drm_dev);
 987 }
 988
 989 static int i915_pm_poweroff(struct device *dev)
 990 {
 991         struct pci_dev *pdev = to_pci_dev(dev);
 992         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 993
 994         return i915_drm_freeze(drm_dev);
 995 }
 996
 997 static const struct dev_pm_ops i915_pm_ops = {
 998         .suspend = i915_pm_suspend,
 999         .resume = i915_pm_resume,
1000         .freeze = i915_pm_freeze,
1001         .thaw = i915_pm_thaw,
1002         .poweroff = i915_pm_poweroff,
1003         .restore = i915_pm_resume,
1004 };
1005
1006 static const struct vm_operations_struct i915_gem_vm_ops = {
1007         .fault = i915_gem_fault,
1008         .open = drm_gem_vm_open,
1009         .close = drm_gem_vm_close,
1010 };
1011
1012 static const struct file_operations i915_driver_fops = {
1013         .owner = THIS_MODULE,
1014         .open = drm_open,
1015         .release = drm_release,
1016         .unlocked_ioctl = drm_ioctl,
1017         .mmap = drm_gem_mmap,
1018         .poll = drm_poll,
1019         .fasync = drm_fasync,
1020         .read = drm_read,
1021 #ifdef CONFIG_COMPAT
1022         .compat_ioctl = i915_compat_ioctl,
1023 #endif
1024         .llseek = noop_llseek,
1025 };
1026
1027 static struct drm_driver driver = {
1028         /* Don't use MTRRs here; the Xserver or userspace app should
1029          * deal with them for Intel hardware.
1030          */
1031         .driver_features =
1032             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
1033             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
1034         .load = i915_driver_load,
1035         .unload = i915_driver_unload,
1036         .open = i915_driver_open,
1037         .lastclose = i915_driver_lastclose,
1038         .preclose = i915_driver_preclose,
1039         .postclose = i915_driver_postclose,
1040
1041         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1042         .suspend = i915_suspend,
1043         .resume = i915_resume,
1044
1045         .device_is_agp = i915_driver_device_is_agp,
1046         .master_create = i915_master_create,
1047         .master_destroy = i915_master_destroy,
1048 #if defined(CONFIG_DEBUG_FS)
1049         .debugfs_init = i915_debugfs_init,
1050         .debugfs_cleanup = i915_debugfs_cleanup,
1051 #endif
1052         .gem_init_object = i915_gem_init_object,
1053         .gem_free_object = i915_gem_free_object,
1054         .gem_vm_ops = &i915_gem_vm_ops,
1055
1056         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1057         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1058         .gem_prime_export = i915_gem_prime_export,
1059         .gem_prime_import = i915_gem_prime_import,
1060
1061         .dumb_create = i915_gem_dumb_create,
1062         .dumb_map_offset = i915_gem_mmap_gtt,
1063         .dumb_destroy = i915_gem_dumb_destroy,
1064         .ioctls = i915_ioctls,
1065         .fops = &i915_driver_fops,
1066         .name = DRIVER_NAME,
1067         .desc = DRIVER_DESC,
1068         .date = DRIVER_DATE,
1069         .major = DRIVER_MAJOR,
1070         .minor = DRIVER_MINOR,
1071         .patchlevel = DRIVER_PATCHLEVEL,
1072 };
1073
1074 static struct pci_driver i915_pci_driver = {
1075         .name = DRIVER_NAME,
1076         .id_table = pciidlist,
1077         .probe = i915_pci_probe,
1078         .remove = i915_pci_remove,
1079         .driver.pm = &i915_pm_ops,
1080 };
1081
1082 static int __init i915_init(void)
1083 {
1084         driver.num_ioctls = i915_max_ioctl;
1085
1086         /*
1087          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1088          * explicitly disabled with the module pararmeter.
1089          *
1090          * Otherwise, just follow the parameter (defaulting to off).
1091          *
1092          * Allow optional vga_text_mode_force boot option to override
1093          * the default behavior.
1094          */
1095 #if defined(CONFIG_DRM_I915_KMS)
1096         if (i915_modeset != 0)
1097                 driver.driver_features |= DRIVER_MODESET;
1098 #endif
1099         if (i915_modeset == 1)
1100                 driver.driver_features |= DRIVER_MODESET;
1101
1102 #ifdef CONFIG_VGA_CONSOLE
1103         if (vgacon_text_force() && i915_modeset == -1)
1104                 driver.driver_features &= ~DRIVER_MODESET;
1105 #endif
1106
1107         if (!(driver.driver_features & DRIVER_MODESET))
1108                 driver.get_vblank_timestamp = NULL;
1109
1110         return drm_pci_init(&driver, &i915_pci_driver);
1111 }
1112
1113 static void __exit i915_exit(void)
1114 {
1115         drm_pci_exit(&driver, &i915_pci_driver);
1116 }
1117
1118 module_init(i915_init);
1119 module_exit(i915_exit);
1120
1121 MODULE_AUTHOR(DRIVER_AUTHOR);
1122 MODULE_DESCRIPTION(DRIVER_DESC);
1123 MODULE_LICENSE("GPL and additional rights");
1124
1125 /* We give fast paths for the really cool registers */
1126 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1127         ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1128          ((reg) < 0x40000) &&            \
1129          ((reg) != FORCEWAKE))
1130 static void
1131 ilk_dummy_write(struct drm_i915_private *dev_priv)
1132 {
1133         /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
1134          * chip from rc6 before touching it for real. MI_MODE is masked, hence
1135          * harmless to write 0 into. */
1136         I915_WRITE_NOTRACE(MI_MODE, 0);
1137 }
1138
1139 static void
1140 hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
1141 {
1142         if (IS_HASWELL(dev_priv->dev) &&
1143             (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1144                 DRM_ERROR("Unknown unclaimed register before writing to %x\n",
1145                           reg);
1146                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1147         }
1148 }
1149
1150 static void
1151 hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
1152 {
1153         if (IS_HASWELL(dev_priv->dev) &&
1154             (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1155                 DRM_ERROR("Unclaimed write to %x\n", reg);
1156                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1157         }
1158 }
1159
1160 #define __i915_read(x, y) \
1161 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1162         u##x val = 0; \
1163         if (IS_GEN5(dev_priv->dev)) \
1164                 ilk_dummy_write(dev_priv); \
1165         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1166                 unsigned long irqflags; \
1167                 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1168                 if (dev_priv->forcewake_count == 0) \
1169                         dev_priv->gt.force_wake_get(dev_priv); \
1170                 val = read##y(dev_priv->regs + reg); \
1171                 if (dev_priv->forcewake_count == 0) \
1172                         dev_priv->gt.force_wake_put(dev_priv); \
1173                 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1174         } else { \
1175                 val = read##y(dev_priv->regs + reg); \
1176         } \
1177         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1178         return val; \
1179 }
1180
1181 __i915_read(8, b)
1182 __i915_read(16, w)
1183 __i915_read(32, l)
1184 __i915_read(64, q)
1185 #undef __i915_read
1186
1187 #define __i915_write(x, y) \
1188 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1189         u32 __fifo_ret = 0; \
1190         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1191         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1192                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1193         } \
1194         if (IS_GEN5(dev_priv->dev)) \
1195                 ilk_dummy_write(dev_priv); \
1196         hsw_unclaimed_reg_clear(dev_priv, reg); \
1197         write##y(val, dev_priv->regs + reg); \
1198         if (unlikely(__fifo_ret)) { \
1199                 gen6_gt_check_fifodbg(dev_priv); \
1200         } \
1201         hsw_unclaimed_reg_check(dev_priv, reg); \
1202 }
1203 __i915_write(8, b)
1204 __i915_write(16, w)
1205 __i915_write(32, l)
1206 __i915_write(64, q)
1207 #undef __i915_write
1208
1209 static const struct register_whitelist {
1210         uint64_t offset;
1211         uint32_t size;
1212         uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1213 } whitelist[] = {
1214         { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
1215 };
1216
1217 int i915_reg_read_ioctl(struct drm_device *dev,
1218                         void *data, struct drm_file *file)
1219 {
1220         struct drm_i915_private *dev_priv = dev->dev_private;
1221         struct drm_i915_reg_read *reg = data;
1222         struct register_whitelist const *entry = whitelist;
1223         int i;
1224
1225         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1226                 if (entry->offset == reg->offset &&
1227                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1228                         break;
1229         }
1230
1231         if (i == ARRAY_SIZE(whitelist))
1232                 return -EINVAL;
1233
1234         switch (entry->size) {
1235         case 8:
1236                 reg->val = I915_READ64(reg->offset);
1237                 break;
1238         case 4:
1239                 reg->val = I915_READ(reg->offset);
1240                 break;
1241         case 2:
1242                 reg->val = I915_READ16(reg->offset);
1243                 break;
1244         case 1:
1245                 reg->val = I915_READ8(reg->offset);
1246                 break;
1247         default:
1248                 WARN_ON(1);
1249                 return -EINVAL;
1250         }
1251
1252         return 0;
1253 }