drivers/gpu/drm/amd/amdgpu/cik_sdma.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "cikd.h"
  30 #include "cik.h"
  31
  32 #include "bif/bif_4_1_d.h"
  33 #include "bif/bif_4_1_sh_mask.h"
  34
  35 #include "gca/gfx_7_2_d.h"
  36 #include "gca/gfx_7_2_enum.h"
  37 #include "gca/gfx_7_2_sh_mask.h"
  38
  39 #include "gmc/gmc_7_1_d.h"
  40 #include "gmc/gmc_7_1_sh_mask.h"
  41
  42 #include "oss/oss_2_0_d.h"
  43 #include "oss/oss_2_0_sh_mask.h"
  44
  45 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  46 {
  47         SDMA0_REGISTER_OFFSET,
  48         SDMA1_REGISTER_OFFSET
  49 };
  50
  51 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
  52 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
  53 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
  54 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
  55
  56 MODULE_FIRMWARE("radeon/bonaire_sdma.bin");
  57 MODULE_FIRMWARE("radeon/bonaire_sdma1.bin");
  58 MODULE_FIRMWARE("radeon/hawaii_sdma.bin");
  59 MODULE_FIRMWARE("radeon/hawaii_sdma1.bin");
  60 MODULE_FIRMWARE("radeon/kaveri_sdma.bin");
  61 MODULE_FIRMWARE("radeon/kaveri_sdma1.bin");
  62 MODULE_FIRMWARE("radeon/kabini_sdma.bin");
  63 MODULE_FIRMWARE("radeon/kabini_sdma1.bin");
  64 MODULE_FIRMWARE("radeon/mullins_sdma.bin");
  65 MODULE_FIRMWARE("radeon/mullins_sdma1.bin");
  66
  67 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
  68
  69 /*
  70  * sDMA - System DMA
  71  * Starting with CIK, the GPU has new asynchronous
  72  * DMA engines.  These engines are used for compute
  73  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  74  * and each one supports 1 ring buffer used for gfx
  75  * and 2 queues used for compute.
  76  *
  77  * The programming model is very similar to the CP
  78  * (ring buffer, IBs, etc.), but sDMA has it's own
  79  * packet format that is different from the PM4 format
  80  * used by the CP. sDMA supports copying data, writing
  81  * embedded data, solid fills, and a number of other
  82  * things.  It also has support for tiling/detiling of
  83  * buffers.
  84  */
  85
  86 /**
  87  * cik_sdma_init_microcode - load ucode images from disk
  88  *
  89  * @adev: amdgpu_device pointer
  90  *
  91  * Use the firmware interface to load the ucode images into
  92  * the driver (not loaded into hw).
  93  * Returns 0 on success, error on failure.
  94  */
  95 static int cik_sdma_init_microcode(struct amdgpu_device *adev)
  96 {
  97         const char *chip_name;
  98         char fw_name[30];
  99         int err, i;
 100
 101         DRM_DEBUG("\n");
 102
 103         switch (adev->asic_type) {
 104         case CHIP_BONAIRE:
 105                 chip_name = "bonaire";
 106                 break;
 107         case CHIP_HAWAII:
 108                 chip_name = "hawaii";
 109                 break;
 110         case CHIP_KAVERI:
 111                 chip_name = "kaveri";
 112                 break;
 113         case CHIP_KABINI:
 114                 chip_name = "kabini";
 115                 break;
 116         case CHIP_MULLINS:
 117                 chip_name = "mullins";
 118                 break;
 119         default: BUG();
 120         }
 121
 122         for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
 123                 if (i == 0)
 124                         snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
 125                 else
 126                         snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name);
 127                 err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev);
 128                 if (err)
 129                         goto out;
 130                 err = amdgpu_ucode_validate(adev->sdma[i].fw);
 131         }
 132 out:
 133         if (err) {
 134                 printk(KERN_ERR
 135                        "cik_sdma: Failed to load firmware \"%s\"\n",
 136                        fw_name);
 137                 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
 138                         release_firmware(adev->sdma[i].fw);
 139                         adev->sdma[i].fw = NULL;
 140                 }
 141         }
 142         return err;
 143 }
 144
 145 /**
 146  * cik_sdma_ring_get_rptr - get the current read pointer
 147  *
 148  * @ring: amdgpu ring pointer
 149  *
 150  * Get the current rptr from the hardware (CIK+).
 151  */
 152 static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
 153 {
 154         u32 rptr;
 155
 156         rptr = ring->adev->wb.wb[ring->rptr_offs];
 157
 158         return (rptr & 0x3fffc) >> 2;
 159 }
 160
 161 /**
 162  * cik_sdma_ring_get_wptr - get the current write pointer
 163  *
 164  * @ring: amdgpu ring pointer
 165  *
 166  * Get the current wptr from the hardware (CIK+).
 167  */
 168 static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
 169 {
 170         struct amdgpu_device *adev = ring->adev;
 171         u32 me = (ring == &adev->sdma[0].ring) ? 0 : 1;
 172
 173         return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
 174 }
 175
 176 /**
 177  * cik_sdma_ring_set_wptr - commit the write pointer
 178  *
 179  * @ring: amdgpu ring pointer
 180  *
 181  * Write the wptr back to the hardware (CIK+).
 182  */
 183 static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
 184 {
 185         struct amdgpu_device *adev = ring->adev;
 186         u32 me = (ring == &adev->sdma[0].ring) ? 0 : 1;
 187
 188         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc);
 189 }
 190
 191 /**
 192  * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
 193  *
 194  * @ring: amdgpu ring pointer
 195  * @ib: IB object to schedule
 196  *
 197  * Schedule an IB in the DMA ring (CIK).
 198  */
 199 static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
 200                            struct amdgpu_ib *ib)
 201 {
 202         u32 extra_bits = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
 203         u32 next_rptr = ring->wptr + 5;
 204
 205         while ((next_rptr & 7) != 4)
 206                 next_rptr++;
 207
 208         next_rptr += 4;
 209         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
 210         amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
 211         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
 212         amdgpu_ring_write(ring, 1); /* number of DWs to follow */
 213         amdgpu_ring_write(ring, next_rptr);
 214
 215         /* IB packet must end on a 8 DW boundary */
 216         while ((ring->wptr & 7) != 4)
 217                 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
 218         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
 219         amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
 220         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
 221         amdgpu_ring_write(ring, ib->length_dw);
 222
 223 }
 224
 225 /**
 226  * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 227  *
 228  * @ring: amdgpu ring pointer
 229  *
 230  * Emit an hdp flush packet on the requested DMA ring.
 231  */
 232 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 233 {
 234         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
 235                           SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
 236         u32 ref_and_mask;
 237
 238         if (ring == &ring->adev->sdma[0].ring)
 239                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
 240         else
 241                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
 242
 243         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 244         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 245         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 246         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 247         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 248         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 249 }
 250
 251 /**
 252  * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
 253  *
 254  * @ring: amdgpu ring pointer
 255  * @fence: amdgpu fence object
 256  *
 257  * Add a DMA fence packet to the ring to write
 258  * the fence seq number and DMA trap packet to generate
 259  * an interrupt if needed (CIK).
 260  */
 261 static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 262                                      unsigned flags)
 263 {
 264         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 265         /* write the fence */
 266         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 267         amdgpu_ring_write(ring, lower_32_bits(addr));
 268         amdgpu_ring_write(ring, upper_32_bits(addr));
 269         amdgpu_ring_write(ring, lower_32_bits(seq));
 270
 271         /* optionally write high bits as well */
 272         if (write64bit) {
 273                 addr += 4;
 274                 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
 275                 amdgpu_ring_write(ring, lower_32_bits(addr));
 276                 amdgpu_ring_write(ring, upper_32_bits(addr));
 277                 amdgpu_ring_write(ring, upper_32_bits(seq));
 278         }
 279
 280         /* generate an interrupt */
 281         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
 282 }
 283
 284 /**
 285  * cik_sdma_ring_emit_semaphore - emit a semaphore on the dma ring
 286  *
 287  * @ring: amdgpu_ring structure holding ring information
 288  * @semaphore: amdgpu semaphore object
 289  * @emit_wait: wait or signal semaphore
 290  *
 291  * Add a DMA semaphore packet to the ring wait on or signal
 292  * other rings (CIK).
 293  */
 294 static bool cik_sdma_ring_emit_semaphore(struct amdgpu_ring *ring,
 295                                          struct amdgpu_semaphore *semaphore,
 296                                          bool emit_wait)
 297 {
 298         u64 addr = semaphore->gpu_addr;
 299         u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S;
 300
 301         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits));
 302         amdgpu_ring_write(ring, addr & 0xfffffff8);
 303         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
 304
 305         return true;
 306 }
 307
 308 /**
 309  * cik_sdma_gfx_stop - stop the gfx async dma engines
 310  *
 311  * @adev: amdgpu_device pointer
 312  *
 313  * Stop the gfx async dma ring buffers (CIK).
 314  */
 315 static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
 316 {
 317         struct amdgpu_ring *sdma0 = &adev->sdma[0].ring;
 318         struct amdgpu_ring *sdma1 = &adev->sdma[1].ring;
 319         u32 rb_cntl;
 320         int i;
 321
 322         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 323             (adev->mman.buffer_funcs_ring == sdma1))
 324                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 325
 326         for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
 327                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 328                 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
 329                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 330                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
 331         }
 332         sdma0->ready = false;
 333         sdma1->ready = false;
 334 }
 335
 336 /**
 337  * cik_sdma_rlc_stop - stop the compute async dma engines
 338  *
 339  * @adev: amdgpu_device pointer
 340  *
 341  * Stop the compute async dma queues (CIK).
 342  */
 343 static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
 344 {
 345         /* XXX todo */
 346 }
 347
 348 /**
 349  * cik_sdma_enable - stop the async dma engines
 350  *
 351  * @adev: amdgpu_device pointer
 352  * @enable: enable/disable the DMA MEs.
 353  *
 354  * Halt or unhalt the async dma engines (CIK).
 355  */
 356 static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
 357 {
 358         u32 me_cntl;
 359         int i;
 360
 361         if (enable == false) {
 362                 cik_sdma_gfx_stop(adev);
 363                 cik_sdma_rlc_stop(adev);
 364         }
 365
 366         for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
 367                 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 368                 if (enable)
 369                         me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
 370                 else
 371                         me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
 372                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
 373         }
 374 }
 375
 376 /**
 377  * cik_sdma_gfx_resume - setup and start the async dma engines
 378  *
 379  * @adev: amdgpu_device pointer
 380  *
 381  * Set up the gfx DMA ring buffers and enable them (CIK).
 382  * Returns 0 for success, error for failure.
 383  */
 384 static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
 385 {
 386         struct amdgpu_ring *ring;
 387         u32 rb_cntl, ib_cntl;
 388         u32 rb_bufsz;
 389         u32 wb_offset;
 390         int i, j, r;
 391
 392         for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
 393                 ring = &adev->sdma[i].ring;
 394                 wb_offset = (ring->rptr_offs * 4);
 395
 396                 mutex_lock(&adev->srbm_mutex);
 397                 for (j = 0; j < 16; j++) {
 398                         cik_srbm_select(adev, 0, 0, 0, j);
 399                         /* SDMA GFX */
 400                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 401                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 402                         /* XXX SDMA RLC - todo */
 403                 }
 404                 cik_srbm_select(adev, 0, 0, 0, 0);
 405                 mutex_unlock(&adev->srbm_mutex);
 406
 407                 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
 408                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 409
 410                 /* Set ring buffer size in dwords */
 411                 rb_bufsz = order_base_2(ring->ring_size / 4);
 412                 rb_cntl = rb_bufsz << 1;
 413 #ifdef __BIG_ENDIAN
 414                 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
 415                         SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
 416 #endif
 417                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 418
 419                 /* Initialize the ring buffer's read and write pointers */
 420                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 421                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 422
 423                 /* set the wb address whether it's enabled or not */
 424                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 425                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 426                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 427                        ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
 428
 429                 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
 430
 431                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 432                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 433
 434                 ring->wptr = 0;
 435                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
 436
 437                 /* enable DMA RB */
 438                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
 439                        rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
 440
 441                 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
 442 #ifdef __BIG_ENDIAN
 443                 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
 444 #endif
 445                 /* enable DMA IBs */
 446                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 447
 448                 ring->ready = true;
 449
 450                 r = amdgpu_ring_test_ring(ring);
 451                 if (r) {
 452                         ring->ready = false;
 453                         return r;
 454                 }
 455
 456                 if (adev->mman.buffer_funcs_ring == ring)
 457                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 458         }
 459
 460         return 0;
 461 }
 462
 463 /**
 464  * cik_sdma_rlc_resume - setup and start the async dma engines
 465  *
 466  * @adev: amdgpu_device pointer
 467  *
 468  * Set up the compute DMA queues and enable them (CIK).
 469  * Returns 0 for success, error for failure.
 470  */
 471 static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
 472 {
 473         /* XXX todo */
 474         return 0;
 475 }
 476
 477 /**
 478  * cik_sdma_load_microcode - load the sDMA ME ucode
 479  *
 480  * @adev: amdgpu_device pointer
 481  *
 482  * Loads the sDMA0/1 ucode.
 483  * Returns 0 for success, -EINVAL if the ucode is not available.
 484  */
 485 static int cik_sdma_load_microcode(struct amdgpu_device *adev)
 486 {
 487         const struct sdma_firmware_header_v1_0 *hdr;
 488         const __le32 *fw_data;
 489         u32 fw_size;
 490         int i, j;
 491
 492         if (!adev->sdma[0].fw || !adev->sdma[1].fw)
 493                 return -EINVAL;
 494
 495         /* halt the MEs */
 496         cik_sdma_enable(adev, false);
 497
 498         for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
 499                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
 500                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 501                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 502                 adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 503                 adev->sdma[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 504                 fw_data = (const __le32 *)
 505                         (adev->sdma[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 506                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 507                 for (j = 0; j < fw_size; j++)
 508                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 509                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version);
 510         }
 511
 512         return 0;
 513 }
 514
 515 /**
 516  * cik_sdma_start - setup and start the async dma engines
 517  *
 518  * @adev: amdgpu_device pointer
 519  *
 520  * Set up the DMA engines and enable them (CIK).
 521  * Returns 0 for success, error for failure.
 522  */
 523 static int cik_sdma_start(struct amdgpu_device *adev)
 524 {
 525         int r;
 526
 527         r = cik_sdma_load_microcode(adev);
 528         if (r)
 529                 return r;
 530
 531         /* unhalt the MEs */
 532         cik_sdma_enable(adev, true);
 533
 534         /* start the gfx rings and rlc compute queues */
 535         r = cik_sdma_gfx_resume(adev);
 536         if (r)
 537                 return r;
 538         r = cik_sdma_rlc_resume(adev);
 539         if (r)
 540                 return r;
 541
 542         return 0;
 543 }
 544
 545 /**
 546  * cik_sdma_ring_test_ring - simple async dma engine test
 547  *
 548  * @ring: amdgpu_ring structure holding ring information
 549  *
 550  * Test the DMA engine by writing using it to write an
 551  * value to memory. (CIK).
 552  * Returns 0 for success, error for failure.
 553  */
 554 static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
 555 {
 556         struct amdgpu_device *adev = ring->adev;
 557         unsigned i;
 558         unsigned index;
 559         int r;
 560         u32 tmp;
 561         u64 gpu_addr;
 562
 563         r = amdgpu_wb_get(adev, &index);
 564         if (r) {
 565                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 566                 return r;
 567         }
 568
 569         gpu_addr = adev->wb.gpu_addr + (index * 4);
 570         tmp = 0xCAFEDEAD;
 571         adev->wb.wb[index] = cpu_to_le32(tmp);
 572
 573         r = amdgpu_ring_lock(ring, 5);
 574         if (r) {
 575                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 576                 amdgpu_wb_free(adev, index);
 577                 return r;
 578         }
 579         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
 580         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 581         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 582         amdgpu_ring_write(ring, 1); /* number of DWs to follow */
 583         amdgpu_ring_write(ring, 0xDEADBEEF);
 584         amdgpu_ring_unlock_commit(ring);
 585
 586         for (i = 0; i < adev->usec_timeout; i++) {
 587                 tmp = le32_to_cpu(adev->wb.wb[index]);
 588                 if (tmp == 0xDEADBEEF)
 589                         break;
 590                 DRM_UDELAY(1);
 591         }
 592
 593         if (i < adev->usec_timeout) {
 594                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 595         } else {
 596                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 597                           ring->idx, tmp);
 598                 r = -EINVAL;
 599         }
 600         amdgpu_wb_free(adev, index);
 601
 602         return r;
 603 }
 604
 605 /**
 606  * cik_sdma_ring_test_ib - test an IB on the DMA engine
 607  *
 608  * @ring: amdgpu_ring structure holding ring information
 609  *
 610  * Test a simple IB in the DMA ring (CIK).
 611  * Returns 0 on success, error on failure.
 612  */
 613 static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
 614 {
 615         struct amdgpu_device *adev = ring->adev;
 616         struct amdgpu_ib ib;
 617         struct fence *f = NULL;
 618         unsigned i;
 619         unsigned index;
 620         int r;
 621         u32 tmp = 0;
 622         u64 gpu_addr;
 623
 624         r = amdgpu_wb_get(adev, &index);
 625         if (r) {
 626                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 627                 return r;
 628         }
 629
 630         gpu_addr = adev->wb.gpu_addr + (index * 4);
 631         tmp = 0xCAFEDEAD;
 632         adev->wb.wb[index] = cpu_to_le32(tmp);
 633         memset(&ib, 0, sizeof(ib));
 634         r = amdgpu_ib_get(ring, NULL, 256, &ib);
 635         if (r) {
 636                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
 637                 goto err0;
 638         }
 639
 640         ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 641         ib.ptr[1] = lower_32_bits(gpu_addr);
 642         ib.ptr[2] = upper_32_bits(gpu_addr);
 643         ib.ptr[3] = 1;
 644         ib.ptr[4] = 0xDEADBEEF;
 645         ib.length_dw = 5;
 646         r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
 647                                                  AMDGPU_FENCE_OWNER_UNDEFINED,
 648                                                  &f);
 649         if (r)
 650                 goto err1;
 651
 652         r = fence_wait(f, false);
 653         if (r) {
 654                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 655                 goto err1;
 656         }
 657         for (i = 0; i < adev->usec_timeout; i++) {
 658                 tmp = le32_to_cpu(adev->wb.wb[index]);
 659                 if (tmp == 0xDEADBEEF)
 660                         break;
 661                 DRM_UDELAY(1);
 662         }
 663         if (i < adev->usec_timeout) {
 664                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
 665                          ring->idx, i);
 666                 goto err1;
 667         } else {
 668                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 669                 r = -EINVAL;
 670         }
 671
 672 err1:
 673         fence_put(f);
 674         amdgpu_ib_free(adev, &ib);
 675 err0:
 676         amdgpu_wb_free(adev, index);
 677         return r;
 678 }
 679
 680 /**
 681  * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
 682  *
 683  * @ib: indirect buffer to fill with commands
 684  * @pe: addr of the page entry
 685  * @src: src addr to copy from
 686  * @count: number of page entries to update
 687  *
 688  * Update PTEs by copying them from the GART using sDMA (CIK).
 689  */
 690 static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
 691                                  uint64_t pe, uint64_t src,
 692                                  unsigned count)
 693 {
 694         while (count) {
 695                 unsigned bytes = count * 8;
 696                 if (bytes > 0x1FFFF8)
 697                         bytes = 0x1FFFF8;
 698
 699                 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
 700                         SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 701                 ib->ptr[ib->length_dw++] = bytes;
 702                 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 703                 ib->ptr[ib->length_dw++] = lower_32_bits(src);
 704                 ib->ptr[ib->length_dw++] = upper_32_bits(src);
 705                 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 706                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 707
 708                 pe += bytes;
 709                 src += bytes;
 710                 count -= bytes / 8;
 711         }
 712 }
 713
 714 /**
 715  * cik_sdma_vm_write_pages - update PTEs by writing them manually
 716  *
 717  * @ib: indirect buffer to fill with commands
 718  * @pe: addr of the page entry
 719  * @addr: dst addr to write into pe
 720  * @count: number of page entries to update
 721  * @incr: increase next addr by incr bytes
 722  * @flags: access flags
 723  *
 724  * Update PTEs by writing them manually using sDMA (CIK).
 725  */
 726 static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib,
 727                                   uint64_t pe,
 728                                   uint64_t addr, unsigned count,
 729                                   uint32_t incr, uint32_t flags)
 730 {
 731         uint64_t value;
 732         unsigned ndw;
 733
 734         while (count) {
 735                 ndw = count * 2;
 736                 if (ndw > 0xFFFFE)
 737                         ndw = 0xFFFFE;
 738
 739                 /* for non-physically contiguous pages (system) */
 740                 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
 741                         SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 742                 ib->ptr[ib->length_dw++] = pe;
 743                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 744                 ib->ptr[ib->length_dw++] = ndw;
 745                 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
 746                         if (flags & AMDGPU_PTE_SYSTEM) {
 747                                 value = amdgpu_vm_map_gart(ib->ring->adev, addr);
 748                                 value &= 0xFFFFFFFFFFFFF000ULL;
 749                         } else if (flags & AMDGPU_PTE_VALID) {
 750                                 value = addr;
 751                         } else {
 752                                 value = 0;
 753                         }
 754                         addr += incr;
 755                         value |= flags;
 756                         ib->ptr[ib->length_dw++] = value;
 757                         ib->ptr[ib->length_dw++] = upper_32_bits(value);
 758                 }
 759         }
 760 }
 761
 762 /**
 763  * cik_sdma_vm_set_pages - update the page tables using sDMA
 764  *
 765  * @ib: indirect buffer to fill with commands
 766  * @pe: addr of the page entry
 767  * @addr: dst addr to write into pe
 768  * @count: number of page entries to update
 769  * @incr: increase next addr by incr bytes
 770  * @flags: access flags
 771  *
 772  * Update the page tables using sDMA (CIK).
 773  */
 774 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib,
 775                                     uint64_t pe,
 776                                     uint64_t addr, unsigned count,
 777                                     uint32_t incr, uint32_t flags)
 778 {
 779         uint64_t value;
 780         unsigned ndw;
 781
 782         while (count) {
 783                 ndw = count;
 784                 if (ndw > 0x7FFFF)
 785                         ndw = 0x7FFFF;
 786
 787                 if (flags & AMDGPU_PTE_VALID)
 788                         value = addr;
 789                 else
 790                         value = 0;
 791
 792                 /* for physically contiguous pages (vram) */
 793                 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
 794                 ib->ptr[ib->length_dw++] = pe; /* dst addr */
 795                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 796                 ib->ptr[ib->length_dw++] = flags; /* mask */
 797                 ib->ptr[ib->length_dw++] = 0;
 798                 ib->ptr[ib->length_dw++] = value; /* value */
 799                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 800                 ib->ptr[ib->length_dw++] = incr; /* increment size */
 801                 ib->ptr[ib->length_dw++] = 0;
 802                 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
 803
 804                 pe += ndw * 8;
 805                 addr += ndw * incr;
 806                 count -= ndw;
 807         }
 808 }
 809
 810 /**
 811  * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
 812  *
 813  * @ib: indirect buffer to fill with padding
 814  *
 815  */
 816 static void cik_sdma_vm_pad_ib(struct amdgpu_ib *ib)
 817 {
 818         while (ib->length_dw & 0x7)
 819                 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
 820 }
 821
 822 /**
 823  * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
 824  *
 825  * @ring: amdgpu_ring pointer
 826  * @vm: amdgpu_vm pointer
 827  *
 828  * Update the page table base and flush the VM TLB
 829  * using sDMA (CIK).
 830  */
 831 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
 832                                         unsigned vm_id, uint64_t pd_addr)
 833 {
 834         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
 835                           SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
 836
 837         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 838         if (vm_id < 8) {
 839                 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
 840         } else {
 841                 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
 842         }
 843         amdgpu_ring_write(ring, pd_addr >> 12);
 844
 845         /* flush TLB */
 846         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
 847         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
 848         amdgpu_ring_write(ring, 1 << vm_id);
 849
 850         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
 851         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 852         amdgpu_ring_write(ring, 0);
 853         amdgpu_ring_write(ring, 0); /* reference */
 854         amdgpu_ring_write(ring, 0); /* mask */
 855         amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
 856 }
 857
 858 static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
 859                                  bool enable)
 860 {
 861         u32 orig, data;
 862
 863         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_MGCG)) {
 864                 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
 865                 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
 866         } else {
 867                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
 868                 data |= 0xff000000;
 869                 if (data != orig)
 870                         WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
 871
 872                 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
 873                 data |= 0xff000000;
 874                 if (data != orig)
 875                         WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
 876         }
 877 }
 878
 879 static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
 880                                  bool enable)
 881 {
 882         u32 orig, data;
 883
 884         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_SDMA_LS)) {
 885                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 886                 data |= 0x100;
 887                 if (orig != data)
 888                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 889
 890                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 891                 data |= 0x100;
 892                 if (orig != data)
 893                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 894         } else {
 895                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
 896                 data &= ~0x100;
 897                 if (orig != data)
 898                         WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
 899
 900                 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
 901                 data &= ~0x100;
 902                 if (orig != data)
 903                         WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
 904         }
 905 }
 906
 907 static int cik_sdma_early_init(void *handle)
 908 {
 909         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 910
 911         cik_sdma_set_ring_funcs(adev);
 912         cik_sdma_set_irq_funcs(adev);
 913         cik_sdma_set_buffer_funcs(adev);
 914         cik_sdma_set_vm_pte_funcs(adev);
 915
 916         return 0;
 917 }
 918
 919 static int cik_sdma_sw_init(void *handle)
 920 {
 921         struct amdgpu_ring *ring;
 922         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 923         int r;
 924
 925         r = cik_sdma_init_microcode(adev);
 926         if (r) {
 927                 DRM_ERROR("Failed to load sdma firmware!\n");
 928                 return r;
 929         }
 930
 931         /* SDMA trap event */
 932         r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq);
 933         if (r)
 934                 return r;
 935
 936         /* SDMA Privileged inst */
 937         r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq);
 938         if (r)
 939                 return r;
 940
 941         /* SDMA Privileged inst */
 942         r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq);
 943         if (r)
 944                 return r;
 945
 946         ring = &adev->sdma[0].ring;
 947         ring->ring_obj = NULL;
 948
 949         ring = &adev->sdma[1].ring;
 950         ring->ring_obj = NULL;
 951
 952         ring = &adev->sdma[0].ring;
 953         sprintf(ring->name, "sdma0");
 954         r = amdgpu_ring_init(adev, ring, 256 * 1024,
 955                              SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf,
 956                              &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0,
 957                              AMDGPU_RING_TYPE_SDMA);
 958         if (r)
 959                 return r;
 960
 961         ring = &adev->sdma[1].ring;
 962         sprintf(ring->name, "sdma1");
 963         r = amdgpu_ring_init(adev, ring, 256 * 1024,
 964                              SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf,
 965                              &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1,
 966                              AMDGPU_RING_TYPE_SDMA);
 967         if (r)
 968                 return r;
 969
 970         return r;
 971 }
 972
 973 static int cik_sdma_sw_fini(void *handle)
 974 {
 975         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 976
 977         amdgpu_ring_fini(&adev->sdma[0].ring);
 978         amdgpu_ring_fini(&adev->sdma[1].ring);
 979
 980         return 0;
 981 }
 982
 983 static int cik_sdma_hw_init(void *handle)
 984 {
 985         int r;
 986         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 987
 988         r = cik_sdma_start(adev);
 989         if (r)
 990                 return r;
 991
 992         return r;
 993 }
 994
 995 static int cik_sdma_hw_fini(void *handle)
 996 {
 997         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 998
 999         cik_sdma_enable(adev, false);
1000
1001         return 0;
1002 }
1003
1004 static int cik_sdma_suspend(void *handle)
1005 {
1006         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1007
1008         return cik_sdma_hw_fini(adev);
1009 }
1010
1011 static int cik_sdma_resume(void *handle)
1012 {
1013         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1014
1015         return cik_sdma_hw_init(adev);
1016 }
1017
1018 static bool cik_sdma_is_idle(void *handle)
1019 {
1020         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1021         u32 tmp = RREG32(mmSRBM_STATUS2);
1022
1023         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1024                                 SRBM_STATUS2__SDMA1_BUSY_MASK))
1025             return false;
1026
1027         return true;
1028 }
1029
1030 static int cik_sdma_wait_for_idle(void *handle)
1031 {
1032         unsigned i;
1033         u32 tmp;
1034         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1035
1036         for (i = 0; i < adev->usec_timeout; i++) {
1037                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1038                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1039
1040                 if (!tmp)
1041                         return 0;
1042                 udelay(1);
1043         }
1044         return -ETIMEDOUT;
1045 }
1046
1047 static void cik_sdma_print_status(void *handle)
1048 {
1049         int i, j;
1050         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1051
1052         dev_info(adev->dev, "CIK SDMA registers\n");
1053         dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
1054                  RREG32(mmSRBM_STATUS2));
1055         for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
1056                 dev_info(adev->dev, "  SDMA%d_STATUS_REG=0x%08X\n",
1057                          i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1058                 dev_info(adev->dev, "  SDMA%d_ME_CNTL=0x%08X\n",
1059                          i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1060                 dev_info(adev->dev, "  SDMA%d_CNTL=0x%08X\n",
1061                          i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1062                 dev_info(adev->dev, "  SDMA%d_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n",
1063                          i, RREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i]));
1064                 dev_info(adev->dev, "  SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1065                          i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1066                 dev_info(adev->dev, "  SDMA%d_GFX_IB_CNTL=0x%08X\n",
1067                          i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1068                 dev_info(adev->dev, "  SDMA%d_GFX_RB_CNTL=0x%08X\n",
1069                          i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1070                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR=0x%08X\n",
1071                          i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1072                 dev_info(adev->dev, "  SDMA%d_GFX_RB_WPTR=0x%08X\n",
1073                          i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1074                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1075                          i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1076                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1077                          i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1078                 dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE=0x%08X\n",
1079                          i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1080                 dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1081                          i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
1082                 mutex_lock(&adev->srbm_mutex);
1083                 for (j = 0; j < 16; j++) {
1084                         cik_srbm_select(adev, 0, 0, 0, j);
1085                         dev_info(adev->dev, "  VM %d:\n", j);
1086                         dev_info(adev->dev, "  SDMA0_GFX_VIRTUAL_ADDR=0x%08X\n",
1087                                  RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1088                         dev_info(adev->dev, "  SDMA0_GFX_APE1_CNTL=0x%08X\n",
1089                                  RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1090                 }
1091                 cik_srbm_select(adev, 0, 0, 0, 0);
1092                 mutex_unlock(&adev->srbm_mutex);
1093         }
1094 }
1095
1096 static int cik_sdma_soft_reset(void *handle)
1097 {
1098         u32 srbm_soft_reset = 0;
1099         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1100         u32 tmp = RREG32(mmSRBM_STATUS2);
1101
1102         if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1103                 /* sdma0 */
1104                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1105                 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1106                 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1107                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1108         }
1109         if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1110                 /* sdma1 */
1111                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1112                 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1113                 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1114                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1115         }
1116
1117         if (srbm_soft_reset) {
1118                 cik_sdma_print_status((void *)adev);
1119
1120                 tmp = RREG32(mmSRBM_SOFT_RESET);
1121                 tmp |= srbm_soft_reset;
1122                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1123                 WREG32(mmSRBM_SOFT_RESET, tmp);
1124                 tmp = RREG32(mmSRBM_SOFT_RESET);
1125
1126                 udelay(50);
1127
1128                 tmp &= ~srbm_soft_reset;
1129                 WREG32(mmSRBM_SOFT_RESET, tmp);
1130                 tmp = RREG32(mmSRBM_SOFT_RESET);
1131
1132                 /* Wait a little for things to settle down */
1133                 udelay(50);
1134
1135                 cik_sdma_print_status((void *)adev);
1136         }
1137
1138         return 0;
1139 }
1140
1141 static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
1142                                        struct amdgpu_irq_src *src,
1143                                        unsigned type,
1144                                        enum amdgpu_interrupt_state state)
1145 {
1146         u32 sdma_cntl;
1147
1148         switch (type) {
1149         case AMDGPU_SDMA_IRQ_TRAP0:
1150                 switch (state) {
1151                 case AMDGPU_IRQ_STATE_DISABLE:
1152                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1153                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1154                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1155                         break;
1156                 case AMDGPU_IRQ_STATE_ENABLE:
1157                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1158                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1159                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1160                         break;
1161                 default:
1162                         break;
1163                 }
1164                 break;
1165         case AMDGPU_SDMA_IRQ_TRAP1:
1166                 switch (state) {
1167                 case AMDGPU_IRQ_STATE_DISABLE:
1168                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1169                         sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1170                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1171                         break;
1172                 case AMDGPU_IRQ_STATE_ENABLE:
1173                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1174                         sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1175                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1176                         break;
1177                 default:
1178                         break;
1179                 }
1180                 break;
1181         default:
1182                 break;
1183         }
1184         return 0;
1185 }
1186
1187 static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
1188                                      struct amdgpu_irq_src *source,
1189                                      struct amdgpu_iv_entry *entry)
1190 {
1191         u8 instance_id, queue_id;
1192
1193         instance_id = (entry->ring_id & 0x3) >> 0;
1194         queue_id = (entry->ring_id & 0xc) >> 2;
1195         DRM_DEBUG("IH: SDMA trap\n");
1196         switch (instance_id) {
1197         case 0:
1198                 switch (queue_id) {
1199                 case 0:
1200                         amdgpu_fence_process(&adev->sdma[0].ring);
1201                         break;
1202                 case 1:
1203                         /* XXX compute */
1204                         break;
1205                 case 2:
1206                         /* XXX compute */
1207                         break;
1208                 }
1209                 break;
1210         case 1:
1211                 switch (queue_id) {
1212                 case 0:
1213                         amdgpu_fence_process(&adev->sdma[1].ring);
1214                         break;
1215                 case 1:
1216                         /* XXX compute */
1217                         break;
1218                 case 2:
1219                         /* XXX compute */
1220                         break;
1221                 }
1222                 break;
1223         }
1224
1225         return 0;
1226 }
1227
1228 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1229                                              struct amdgpu_irq_src *source,
1230                                              struct amdgpu_iv_entry *entry)
1231 {
1232         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1233         schedule_work(&adev->reset_work);
1234         return 0;
1235 }
1236
1237 static int cik_sdma_set_clockgating_state(void *handle,
1238                                           enum amd_clockgating_state state)
1239 {
1240         bool gate = false;
1241         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1242
1243         if (state == AMD_CG_STATE_GATE)
1244                 gate = true;
1245
1246         cik_enable_sdma_mgcg(adev, gate);
1247         cik_enable_sdma_mgls(adev, gate);
1248
1249         return 0;
1250 }
1251
1252 static int cik_sdma_set_powergating_state(void *handle,
1253                                           enum amd_powergating_state state)
1254 {
1255         return 0;
1256 }
1257
1258 const struct amd_ip_funcs cik_sdma_ip_funcs = {
1259         .early_init = cik_sdma_early_init,
1260         .late_init = NULL,
1261         .sw_init = cik_sdma_sw_init,
1262         .sw_fini = cik_sdma_sw_fini,
1263         .hw_init = cik_sdma_hw_init,
1264         .hw_fini = cik_sdma_hw_fini,
1265         .suspend = cik_sdma_suspend,
1266         .resume = cik_sdma_resume,
1267         .is_idle = cik_sdma_is_idle,
1268         .wait_for_idle = cik_sdma_wait_for_idle,
1269         .soft_reset = cik_sdma_soft_reset,
1270         .print_status = cik_sdma_print_status,
1271         .set_clockgating_state = cik_sdma_set_clockgating_state,
1272         .set_powergating_state = cik_sdma_set_powergating_state,
1273 };
1274
1275 /**
1276  * cik_sdma_ring_is_lockup - Check if the DMA engine is locked up
1277  *
1278  * @ring: amdgpu_ring structure holding ring information
1279  *
1280  * Check if the async DMA engine is locked up (CIK).
1281  * Returns true if the engine appears to be locked up, false if not.
1282  */
1283 static bool cik_sdma_ring_is_lockup(struct amdgpu_ring *ring)
1284 {
1285
1286         if (cik_sdma_is_idle(ring->adev)) {
1287                 amdgpu_ring_lockup_update(ring);
1288                 return false;
1289         }
1290         return amdgpu_ring_test_lockup(ring);
1291 }
1292
1293 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1294         .get_rptr = cik_sdma_ring_get_rptr,
1295         .get_wptr = cik_sdma_ring_get_wptr,
1296         .set_wptr = cik_sdma_ring_set_wptr,
1297         .parse_cs = NULL,
1298         .emit_ib = cik_sdma_ring_emit_ib,
1299         .emit_fence = cik_sdma_ring_emit_fence,
1300         .emit_semaphore = cik_sdma_ring_emit_semaphore,
1301         .emit_vm_flush = cik_sdma_ring_emit_vm_flush,
1302         .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
1303         .test_ring = cik_sdma_ring_test_ring,
1304         .test_ib = cik_sdma_ring_test_ib,
1305         .is_lockup = cik_sdma_ring_is_lockup,
1306 };
1307
1308 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
1309 {
1310         adev->sdma[0].ring.funcs = &cik_sdma_ring_funcs;
1311         adev->sdma[1].ring.funcs = &cik_sdma_ring_funcs;
1312 }
1313
1314 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
1315         .set = cik_sdma_set_trap_irq_state,
1316         .process = cik_sdma_process_trap_irq,
1317 };
1318
1319 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
1320         .process = cik_sdma_process_illegal_inst_irq,
1321 };
1322
1323 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
1324 {
1325         adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1326         adev->sdma_trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1327         adev->sdma_illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
1328 }
1329
1330 /**
1331  * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1332  *
1333  * @ring: amdgpu_ring structure holding ring information
1334  * @src_offset: src GPU address
1335  * @dst_offset: dst GPU address
1336  * @byte_count: number of bytes to xfer
1337  *
1338  * Copy GPU buffers using the DMA engine (CIK).
1339  * Used by the amdgpu ttm implementation to move pages if
1340  * registered as the asic copy callback.
1341  */
1342 static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
1343                                       uint64_t src_offset,
1344                                       uint64_t dst_offset,
1345                                       uint32_t byte_count)
1346 {
1347         ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
1348         ib->ptr[ib->length_dw++] = byte_count;
1349         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1350         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1351         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1352         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1353         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1354 }
1355
1356 /**
1357  * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1358  *
1359  * @ring: amdgpu_ring structure holding ring information
1360  * @src_data: value to write to buffer
1361  * @dst_offset: dst GPU address
1362  * @byte_count: number of bytes to xfer
1363  *
1364  * Fill GPU buffers using the DMA engine (CIK).
1365  */
1366 static void cik_sdma_emit_fill_buffer(struct amdgpu_ring *ring,
1367                                       uint32_t src_data,
1368                                       uint64_t dst_offset,
1369                                       uint32_t byte_count)
1370 {
1371         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0));
1372         amdgpu_ring_write(ring, lower_32_bits(dst_offset));
1373         amdgpu_ring_write(ring, upper_32_bits(dst_offset));
1374         amdgpu_ring_write(ring, src_data);
1375         amdgpu_ring_write(ring, byte_count);
1376 }
1377
1378 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
1379         .copy_max_bytes = 0x1fffff,
1380         .copy_num_dw = 7,
1381         .emit_copy_buffer = cik_sdma_emit_copy_buffer,
1382
1383         .fill_max_bytes = 0x1fffff,
1384         .fill_num_dw = 5,
1385         .emit_fill_buffer = cik_sdma_emit_fill_buffer,
1386 };
1387
1388 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1389 {
1390         if (adev->mman.buffer_funcs == NULL) {
1391                 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
1392                 adev->mman.buffer_funcs_ring = &adev->sdma[0].ring;
1393         }
1394 }
1395
1396 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1397         .copy_pte = cik_sdma_vm_copy_pte,
1398         .write_pte = cik_sdma_vm_write_pte,
1399         .set_pte_pde = cik_sdma_vm_set_pte_pde,
1400         .pad_ib = cik_sdma_vm_pad_ib,
1401 };
1402
1403 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1404 {
1405         if (adev->vm_manager.vm_pte_funcs == NULL) {
1406                 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
1407                 adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring;
1408                 adev->vm_manager.vm_pte_funcs_ring->is_pte_ring = true;
1409         }
1410 }