2 * arch/arm/mach-tegra/gpio.c
4 * Copyright (c) 2010 Google, Inc
7 * Erik Gilling <konkers@google.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/init.h>
21 #include <linux/irq.h>
22 #include <linux/interrupt.h>
25 #include <linux/gpio.h>
28 #include <asm/mach/irq.h>
30 #include <mach/gpio-tegra.h>
31 #include <mach/iomap.h>
32 #include <mach/suspend.h>
34 #define GPIO_BANK(x) ((x) >> 5)
35 #define GPIO_PORT(x) (((x) >> 3) & 0x3)
36 #define GPIO_BIT(x) ((x) & 0x7)
38 #define GPIO_REG(x) (IO_TO_VIRT(TEGRA_GPIO_BASE) + \
39 GPIO_BANK(x) * 0x80 + \
42 #define GPIO_CNF(x) (GPIO_REG(x) + 0x00)
43 #define GPIO_OE(x) (GPIO_REG(x) + 0x10)
44 #define GPIO_OUT(x) (GPIO_REG(x) + 0X20)
45 #define GPIO_IN(x) (GPIO_REG(x) + 0x30)
46 #define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40)
47 #define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50)
48 #define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60)
49 #define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70)
51 #define GPIO_MSK_CNF(x) (GPIO_REG(x) + 0x800)
52 #define GPIO_MSK_OE(x) (GPIO_REG(x) + 0x810)
53 #define GPIO_MSK_OUT(x) (GPIO_REG(x) + 0X820)
54 #define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + 0x840)
55 #define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + 0x850)
56 #define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + 0x860)
58 #define GPIO_INT_LVL_MASK 0x010101
59 #define GPIO_INT_LVL_EDGE_RISING 0x000101
60 #define GPIO_INT_LVL_EDGE_FALLING 0x000100
61 #define GPIO_INT_LVL_EDGE_BOTH 0x010100
62 #define GPIO_INT_LVL_LEVEL_HIGH 0x000001
63 #define GPIO_INT_LVL_LEVEL_LOW 0x000000
65 struct tegra_gpio_bank {
68 spinlock_t lvl_lock[4];
79 static struct tegra_gpio_bank tegra_gpio_banks[] = {
80 {.bank = 0, .irq = INT_GPIO1},
81 {.bank = 1, .irq = INT_GPIO2},
82 {.bank = 2, .irq = INT_GPIO3},
83 {.bank = 3, .irq = INT_GPIO4},
84 {.bank = 4, .irq = INT_GPIO5},
85 {.bank = 5, .irq = INT_GPIO6},
86 {.bank = 6, .irq = INT_GPIO7},
89 static int tegra_gpio_compose(int bank, int port, int bit)
91 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
94 static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
98 val = 0x100 << GPIO_BIT(gpio);
100 val |= 1 << GPIO_BIT(gpio);
101 __raw_writel(val, reg);
104 void tegra_gpio_enable(int gpio)
106 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
109 void tegra_gpio_disable(int gpio)
111 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
114 static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
116 tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
119 static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
121 return (__raw_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
124 static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
126 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
130 static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
133 tegra_gpio_set(chip, offset, value);
134 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
138 static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
140 return TEGRA_GPIO_TO_IRQ(offset);
143 static struct gpio_chip tegra_gpio_chip = {
144 .label = "tegra-gpio",
145 .direction_input = tegra_gpio_direction_input,
146 .get = tegra_gpio_get,
147 .direction_output = tegra_gpio_direction_output,
148 .set = tegra_gpio_set,
149 .to_irq = tegra_gpio_to_irq,
151 .ngpio = TEGRA_NR_GPIOS,
154 static void tegra_gpio_irq_ack(struct irq_data *d)
156 int gpio = d->irq - INT_GPIO_BASE;
158 __raw_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
161 static void tegra_gpio_irq_mask(struct irq_data *d)
163 int gpio = d->irq - INT_GPIO_BASE;
165 tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
168 static void tegra_gpio_irq_unmask(struct irq_data *d)
170 int gpio = d->irq - INT_GPIO_BASE;
172 tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
175 static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
177 int gpio = d->irq - INT_GPIO_BASE;
178 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
179 int port = GPIO_PORT(gpio);
184 switch (type & IRQ_TYPE_SENSE_MASK) {
185 case IRQ_TYPE_EDGE_RISING:
186 lvl_type = GPIO_INT_LVL_EDGE_RISING;
189 case IRQ_TYPE_EDGE_FALLING:
190 lvl_type = GPIO_INT_LVL_EDGE_FALLING;
193 case IRQ_TYPE_EDGE_BOTH:
194 lvl_type = GPIO_INT_LVL_EDGE_BOTH;
197 case IRQ_TYPE_LEVEL_HIGH:
198 lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
201 case IRQ_TYPE_LEVEL_LOW:
202 lvl_type = GPIO_INT_LVL_LEVEL_LOW;
209 spin_lock_irqsave(&bank->lvl_lock[port], flags);
211 val = __raw_readl(GPIO_INT_LVL(gpio));
212 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
213 val |= lvl_type << GPIO_BIT(gpio);
214 __raw_writel(val, GPIO_INT_LVL(gpio));
216 spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
218 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
219 __irq_set_handler_locked(d->irq, handle_level_irq);
220 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
221 __irq_set_handler_locked(d->irq, handle_edge_irq);
226 static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
228 struct tegra_gpio_bank *bank;
232 struct irq_chip *chip = irq_desc_get_chip(desc);
234 chained_irq_enter(chip, desc);
236 bank = irq_get_handler_data(irq);
238 for (port = 0; port < 4; port++) {
239 int gpio = tegra_gpio_compose(bank->bank, port, 0);
240 unsigned long sta = __raw_readl(GPIO_INT_STA(gpio)) &
241 __raw_readl(GPIO_INT_ENB(gpio));
242 u32 lvl = __raw_readl(GPIO_INT_LVL(gpio));
244 for_each_set_bit(pin, &sta, 8) {
245 __raw_writel(1 << pin, GPIO_INT_CLR(gpio));
247 /* if gpio is edge triggered, clear condition
248 * before executing the hander so that we don't
251 if (lvl & (0x100 << pin)) {
253 chained_irq_exit(chip, desc);
256 generic_handle_irq(gpio_to_irq(gpio + pin));
261 chained_irq_exit(chip, desc);
266 void tegra_gpio_resume(void)
272 local_irq_save(flags);
274 for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
275 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
277 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
278 unsigned int gpio = (b<<5) | (p<<3);
279 __raw_writel(bank->cnf[p], GPIO_CNF(gpio));
280 __raw_writel(bank->out[p], GPIO_OUT(gpio));
281 __raw_writel(bank->oe[p], GPIO_OE(gpio));
282 __raw_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
283 __raw_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
287 local_irq_restore(flags);
290 void tegra_gpio_suspend(void)
296 local_irq_save(flags);
297 for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
298 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
300 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
301 unsigned int gpio = (b<<5) | (p<<3);
302 bank->cnf[p] = __raw_readl(GPIO_CNF(gpio));
303 bank->out[p] = __raw_readl(GPIO_OUT(gpio));
304 bank->oe[p] = __raw_readl(GPIO_OE(gpio));
305 bank->int_enb[p] = __raw_readl(GPIO_INT_ENB(gpio));
306 bank->int_lvl[p] = __raw_readl(GPIO_INT_LVL(gpio));
309 local_irq_restore(flags);
312 static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
314 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
315 return irq_set_irq_wake(bank->irq, enable);
319 static struct irq_chip tegra_gpio_irq_chip = {
321 .irq_ack = tegra_gpio_irq_ack,
322 .irq_mask = tegra_gpio_irq_mask,
323 .irq_unmask = tegra_gpio_irq_unmask,
324 .irq_set_type = tegra_gpio_irq_set_type,
326 .irq_set_wake = tegra_gpio_wake_enable,
331 /* This lock class tells lockdep that GPIO irqs are in a different
332 * category than their parents, so it won't report false recursion.
334 static struct lock_class_key gpio_lock_class;
336 static int __init tegra_gpio_init(void)
338 struct tegra_gpio_bank *bank;
343 for (i = 0; i < 7; i++) {
344 for (j = 0; j < 4; j++) {
345 int gpio = tegra_gpio_compose(i, j, 0);
346 __raw_writel(0x00, GPIO_INT_ENB(gpio));
350 #ifdef CONFIG_OF_GPIO
352 * This isn't ideal, but it gets things hooked up until this
353 * driver is converted into a platform_device
355 tegra_gpio_chip.of_node = of_find_compatible_node(NULL, NULL,
356 "nvidia,tegra20-gpio");
357 #endif /* CONFIG_OF_GPIO */
359 gpiochip_add(&tegra_gpio_chip);
361 for (gpio = 0; gpio < TEGRA_NR_GPIOS; gpio++) {
362 int irq = TEGRA_GPIO_TO_IRQ(gpio);
363 /* No validity check; all Tegra GPIOs are valid IRQs */
365 bank = &tegra_gpio_banks[GPIO_BANK(gpio)];
367 irq_set_lockdep_class(irq, &gpio_lock_class);
368 irq_set_chip_data(irq, bank);
369 irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
371 set_irq_flags(irq, IRQF_VALID);
374 for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
375 bank = &tegra_gpio_banks[i];
377 irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
378 irq_set_handler_data(bank->irq, bank);
380 for (j = 0; j < 4; j++)
381 spin_lock_init(&bank->lvl_lock[j]);
387 postcore_initcall(tegra_gpio_init);
389 void __init tegra_gpio_config(struct tegra_gpio_table *table, int num)
393 for (i = 0; i < num; i++) {
394 int gpio = table[i].gpio;
397 tegra_gpio_enable(gpio);
399 tegra_gpio_disable(gpio);
403 #ifdef CONFIG_DEBUG_FS
405 #include <linux/debugfs.h>
406 #include <linux/seq_file.h>
408 static int dbg_gpio_show(struct seq_file *s, void *unused)
413 for (i = 0; i < 7; i++) {
414 for (j = 0; j < 4; j++) {
415 int gpio = tegra_gpio_compose(i, j, 0);
417 "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
419 __raw_readl(GPIO_CNF(gpio)),
420 __raw_readl(GPIO_OE(gpio)),
421 __raw_readl(GPIO_OUT(gpio)),
422 __raw_readl(GPIO_IN(gpio)),
423 __raw_readl(GPIO_INT_STA(gpio)),
424 __raw_readl(GPIO_INT_ENB(gpio)),
425 __raw_readl(GPIO_INT_LVL(gpio)));
431 static int dbg_gpio_open(struct inode *inode, struct file *file)
433 return single_open(file, dbg_gpio_show, &inode->i_private);
436 static const struct file_operations debug_fops = {
437 .open = dbg_gpio_open,
440 .release = single_release,
443 static int __init tegra_gpio_debuginit(void)
445 (void) debugfs_create_file("tegra_gpio", S_IRUGO,
446 NULL, NULL, &debug_fops);
449 late_initcall(tegra_gpio_debuginit);