2 * Support functions for OMAP GPIO
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
22 #include <linux/slab.h>
23 #include <linux/pm_runtime.h>
25 #include <mach/hardware.h>
27 #include <mach/irqs.h>
29 #include <asm/mach/irq.h>
35 u16 virtual_irq_start;
38 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
42 u32 enabled_non_wakeup_gpios;
45 u32 saved_fallingdetect;
46 u32 saved_risingdetect;
51 struct gpio_chip chip;
60 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
62 struct omap_gpio_reg_offs *regs;
65 #ifdef CONFIG_ARCH_OMAP3
66 struct omap3_gpio_regs {
79 static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
83 * TODO: Cleanup gpio_bank usage as it is having information
84 * related to all instances of the device
86 static struct gpio_bank *gpio_bank;
88 /* TODO: Analyze removing gpio_bank_count usage from driver code */
91 #define GPIO_INDEX(bank, gpio) (gpio % bank->width)
92 #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
94 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
96 void __iomem *reg = bank->base;
99 reg += bank->regs->direction;
100 l = __raw_readl(reg);
105 __raw_writel(l, reg);
109 /* set data out value using dedicate set/clear register */
110 static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
112 void __iomem *reg = bank->base;
113 u32 l = GPIO_BIT(bank, gpio);
116 reg += bank->regs->set_dataout;
118 reg += bank->regs->clr_dataout;
120 __raw_writel(l, reg);
123 /* set data out value using mask register */
124 static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
126 void __iomem *reg = bank->base + bank->regs->dataout;
127 u32 gpio_bit = GPIO_BIT(bank, gpio);
130 l = __raw_readl(reg);
135 __raw_writel(l, reg);
138 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
140 void __iomem *reg = bank->base + bank->regs->datain;
142 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
145 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
147 void __iomem *reg = bank->base + bank->regs->dataout;
149 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
152 static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
154 int l = __raw_readl(base + reg);
161 __raw_writel(l, base + reg);
165 * _set_gpio_debounce - low level gpio debounce time
166 * @bank: the gpio bank we're acting upon
167 * @gpio: the gpio number on this @gpio
168 * @debounce: debounce time to use
170 * OMAP's debounce time is in 31us steps so we need
171 * to convert and round up to the closest unit.
173 static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
180 if (!bank->dbck_flag)
185 else if (debounce > 7936)
188 debounce = (debounce / 0x1f) - 1;
190 l = GPIO_BIT(bank, gpio);
192 reg = bank->base + bank->regs->debounce;
193 __raw_writel(debounce, reg);
195 reg = bank->base + bank->regs->debounce_en;
196 val = __raw_readl(reg);
200 clk_enable(bank->dbck);
203 clk_disable(bank->dbck);
205 bank->dbck_enable_mask = val;
207 __raw_writel(val, reg);
210 #ifdef CONFIG_ARCH_OMAP2PLUS
211 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
214 void __iomem *base = bank->base;
215 u32 gpio_bit = 1 << gpio;
217 if (cpu_is_omap44xx()) {
218 _gpio_rmw(base, OMAP4_GPIO_LEVELDETECT0, gpio_bit,
219 trigger & IRQ_TYPE_LEVEL_LOW);
220 _gpio_rmw(base, OMAP4_GPIO_LEVELDETECT1, gpio_bit,
221 trigger & IRQ_TYPE_LEVEL_HIGH);
222 _gpio_rmw(base, OMAP4_GPIO_RISINGDETECT, gpio_bit,
223 trigger & IRQ_TYPE_EDGE_RISING);
224 _gpio_rmw(base, OMAP4_GPIO_FALLINGDETECT, gpio_bit,
225 trigger & IRQ_TYPE_EDGE_FALLING);
227 _gpio_rmw(base, OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
228 trigger & IRQ_TYPE_LEVEL_LOW);
229 _gpio_rmw(base, OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
230 trigger & IRQ_TYPE_LEVEL_HIGH);
231 _gpio_rmw(base, OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
232 trigger & IRQ_TYPE_EDGE_RISING);
233 _gpio_rmw(base, OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
234 trigger & IRQ_TYPE_EDGE_FALLING);
236 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
237 if (cpu_is_omap44xx()) {
238 _gpio_rmw(base, OMAP4_GPIO_IRQWAKEN0, gpio_bit,
242 * GPIO wakeup request can only be generated on edge
245 if (trigger & IRQ_TYPE_EDGE_BOTH)
246 __raw_writel(1 << gpio, bank->base
247 + OMAP24XX_GPIO_SETWKUENA);
249 __raw_writel(1 << gpio, bank->base
250 + OMAP24XX_GPIO_CLEARWKUENA);
253 /* This part needs to be executed always for OMAP{34xx, 44xx} */
254 if (cpu_is_omap34xx() || cpu_is_omap44xx() ||
255 (bank->non_wakeup_gpios & gpio_bit)) {
257 * Log the edge gpio and manually trigger the IRQ
258 * after resume if the input level changes
259 * to avoid irq lost during PER RET/OFF mode
260 * Applies for omap2 non-wakeup gpio and all omap3 gpios
262 if (trigger & IRQ_TYPE_EDGE_BOTH)
263 bank->enabled_non_wakeup_gpios |= gpio_bit;
265 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
268 if (cpu_is_omap44xx()) {
270 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
271 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
274 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
275 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
280 #ifdef CONFIG_ARCH_OMAP1
282 * This only applies to chips that can't do both rising and falling edge
283 * detection at once. For all other chips, this function is a noop.
285 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
287 void __iomem *reg = bank->base;
290 switch (bank->method) {
292 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
294 #ifdef CONFIG_ARCH_OMAP15XX
295 case METHOD_GPIO_1510:
296 reg += OMAP1510_GPIO_INT_CONTROL;
299 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
300 case METHOD_GPIO_7XX:
301 reg += OMAP7XX_GPIO_INT_CONTROL;
308 l = __raw_readl(reg);
314 __raw_writel(l, reg);
318 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
320 void __iomem *reg = bank->base;
323 switch (bank->method) {
324 #ifdef CONFIG_ARCH_OMAP1
326 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
327 l = __raw_readl(reg);
328 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
329 bank->toggle_mask |= 1 << gpio;
330 if (trigger & IRQ_TYPE_EDGE_RISING)
332 else if (trigger & IRQ_TYPE_EDGE_FALLING)
338 #ifdef CONFIG_ARCH_OMAP15XX
339 case METHOD_GPIO_1510:
340 reg += OMAP1510_GPIO_INT_CONTROL;
341 l = __raw_readl(reg);
342 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
343 bank->toggle_mask |= 1 << gpio;
344 if (trigger & IRQ_TYPE_EDGE_RISING)
346 else if (trigger & IRQ_TYPE_EDGE_FALLING)
352 #ifdef CONFIG_ARCH_OMAP16XX
353 case METHOD_GPIO_1610:
355 reg += OMAP1610_GPIO_EDGE_CTRL2;
357 reg += OMAP1610_GPIO_EDGE_CTRL1;
359 l = __raw_readl(reg);
360 l &= ~(3 << (gpio << 1));
361 if (trigger & IRQ_TYPE_EDGE_RISING)
362 l |= 2 << (gpio << 1);
363 if (trigger & IRQ_TYPE_EDGE_FALLING)
364 l |= 1 << (gpio << 1);
366 /* Enable wake-up during idle for dynamic tick */
367 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
369 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
372 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
373 case METHOD_GPIO_7XX:
374 reg += OMAP7XX_GPIO_INT_CONTROL;
375 l = __raw_readl(reg);
376 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
377 bank->toggle_mask |= 1 << gpio;
378 if (trigger & IRQ_TYPE_EDGE_RISING)
380 else if (trigger & IRQ_TYPE_EDGE_FALLING)
386 #ifdef CONFIG_ARCH_OMAP2PLUS
387 case METHOD_GPIO_24XX:
388 case METHOD_GPIO_44XX:
389 set_24xx_gpio_triggering(bank, gpio, trigger);
395 __raw_writel(l, reg);
401 static int gpio_irq_type(struct irq_data *d, unsigned type)
403 struct gpio_bank *bank;
408 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
409 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
411 gpio = d->irq - IH_GPIO_BASE;
413 if (type & ~IRQ_TYPE_SENSE_MASK)
416 /* OMAP1 allows only only edge triggering */
417 if (!cpu_class_is_omap2()
418 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
421 bank = irq_data_get_irq_chip_data(d);
422 spin_lock_irqsave(&bank->lock, flags);
423 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
424 spin_unlock_irqrestore(&bank->lock, flags);
426 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
427 __irq_set_handler_locked(d->irq, handle_level_irq);
428 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
429 __irq_set_handler_locked(d->irq, handle_edge_irq);
434 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
436 void __iomem *reg = bank->base;
438 reg += bank->regs->irqstatus;
439 __raw_writel(gpio_mask, reg);
441 /* Workaround for clearing DSP GPIO interrupts to allow retention */
442 if (bank->regs->irqstatus2) {
443 reg = bank->base + bank->regs->irqstatus2;
444 __raw_writel(gpio_mask, reg);
447 /* Flush posted write for the irq status to avoid spurious interrupts */
451 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
453 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
456 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
458 void __iomem *reg = bank->base;
460 u32 mask = (1 << bank->width) - 1;
462 reg += bank->regs->irqenable;
463 l = __raw_readl(reg);
464 if (bank->regs->irqenable_inv)
470 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
472 void __iomem *reg = bank->base;
475 if (bank->regs->set_irqenable) {
476 reg += bank->regs->set_irqenable;
479 reg += bank->regs->irqenable;
480 l = __raw_readl(reg);
481 if (bank->regs->irqenable_inv)
487 __raw_writel(l, reg);
490 static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
492 void __iomem *reg = bank->base;
495 if (bank->regs->clr_irqenable) {
496 reg += bank->regs->clr_irqenable;
499 reg += bank->regs->irqenable;
500 l = __raw_readl(reg);
501 if (bank->regs->irqenable_inv)
507 __raw_writel(l, reg);
510 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
513 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
515 _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
519 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
520 * 1510 does not seem to have a wake-up register. If JTAG is connected
521 * to the target, system will wake up always on GPIO events. While
522 * system is running all registered GPIO interrupts need to have wake-up
523 * enabled. When system is suspended, only selected GPIO interrupts need
524 * to have wake-up enabled.
526 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
528 u32 gpio_bit = GPIO_BIT(bank, gpio);
531 if (bank->non_wakeup_gpios & gpio_bit) {
533 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
537 spin_lock_irqsave(&bank->lock, flags);
539 bank->suspend_wakeup |= gpio_bit;
541 bank->suspend_wakeup &= ~gpio_bit;
543 spin_unlock_irqrestore(&bank->lock, flags);
548 static void _reset_gpio(struct gpio_bank *bank, int gpio)
550 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
551 _set_gpio_irqenable(bank, gpio, 0);
552 _clear_gpio_irqstatus(bank, gpio);
553 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
556 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
557 static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
559 unsigned int gpio = d->irq - IH_GPIO_BASE;
560 struct gpio_bank *bank;
563 bank = irq_data_get_irq_chip_data(d);
564 retval = _set_gpio_wakeup(bank, gpio, enable);
569 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
571 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
574 spin_lock_irqsave(&bank->lock, flags);
576 /* Set trigger to none. You need to enable the desired trigger with
577 * request_irq() or set_irq_type().
579 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
581 #ifdef CONFIG_ARCH_OMAP15XX
582 if (bank->method == METHOD_GPIO_1510) {
585 /* Claim the pin for MPU */
586 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
587 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
590 if (!cpu_class_is_omap1()) {
591 if (!bank->mod_usage) {
592 void __iomem *reg = bank->base;
595 if (cpu_is_omap24xx() || cpu_is_omap34xx())
596 reg += OMAP24XX_GPIO_CTRL;
597 else if (cpu_is_omap44xx())
598 reg += OMAP4_GPIO_CTRL;
599 ctrl = __raw_readl(reg);
600 /* Module is enabled, clocks are not gated */
602 __raw_writel(ctrl, reg);
604 bank->mod_usage |= 1 << offset;
606 spin_unlock_irqrestore(&bank->lock, flags);
611 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
613 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
616 spin_lock_irqsave(&bank->lock, flags);
617 #ifdef CONFIG_ARCH_OMAP16XX
618 if (bank->method == METHOD_GPIO_1610) {
619 /* Disable wake-up during idle for dynamic tick */
620 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
621 __raw_writel(1 << offset, reg);
624 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
625 if (bank->method == METHOD_GPIO_24XX) {
626 /* Disable wake-up during idle for dynamic tick */
627 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
628 __raw_writel(1 << offset, reg);
631 #ifdef CONFIG_ARCH_OMAP4
632 if (bank->method == METHOD_GPIO_44XX) {
633 /* Disable wake-up during idle for dynamic tick */
634 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
635 __raw_writel(1 << offset, reg);
638 if (!cpu_class_is_omap1()) {
639 bank->mod_usage &= ~(1 << offset);
640 if (!bank->mod_usage) {
641 void __iomem *reg = bank->base;
644 if (cpu_is_omap24xx() || cpu_is_omap34xx())
645 reg += OMAP24XX_GPIO_CTRL;
646 else if (cpu_is_omap44xx())
647 reg += OMAP4_GPIO_CTRL;
648 ctrl = __raw_readl(reg);
649 /* Module is disabled, clocks are gated */
651 __raw_writel(ctrl, reg);
654 _reset_gpio(bank, bank->chip.base + offset);
655 spin_unlock_irqrestore(&bank->lock, flags);
659 * We need to unmask the GPIO bank interrupt as soon as possible to
660 * avoid missing GPIO interrupts for other lines in the bank.
661 * Then we need to mask-read-clear-unmask the triggered GPIO lines
662 * in the bank to avoid missing nested interrupts for a GPIO line.
663 * If we wait to unmask individual GPIO lines in the bank after the
664 * line's interrupt handler has been run, we may miss some nested
667 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
669 void __iomem *isr_reg = NULL;
671 unsigned int gpio_irq, gpio_index;
672 struct gpio_bank *bank;
675 struct irq_chip *chip = irq_desc_get_chip(desc);
677 chained_irq_enter(chip, desc);
679 bank = irq_get_handler_data(irq);
680 isr_reg = bank->base + bank->regs->irqstatus;
682 if (WARN_ON(!isr_reg))
686 u32 isr_saved, level_mask = 0;
689 enabled = _get_gpio_irqbank_mask(bank);
690 isr_saved = isr = __raw_readl(isr_reg) & enabled;
692 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
695 if (cpu_class_is_omap2()) {
696 level_mask = bank->level_mask & enabled;
699 /* clear edge sensitive interrupts before handler(s) are
700 called so that we don't miss any interrupt occurred while
702 _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
703 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
704 _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
706 /* if there is only edge sensitive GPIO pin interrupts
707 configured, we could unmask GPIO bank interrupt immediately */
708 if (!level_mask && !unmasked) {
710 chained_irq_exit(chip, desc);
718 gpio_irq = bank->virtual_irq_start;
719 for (; isr != 0; isr >>= 1, gpio_irq++) {
720 gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq));
725 #ifdef CONFIG_ARCH_OMAP1
727 * Some chips can't respond to both rising and falling
728 * at the same time. If this irq was requested with
729 * both flags, we need to flip the ICR data for the IRQ
730 * to respond to the IRQ for the opposite direction.
731 * This will be indicated in the bank toggle_mask.
733 if (bank->toggle_mask & (1 << gpio_index))
734 _toggle_gpio_edge_triggering(bank, gpio_index);
737 generic_handle_irq(gpio_irq);
740 /* if bank has any level sensitive GPIO pin interrupt
741 configured, we must unmask the bank interrupt only after
742 handler(s) are executed in order to avoid spurious bank
746 chained_irq_exit(chip, desc);
749 static void gpio_irq_shutdown(struct irq_data *d)
751 unsigned int gpio = d->irq - IH_GPIO_BASE;
752 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
755 spin_lock_irqsave(&bank->lock, flags);
756 _reset_gpio(bank, gpio);
757 spin_unlock_irqrestore(&bank->lock, flags);
760 static void gpio_ack_irq(struct irq_data *d)
762 unsigned int gpio = d->irq - IH_GPIO_BASE;
763 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
765 _clear_gpio_irqstatus(bank, gpio);
768 static void gpio_mask_irq(struct irq_data *d)
770 unsigned int gpio = d->irq - IH_GPIO_BASE;
771 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
774 spin_lock_irqsave(&bank->lock, flags);
775 _set_gpio_irqenable(bank, gpio, 0);
776 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
777 spin_unlock_irqrestore(&bank->lock, flags);
780 static void gpio_unmask_irq(struct irq_data *d)
782 unsigned int gpio = d->irq - IH_GPIO_BASE;
783 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
784 unsigned int irq_mask = GPIO_BIT(bank, gpio);
785 u32 trigger = irqd_get_trigger_type(d);
788 spin_lock_irqsave(&bank->lock, flags);
790 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
792 /* For level-triggered GPIOs, the clearing must be done after
793 * the HW source is cleared, thus after the handler has run */
794 if (bank->level_mask & irq_mask) {
795 _set_gpio_irqenable(bank, gpio, 0);
796 _clear_gpio_irqstatus(bank, gpio);
799 _set_gpio_irqenable(bank, gpio, 1);
800 spin_unlock_irqrestore(&bank->lock, flags);
803 static struct irq_chip gpio_irq_chip = {
805 .irq_shutdown = gpio_irq_shutdown,
806 .irq_ack = gpio_ack_irq,
807 .irq_mask = gpio_mask_irq,
808 .irq_unmask = gpio_unmask_irq,
809 .irq_set_type = gpio_irq_type,
810 .irq_set_wake = gpio_wake_enable,
813 /*---------------------------------------------------------------------*/
815 #ifdef CONFIG_ARCH_OMAP1
817 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
819 #ifdef CONFIG_ARCH_OMAP16XX
821 #include <linux/platform_device.h>
823 static int omap_mpuio_suspend_noirq(struct device *dev)
825 struct platform_device *pdev = to_platform_device(dev);
826 struct gpio_bank *bank = platform_get_drvdata(pdev);
827 void __iomem *mask_reg = bank->base +
828 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
831 spin_lock_irqsave(&bank->lock, flags);
832 bank->saved_wakeup = __raw_readl(mask_reg);
833 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
834 spin_unlock_irqrestore(&bank->lock, flags);
839 static int omap_mpuio_resume_noirq(struct device *dev)
841 struct platform_device *pdev = to_platform_device(dev);
842 struct gpio_bank *bank = platform_get_drvdata(pdev);
843 void __iomem *mask_reg = bank->base +
844 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
847 spin_lock_irqsave(&bank->lock, flags);
848 __raw_writel(bank->saved_wakeup, mask_reg);
849 spin_unlock_irqrestore(&bank->lock, flags);
854 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
855 .suspend_noirq = omap_mpuio_suspend_noirq,
856 .resume_noirq = omap_mpuio_resume_noirq,
859 /* use platform_driver for this. */
860 static struct platform_driver omap_mpuio_driver = {
863 .pm = &omap_mpuio_dev_pm_ops,
867 static struct platform_device omap_mpuio_device = {
871 .driver = &omap_mpuio_driver.driver,
873 /* could list the /proc/iomem resources */
876 static inline void mpuio_init(void)
878 struct gpio_bank *bank = &gpio_bank[0];
879 platform_set_drvdata(&omap_mpuio_device, bank);
881 if (platform_driver_register(&omap_mpuio_driver) == 0)
882 (void) platform_device_register(&omap_mpuio_device);
886 static inline void mpuio_init(void) {}
891 #define bank_is_mpuio(bank) 0
892 static inline void mpuio_init(void) {}
896 /*---------------------------------------------------------------------*/
898 /* REVISIT these are stupid implementations! replace by ones that
899 * don't switch on METHOD_* and which mostly avoid spinlocks
902 static int gpio_input(struct gpio_chip *chip, unsigned offset)
904 struct gpio_bank *bank;
907 bank = container_of(chip, struct gpio_bank, chip);
908 spin_lock_irqsave(&bank->lock, flags);
909 _set_gpio_direction(bank, offset, 1);
910 spin_unlock_irqrestore(&bank->lock, flags);
914 static int gpio_is_input(struct gpio_bank *bank, int mask)
916 void __iomem *reg = bank->base + bank->regs->direction;
918 return __raw_readl(reg) & mask;
921 static int gpio_get(struct gpio_chip *chip, unsigned offset)
923 struct gpio_bank *bank;
928 gpio = chip->base + offset;
929 bank = container_of(chip, struct gpio_bank, chip);
931 mask = GPIO_BIT(bank, gpio);
933 if (gpio_is_input(bank, mask))
934 return _get_gpio_datain(bank, gpio);
936 return _get_gpio_dataout(bank, gpio);
939 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
941 struct gpio_bank *bank;
944 bank = container_of(chip, struct gpio_bank, chip);
945 spin_lock_irqsave(&bank->lock, flags);
946 bank->set_dataout(bank, offset, value);
947 _set_gpio_direction(bank, offset, 0);
948 spin_unlock_irqrestore(&bank->lock, flags);
952 static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
955 struct gpio_bank *bank;
958 bank = container_of(chip, struct gpio_bank, chip);
961 bank->dbck = clk_get(bank->dev, "dbclk");
962 if (IS_ERR(bank->dbck))
963 dev_err(bank->dev, "Could not get gpio dbck\n");
966 spin_lock_irqsave(&bank->lock, flags);
967 _set_gpio_debounce(bank, offset, debounce);
968 spin_unlock_irqrestore(&bank->lock, flags);
973 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
975 struct gpio_bank *bank;
978 bank = container_of(chip, struct gpio_bank, chip);
979 spin_lock_irqsave(&bank->lock, flags);
980 bank->set_dataout(bank, offset, value);
981 spin_unlock_irqrestore(&bank->lock, flags);
984 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
986 struct gpio_bank *bank;
988 bank = container_of(chip, struct gpio_bank, chip);
989 return bank->virtual_irq_start + offset;
992 /*---------------------------------------------------------------------*/
994 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
999 if (called || bank->regs->revision == USHRT_MAX)
1002 rev = __raw_readw(bank->base + bank->regs->revision);
1003 pr_info("OMAP GPIO hardware version %d.%d\n",
1004 (rev >> 4) & 0x0f, rev & 0x0f);
1009 /* This lock class tells lockdep that GPIO irqs are in a different
1010 * category than their parents, so it won't report false recursion.
1012 static struct lock_class_key gpio_lock_class;
1014 static inline int init_gpio_info(struct platform_device *pdev)
1016 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1017 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1020 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1026 /* TODO: Cleanup cpu_is_* checks */
1027 static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1029 if (cpu_class_is_omap2()) {
1030 if (cpu_is_omap44xx()) {
1031 __raw_writel(0xffffffff, bank->base +
1032 OMAP4_GPIO_IRQSTATUSCLR0);
1033 __raw_writel(0x00000000, bank->base +
1034 OMAP4_GPIO_DEBOUNCENABLE);
1035 /* Initialize interface clk ungated, module enabled */
1036 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1037 } else if (cpu_is_omap34xx()) {
1038 __raw_writel(0x00000000, bank->base +
1039 OMAP24XX_GPIO_IRQENABLE1);
1040 __raw_writel(0xffffffff, bank->base +
1041 OMAP24XX_GPIO_IRQSTATUS1);
1042 __raw_writel(0x00000000, bank->base +
1043 OMAP24XX_GPIO_DEBOUNCE_EN);
1045 /* Initialize interface clk ungated, module enabled */
1046 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1047 } else if (cpu_is_omap24xx()) {
1048 static const u32 non_wakeup_gpios[] = {
1049 0xe203ffc0, 0x08700040
1051 if (id < ARRAY_SIZE(non_wakeup_gpios))
1052 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1054 } else if (cpu_class_is_omap1()) {
1055 if (bank_is_mpuio(bank))
1056 __raw_writew(0xffff, bank->base +
1057 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
1058 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1059 __raw_writew(0xffff, bank->base
1060 + OMAP1510_GPIO_INT_MASK);
1061 __raw_writew(0x0000, bank->base
1062 + OMAP1510_GPIO_INT_STATUS);
1064 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1065 __raw_writew(0x0000, bank->base
1066 + OMAP1610_GPIO_IRQENABLE1);
1067 __raw_writew(0xffff, bank->base
1068 + OMAP1610_GPIO_IRQSTATUS1);
1069 __raw_writew(0x0014, bank->base
1070 + OMAP1610_GPIO_SYSCONFIG);
1073 * Enable system clock for GPIO module.
1074 * The CAM_CLK_CTRL *is* really the right place.
1076 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1079 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1080 __raw_writel(0xffffffff, bank->base
1081 + OMAP7XX_GPIO_INT_MASK);
1082 __raw_writel(0x00000000, bank->base
1083 + OMAP7XX_GPIO_INT_STATUS);
1089 omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
1092 struct irq_chip_generic *gc;
1093 struct irq_chip_type *ct;
1095 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
1098 dev_err(bank->dev, "Memory alloc failed for gc\n");
1102 ct = gc->chip_types;
1104 /* NOTE: No ack required, reading IRQ status clears it. */
1105 ct->chip.irq_mask = irq_gc_mask_set_bit;
1106 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
1107 ct->chip.irq_set_type = gpio_irq_type;
1108 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1109 if (cpu_is_omap16xx())
1110 ct->chip.irq_set_wake = gpio_wake_enable,
1112 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1113 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1114 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1117 static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1122 bank->mod_usage = 0;
1124 * REVISIT eventually switch from OMAP-specific gpio structs
1125 * over to the generic ones
1127 bank->chip.request = omap_gpio_request;
1128 bank->chip.free = omap_gpio_free;
1129 bank->chip.direction_input = gpio_input;
1130 bank->chip.get = gpio_get;
1131 bank->chip.direction_output = gpio_output;
1132 bank->chip.set_debounce = gpio_debounce;
1133 bank->chip.set = gpio_set;
1134 bank->chip.to_irq = gpio_2irq;
1135 if (bank_is_mpuio(bank)) {
1136 bank->chip.label = "mpuio";
1137 #ifdef CONFIG_ARCH_OMAP16XX
1138 bank->chip.dev = &omap_mpuio_device.dev;
1140 bank->chip.base = OMAP_MPUIO(0);
1142 bank->chip.label = "gpio";
1143 bank->chip.base = gpio;
1144 gpio += bank->width;
1146 bank->chip.ngpio = bank->width;
1148 gpiochip_add(&bank->chip);
1150 for (j = bank->virtual_irq_start;
1151 j < bank->virtual_irq_start + bank->width; j++) {
1152 irq_set_lockdep_class(j, &gpio_lock_class);
1153 irq_set_chip_data(j, bank);
1154 if (bank_is_mpuio(bank)) {
1155 omap_mpuio_alloc_gc(bank, j, bank->width);
1157 irq_set_chip(j, &gpio_irq_chip);
1158 irq_set_handler(j, handle_simple_irq);
1159 set_irq_flags(j, IRQF_VALID);
1162 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1163 irq_set_handler_data(bank->irq, bank);
1166 static int __devinit omap_gpio_probe(struct platform_device *pdev)
1168 static int gpio_init_done;
1169 struct omap_gpio_platform_data *pdata;
1170 struct resource *res;
1172 struct gpio_bank *bank;
1174 if (!pdev->dev.platform_data)
1177 pdata = pdev->dev.platform_data;
1179 if (!gpio_init_done) {
1182 ret = init_gpio_info(pdev);
1188 bank = &gpio_bank[id];
1190 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1191 if (unlikely(!res)) {
1192 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1196 bank->irq = res->start;
1197 bank->virtual_irq_start = pdata->virtual_irq_start;
1198 bank->method = pdata->bank_type;
1199 bank->dev = &pdev->dev;
1200 bank->dbck_flag = pdata->dbck_flag;
1201 bank->stride = pdata->bank_stride;
1202 bank->width = pdata->bank_width;
1204 bank->regs = pdata->regs;
1206 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1207 bank->set_dataout = _set_gpio_dataout_reg;
1209 bank->set_dataout = _set_gpio_dataout_mask;
1211 spin_lock_init(&bank->lock);
1213 /* Static mapping, never released */
1214 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1215 if (unlikely(!res)) {
1216 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1220 bank->base = ioremap(res->start, resource_size(res));
1222 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1226 pm_runtime_enable(bank->dev);
1227 pm_runtime_get_sync(bank->dev);
1229 omap_gpio_mod_init(bank, id);
1230 omap_gpio_chip_init(bank);
1231 omap_gpio_show_rev(bank);
1233 if (!gpio_init_done)
1239 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1240 static int omap_gpio_suspend(void)
1244 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1247 for (i = 0; i < gpio_bank_count; i++) {
1248 struct gpio_bank *bank = &gpio_bank[i];
1249 void __iomem *wake_status;
1250 void __iomem *wake_clear;
1251 void __iomem *wake_set;
1252 unsigned long flags;
1254 switch (bank->method) {
1255 #ifdef CONFIG_ARCH_OMAP16XX
1256 case METHOD_GPIO_1610:
1257 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1258 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1259 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1262 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1263 case METHOD_GPIO_24XX:
1264 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1265 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1266 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1269 #ifdef CONFIG_ARCH_OMAP4
1270 case METHOD_GPIO_44XX:
1271 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1272 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1273 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1280 spin_lock_irqsave(&bank->lock, flags);
1281 bank->saved_wakeup = __raw_readl(wake_status);
1282 __raw_writel(0xffffffff, wake_clear);
1283 __raw_writel(bank->suspend_wakeup, wake_set);
1284 spin_unlock_irqrestore(&bank->lock, flags);
1290 static void omap_gpio_resume(void)
1294 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1297 for (i = 0; i < gpio_bank_count; i++) {
1298 struct gpio_bank *bank = &gpio_bank[i];
1299 void __iomem *wake_clear;
1300 void __iomem *wake_set;
1301 unsigned long flags;
1303 switch (bank->method) {
1304 #ifdef CONFIG_ARCH_OMAP16XX
1305 case METHOD_GPIO_1610:
1306 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1307 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1310 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1311 case METHOD_GPIO_24XX:
1312 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1313 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1316 #ifdef CONFIG_ARCH_OMAP4
1317 case METHOD_GPIO_44XX:
1318 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1319 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1326 spin_lock_irqsave(&bank->lock, flags);
1327 __raw_writel(0xffffffff, wake_clear);
1328 __raw_writel(bank->saved_wakeup, wake_set);
1329 spin_unlock_irqrestore(&bank->lock, flags);
1333 static struct syscore_ops omap_gpio_syscore_ops = {
1334 .suspend = omap_gpio_suspend,
1335 .resume = omap_gpio_resume,
1340 #ifdef CONFIG_ARCH_OMAP2PLUS
1342 static int workaround_enabled;
1344 void omap2_gpio_prepare_for_idle(int off_mode)
1349 if (cpu_is_omap34xx())
1352 for (i = min; i < gpio_bank_count; i++) {
1353 struct gpio_bank *bank = &gpio_bank[i];
1359 * Disable debounce since clock disable below will cause
1360 * problems if GPIO module doesn't go idle for some reason.
1362 if (bank->dbck_enable_mask != 0) {
1363 reg = bank->base + bank->regs->datain;
1364 bank->saved_datain = __raw_readl(reg);
1365 reg = bank->base + bank->regs->irqstatus;
1366 bank->saved_irqstatus = __raw_readl(reg);
1367 reg = bank->base + bank->regs->debounce_en;
1368 __raw_writel(0, reg);
1371 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1372 clk_disable(bank->dbck);
1377 /* If going to OFF, remove triggering for all
1378 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1379 * generated. See OMAP2420 Errata item 1.101. */
1380 if (!(bank->enabled_non_wakeup_gpios))
1383 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1384 bank->saved_datain = __raw_readl(bank->base +
1385 OMAP24XX_GPIO_DATAIN);
1386 l1 = __raw_readl(bank->base +
1387 OMAP24XX_GPIO_FALLINGDETECT);
1388 l2 = __raw_readl(bank->base +
1389 OMAP24XX_GPIO_RISINGDETECT);
1392 if (cpu_is_omap44xx()) {
1393 bank->saved_datain = __raw_readl(bank->base +
1395 l1 = __raw_readl(bank->base +
1396 OMAP4_GPIO_FALLINGDETECT);
1397 l2 = __raw_readl(bank->base +
1398 OMAP4_GPIO_RISINGDETECT);
1401 bank->saved_fallingdetect = l1;
1402 bank->saved_risingdetect = l2;
1403 l1 &= ~bank->enabled_non_wakeup_gpios;
1404 l2 &= ~bank->enabled_non_wakeup_gpios;
1406 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1407 __raw_writel(l1, bank->base +
1408 OMAP24XX_GPIO_FALLINGDETECT);
1409 __raw_writel(l2, bank->base +
1410 OMAP24XX_GPIO_RISINGDETECT);
1413 if (cpu_is_omap44xx()) {
1414 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1415 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1421 workaround_enabled = 0;
1424 workaround_enabled = 1;
1427 void omap2_gpio_resume_after_idle(void)
1432 if (cpu_is_omap34xx())
1434 for (i = min; i < gpio_bank_count; i++) {
1435 struct gpio_bank *bank = &gpio_bank[i];
1437 u32 l = 0, gen, gen0, gen1;
1440 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1441 clk_enable(bank->dbck);
1443 if (bank->dbck_enable_mask != 0) {
1444 reg = bank->base + bank->regs->debounce_en;
1445 __raw_writel(bank->dbck_enable_mask, reg);
1446 /* clear irqs that could come from glitches
1447 * because debounce was disabled */
1448 reg = bank->base + bank->regs->irqstatus;
1449 gen = __raw_readl(reg) & ~bank->saved_irqstatus;
1450 reg = bank->base + bank->regs->datain;
1451 l = __raw_readl(reg) ^ bank->saved_datain;
1453 l = l & bank->dbck_enable_mask & ~bank->level_mask;
1455 _clear_gpio_irqbank(bank, l);
1458 if (!workaround_enabled)
1461 if (!(bank->enabled_non_wakeup_gpios))
1464 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1465 __raw_writel(bank->saved_fallingdetect,
1466 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1467 __raw_writel(bank->saved_risingdetect,
1468 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1469 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1472 if (cpu_is_omap44xx()) {
1473 __raw_writel(bank->saved_fallingdetect,
1474 bank->base + OMAP4_GPIO_FALLINGDETECT);
1475 __raw_writel(bank->saved_risingdetect,
1476 bank->base + OMAP4_GPIO_RISINGDETECT);
1477 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1480 /* Check if any of the non-wakeup interrupt GPIOs have changed
1481 * state. If so, generate an IRQ by software. This is
1482 * horribly racy, but it's the best we can do to work around
1483 * this silicon bug. */
1484 l ^= bank->saved_datain;
1485 l &= bank->enabled_non_wakeup_gpios;
1488 * No need to generate IRQs for the rising edge for gpio IRQs
1489 * configured with falling edge only; and vice versa.
1491 gen0 = l & bank->saved_fallingdetect;
1492 gen0 &= bank->saved_datain;
1494 gen1 = l & bank->saved_risingdetect;
1495 gen1 &= ~(bank->saved_datain);
1497 /* FIXME: Consider GPIO IRQs with level detections properly! */
1498 gen = l & (~(bank->saved_fallingdetect) &
1499 ~(bank->saved_risingdetect));
1500 /* Consider all GPIO IRQs needed to be updated */
1506 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1507 old0 = __raw_readl(bank->base +
1508 OMAP24XX_GPIO_LEVELDETECT0);
1509 old1 = __raw_readl(bank->base +
1510 OMAP24XX_GPIO_LEVELDETECT1);
1511 __raw_writel(old0 | gen, bank->base +
1512 OMAP24XX_GPIO_LEVELDETECT0);
1513 __raw_writel(old1 | gen, bank->base +
1514 OMAP24XX_GPIO_LEVELDETECT1);
1515 __raw_writel(old0, bank->base +
1516 OMAP24XX_GPIO_LEVELDETECT0);
1517 __raw_writel(old1, bank->base +
1518 OMAP24XX_GPIO_LEVELDETECT1);
1521 if (cpu_is_omap44xx()) {
1522 old0 = __raw_readl(bank->base +
1523 OMAP4_GPIO_LEVELDETECT0);
1524 old1 = __raw_readl(bank->base +
1525 OMAP4_GPIO_LEVELDETECT1);
1526 __raw_writel(old0 | l, bank->base +
1527 OMAP4_GPIO_LEVELDETECT0);
1528 __raw_writel(old1 | l, bank->base +
1529 OMAP4_GPIO_LEVELDETECT1);
1530 __raw_writel(old0, bank->base +
1531 OMAP4_GPIO_LEVELDETECT0);
1532 __raw_writel(old1, bank->base +
1533 OMAP4_GPIO_LEVELDETECT1);
1542 #ifdef CONFIG_ARCH_OMAP3
1543 /* save the registers of bank 2-6 */
1544 void omap_gpio_save_context(void)
1548 /* saving banks from 2-6 only since GPIO1 is in WKUP */
1549 for (i = 1; i < gpio_bank_count; i++) {
1550 struct gpio_bank *bank = &gpio_bank[i];
1551 gpio_context[i].irqenable1 =
1552 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
1553 gpio_context[i].irqenable2 =
1554 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
1555 gpio_context[i].wake_en =
1556 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
1557 gpio_context[i].ctrl =
1558 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1559 gpio_context[i].oe =
1560 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
1561 gpio_context[i].leveldetect0 =
1562 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1563 gpio_context[i].leveldetect1 =
1564 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1565 gpio_context[i].risingdetect =
1566 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1567 gpio_context[i].fallingdetect =
1568 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1569 gpio_context[i].dataout =
1570 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
1574 /* restore the required registers of bank 2-6 */
1575 void omap_gpio_restore_context(void)
1579 for (i = 1; i < gpio_bank_count; i++) {
1580 struct gpio_bank *bank = &gpio_bank[i];
1581 __raw_writel(gpio_context[i].irqenable1,
1582 bank->base + OMAP24XX_GPIO_IRQENABLE1);
1583 __raw_writel(gpio_context[i].irqenable2,
1584 bank->base + OMAP24XX_GPIO_IRQENABLE2);
1585 __raw_writel(gpio_context[i].wake_en,
1586 bank->base + OMAP24XX_GPIO_WAKE_EN);
1587 __raw_writel(gpio_context[i].ctrl,
1588 bank->base + OMAP24XX_GPIO_CTRL);
1589 __raw_writel(gpio_context[i].oe,
1590 bank->base + OMAP24XX_GPIO_OE);
1591 __raw_writel(gpio_context[i].leveldetect0,
1592 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1593 __raw_writel(gpio_context[i].leveldetect1,
1594 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1595 __raw_writel(gpio_context[i].risingdetect,
1596 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1597 __raw_writel(gpio_context[i].fallingdetect,
1598 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1599 __raw_writel(gpio_context[i].dataout,
1600 bank->base + OMAP24XX_GPIO_DATAOUT);
1605 static struct platform_driver omap_gpio_driver = {
1606 .probe = omap_gpio_probe,
1608 .name = "omap_gpio",
1613 * gpio driver register needs to be done before
1614 * machine_init functions access gpio APIs.
1615 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1617 static int __init omap_gpio_drv_reg(void)
1619 return platform_driver_register(&omap_gpio_driver);
1621 postcore_initcall(omap_gpio_drv_reg);
1623 static int __init omap_gpio_sysinit(void)
1627 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1628 if (cpu_is_omap16xx() || cpu_class_is_omap2())
1629 register_syscore_ops(&omap_gpio_syscore_ops);
1635 arch_initcall(omap_gpio_sysinit);