2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
5 * Based on code from Freescale,
6 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/gpio.h>
27 #include <linux/platform_device.h>
28 #include <linux/slab.h>
29 #include <linux/basic_mmio_gpio.h>
31 #include <linux/of_device.h>
32 #include <asm-generic/bug.h>
34 #define irq_to_gpio(irq) ((irq) - MXC_GPIO_IRQ_START)
36 enum mxc_gpio_hwtype {
37 IMX1_GPIO, /* runs on i.mx1 */
38 IMX21_GPIO, /* runs on i.mx21 and i.mx27 */
39 IMX31_GPIO, /* runs on all other i.mx */
42 /* device type dependent stuff */
43 struct mxc_gpio_hwdata {
57 struct mxc_gpio_port {
58 struct list_head node;
62 int virtual_irq_start;
63 struct bgpio_chip bgc;
67 static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
81 static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
95 static enum mxc_gpio_hwtype mxc_gpio_hwtype;
96 static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
98 #define GPIO_DR (mxc_gpio_hwdata->dr_reg)
99 #define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg)
100 #define GPIO_PSR (mxc_gpio_hwdata->psr_reg)
101 #define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg)
102 #define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg)
103 #define GPIO_IMR (mxc_gpio_hwdata->imr_reg)
104 #define GPIO_ISR (mxc_gpio_hwdata->isr_reg)
106 #define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level)
107 #define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level)
108 #define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge)
109 #define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge)
110 #define GPIO_INT_NONE 0x4
112 static struct platform_device_id mxc_gpio_devtype[] = {
115 .driver_data = IMX1_GPIO,
117 .name = "imx21-gpio",
118 .driver_data = IMX21_GPIO,
120 .name = "imx31-gpio",
121 .driver_data = IMX31_GPIO,
127 static const struct of_device_id mxc_gpio_dt_ids[] = {
128 { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
129 { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
130 { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
135 * MX2 has one interrupt *for all* gpio ports. The list is used
136 * to save the references to all ports, so that mx2_gpio_irq_handler
137 * can walk through all interrupt status registers.
139 static LIST_HEAD(mxc_gpio_ports);
141 /* Note: This driver assumes 32 GPIOs are handled in one register */
143 static int gpio_set_irq_type(struct irq_data *d, u32 type)
145 u32 gpio = irq_to_gpio(d->irq);
146 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
147 struct mxc_gpio_port *port = gc->private;
150 void __iomem *reg = port->base;
152 port->both_edges &= ~(1 << (gpio & 31));
154 case IRQ_TYPE_EDGE_RISING:
155 edge = GPIO_INT_RISE_EDGE;
157 case IRQ_TYPE_EDGE_FALLING:
158 edge = GPIO_INT_FALL_EDGE;
160 case IRQ_TYPE_EDGE_BOTH:
161 val = gpio_get_value(gpio);
163 edge = GPIO_INT_LOW_LEV;
164 pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
166 edge = GPIO_INT_HIGH_LEV;
167 pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
169 port->both_edges |= 1 << (gpio & 31);
171 case IRQ_TYPE_LEVEL_LOW:
172 edge = GPIO_INT_LOW_LEV;
174 case IRQ_TYPE_LEVEL_HIGH:
175 edge = GPIO_INT_HIGH_LEV;
181 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
183 val = readl(reg) & ~(0x3 << (bit << 1));
184 writel(val | (edge << (bit << 1)), reg);
185 writel(1 << (gpio & 0x1f), port->base + GPIO_ISR);
190 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
192 void __iomem *reg = port->base;
196 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
199 edge = (val >> (bit << 1)) & 3;
200 val &= ~(0x3 << (bit << 1));
201 if (edge == GPIO_INT_HIGH_LEV) {
202 edge = GPIO_INT_LOW_LEV;
203 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
204 } else if (edge == GPIO_INT_LOW_LEV) {
205 edge = GPIO_INT_HIGH_LEV;
206 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
208 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
212 writel(val | (edge << (bit << 1)), reg);
215 /* handle 32 interrupts in one status register */
216 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
218 u32 gpio_irq_no_base = port->virtual_irq_start;
220 while (irq_stat != 0) {
221 int irqoffset = fls(irq_stat) - 1;
223 if (port->both_edges & (1 << irqoffset))
224 mxc_flip_edge(port, irqoffset);
226 generic_handle_irq(gpio_irq_no_base + irqoffset);
228 irq_stat &= ~(1 << irqoffset);
232 /* MX1 and MX3 has one interrupt *per* gpio port */
233 static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
236 struct mxc_gpio_port *port = irq_get_handler_data(irq);
238 irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
240 mxc_gpio_irq_handler(port, irq_stat);
243 /* MX2 has one interrupt *for all* gpio ports */
244 static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
246 u32 irq_msk, irq_stat;
247 struct mxc_gpio_port *port;
249 /* walk through all interrupt status registers */
250 list_for_each_entry(port, &mxc_gpio_ports, node) {
251 irq_msk = readl(port->base + GPIO_IMR);
255 irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
257 mxc_gpio_irq_handler(port, irq_stat);
262 * Set interrupt number "irq" in the GPIO as a wake-up source.
263 * While system is running, all registered GPIO interrupts need to have
264 * wake-up enabled. When system is suspended, only selected GPIO interrupts
265 * need to have wake-up enabled.
266 * @param irq interrupt source number
267 * @param enable enable as wake-up if equal to non-zero
268 * @return This function returns 0 on success.
270 static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
272 u32 gpio = irq_to_gpio(d->irq);
273 u32 gpio_idx = gpio & 0x1F;
274 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
275 struct mxc_gpio_port *port = gc->private;
278 if (port->irq_high && (gpio_idx >= 16))
279 enable_irq_wake(port->irq_high);
281 enable_irq_wake(port->irq);
283 if (port->irq_high && (gpio_idx >= 16))
284 disable_irq_wake(port->irq_high);
286 disable_irq_wake(port->irq);
292 static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port)
294 struct irq_chip_generic *gc;
295 struct irq_chip_type *ct;
297 gc = irq_alloc_generic_chip("gpio-mxc", 1, port->virtual_irq_start,
298 port->base, handle_level_irq);
302 ct->chip.irq_ack = irq_gc_ack_set_bit;
303 ct->chip.irq_mask = irq_gc_mask_clr_bit;
304 ct->chip.irq_unmask = irq_gc_mask_set_bit;
305 ct->chip.irq_set_type = gpio_set_irq_type;
306 ct->chip.irq_set_wake = gpio_set_wake_irq;
307 ct->regs.ack = GPIO_ISR;
308 ct->regs.mask = GPIO_IMR;
310 irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
314 static void __devinit mxc_gpio_get_hw(struct platform_device *pdev)
316 const struct of_device_id *of_id =
317 of_match_device(mxc_gpio_dt_ids, &pdev->dev);
318 enum mxc_gpio_hwtype hwtype;
321 pdev->id_entry = of_id->data;
322 hwtype = pdev->id_entry->driver_data;
324 if (mxc_gpio_hwtype) {
326 * The driver works with a reasonable presupposition,
327 * that is all gpio ports must be the same type when
328 * running on one soc.
330 BUG_ON(mxc_gpio_hwtype != hwtype);
334 if (hwtype == IMX31_GPIO)
335 mxc_gpio_hwdata = &imx31_gpio_hwdata;
337 mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
339 mxc_gpio_hwtype = hwtype;
342 static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
344 struct bgpio_chip *bgc = to_bgpio_chip(gc);
345 struct mxc_gpio_port *port =
346 container_of(bgc, struct mxc_gpio_port, bgc);
348 return port->virtual_irq_start + offset;
351 static int __devinit mxc_gpio_probe(struct platform_device *pdev)
353 struct device_node *np = pdev->dev.of_node;
354 struct mxc_gpio_port *port;
355 struct resource *iores;
358 mxc_gpio_get_hw(pdev);
360 port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL);
364 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
370 if (!request_mem_region(iores->start, resource_size(iores),
376 port->base = ioremap(iores->start, resource_size(iores));
379 goto out_release_mem;
382 port->irq_high = platform_get_irq(pdev, 1);
383 port->irq = platform_get_irq(pdev, 0);
389 /* disable the interrupt and clear the status */
390 writel(0, port->base + GPIO_IMR);
391 writel(~0, port->base + GPIO_ISR);
393 if (mxc_gpio_hwtype == IMX21_GPIO) {
394 /* setup one handler for all GPIO interrupts */
396 irq_set_chained_handler(port->irq,
397 mx2_gpio_irq_handler);
399 /* setup one handler for each entry */
400 irq_set_chained_handler(port->irq, mx3_gpio_irq_handler);
401 irq_set_handler_data(port->irq, port);
402 if (port->irq_high > 0) {
403 /* setup handler for GPIO 16 to 31 */
404 irq_set_chained_handler(port->irq_high,
405 mx3_gpio_irq_handler);
406 irq_set_handler_data(port->irq_high, port);
410 err = bgpio_init(&port->bgc, &pdev->dev, 4,
411 port->base + GPIO_PSR,
412 port->base + GPIO_DR, NULL,
413 port->base + GPIO_GDIR, NULL, false);
417 port->bgc.gc.to_irq = mxc_gpio_to_irq;
418 port->bgc.gc.base = pdev->id * 32;
419 port->bgc.dir = port->bgc.read_reg(port->bgc.reg_dir);
420 port->bgc.data = port->bgc.read_reg(port->bgc.reg_set);
422 err = gpiochip_add(&port->bgc.gc);
424 goto out_bgpio_remove;
427 * In dt case, we use gpio number range dynamically
428 * allocated by gpio core.
430 port->virtual_irq_start = MXC_GPIO_IRQ_START + (np ? port->bgc.gc.base :
433 /* gpio-mxc can be a generic irq chip */
434 mxc_gpio_init_gc(port);
436 list_add_tail(&port->node, &mxc_gpio_ports);
441 bgpio_remove(&port->bgc);
445 release_mem_region(iores->start, resource_size(iores));
448 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
452 static struct platform_driver mxc_gpio_driver = {
455 .owner = THIS_MODULE,
456 .of_match_table = mxc_gpio_dt_ids,
458 .probe = mxc_gpio_probe,
459 .id_table = mxc_gpio_devtype,
462 static int __init gpio_mxc_init(void)
464 return platform_driver_register(&mxc_gpio_driver);
466 postcore_initcall(gpio_mxc_init);
468 MODULE_AUTHOR("Freescale Semiconductor, "
469 "Daniel Mack <danielncaiaq.de>, "
470 "Juergen Beisert <kernel@pengutronix.de>");
471 MODULE_DESCRIPTION("Freescale MXC GPIO");
472 MODULE_LICENSE("GPL");