2 * Generic EP93xx GPIO handling
4 * Copyright (c) 2008 Ryan Mallon <ryan@bluewatersys.com>
6 * Based on code originally from:
7 * linux/arch/arm/mach-ep93xx/core.c
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/seq_file.h>
20 #include <linux/gpio.h>
21 #include <linux/irq.h>
23 #include <mach/hardware.h>
25 /*************************************************************************
26 * Interrupt handling for EP93xx on-chip GPIOs
27 *************************************************************************/
28 static unsigned char gpio_int_unmasked[3];
29 static unsigned char gpio_int_enabled[3];
30 static unsigned char gpio_int_type1[3];
31 static unsigned char gpio_int_type2[3];
32 static unsigned char gpio_int_debounce[3];
34 /* Port ordering is: A B F */
35 static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
36 static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
37 static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
38 static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
39 static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
41 static void ep93xx_gpio_update_int_params(unsigned port)
45 __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
47 __raw_writeb(gpio_int_type2[port],
48 EP93XX_GPIO_REG(int_type2_register_offset[port]));
50 __raw_writeb(gpio_int_type1[port],
51 EP93XX_GPIO_REG(int_type1_register_offset[port]));
53 __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
54 EP93XX_GPIO_REG(int_en_register_offset[port]));
57 static inline void ep93xx_gpio_int_mask(unsigned line)
59 gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
62 static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable)
64 int line = irq_to_gpio(irq);
66 int port_mask = 1 << (line & 7);
69 gpio_int_debounce[port] |= port_mask;
71 gpio_int_debounce[port] &= ~port_mask;
73 __raw_writeb(gpio_int_debounce[port],
74 EP93XX_GPIO_REG(int_debounce_register_offset[port]));
77 static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
82 status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
83 for (i = 0; i < 8; i++) {
84 if (status & (1 << i)) {
85 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
86 generic_handle_irq(gpio_irq);
90 status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
91 for (i = 0; i < 8; i++) {
92 if (status & (1 << i)) {
93 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
94 generic_handle_irq(gpio_irq);
99 static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
102 * map discontiguous hw irq range to continuous sw irq range:
104 * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
106 int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
107 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
109 generic_handle_irq(gpio_irq);
112 static void ep93xx_gpio_irq_ack(struct irq_data *d)
114 int line = irq_to_gpio(d->irq);
115 int port = line >> 3;
116 int port_mask = 1 << (line & 7);
118 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
119 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
120 ep93xx_gpio_update_int_params(port);
123 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
126 static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
128 int line = irq_to_gpio(d->irq);
129 int port = line >> 3;
130 int port_mask = 1 << (line & 7);
132 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
133 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
135 gpio_int_unmasked[port] &= ~port_mask;
136 ep93xx_gpio_update_int_params(port);
138 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
141 static void ep93xx_gpio_irq_mask(struct irq_data *d)
143 int line = irq_to_gpio(d->irq);
144 int port = line >> 3;
146 gpio_int_unmasked[port] &= ~(1 << (line & 7));
147 ep93xx_gpio_update_int_params(port);
150 static void ep93xx_gpio_irq_unmask(struct irq_data *d)
152 int line = irq_to_gpio(d->irq);
153 int port = line >> 3;
155 gpio_int_unmasked[port] |= 1 << (line & 7);
156 ep93xx_gpio_update_int_params(port);
160 * gpio_int_type1 controls whether the interrupt is level (0) or
161 * edge (1) triggered, while gpio_int_type2 controls whether it
162 * triggers on low/falling (0) or high/rising (1).
164 static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
166 const int gpio = irq_to_gpio(d->irq);
167 const int port = gpio >> 3;
168 const int port_mask = 1 << (gpio & 7);
169 irq_flow_handler_t handler;
171 gpio_direction_input(gpio);
174 case IRQ_TYPE_EDGE_RISING:
175 gpio_int_type1[port] |= port_mask;
176 gpio_int_type2[port] |= port_mask;
177 handler = handle_edge_irq;
179 case IRQ_TYPE_EDGE_FALLING:
180 gpio_int_type1[port] |= port_mask;
181 gpio_int_type2[port] &= ~port_mask;
182 handler = handle_edge_irq;
184 case IRQ_TYPE_LEVEL_HIGH:
185 gpio_int_type1[port] &= ~port_mask;
186 gpio_int_type2[port] |= port_mask;
187 handler = handle_level_irq;
189 case IRQ_TYPE_LEVEL_LOW:
190 gpio_int_type1[port] &= ~port_mask;
191 gpio_int_type2[port] &= ~port_mask;
192 handler = handle_level_irq;
194 case IRQ_TYPE_EDGE_BOTH:
195 gpio_int_type1[port] |= port_mask;
196 /* set initial polarity based on current input level */
197 if (gpio_get_value(gpio))
198 gpio_int_type2[port] &= ~port_mask; /* falling */
200 gpio_int_type2[port] |= port_mask; /* rising */
201 handler = handle_edge_irq;
204 pr_err("failed to set irq type %d for gpio %d\n", type, gpio);
208 __irq_set_handler_locked(d->irq, handler);
210 gpio_int_enabled[port] |= port_mask;
212 ep93xx_gpio_update_int_params(port);
217 static struct irq_chip ep93xx_gpio_irq_chip = {
219 .irq_ack = ep93xx_gpio_irq_ack,
220 .irq_mask_ack = ep93xx_gpio_irq_mask_ack,
221 .irq_mask = ep93xx_gpio_irq_mask,
222 .irq_unmask = ep93xx_gpio_irq_unmask,
223 .irq_set_type = ep93xx_gpio_irq_type,
226 void __init ep93xx_gpio_init_irq(void)
230 for (gpio_irq = gpio_to_irq(0);
231 gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
232 irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
234 set_irq_flags(gpio_irq, IRQF_VALID);
237 irq_set_chained_handler(IRQ_EP93XX_GPIO_AB,
238 ep93xx_gpio_ab_irq_handler);
239 irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX,
240 ep93xx_gpio_f_irq_handler);
241 irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX,
242 ep93xx_gpio_f_irq_handler);
243 irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX,
244 ep93xx_gpio_f_irq_handler);
245 irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX,
246 ep93xx_gpio_f_irq_handler);
247 irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX,
248 ep93xx_gpio_f_irq_handler);
249 irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX,
250 ep93xx_gpio_f_irq_handler);
251 irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX,
252 ep93xx_gpio_f_irq_handler);
253 irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX,
254 ep93xx_gpio_f_irq_handler);
258 /*************************************************************************
259 * gpiolib interface for EP93xx on-chip GPIOs
260 *************************************************************************/
261 struct ep93xx_gpio_chip {
262 struct gpio_chip chip;
264 void __iomem *data_reg;
265 void __iomem *data_dir_reg;
268 #define to_ep93xx_gpio_chip(c) container_of(c, struct ep93xx_gpio_chip, chip)
270 static int ep93xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
272 struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
276 local_irq_save(flags);
277 v = __raw_readb(ep93xx_chip->data_dir_reg);
279 __raw_writeb(v, ep93xx_chip->data_dir_reg);
280 local_irq_restore(flags);
285 static int ep93xx_gpio_direction_output(struct gpio_chip *chip,
286 unsigned offset, int val)
288 struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
293 local_irq_save(flags);
296 v = __raw_readb(ep93xx_chip->data_reg);
301 __raw_writeb(v, ep93xx_chip->data_reg);
303 /* Drive as an output */
304 line = chip->base + offset;
305 if (line <= EP93XX_GPIO_LINE_MAX_IRQ) {
307 ep93xx_gpio_int_mask(line);
308 ep93xx_gpio_update_int_params(line >> 3);
311 v = __raw_readb(ep93xx_chip->data_dir_reg);
313 __raw_writeb(v, ep93xx_chip->data_dir_reg);
315 local_irq_restore(flags);
320 static int ep93xx_gpio_get(struct gpio_chip *chip, unsigned offset)
322 struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
324 return !!(__raw_readb(ep93xx_chip->data_reg) & (1 << offset));
327 static void ep93xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
329 struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
333 local_irq_save(flags);
334 v = __raw_readb(ep93xx_chip->data_reg);
339 __raw_writeb(v, ep93xx_chip->data_reg);
340 local_irq_restore(flags);
343 static int ep93xx_gpio_set_debounce(struct gpio_chip *chip,
344 unsigned offset, unsigned debounce)
346 int gpio = chip->base + offset;
347 int irq = gpio_to_irq(gpio);
352 ep93xx_gpio_int_debounce(irq, debounce ? true : false);
357 #define EP93XX_GPIO_BANK(name, dr, ddr, base_gpio) \
361 .direction_input = ep93xx_gpio_direction_input, \
362 .direction_output = ep93xx_gpio_direction_output, \
363 .get = ep93xx_gpio_get, \
364 .set = ep93xx_gpio_set, \
368 .data_reg = EP93XX_GPIO_REG(dr), \
369 .data_dir_reg = EP93XX_GPIO_REG(ddr), \
372 static struct ep93xx_gpio_chip ep93xx_gpio_banks[] = {
373 EP93XX_GPIO_BANK("A", 0x00, 0x10, 0),
374 EP93XX_GPIO_BANK("B", 0x04, 0x14, 8),
375 EP93XX_GPIO_BANK("C", 0x08, 0x18, 40),
376 EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24),
377 EP93XX_GPIO_BANK("E", 0x20, 0x24, 32),
378 EP93XX_GPIO_BANK("F", 0x30, 0x34, 16),
379 EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48),
380 EP93XX_GPIO_BANK("H", 0x40, 0x44, 56),
383 void __init ep93xx_gpio_init(void)
387 /* Set Ports C, D, E, G, and H for GPIO use */
388 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
389 EP93XX_SYSCON_DEVCFG_GONK |
390 EP93XX_SYSCON_DEVCFG_EONIDE |
391 EP93XX_SYSCON_DEVCFG_GONIDE |
392 EP93XX_SYSCON_DEVCFG_HONIDE);
394 for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
395 struct gpio_chip *chip = &ep93xx_gpio_banks[i].chip;
398 * Ports A, B, and F support input debouncing when
399 * used as interrupts.
401 if (!strcmp(chip->label, "A") ||
402 !strcmp(chip->label, "B") ||
403 !strcmp(chip->label, "F"))
404 chip->set_debounce = ep93xx_gpio_set_debounce;