2 * Driver for OHCI 1394 controllers
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/firewire.h>
26 #include <linux/firewire-constants.h>
27 #include <linux/gfp.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/pci.h>
37 #include <linux/pci_ids.h>
38 #include <linux/spinlock.h>
39 #include <linux/string.h>
41 #include <asm/byteorder.h>
43 #include <asm/system.h>
45 #ifdef CONFIG_PPC_PMAC
46 #include <asm/pmac_feature.h>
52 #define DESCRIPTOR_OUTPUT_MORE 0
53 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
54 #define DESCRIPTOR_INPUT_MORE (2 << 12)
55 #define DESCRIPTOR_INPUT_LAST (3 << 12)
56 #define DESCRIPTOR_STATUS (1 << 11)
57 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
58 #define DESCRIPTOR_PING (1 << 7)
59 #define DESCRIPTOR_YY (1 << 6)
60 #define DESCRIPTOR_NO_IRQ (0 << 4)
61 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
62 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
63 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
64 #define DESCRIPTOR_WAIT (3 << 0)
70 __le32 branch_address;
72 __le16 transfer_status;
73 } __attribute__((aligned(16)));
75 struct db_descriptor {
78 __le16 second_req_count;
79 __le16 first_req_count;
80 __le32 branch_address;
81 __le16 second_res_count;
82 __le16 first_res_count;
87 } __attribute__((aligned(16)));
89 #define CONTROL_SET(regs) (regs)
90 #define CONTROL_CLEAR(regs) ((regs) + 4)
91 #define COMMAND_PTR(regs) ((regs) + 12)
92 #define CONTEXT_MATCH(regs) ((regs) + 16)
95 struct descriptor descriptor;
96 struct ar_buffer *next;
101 struct fw_ohci *ohci;
102 struct ar_buffer *current_buffer;
103 struct ar_buffer *last_buffer;
106 struct tasklet_struct tasklet;
111 typedef int (*descriptor_callback_t)(struct context *ctx,
112 struct descriptor *d,
113 struct descriptor *last);
116 * A buffer that contains a block of DMA-able coherent memory used for
117 * storing a portion of a DMA descriptor program.
119 struct descriptor_buffer {
120 struct list_head list;
121 dma_addr_t buffer_bus;
124 struct descriptor buffer[0];
128 struct fw_ohci *ohci;
130 int total_allocation;
133 * List of page-sized buffers for storing DMA descriptors.
134 * Head of list contains buffers in use and tail of list contains
137 struct list_head buffer_list;
140 * Pointer to a buffer inside buffer_list that contains the tail
141 * end of the current DMA program.
143 struct descriptor_buffer *buffer_tail;
146 * The descriptor containing the branch address of the first
147 * descriptor that has not yet been filled by the device.
149 struct descriptor *last;
152 * The last descriptor in the DMA program. It contains the branch
153 * address that must be updated upon appending a new descriptor.
155 struct descriptor *prev;
157 descriptor_callback_t callback;
159 struct tasklet_struct tasklet;
162 #define IT_HEADER_SY(v) ((v) << 0)
163 #define IT_HEADER_TCODE(v) ((v) << 4)
164 #define IT_HEADER_CHANNEL(v) ((v) << 8)
165 #define IT_HEADER_TAG(v) ((v) << 14)
166 #define IT_HEADER_SPEED(v) ((v) << 16)
167 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
170 struct fw_iso_context base;
171 struct context context;
174 size_t header_length;
177 #define CONFIG_ROM_SIZE 1024
182 __iomem char *registers;
183 dma_addr_t self_id_bus;
185 struct tasklet_struct bus_reset_tasklet;
188 int request_generation; /* for timestamping incoming requests */
192 bool bus_reset_packet_quirk;
193 bool iso_cycle_timer_quirk;
196 * Spinlock for accessing fw_ohci data. Never call out of
197 * this driver with this lock held.
200 u32 self_id_buffer[512];
202 /* Config rom buffers */
204 dma_addr_t config_rom_bus;
205 __be32 *next_config_rom;
206 dma_addr_t next_config_rom_bus;
209 struct ar_context ar_request_ctx;
210 struct ar_context ar_response_ctx;
211 struct context at_request_ctx;
212 struct context at_response_ctx;
215 struct iso_context *it_context_list;
216 u64 ir_context_channels;
218 struct iso_context *ir_context_list;
221 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
223 return container_of(card, struct fw_ohci, card);
226 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
227 #define IR_CONTEXT_BUFFER_FILL 0x80000000
228 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
229 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
230 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
231 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
233 #define CONTEXT_RUN 0x8000
234 #define CONTEXT_WAKE 0x1000
235 #define CONTEXT_DEAD 0x0800
236 #define CONTEXT_ACTIVE 0x0400
238 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
239 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
240 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
242 #define OHCI1394_REGISTER_SIZE 0x800
243 #define OHCI_LOOP_COUNT 500
244 #define OHCI1394_PCI_HCI_Control 0x40
245 #define SELF_ID_BUF_SIZE 0x800
246 #define OHCI_TCODE_PHY_PACKET 0x0e
247 #define OHCI_VERSION_1_1 0x010010
249 static char ohci_driver_name[] = KBUILD_MODNAME;
251 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
253 #define OHCI_PARAM_DEBUG_AT_AR 1
254 #define OHCI_PARAM_DEBUG_SELFIDS 2
255 #define OHCI_PARAM_DEBUG_IRQS 4
256 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
258 static int param_debug;
259 module_param_named(debug, param_debug, int, 0644);
260 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
261 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
262 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
263 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
264 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
265 ", or a combination, or all = -1)");
267 static void log_irqs(u32 evt)
269 if (likely(!(param_debug &
270 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
273 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
274 !(evt & OHCI1394_busReset))
277 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
278 evt & OHCI1394_selfIDComplete ? " selfID" : "",
279 evt & OHCI1394_RQPkt ? " AR_req" : "",
280 evt & OHCI1394_RSPkt ? " AR_resp" : "",
281 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
282 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
283 evt & OHCI1394_isochRx ? " IR" : "",
284 evt & OHCI1394_isochTx ? " IT" : "",
285 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
286 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
287 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
288 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
289 evt & OHCI1394_busReset ? " busReset" : "",
290 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
291 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
292 OHCI1394_respTxComplete | OHCI1394_isochRx |
293 OHCI1394_isochTx | OHCI1394_postedWriteErr |
294 OHCI1394_cycleTooLong | OHCI1394_cycleInconsistent |
295 OHCI1394_regAccessFail | OHCI1394_busReset)
299 static const char *speed[] = {
300 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
302 static const char *power[] = {
303 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
304 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
306 static const char port[] = { '.', '-', 'p', 'c', };
308 static char _p(u32 *s, int shift)
310 return port[*s >> shift & 3];
313 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
315 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
318 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
319 self_id_count, generation, node_id);
321 for (; self_id_count--; ++s)
322 if ((*s & 1 << 23) == 0)
323 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
324 "%s gc=%d %s %s%s%s\n",
325 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
326 speed[*s >> 14 & 3], *s >> 16 & 63,
327 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
328 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
330 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
332 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
333 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
336 static const char *evts[] = {
337 [0x00] = "evt_no_status", [0x01] = "-reserved-",
338 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
339 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
340 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
341 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
342 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
343 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
344 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
345 [0x10] = "-reserved-", [0x11] = "ack_complete",
346 [0x12] = "ack_pending ", [0x13] = "-reserved-",
347 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
348 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
349 [0x18] = "-reserved-", [0x19] = "-reserved-",
350 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
351 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
352 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
353 [0x20] = "pending/cancelled",
355 static const char *tcodes[] = {
356 [0x0] = "QW req", [0x1] = "BW req",
357 [0x2] = "W resp", [0x3] = "-reserved-",
358 [0x4] = "QR req", [0x5] = "BR req",
359 [0x6] = "QR resp", [0x7] = "BR resp",
360 [0x8] = "cycle start", [0x9] = "Lk req",
361 [0xa] = "async stream packet", [0xb] = "Lk resp",
362 [0xc] = "-reserved-", [0xd] = "-reserved-",
363 [0xe] = "link internal", [0xf] = "-reserved-",
365 static const char *phys[] = {
366 [0x0] = "phy config packet", [0x1] = "link-on packet",
367 [0x2] = "self-id packet", [0x3] = "-reserved-",
370 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
372 int tcode = header[0] >> 4 & 0xf;
375 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
378 if (unlikely(evt >= ARRAY_SIZE(evts)))
381 if (evt == OHCI1394_evt_bus_reset) {
382 fw_notify("A%c evt_bus_reset, generation %d\n",
383 dir, (header[2] >> 16) & 0xff);
387 if (header[0] == ~header[1]) {
388 fw_notify("A%c %s, %s, %08x\n",
389 dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
394 case 0x0: case 0x6: case 0x8:
395 snprintf(specific, sizeof(specific), " = %08x",
396 be32_to_cpu((__force __be32)header[3]));
398 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
399 snprintf(specific, sizeof(specific), " %x,%x",
400 header[3] >> 16, header[3] & 0xffff);
408 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
410 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
411 fw_notify("A%c spd %x tl %02x, "
414 dir, speed, header[0] >> 10 & 0x3f,
415 header[1] >> 16, header[0] >> 16, evts[evt],
416 tcodes[tcode], header[1] & 0xffff, header[2], specific);
419 fw_notify("A%c spd %x tl %02x, "
422 dir, speed, header[0] >> 10 & 0x3f,
423 header[1] >> 16, header[0] >> 16, evts[evt],
424 tcodes[tcode], specific);
430 #define log_irqs(evt)
431 #define log_selfids(node_id, generation, self_id_count, sid)
432 #define log_ar_at_event(dir, speed, header, evt)
434 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
436 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
438 writel(data, ohci->registers + offset);
441 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
443 return readl(ohci->registers + offset);
446 static inline void flush_writes(const struct fw_ohci *ohci)
448 /* Do a dummy read to flush writes. */
449 reg_read(ohci, OHCI1394_Version);
452 static int ohci_update_phy_reg(struct fw_card *card, int addr,
453 int clear_bits, int set_bits)
455 struct fw_ohci *ohci = fw_ohci(card);
458 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
461 val = reg_read(ohci, OHCI1394_PhyControl);
462 if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
463 fw_error("failed to set phy reg bits.\n");
467 old = OHCI1394_PhyControl_ReadData(val);
468 old = (old & ~clear_bits) | set_bits;
469 reg_write(ohci, OHCI1394_PhyControl,
470 OHCI1394_PhyControl_Write(addr, old));
475 static int ar_context_add_page(struct ar_context *ctx)
477 struct device *dev = ctx->ohci->card.device;
478 struct ar_buffer *ab;
479 dma_addr_t uninitialized_var(ab_bus);
482 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
487 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
488 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
490 DESCRIPTOR_BRANCH_ALWAYS);
491 offset = offsetof(struct ar_buffer, data);
492 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
493 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
494 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
495 ab->descriptor.branch_address = 0;
497 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
498 ctx->last_buffer->next = ab;
499 ctx->last_buffer = ab;
501 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
502 flush_writes(ctx->ohci);
507 static void ar_context_release(struct ar_context *ctx)
509 struct ar_buffer *ab, *ab_next;
513 for (ab = ctx->current_buffer; ab; ab = ab_next) {
515 offset = offsetof(struct ar_buffer, data);
516 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
517 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
522 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
523 #define cond_le32_to_cpu(v) \
524 (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
526 #define cond_le32_to_cpu(v) le32_to_cpu(v)
529 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
531 struct fw_ohci *ohci = ctx->ohci;
533 u32 status, length, tcode;
536 p.header[0] = cond_le32_to_cpu(buffer[0]);
537 p.header[1] = cond_le32_to_cpu(buffer[1]);
538 p.header[2] = cond_le32_to_cpu(buffer[2]);
540 tcode = (p.header[0] >> 4) & 0x0f;
542 case TCODE_WRITE_QUADLET_REQUEST:
543 case TCODE_READ_QUADLET_RESPONSE:
544 p.header[3] = (__force __u32) buffer[3];
545 p.header_length = 16;
546 p.payload_length = 0;
549 case TCODE_READ_BLOCK_REQUEST :
550 p.header[3] = cond_le32_to_cpu(buffer[3]);
551 p.header_length = 16;
552 p.payload_length = 0;
555 case TCODE_WRITE_BLOCK_REQUEST:
556 case TCODE_READ_BLOCK_RESPONSE:
557 case TCODE_LOCK_REQUEST:
558 case TCODE_LOCK_RESPONSE:
559 p.header[3] = cond_le32_to_cpu(buffer[3]);
560 p.header_length = 16;
561 p.payload_length = p.header[3] >> 16;
564 case TCODE_WRITE_RESPONSE:
565 case TCODE_READ_QUADLET_REQUEST:
566 case OHCI_TCODE_PHY_PACKET:
567 p.header_length = 12;
568 p.payload_length = 0;
572 /* FIXME: Stop context, discard everything, and restart? */
574 p.payload_length = 0;
577 p.payload = (void *) buffer + p.header_length;
579 /* FIXME: What to do about evt_* errors? */
580 length = (p.header_length + p.payload_length + 3) / 4;
581 status = cond_le32_to_cpu(buffer[length]);
582 evt = (status >> 16) & 0x1f;
585 p.speed = (status >> 21) & 0x7;
586 p.timestamp = status & 0xffff;
587 p.generation = ohci->request_generation;
589 log_ar_at_event('R', p.speed, p.header, evt);
592 * The OHCI bus reset handler synthesizes a phy packet with
593 * the new generation number when a bus reset happens (see
594 * section 8.4.2.3). This helps us determine when a request
595 * was received and make sure we send the response in the same
596 * generation. We only need this for requests; for responses
597 * we use the unique tlabel for finding the matching
600 * Alas some chips sometimes emit bus reset packets with a
601 * wrong generation. We set the correct generation for these
602 * at a slightly incorrect time (in bus_reset_tasklet).
604 if (evt == OHCI1394_evt_bus_reset) {
605 if (!ohci->bus_reset_packet_quirk)
606 ohci->request_generation = (p.header[2] >> 16) & 0xff;
607 } else if (ctx == &ohci->ar_request_ctx) {
608 fw_core_handle_request(&ohci->card, &p);
610 fw_core_handle_response(&ohci->card, &p);
613 return buffer + length + 1;
616 static void ar_context_tasklet(unsigned long data)
618 struct ar_context *ctx = (struct ar_context *)data;
619 struct fw_ohci *ohci = ctx->ohci;
620 struct ar_buffer *ab;
621 struct descriptor *d;
624 ab = ctx->current_buffer;
627 if (d->res_count == 0) {
628 size_t size, rest, offset;
629 dma_addr_t start_bus;
633 * This descriptor is finished and we may have a
634 * packet split across this and the next buffer. We
635 * reuse the page for reassembling the split packet.
638 offset = offsetof(struct ar_buffer, data);
640 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
644 size = buffer + PAGE_SIZE - ctx->pointer;
645 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
646 memmove(buffer, ctx->pointer, size);
647 memcpy(buffer + size, ab->data, rest);
648 ctx->current_buffer = ab;
649 ctx->pointer = (void *) ab->data + rest;
650 end = buffer + size + rest;
653 buffer = handle_ar_packet(ctx, buffer);
655 dma_free_coherent(ohci->card.device, PAGE_SIZE,
657 ar_context_add_page(ctx);
659 buffer = ctx->pointer;
661 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
664 buffer = handle_ar_packet(ctx, buffer);
668 static int ar_context_init(struct ar_context *ctx,
669 struct fw_ohci *ohci, u32 regs)
675 ctx->last_buffer = &ab;
676 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
678 ar_context_add_page(ctx);
679 ar_context_add_page(ctx);
680 ctx->current_buffer = ab.next;
681 ctx->pointer = ctx->current_buffer->data;
686 static void ar_context_run(struct ar_context *ctx)
688 struct ar_buffer *ab = ctx->current_buffer;
692 offset = offsetof(struct ar_buffer, data);
693 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
695 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
696 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
697 flush_writes(ctx->ohci);
700 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
704 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
705 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
707 /* figure out which descriptor the branch address goes in */
708 if (z == 2 && (b == 3 || key == 2))
714 static void context_tasklet(unsigned long data)
716 struct context *ctx = (struct context *) data;
717 struct descriptor *d, *last;
720 struct descriptor_buffer *desc;
722 desc = list_entry(ctx->buffer_list.next,
723 struct descriptor_buffer, list);
725 while (last->branch_address != 0) {
726 struct descriptor_buffer *old_desc = desc;
727 address = le32_to_cpu(last->branch_address);
731 /* If the branch address points to a buffer outside of the
732 * current buffer, advance to the next buffer. */
733 if (address < desc->buffer_bus ||
734 address >= desc->buffer_bus + desc->used)
735 desc = list_entry(desc->list.next,
736 struct descriptor_buffer, list);
737 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
738 last = find_branch_descriptor(d, z);
740 if (!ctx->callback(ctx, d, last))
743 if (old_desc != desc) {
744 /* If we've advanced to the next buffer, move the
745 * previous buffer to the free list. */
748 spin_lock_irqsave(&ctx->ohci->lock, flags);
749 list_move_tail(&old_desc->list, &ctx->buffer_list);
750 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
757 * Allocate a new buffer and add it to the list of free buffers for this
758 * context. Must be called with ohci->lock held.
760 static int context_add_buffer(struct context *ctx)
762 struct descriptor_buffer *desc;
763 dma_addr_t uninitialized_var(bus_addr);
767 * 16MB of descriptors should be far more than enough for any DMA
768 * program. This will catch run-away userspace or DoS attacks.
770 if (ctx->total_allocation >= 16*1024*1024)
773 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
774 &bus_addr, GFP_ATOMIC);
778 offset = (void *)&desc->buffer - (void *)desc;
779 desc->buffer_size = PAGE_SIZE - offset;
780 desc->buffer_bus = bus_addr + offset;
783 list_add_tail(&desc->list, &ctx->buffer_list);
784 ctx->total_allocation += PAGE_SIZE;
789 static int context_init(struct context *ctx, struct fw_ohci *ohci,
790 u32 regs, descriptor_callback_t callback)
794 ctx->total_allocation = 0;
796 INIT_LIST_HEAD(&ctx->buffer_list);
797 if (context_add_buffer(ctx) < 0)
800 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
801 struct descriptor_buffer, list);
803 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
804 ctx->callback = callback;
807 * We put a dummy descriptor in the buffer that has a NULL
808 * branch address and looks like it's been sent. That way we
809 * have a descriptor to append DMA programs to.
811 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
812 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
813 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
814 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
815 ctx->last = ctx->buffer_tail->buffer;
816 ctx->prev = ctx->buffer_tail->buffer;
821 static void context_release(struct context *ctx)
823 struct fw_card *card = &ctx->ohci->card;
824 struct descriptor_buffer *desc, *tmp;
826 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
827 dma_free_coherent(card->device, PAGE_SIZE, desc,
829 ((void *)&desc->buffer - (void *)desc));
832 /* Must be called with ohci->lock held */
833 static struct descriptor *context_get_descriptors(struct context *ctx,
834 int z, dma_addr_t *d_bus)
836 struct descriptor *d = NULL;
837 struct descriptor_buffer *desc = ctx->buffer_tail;
839 if (z * sizeof(*d) > desc->buffer_size)
842 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
843 /* No room for the descriptor in this buffer, so advance to the
846 if (desc->list.next == &ctx->buffer_list) {
847 /* If there is no free buffer next in the list,
849 if (context_add_buffer(ctx) < 0)
852 desc = list_entry(desc->list.next,
853 struct descriptor_buffer, list);
854 ctx->buffer_tail = desc;
857 d = desc->buffer + desc->used / sizeof(*d);
858 memset(d, 0, z * sizeof(*d));
859 *d_bus = desc->buffer_bus + desc->used;
864 static void context_run(struct context *ctx, u32 extra)
866 struct fw_ohci *ohci = ctx->ohci;
868 reg_write(ohci, COMMAND_PTR(ctx->regs),
869 le32_to_cpu(ctx->last->branch_address));
870 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
871 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
875 static void context_append(struct context *ctx,
876 struct descriptor *d, int z, int extra)
879 struct descriptor_buffer *desc = ctx->buffer_tail;
881 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
883 desc->used += (z + extra) * sizeof(*d);
884 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
885 ctx->prev = find_branch_descriptor(d, z);
887 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
888 flush_writes(ctx->ohci);
891 static void context_stop(struct context *ctx)
896 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
897 flush_writes(ctx->ohci);
899 for (i = 0; i < 10; i++) {
900 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
901 if ((reg & CONTEXT_ACTIVE) == 0)
906 fw_error("Error: DMA context still active (0x%08x)\n", reg);
910 struct fw_packet *packet;
914 * This function apppends a packet to the DMA queue for transmission.
915 * Must always be called with the ochi->lock held to ensure proper
916 * generation handling and locking around packet queue manipulation.
918 static int at_context_queue_packet(struct context *ctx,
919 struct fw_packet *packet)
921 struct fw_ohci *ohci = ctx->ohci;
922 dma_addr_t d_bus, uninitialized_var(payload_bus);
923 struct driver_data *driver_data;
924 struct descriptor *d, *last;
929 d = context_get_descriptors(ctx, 4, &d_bus);
931 packet->ack = RCODE_SEND_ERROR;
935 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
936 d[0].res_count = cpu_to_le16(packet->timestamp);
939 * The DMA format for asyncronous link packets is different
940 * from the IEEE1394 layout, so shift the fields around
941 * accordingly. If header_length is 8, it's a PHY packet, to
942 * which we need to prepend an extra quadlet.
945 header = (__le32 *) &d[1];
946 switch (packet->header_length) {
949 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
950 (packet->speed << 16));
951 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
952 (packet->header[0] & 0xffff0000));
953 header[2] = cpu_to_le32(packet->header[2]);
955 tcode = (packet->header[0] >> 4) & 0x0f;
956 if (TCODE_IS_BLOCK_PACKET(tcode))
957 header[3] = cpu_to_le32(packet->header[3]);
959 header[3] = (__force __le32) packet->header[3];
961 d[0].req_count = cpu_to_le16(packet->header_length);
965 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
966 (packet->speed << 16));
967 header[1] = cpu_to_le32(packet->header[0]);
968 header[2] = cpu_to_le32(packet->header[1]);
969 d[0].req_count = cpu_to_le16(12);
973 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
974 (packet->speed << 16));
975 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
976 d[0].req_count = cpu_to_le16(8);
981 packet->ack = RCODE_SEND_ERROR;
985 driver_data = (struct driver_data *) &d[3];
986 driver_data->packet = packet;
987 packet->driver_data = driver_data;
989 if (packet->payload_length > 0) {
991 dma_map_single(ohci->card.device, packet->payload,
992 packet->payload_length, DMA_TO_DEVICE);
993 if (dma_mapping_error(ohci->card.device, payload_bus)) {
994 packet->ack = RCODE_SEND_ERROR;
997 packet->payload_bus = payload_bus;
998 packet->payload_mapped = true;
1000 d[2].req_count = cpu_to_le16(packet->payload_length);
1001 d[2].data_address = cpu_to_le32(payload_bus);
1009 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1010 DESCRIPTOR_IRQ_ALWAYS |
1011 DESCRIPTOR_BRANCH_ALWAYS);
1014 * If the controller and packet generations don't match, we need to
1015 * bail out and try again. If IntEvent.busReset is set, the AT context
1016 * is halted, so appending to the context and trying to run it is
1017 * futile. Most controllers do the right thing and just flush the AT
1018 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1019 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1020 * up stalling out. So we just bail out in software and try again
1021 * later, and everyone is happy.
1022 * FIXME: Document how the locking works.
1024 if (ohci->generation != packet->generation ||
1025 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1026 if (packet->payload_mapped)
1027 dma_unmap_single(ohci->card.device, payload_bus,
1028 packet->payload_length, DMA_TO_DEVICE);
1029 packet->ack = RCODE_GENERATION;
1033 context_append(ctx, d, z, 4 - z);
1035 /* If the context isn't already running, start it up. */
1036 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1037 if ((reg & CONTEXT_RUN) == 0)
1038 context_run(ctx, 0);
1043 static int handle_at_packet(struct context *context,
1044 struct descriptor *d,
1045 struct descriptor *last)
1047 struct driver_data *driver_data;
1048 struct fw_packet *packet;
1049 struct fw_ohci *ohci = context->ohci;
1052 if (last->transfer_status == 0)
1053 /* This descriptor isn't done yet, stop iteration. */
1056 driver_data = (struct driver_data *) &d[3];
1057 packet = driver_data->packet;
1059 /* This packet was cancelled, just continue. */
1062 if (packet->payload_mapped)
1063 dma_unmap_single(ohci->card.device, packet->payload_bus,
1064 packet->payload_length, DMA_TO_DEVICE);
1066 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1067 packet->timestamp = le16_to_cpu(last->res_count);
1069 log_ar_at_event('T', packet->speed, packet->header, evt);
1072 case OHCI1394_evt_timeout:
1073 /* Async response transmit timed out. */
1074 packet->ack = RCODE_CANCELLED;
1077 case OHCI1394_evt_flushed:
1079 * The packet was flushed should give same error as
1080 * when we try to use a stale generation count.
1082 packet->ack = RCODE_GENERATION;
1085 case OHCI1394_evt_missing_ack:
1087 * Using a valid (current) generation count, but the
1088 * node is not on the bus or not sending acks.
1090 packet->ack = RCODE_NO_ACK;
1093 case ACK_COMPLETE + 0x10:
1094 case ACK_PENDING + 0x10:
1095 case ACK_BUSY_X + 0x10:
1096 case ACK_BUSY_A + 0x10:
1097 case ACK_BUSY_B + 0x10:
1098 case ACK_DATA_ERROR + 0x10:
1099 case ACK_TYPE_ERROR + 0x10:
1100 packet->ack = evt - 0x10;
1104 packet->ack = RCODE_SEND_ERROR;
1108 packet->callback(packet, &ohci->card, packet->ack);
1113 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1114 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1115 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1116 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1117 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1119 static void handle_local_rom(struct fw_ohci *ohci,
1120 struct fw_packet *packet, u32 csr)
1122 struct fw_packet response;
1123 int tcode, length, i;
1125 tcode = HEADER_GET_TCODE(packet->header[0]);
1126 if (TCODE_IS_BLOCK_PACKET(tcode))
1127 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1131 i = csr - CSR_CONFIG_ROM;
1132 if (i + length > CONFIG_ROM_SIZE) {
1133 fw_fill_response(&response, packet->header,
1134 RCODE_ADDRESS_ERROR, NULL, 0);
1135 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1136 fw_fill_response(&response, packet->header,
1137 RCODE_TYPE_ERROR, NULL, 0);
1139 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1140 (void *) ohci->config_rom + i, length);
1143 fw_core_handle_response(&ohci->card, &response);
1146 static void handle_local_lock(struct fw_ohci *ohci,
1147 struct fw_packet *packet, u32 csr)
1149 struct fw_packet response;
1150 int tcode, length, ext_tcode, sel;
1151 __be32 *payload, lock_old;
1152 u32 lock_arg, lock_data;
1154 tcode = HEADER_GET_TCODE(packet->header[0]);
1155 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1156 payload = packet->payload;
1157 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1159 if (tcode == TCODE_LOCK_REQUEST &&
1160 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1161 lock_arg = be32_to_cpu(payload[0]);
1162 lock_data = be32_to_cpu(payload[1]);
1163 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1167 fw_fill_response(&response, packet->header,
1168 RCODE_TYPE_ERROR, NULL, 0);
1172 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1173 reg_write(ohci, OHCI1394_CSRData, lock_data);
1174 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1175 reg_write(ohci, OHCI1394_CSRControl, sel);
1177 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1178 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1180 fw_notify("swap not done yet\n");
1182 fw_fill_response(&response, packet->header,
1183 RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1185 fw_core_handle_response(&ohci->card, &response);
1188 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1193 if (ctx == &ctx->ohci->at_request_ctx) {
1194 packet->ack = ACK_PENDING;
1195 packet->callback(packet, &ctx->ohci->card, packet->ack);
1199 ((unsigned long long)
1200 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1202 csr = offset - CSR_REGISTER_BASE;
1204 /* Handle config rom reads. */
1205 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1206 handle_local_rom(ctx->ohci, packet, csr);
1208 case CSR_BUS_MANAGER_ID:
1209 case CSR_BANDWIDTH_AVAILABLE:
1210 case CSR_CHANNELS_AVAILABLE_HI:
1211 case CSR_CHANNELS_AVAILABLE_LO:
1212 handle_local_lock(ctx->ohci, packet, csr);
1215 if (ctx == &ctx->ohci->at_request_ctx)
1216 fw_core_handle_request(&ctx->ohci->card, packet);
1218 fw_core_handle_response(&ctx->ohci->card, packet);
1222 if (ctx == &ctx->ohci->at_response_ctx) {
1223 packet->ack = ACK_COMPLETE;
1224 packet->callback(packet, &ctx->ohci->card, packet->ack);
1228 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1230 unsigned long flags;
1233 spin_lock_irqsave(&ctx->ohci->lock, flags);
1235 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1236 ctx->ohci->generation == packet->generation) {
1237 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1238 handle_local_request(ctx, packet);
1242 ret = at_context_queue_packet(ctx, packet);
1243 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1246 packet->callback(packet, &ctx->ohci->card, packet->ack);
1250 static void bus_reset_tasklet(unsigned long data)
1252 struct fw_ohci *ohci = (struct fw_ohci *)data;
1253 int self_id_count, i, j, reg;
1254 int generation, new_generation;
1255 unsigned long flags;
1256 void *free_rom = NULL;
1257 dma_addr_t free_rom_bus = 0;
1259 reg = reg_read(ohci, OHCI1394_NodeID);
1260 if (!(reg & OHCI1394_NodeID_idValid)) {
1261 fw_notify("node ID not valid, new bus reset in progress\n");
1264 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1265 fw_notify("malconfigured bus\n");
1268 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1269 OHCI1394_NodeID_nodeNumber);
1271 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1272 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1273 fw_notify("inconsistent self IDs\n");
1277 * The count in the SelfIDCount register is the number of
1278 * bytes in the self ID receive buffer. Since we also receive
1279 * the inverted quadlets and a header quadlet, we shift one
1280 * bit extra to get the actual number of self IDs.
1282 self_id_count = (reg >> 3) & 0xff;
1283 if (self_id_count == 0 || self_id_count > 252) {
1284 fw_notify("inconsistent self IDs\n");
1287 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1290 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1291 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1292 fw_notify("inconsistent self IDs\n");
1295 ohci->self_id_buffer[j] =
1296 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1301 * Check the consistency of the self IDs we just read. The
1302 * problem we face is that a new bus reset can start while we
1303 * read out the self IDs from the DMA buffer. If this happens,
1304 * the DMA buffer will be overwritten with new self IDs and we
1305 * will read out inconsistent data. The OHCI specification
1306 * (section 11.2) recommends a technique similar to
1307 * linux/seqlock.h, where we remember the generation of the
1308 * self IDs in the buffer before reading them out and compare
1309 * it to the current generation after reading them out. If
1310 * the two generations match we know we have a consistent set
1314 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1315 if (new_generation != generation) {
1316 fw_notify("recursive bus reset detected, "
1317 "discarding self ids\n");
1321 /* FIXME: Document how the locking works. */
1322 spin_lock_irqsave(&ohci->lock, flags);
1324 ohci->generation = generation;
1325 context_stop(&ohci->at_request_ctx);
1326 context_stop(&ohci->at_response_ctx);
1327 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1329 if (ohci->bus_reset_packet_quirk)
1330 ohci->request_generation = generation;
1333 * This next bit is unrelated to the AT context stuff but we
1334 * have to do it under the spinlock also. If a new config rom
1335 * was set up before this reset, the old one is now no longer
1336 * in use and we can free it. Update the config rom pointers
1337 * to point to the current config rom and clear the
1338 * next_config_rom pointer so a new udpate can take place.
1341 if (ohci->next_config_rom != NULL) {
1342 if (ohci->next_config_rom != ohci->config_rom) {
1343 free_rom = ohci->config_rom;
1344 free_rom_bus = ohci->config_rom_bus;
1346 ohci->config_rom = ohci->next_config_rom;
1347 ohci->config_rom_bus = ohci->next_config_rom_bus;
1348 ohci->next_config_rom = NULL;
1351 * Restore config_rom image and manually update
1352 * config_rom registers. Writing the header quadlet
1353 * will indicate that the config rom is ready, so we
1356 reg_write(ohci, OHCI1394_BusOptions,
1357 be32_to_cpu(ohci->config_rom[2]));
1358 ohci->config_rom[0] = ohci->next_header;
1359 reg_write(ohci, OHCI1394_ConfigROMhdr,
1360 be32_to_cpu(ohci->next_header));
1363 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1364 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1365 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1368 spin_unlock_irqrestore(&ohci->lock, flags);
1371 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1372 free_rom, free_rom_bus);
1374 log_selfids(ohci->node_id, generation,
1375 self_id_count, ohci->self_id_buffer);
1377 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1378 self_id_count, ohci->self_id_buffer);
1381 static irqreturn_t irq_handler(int irq, void *data)
1383 struct fw_ohci *ohci = data;
1384 u32 event, iso_event;
1387 event = reg_read(ohci, OHCI1394_IntEventClear);
1389 if (!event || !~event)
1392 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1393 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1396 if (event & OHCI1394_selfIDComplete)
1397 tasklet_schedule(&ohci->bus_reset_tasklet);
1399 if (event & OHCI1394_RQPkt)
1400 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1402 if (event & OHCI1394_RSPkt)
1403 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1405 if (event & OHCI1394_reqTxComplete)
1406 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1408 if (event & OHCI1394_respTxComplete)
1409 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1411 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1412 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1415 i = ffs(iso_event) - 1;
1416 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1417 iso_event &= ~(1 << i);
1420 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1421 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1424 i = ffs(iso_event) - 1;
1425 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1426 iso_event &= ~(1 << i);
1429 if (unlikely(event & OHCI1394_regAccessFail))
1430 fw_error("Register access failure - "
1431 "please notify linux1394-devel@lists.sf.net\n");
1433 if (unlikely(event & OHCI1394_postedWriteErr))
1434 fw_error("PCI posted write error\n");
1436 if (unlikely(event & OHCI1394_cycleTooLong)) {
1437 if (printk_ratelimit())
1438 fw_notify("isochronous cycle too long\n");
1439 reg_write(ohci, OHCI1394_LinkControlSet,
1440 OHCI1394_LinkControl_cycleMaster);
1443 if (unlikely(event & OHCI1394_cycleInconsistent)) {
1445 * We need to clear this event bit in order to make
1446 * cycleMatch isochronous I/O work. In theory we should
1447 * stop active cycleMatch iso contexts now and restart
1448 * them at least two cycles later. (FIXME?)
1450 if (printk_ratelimit())
1451 fw_notify("isochronous cycle inconsistent\n");
1457 static int software_reset(struct fw_ohci *ohci)
1461 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1463 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1464 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1465 OHCI1394_HCControl_softReset) == 0)
1473 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1475 size_t size = length * 4;
1477 memcpy(dest, src, size);
1478 if (size < CONFIG_ROM_SIZE)
1479 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1482 static int ohci_enable(struct fw_card *card,
1483 const __be32 *config_rom, size_t length)
1485 struct fw_ohci *ohci = fw_ohci(card);
1486 struct pci_dev *dev = to_pci_dev(card->device);
1490 if (software_reset(ohci)) {
1491 fw_error("Failed to reset ohci card.\n");
1496 * Now enable LPS, which we need in order to start accessing
1497 * most of the registers. In fact, on some cards (ALI M5251),
1498 * accessing registers in the SClk domain without LPS enabled
1499 * will lock up the machine. Wait 50msec to make sure we have
1500 * full link enabled. However, with some cards (well, at least
1501 * a JMicron PCIe card), we have to try again sometimes.
1503 reg_write(ohci, OHCI1394_HCControlSet,
1504 OHCI1394_HCControl_LPS |
1505 OHCI1394_HCControl_postedWriteEnable);
1508 for (lps = 0, i = 0; !lps && i < 3; i++) {
1510 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1511 OHCI1394_HCControl_LPS;
1515 fw_error("Failed to set Link Power Status\n");
1519 reg_write(ohci, OHCI1394_HCControlClear,
1520 OHCI1394_HCControl_noByteSwapData);
1522 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1523 reg_write(ohci, OHCI1394_LinkControlClear,
1524 OHCI1394_LinkControl_rcvPhyPkt);
1525 reg_write(ohci, OHCI1394_LinkControlSet,
1526 OHCI1394_LinkControl_rcvSelfID |
1527 OHCI1394_LinkControl_cycleTimerEnable |
1528 OHCI1394_LinkControl_cycleMaster);
1530 reg_write(ohci, OHCI1394_ATRetries,
1531 OHCI1394_MAX_AT_REQ_RETRIES |
1532 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1533 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1535 ar_context_run(&ohci->ar_request_ctx);
1536 ar_context_run(&ohci->ar_response_ctx);
1538 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1539 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1540 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1541 reg_write(ohci, OHCI1394_IntMaskSet,
1542 OHCI1394_selfIDComplete |
1543 OHCI1394_RQPkt | OHCI1394_RSPkt |
1544 OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1545 OHCI1394_isochRx | OHCI1394_isochTx |
1546 OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
1547 OHCI1394_cycleInconsistent | OHCI1394_regAccessFail |
1548 OHCI1394_masterIntEnable);
1549 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1550 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
1552 /* Activate link_on bit and contender bit in our self ID packets.*/
1553 if (ohci_update_phy_reg(card, 4, 0,
1554 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1558 * When the link is not yet enabled, the atomic config rom
1559 * update mechanism described below in ohci_set_config_rom()
1560 * is not active. We have to update ConfigRomHeader and
1561 * BusOptions manually, and the write to ConfigROMmap takes
1562 * effect immediately. We tie this to the enabling of the
1563 * link, so we have a valid config rom before enabling - the
1564 * OHCI requires that ConfigROMhdr and BusOptions have valid
1565 * values before enabling.
1567 * However, when the ConfigROMmap is written, some controllers
1568 * always read back quadlets 0 and 2 from the config rom to
1569 * the ConfigRomHeader and BusOptions registers on bus reset.
1570 * They shouldn't do that in this initial case where the link
1571 * isn't enabled. This means we have to use the same
1572 * workaround here, setting the bus header to 0 and then write
1573 * the right values in the bus reset tasklet.
1577 ohci->next_config_rom =
1578 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1579 &ohci->next_config_rom_bus,
1581 if (ohci->next_config_rom == NULL)
1584 copy_config_rom(ohci->next_config_rom, config_rom, length);
1587 * In the suspend case, config_rom is NULL, which
1588 * means that we just reuse the old config rom.
1590 ohci->next_config_rom = ohci->config_rom;
1591 ohci->next_config_rom_bus = ohci->config_rom_bus;
1594 ohci->next_header = ohci->next_config_rom[0];
1595 ohci->next_config_rom[0] = 0;
1596 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1597 reg_write(ohci, OHCI1394_BusOptions,
1598 be32_to_cpu(ohci->next_config_rom[2]));
1599 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1601 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1603 if (request_irq(dev->irq, irq_handler,
1604 IRQF_SHARED, ohci_driver_name, ohci)) {
1605 fw_error("Failed to allocate shared interrupt %d.\n",
1607 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1608 ohci->config_rom, ohci->config_rom_bus);
1612 reg_write(ohci, OHCI1394_HCControlSet,
1613 OHCI1394_HCControl_linkEnable |
1614 OHCI1394_HCControl_BIBimageValid);
1618 * We are ready to go, initiate bus reset to finish the
1622 fw_core_initiate_bus_reset(&ohci->card, 1);
1627 static int ohci_set_config_rom(struct fw_card *card,
1628 const __be32 *config_rom, size_t length)
1630 struct fw_ohci *ohci;
1631 unsigned long flags;
1633 __be32 *next_config_rom;
1634 dma_addr_t uninitialized_var(next_config_rom_bus);
1636 ohci = fw_ohci(card);
1639 * When the OHCI controller is enabled, the config rom update
1640 * mechanism is a bit tricky, but easy enough to use. See
1641 * section 5.5.6 in the OHCI specification.
1643 * The OHCI controller caches the new config rom address in a
1644 * shadow register (ConfigROMmapNext) and needs a bus reset
1645 * for the changes to take place. When the bus reset is
1646 * detected, the controller loads the new values for the
1647 * ConfigRomHeader and BusOptions registers from the specified
1648 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1649 * shadow register. All automatically and atomically.
1651 * Now, there's a twist to this story. The automatic load of
1652 * ConfigRomHeader and BusOptions doesn't honor the
1653 * noByteSwapData bit, so with a be32 config rom, the
1654 * controller will load be32 values in to these registers
1655 * during the atomic update, even on litte endian
1656 * architectures. The workaround we use is to put a 0 in the
1657 * header quadlet; 0 is endian agnostic and means that the
1658 * config rom isn't ready yet. In the bus reset tasklet we
1659 * then set up the real values for the two registers.
1661 * We use ohci->lock to avoid racing with the code that sets
1662 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1666 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1667 &next_config_rom_bus, GFP_KERNEL);
1668 if (next_config_rom == NULL)
1671 spin_lock_irqsave(&ohci->lock, flags);
1673 if (ohci->next_config_rom == NULL) {
1674 ohci->next_config_rom = next_config_rom;
1675 ohci->next_config_rom_bus = next_config_rom_bus;
1677 copy_config_rom(ohci->next_config_rom, config_rom, length);
1679 ohci->next_header = config_rom[0];
1680 ohci->next_config_rom[0] = 0;
1682 reg_write(ohci, OHCI1394_ConfigROMmap,
1683 ohci->next_config_rom_bus);
1687 spin_unlock_irqrestore(&ohci->lock, flags);
1690 * Now initiate a bus reset to have the changes take
1691 * effect. We clean up the old config rom memory and DMA
1692 * mappings in the bus reset tasklet, since the OHCI
1693 * controller could need to access it before the bus reset
1697 fw_core_initiate_bus_reset(&ohci->card, 1);
1699 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1700 next_config_rom, next_config_rom_bus);
1705 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1707 struct fw_ohci *ohci = fw_ohci(card);
1709 at_context_transmit(&ohci->at_request_ctx, packet);
1712 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1714 struct fw_ohci *ohci = fw_ohci(card);
1716 at_context_transmit(&ohci->at_response_ctx, packet);
1719 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1721 struct fw_ohci *ohci = fw_ohci(card);
1722 struct context *ctx = &ohci->at_request_ctx;
1723 struct driver_data *driver_data = packet->driver_data;
1726 tasklet_disable(&ctx->tasklet);
1728 if (packet->ack != 0)
1731 if (packet->payload_mapped)
1732 dma_unmap_single(ohci->card.device, packet->payload_bus,
1733 packet->payload_length, DMA_TO_DEVICE);
1735 log_ar_at_event('T', packet->speed, packet->header, 0x20);
1736 driver_data->packet = NULL;
1737 packet->ack = RCODE_CANCELLED;
1738 packet->callback(packet, &ohci->card, packet->ack);
1741 tasklet_enable(&ctx->tasklet);
1746 static int ohci_enable_phys_dma(struct fw_card *card,
1747 int node_id, int generation)
1749 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1752 struct fw_ohci *ohci = fw_ohci(card);
1753 unsigned long flags;
1757 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1758 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1761 spin_lock_irqsave(&ohci->lock, flags);
1763 if (ohci->generation != generation) {
1769 * Note, if the node ID contains a non-local bus ID, physical DMA is
1770 * enabled for _all_ nodes on remote buses.
1773 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1775 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1777 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1781 spin_unlock_irqrestore(&ohci->lock, flags);
1784 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1787 static u32 cycle_timer_ticks(u32 cycle_timer)
1791 ticks = cycle_timer & 0xfff;
1792 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1793 ticks += (3072 * 8000) * (cycle_timer >> 25);
1799 * Some controllers exhibit one or more of the following bugs when updating the
1800 * iso cycle timer register:
1801 * - When the lowest six bits are wrapping around to zero, a read that happens
1802 * at the same time will return garbage in the lowest ten bits.
1803 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1804 * not incremented for about 60 ns.
1805 * - Occasionally, the entire register reads zero.
1807 * To catch these, we read the register three times and ensure that the
1808 * difference between each two consecutive reads is approximately the same, i.e.
1809 * less than twice the other. Furthermore, any negative difference indicates an
1810 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1811 * execute, so we have enough precision to compute the ratio of the differences.)
1813 static u32 ohci_get_cycle_time(struct fw_card *card)
1815 struct fw_ohci *ohci = fw_ohci(card);
1821 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1823 if (ohci->iso_cycle_timer_quirk) {
1826 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1830 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1831 t0 = cycle_timer_ticks(c0);
1832 t1 = cycle_timer_ticks(c1);
1833 t2 = cycle_timer_ticks(c2);
1836 } while ((diff01 <= 0 || diff12 <= 0 ||
1837 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1844 static void copy_iso_headers(struct iso_context *ctx, void *p)
1846 int i = ctx->header_length;
1848 if (i + ctx->base.header_size > PAGE_SIZE)
1852 * The iso header is byteswapped to little endian by
1853 * the controller, but the remaining header quadlets
1854 * are big endian. We want to present all the headers
1855 * as big endian, so we have to swap the first quadlet.
1857 if (ctx->base.header_size > 0)
1858 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1859 if (ctx->base.header_size > 4)
1860 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
1861 if (ctx->base.header_size > 8)
1862 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
1863 ctx->header_length += ctx->base.header_size;
1866 static int handle_ir_dualbuffer_packet(struct context *context,
1867 struct descriptor *d,
1868 struct descriptor *last)
1870 struct iso_context *ctx =
1871 container_of(context, struct iso_context, context);
1872 struct db_descriptor *db = (struct db_descriptor *) d;
1874 size_t header_length;
1877 if (db->first_res_count != 0 && db->second_res_count != 0) {
1878 if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) {
1879 /* This descriptor isn't done yet, stop iteration. */
1882 ctx->excess_bytes -= le16_to_cpu(db->second_req_count);
1885 header_length = le16_to_cpu(db->first_req_count) -
1886 le16_to_cpu(db->first_res_count);
1889 end = p + header_length;
1891 copy_iso_headers(ctx, p);
1892 ctx->excess_bytes +=
1893 (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff;
1894 p += max(ctx->base.header_size, (size_t)8);
1897 ctx->excess_bytes -= le16_to_cpu(db->second_req_count) -
1898 le16_to_cpu(db->second_res_count);
1900 if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
1901 ir_header = (__le32 *) (db + 1);
1902 ctx->base.callback(&ctx->base,
1903 le32_to_cpu(ir_header[0]) & 0xffff,
1904 ctx->header_length, ctx->header,
1905 ctx->base.callback_data);
1906 ctx->header_length = 0;
1912 static int handle_ir_packet_per_buffer(struct context *context,
1913 struct descriptor *d,
1914 struct descriptor *last)
1916 struct iso_context *ctx =
1917 container_of(context, struct iso_context, context);
1918 struct descriptor *pd;
1922 for (pd = d; pd <= last; pd++) {
1923 if (pd->transfer_status)
1927 /* Descriptor(s) not done yet, stop iteration */
1931 copy_iso_headers(ctx, p);
1933 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1934 ir_header = (__le32 *) p;
1935 ctx->base.callback(&ctx->base,
1936 le32_to_cpu(ir_header[0]) & 0xffff,
1937 ctx->header_length, ctx->header,
1938 ctx->base.callback_data);
1939 ctx->header_length = 0;
1945 static int handle_it_packet(struct context *context,
1946 struct descriptor *d,
1947 struct descriptor *last)
1949 struct iso_context *ctx =
1950 container_of(context, struct iso_context, context);
1952 struct descriptor *pd;
1954 for (pd = d; pd <= last; pd++)
1955 if (pd->transfer_status)
1958 /* Descriptor(s) not done yet, stop iteration */
1961 i = ctx->header_length;
1962 if (i + 4 < PAGE_SIZE) {
1963 /* Present this value as big-endian to match the receive code */
1964 *(__be32 *)(ctx->header + i) = cpu_to_be32(
1965 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
1966 le16_to_cpu(pd->res_count));
1967 ctx->header_length += 4;
1969 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1970 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1971 ctx->header_length, ctx->header,
1972 ctx->base.callback_data);
1973 ctx->header_length = 0;
1978 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
1979 int type, int channel, size_t header_size)
1981 struct fw_ohci *ohci = fw_ohci(card);
1982 struct iso_context *ctx, *list;
1983 descriptor_callback_t callback;
1984 u64 *channels, dont_care = ~0ULL;
1986 unsigned long flags;
1987 int index, ret = -ENOMEM;
1989 if (type == FW_ISO_CONTEXT_TRANSMIT) {
1990 channels = &dont_care;
1991 mask = &ohci->it_context_mask;
1992 list = ohci->it_context_list;
1993 callback = handle_it_packet;
1995 channels = &ohci->ir_context_channels;
1996 mask = &ohci->ir_context_mask;
1997 list = ohci->ir_context_list;
1998 if (ohci->use_dualbuffer)
1999 callback = handle_ir_dualbuffer_packet;
2001 callback = handle_ir_packet_per_buffer;
2004 spin_lock_irqsave(&ohci->lock, flags);
2005 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2007 *channels &= ~(1ULL << channel);
2008 *mask &= ~(1 << index);
2010 spin_unlock_irqrestore(&ohci->lock, flags);
2013 return ERR_PTR(-EBUSY);
2015 if (type == FW_ISO_CONTEXT_TRANSMIT)
2016 regs = OHCI1394_IsoXmitContextBase(index);
2018 regs = OHCI1394_IsoRcvContextBase(index);
2021 memset(ctx, 0, sizeof(*ctx));
2022 ctx->header_length = 0;
2023 ctx->header = (void *) __get_free_page(GFP_KERNEL);
2024 if (ctx->header == NULL)
2027 ret = context_init(&ctx->context, ohci, regs, callback);
2029 goto out_with_header;
2034 free_page((unsigned long)ctx->header);
2036 spin_lock_irqsave(&ohci->lock, flags);
2037 *mask |= 1 << index;
2038 spin_unlock_irqrestore(&ohci->lock, flags);
2040 return ERR_PTR(ret);
2043 static int ohci_start_iso(struct fw_iso_context *base,
2044 s32 cycle, u32 sync, u32 tags)
2046 struct iso_context *ctx = container_of(base, struct iso_context, base);
2047 struct fw_ohci *ohci = ctx->context.ohci;
2051 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2052 index = ctx - ohci->it_context_list;
2055 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2056 (cycle & 0x7fff) << 16;
2058 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2059 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2060 context_run(&ctx->context, match);
2062 index = ctx - ohci->ir_context_list;
2063 control = IR_CONTEXT_ISOCH_HEADER;
2064 if (ohci->use_dualbuffer)
2065 control |= IR_CONTEXT_DUAL_BUFFER_MODE;
2066 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2068 match |= (cycle & 0x07fff) << 12;
2069 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2072 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2073 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2074 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2075 context_run(&ctx->context, control);
2081 static int ohci_stop_iso(struct fw_iso_context *base)
2083 struct fw_ohci *ohci = fw_ohci(base->card);
2084 struct iso_context *ctx = container_of(base, struct iso_context, base);
2087 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2088 index = ctx - ohci->it_context_list;
2089 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2091 index = ctx - ohci->ir_context_list;
2092 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2095 context_stop(&ctx->context);
2100 static void ohci_free_iso_context(struct fw_iso_context *base)
2102 struct fw_ohci *ohci = fw_ohci(base->card);
2103 struct iso_context *ctx = container_of(base, struct iso_context, base);
2104 unsigned long flags;
2107 ohci_stop_iso(base);
2108 context_release(&ctx->context);
2109 free_page((unsigned long)ctx->header);
2111 spin_lock_irqsave(&ohci->lock, flags);
2113 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2114 index = ctx - ohci->it_context_list;
2115 ohci->it_context_mask |= 1 << index;
2117 index = ctx - ohci->ir_context_list;
2118 ohci->ir_context_mask |= 1 << index;
2119 ohci->ir_context_channels |= 1ULL << base->channel;
2122 spin_unlock_irqrestore(&ohci->lock, flags);
2125 static int ohci_queue_iso_transmit(struct fw_iso_context *base,
2126 struct fw_iso_packet *packet,
2127 struct fw_iso_buffer *buffer,
2128 unsigned long payload)
2130 struct iso_context *ctx = container_of(base, struct iso_context, base);
2131 struct descriptor *d, *last, *pd;
2132 struct fw_iso_packet *p;
2134 dma_addr_t d_bus, page_bus;
2135 u32 z, header_z, payload_z, irq;
2136 u32 payload_index, payload_end_index, next_page_index;
2137 int page, end_page, i, length, offset;
2140 * FIXME: Cycle lost behavior should be configurable: lose
2141 * packet, retransmit or terminate..
2145 payload_index = payload;
2151 if (p->header_length > 0)
2154 /* Determine the first page the payload isn't contained in. */
2155 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2156 if (p->payload_length > 0)
2157 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2163 /* Get header size in number of descriptors. */
2164 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2166 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2171 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2172 d[0].req_count = cpu_to_le16(8);
2174 header = (__le32 *) &d[1];
2175 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2176 IT_HEADER_TAG(p->tag) |
2177 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2178 IT_HEADER_CHANNEL(ctx->base.channel) |
2179 IT_HEADER_SPEED(ctx->base.speed));
2181 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2182 p->payload_length));
2185 if (p->header_length > 0) {
2186 d[2].req_count = cpu_to_le16(p->header_length);
2187 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2188 memcpy(&d[z], p->header, p->header_length);
2191 pd = d + z - payload_z;
2192 payload_end_index = payload_index + p->payload_length;
2193 for (i = 0; i < payload_z; i++) {
2194 page = payload_index >> PAGE_SHIFT;
2195 offset = payload_index & ~PAGE_MASK;
2196 next_page_index = (page + 1) << PAGE_SHIFT;
2198 min(next_page_index, payload_end_index) - payload_index;
2199 pd[i].req_count = cpu_to_le16(length);
2201 page_bus = page_private(buffer->pages[page]);
2202 pd[i].data_address = cpu_to_le32(page_bus + offset);
2204 payload_index += length;
2208 irq = DESCRIPTOR_IRQ_ALWAYS;
2210 irq = DESCRIPTOR_NO_IRQ;
2212 last = z == 2 ? d : d + z - 1;
2213 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2215 DESCRIPTOR_BRANCH_ALWAYS |
2218 context_append(&ctx->context, d, z, header_z);
2223 static int ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
2224 struct fw_iso_packet *packet,
2225 struct fw_iso_buffer *buffer,
2226 unsigned long payload)
2228 struct iso_context *ctx = container_of(base, struct iso_context, base);
2229 struct db_descriptor *db = NULL;
2230 struct descriptor *d;
2231 struct fw_iso_packet *p;
2232 dma_addr_t d_bus, page_bus;
2233 u32 z, header_z, length, rest;
2234 int page, offset, packet_count, header_size;
2237 * FIXME: Cycle lost behavior should be configurable: lose
2238 * packet, retransmit or terminate..
2245 * The OHCI controller puts the isochronous header and trailer in the
2246 * buffer, so we need at least 8 bytes.
2248 packet_count = p->header_length / ctx->base.header_size;
2249 header_size = packet_count * max(ctx->base.header_size, (size_t)8);
2251 /* Get header size in number of descriptors. */
2252 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2253 page = payload >> PAGE_SHIFT;
2254 offset = payload & ~PAGE_MASK;
2255 rest = p->payload_length;
2257 * The controllers I've tested have not worked correctly when
2258 * second_req_count is zero. Rather than do something we know won't
2259 * work, return an error
2265 d = context_get_descriptors(&ctx->context,
2266 z + header_z, &d_bus);
2270 db = (struct db_descriptor *) d;
2271 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
2272 DESCRIPTOR_BRANCH_ALWAYS);
2274 cpu_to_le16(max(ctx->base.header_size, (size_t)8));
2275 if (p->skip && rest == p->payload_length) {
2276 db->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2277 db->first_req_count = db->first_size;
2279 db->first_req_count = cpu_to_le16(header_size);
2281 db->first_res_count = db->first_req_count;
2282 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
2284 if (p->skip && rest == p->payload_length)
2286 else if (offset + rest < PAGE_SIZE)
2289 length = PAGE_SIZE - offset;
2291 db->second_req_count = cpu_to_le16(length);
2292 db->second_res_count = db->second_req_count;
2293 page_bus = page_private(buffer->pages[page]);
2294 db->second_buffer = cpu_to_le32(page_bus + offset);
2296 if (p->interrupt && length == rest)
2297 db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2299 context_append(&ctx->context, d, z, header_z);
2300 offset = (offset + length) & ~PAGE_MASK;
2309 static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2310 struct fw_iso_packet *packet,
2311 struct fw_iso_buffer *buffer,
2312 unsigned long payload)
2314 struct iso_context *ctx = container_of(base, struct iso_context, base);
2315 struct descriptor *d, *pd;
2316 struct fw_iso_packet *p = packet;
2317 dma_addr_t d_bus, page_bus;
2318 u32 z, header_z, rest;
2320 int page, offset, packet_count, header_size, payload_per_buffer;
2323 * The OHCI controller puts the isochronous header and trailer in the
2324 * buffer, so we need at least 8 bytes.
2326 packet_count = p->header_length / ctx->base.header_size;
2327 header_size = max(ctx->base.header_size, (size_t)8);
2329 /* Get header size in number of descriptors. */
2330 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2331 page = payload >> PAGE_SHIFT;
2332 offset = payload & ~PAGE_MASK;
2333 payload_per_buffer = p->payload_length / packet_count;
2335 for (i = 0; i < packet_count; i++) {
2336 /* d points to the header descriptor */
2337 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2338 d = context_get_descriptors(&ctx->context,
2339 z + header_z, &d_bus);
2343 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2344 DESCRIPTOR_INPUT_MORE);
2345 if (p->skip && i == 0)
2346 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2347 d->req_count = cpu_to_le16(header_size);
2348 d->res_count = d->req_count;
2349 d->transfer_status = 0;
2350 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2352 rest = payload_per_buffer;
2354 for (j = 1; j < z; j++) {
2356 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2357 DESCRIPTOR_INPUT_MORE);
2359 if (offset + rest < PAGE_SIZE)
2362 length = PAGE_SIZE - offset;
2363 pd->req_count = cpu_to_le16(length);
2364 pd->res_count = pd->req_count;
2365 pd->transfer_status = 0;
2367 page_bus = page_private(buffer->pages[page]);
2368 pd->data_address = cpu_to_le32(page_bus + offset);
2370 offset = (offset + length) & ~PAGE_MASK;
2375 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2376 DESCRIPTOR_INPUT_LAST |
2377 DESCRIPTOR_BRANCH_ALWAYS);
2378 if (p->interrupt && i == packet_count - 1)
2379 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2381 context_append(&ctx->context, d, z, header_z);
2387 static int ohci_queue_iso(struct fw_iso_context *base,
2388 struct fw_iso_packet *packet,
2389 struct fw_iso_buffer *buffer,
2390 unsigned long payload)
2392 struct iso_context *ctx = container_of(base, struct iso_context, base);
2393 unsigned long flags;
2396 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2397 if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2398 ret = ohci_queue_iso_transmit(base, packet, buffer, payload);
2399 else if (ctx->context.ohci->use_dualbuffer)
2400 ret = ohci_queue_iso_receive_dualbuffer(base, packet,
2403 ret = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2405 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2410 static const struct fw_card_driver ohci_driver = {
2411 .enable = ohci_enable,
2412 .update_phy_reg = ohci_update_phy_reg,
2413 .set_config_rom = ohci_set_config_rom,
2414 .send_request = ohci_send_request,
2415 .send_response = ohci_send_response,
2416 .cancel_packet = ohci_cancel_packet,
2417 .enable_phys_dma = ohci_enable_phys_dma,
2418 .get_cycle_time = ohci_get_cycle_time,
2420 .allocate_iso_context = ohci_allocate_iso_context,
2421 .free_iso_context = ohci_free_iso_context,
2422 .queue_iso = ohci_queue_iso,
2423 .start_iso = ohci_start_iso,
2424 .stop_iso = ohci_stop_iso,
2427 #ifdef CONFIG_PPC_PMAC
2428 static void ohci_pmac_on(struct pci_dev *dev)
2430 if (machine_is(powermac)) {
2431 struct device_node *ofn = pci_device_to_OF_node(dev);
2434 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2435 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2440 static void ohci_pmac_off(struct pci_dev *dev)
2442 if (machine_is(powermac)) {
2443 struct device_node *ofn = pci_device_to_OF_node(dev);
2446 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2447 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2452 #define ohci_pmac_on(dev)
2453 #define ohci_pmac_off(dev)
2454 #endif /* CONFIG_PPC_PMAC */
2456 #define PCI_VENDOR_ID_AGERE PCI_VENDOR_ID_ATT
2457 #define PCI_DEVICE_ID_AGERE_FW643 0x5901
2459 static int __devinit pci_probe(struct pci_dev *dev,
2460 const struct pci_device_id *ent)
2462 struct fw_ohci *ohci;
2463 u32 bus_options, max_receive, link_speed, version;
2468 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2474 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2478 err = pci_enable_device(dev);
2480 fw_error("Failed to enable OHCI hardware\n");
2484 pci_set_master(dev);
2485 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2486 pci_set_drvdata(dev, ohci);
2488 spin_lock_init(&ohci->lock);
2490 tasklet_init(&ohci->bus_reset_tasklet,
2491 bus_reset_tasklet, (unsigned long)ohci);
2493 err = pci_request_region(dev, 0, ohci_driver_name);
2495 fw_error("MMIO resource unavailable\n");
2499 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2500 if (ohci->registers == NULL) {
2501 fw_error("Failed to remap registers\n");
2506 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2508 /* FIXME: make it a context option or remove dual-buffer mode */
2509 ohci->use_dualbuffer = version >= OHCI_VERSION_1_1;
2512 /* dual-buffer mode is broken if more than one IR context is active */
2513 if (dev->vendor == PCI_VENDOR_ID_AGERE &&
2514 dev->device == PCI_DEVICE_ID_AGERE_FW643)
2515 ohci->use_dualbuffer = false;
2517 /* dual-buffer mode is broken */
2518 if (dev->vendor == PCI_VENDOR_ID_RICOH &&
2519 dev->device == PCI_DEVICE_ID_RICOH_R5C832)
2520 ohci->use_dualbuffer = false;
2522 /* x86-32 currently doesn't use highmem for dma_alloc_coherent */
2523 #if !defined(CONFIG_X86_32)
2524 /* dual-buffer mode is broken with descriptor addresses above 2G */
2525 if (dev->vendor == PCI_VENDOR_ID_TI &&
2526 dev->device == PCI_DEVICE_ID_TI_TSB43AB22)
2527 ohci->use_dualbuffer = false;
2530 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
2531 ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE &&
2532 dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW;
2534 ohci->bus_reset_packet_quirk = dev->vendor == PCI_VENDOR_ID_TI;
2536 ohci->iso_cycle_timer_quirk = dev->vendor == PCI_VENDOR_ID_AL ||
2537 dev->vendor == PCI_VENDOR_ID_NEC ||
2538 dev->vendor == PCI_VENDOR_ID_VIA;
2540 ar_context_init(&ohci->ar_request_ctx, ohci,
2541 OHCI1394_AsReqRcvContextControlSet);
2543 ar_context_init(&ohci->ar_response_ctx, ohci,
2544 OHCI1394_AsRspRcvContextControlSet);
2546 context_init(&ohci->at_request_ctx, ohci,
2547 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2549 context_init(&ohci->at_response_ctx, ohci,
2550 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2552 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2553 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2554 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2555 size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
2556 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2558 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2559 ohci->ir_context_channels = ~0ULL;
2560 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2561 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2562 size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
2563 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2565 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2570 /* self-id dma buffer allocation */
2571 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2575 if (ohci->self_id_cpu == NULL) {
2580 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2581 max_receive = (bus_options >> 12) & 0xf;
2582 link_speed = bus_options & 0x7;
2583 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2584 reg_read(ohci, OHCI1394_GUIDLo);
2586 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2590 fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
2591 dev_name(&dev->dev), version >> 16, version & 0xff);
2596 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2597 ohci->self_id_cpu, ohci->self_id_bus);
2599 kfree(ohci->ir_context_list);
2600 kfree(ohci->it_context_list);
2601 context_release(&ohci->at_response_ctx);
2602 context_release(&ohci->at_request_ctx);
2603 ar_context_release(&ohci->ar_response_ctx);
2604 ar_context_release(&ohci->ar_request_ctx);
2605 pci_iounmap(dev, ohci->registers);
2607 pci_release_region(dev, 0);
2609 pci_disable_device(dev);
2615 fw_error("Out of memory\n");
2620 static void pci_remove(struct pci_dev *dev)
2622 struct fw_ohci *ohci;
2624 ohci = pci_get_drvdata(dev);
2625 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2627 fw_core_remove_card(&ohci->card);
2630 * FIXME: Fail all pending packets here, now that the upper
2631 * layers can't queue any more.
2634 software_reset(ohci);
2635 free_irq(dev->irq, ohci);
2637 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
2638 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2639 ohci->next_config_rom, ohci->next_config_rom_bus);
2640 if (ohci->config_rom)
2641 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2642 ohci->config_rom, ohci->config_rom_bus);
2643 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2644 ohci->self_id_cpu, ohci->self_id_bus);
2645 ar_context_release(&ohci->ar_request_ctx);
2646 ar_context_release(&ohci->ar_response_ctx);
2647 context_release(&ohci->at_request_ctx);
2648 context_release(&ohci->at_response_ctx);
2649 kfree(ohci->it_context_list);
2650 kfree(ohci->ir_context_list);
2651 pci_iounmap(dev, ohci->registers);
2652 pci_release_region(dev, 0);
2653 pci_disable_device(dev);
2657 fw_notify("Removed fw-ohci device.\n");
2661 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2663 struct fw_ohci *ohci = pci_get_drvdata(dev);
2666 software_reset(ohci);
2667 free_irq(dev->irq, ohci);
2668 err = pci_save_state(dev);
2670 fw_error("pci_save_state failed\n");
2673 err = pci_set_power_state(dev, pci_choose_state(dev, state));
2675 fw_error("pci_set_power_state failed with %d\n", err);
2681 static int pci_resume(struct pci_dev *dev)
2683 struct fw_ohci *ohci = pci_get_drvdata(dev);
2687 pci_set_power_state(dev, PCI_D0);
2688 pci_restore_state(dev);
2689 err = pci_enable_device(dev);
2691 fw_error("pci_enable_device failed\n");
2695 return ohci_enable(&ohci->card, NULL, 0);
2699 static const struct pci_device_id pci_table[] = {
2700 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2704 MODULE_DEVICE_TABLE(pci, pci_table);
2706 static struct pci_driver fw_ohci_pci_driver = {
2707 .name = ohci_driver_name,
2708 .id_table = pci_table,
2710 .remove = pci_remove,
2712 .resume = pci_resume,
2713 .suspend = pci_suspend,
2717 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2718 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2719 MODULE_LICENSE("GPL");
2721 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2722 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2723 MODULE_ALIAS("ohci1394");
2726 static int __init fw_ohci_init(void)
2728 return pci_register_driver(&fw_ohci_pci_driver);
2731 static void __exit fw_ohci_cleanup(void)
2733 pci_unregister_driver(&fw_ohci_pci_driver);
2736 module_init(fw_ohci_init);
2737 module_exit(fw_ohci_cleanup);