drivers/firewire/ohci.c

   1 /*
   2  * Driver for OHCI 1394 controllers
   3  *
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/bitops.h>
  22 #include <linux/bug.h>
  23 #include <linux/compiler.h>
  24 #include <linux/delay.h>
  25 #include <linux/device.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/firewire.h>
  28 #include <linux/firewire-constants.h>
  29 #include <linux/init.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/io.h>
  32 #include <linux/kernel.h>
  33 #include <linux/list.h>
  34 #include <linux/mm.h>
  35 #include <linux/module.h>
  36 #include <linux/moduleparam.h>
  37 #include <linux/mutex.h>
  38 #include <linux/pci.h>
  39 #include <linux/pci_ids.h>
  40 #include <linux/slab.h>
  41 #include <linux/spinlock.h>
  42 #include <linux/string.h>
  43 #include <linux/time.h>
  44 #include <linux/vmalloc.h>
  45 #include <linux/workqueue.h>
  46
  47 #include <asm/byteorder.h>
  48 #include <asm/page.h>
  49
  50 #ifdef CONFIG_PPC_PMAC
  51 #include <asm/pmac_feature.h>
  52 #endif
  53
  54 #include "core.h"
  55 #include "ohci.h"
  56
  57 #define DESCRIPTOR_OUTPUT_MORE          0
  58 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  59 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
  60 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
  61 #define DESCRIPTOR_STATUS               (1 << 11)
  62 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  63 #define DESCRIPTOR_PING                 (1 << 7)
  64 #define DESCRIPTOR_YY                   (1 << 6)
  65 #define DESCRIPTOR_NO_IRQ               (0 << 4)
  66 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  67 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  68 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  69 #define DESCRIPTOR_WAIT                 (3 << 0)
  70
  71 struct descriptor {
  72         __le16 req_count;
  73         __le16 control;
  74         __le32 data_address;
  75         __le32 branch_address;
  76         __le16 res_count;
  77         __le16 transfer_status;
  78 } __attribute__((aligned(16)));
  79
  80 #define CONTROL_SET(regs)       (regs)
  81 #define CONTROL_CLEAR(regs)     ((regs) + 4)
  82 #define COMMAND_PTR(regs)       ((regs) + 12)
  83 #define CONTEXT_MATCH(regs)     ((regs) + 16)
  84
  85 #define AR_BUFFER_SIZE  (32*1024)
  86 #define AR_BUFFERS_MIN  DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
  87 /* we need at least two pages for proper list management */
  88 #define AR_BUFFERS      (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
  89
  90 #define MAX_ASYNC_PAYLOAD       4096
  91 #define MAX_AR_PACKET_SIZE      (16 + MAX_ASYNC_PAYLOAD + 4)
  92 #define AR_WRAPAROUND_PAGES     DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
  93
  94 struct ar_context {
  95         struct fw_ohci *ohci;
  96         struct page *pages[AR_BUFFERS];
  97         void *buffer;
  98         struct descriptor *descriptors;
  99         dma_addr_t descriptors_bus;
 100         void *pointer;
 101         unsigned int last_buffer_index;
 102         u32 regs;
 103         struct tasklet_struct tasklet;
 104 };
 105
 106 struct context;
 107
 108 typedef int (*descriptor_callback_t)(struct context *ctx,
 109                                      struct descriptor *d,
 110                                      struct descriptor *last);
 111
 112 /*
 113  * A buffer that contains a block of DMA-able coherent memory used for
 114  * storing a portion of a DMA descriptor program.
 115  */
 116 struct descriptor_buffer {
 117         struct list_head list;
 118         dma_addr_t buffer_bus;
 119         size_t buffer_size;
 120         size_t used;
 121         struct descriptor buffer[0];
 122 };
 123
 124 struct context {
 125         struct fw_ohci *ohci;
 126         u32 regs;
 127         int total_allocation;
 128         u32 current_bus;
 129         bool running;
 130         bool flushing;
 131
 132         /*
 133          * List of page-sized buffers for storing DMA descriptors.
 134          * Head of list contains buffers in use and tail of list contains
 135          * free buffers.
 136          */
 137         struct list_head buffer_list;
 138
 139         /*
 140          * Pointer to a buffer inside buffer_list that contains the tail
 141          * end of the current DMA program.
 142          */
 143         struct descriptor_buffer *buffer_tail;
 144
 145         /*
 146          * The descriptor containing the branch address of the first
 147          * descriptor that has not yet been filled by the device.
 148          */
 149         struct descriptor *last;
 150
 151         /*
 152          * The last descriptor in the DMA program.  It contains the branch
 153          * address that must be updated upon appending a new descriptor.
 154          */
 155         struct descriptor *prev;
 156
 157         descriptor_callback_t callback;
 158
 159         struct tasklet_struct tasklet;
 160 };
 161
 162 #define IT_HEADER_SY(v)          ((v) <<  0)
 163 #define IT_HEADER_TCODE(v)       ((v) <<  4)
 164 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 165 #define IT_HEADER_TAG(v)         ((v) << 14)
 166 #define IT_HEADER_SPEED(v)       ((v) << 16)
 167 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 168
 169 struct iso_context {
 170         struct fw_iso_context base;
 171         struct context context;
 172         void *header;
 173         size_t header_length;
 174         unsigned long flushing_completions;
 175         u32 mc_buffer_bus;
 176         u16 mc_completed;
 177         u16 last_timestamp;
 178         u8 sync;
 179         u8 tags;
 180 };
 181
 182 #define CONFIG_ROM_SIZE 1024
 183
 184 struct fw_ohci {
 185         struct fw_card card;
 186
 187         __iomem char *registers;
 188         int node_id;
 189         int generation;
 190         int request_generation; /* for timestamping incoming requests */
 191         unsigned quirks;
 192         unsigned int pri_req_max;
 193         u32 bus_time;
 194         bool bus_time_running;
 195         bool is_root;
 196         bool csr_state_setclear_abdicate;
 197         int n_ir;
 198         int n_it;
 199         /*
 200          * Spinlock for accessing fw_ohci data.  Never call out of
 201          * this driver with this lock held.
 202          */
 203         spinlock_t lock;
 204
 205         struct mutex phy_reg_mutex;
 206
 207         void *misc_buffer;
 208         dma_addr_t misc_buffer_bus;
 209
 210         struct ar_context ar_request_ctx;
 211         struct ar_context ar_response_ctx;
 212         struct context at_request_ctx;
 213         struct context at_response_ctx;
 214
 215         u32 it_context_support;
 216         u32 it_context_mask;     /* unoccupied IT contexts */
 217         struct iso_context *it_context_list;
 218         u64 ir_context_channels; /* unoccupied channels */
 219         u32 ir_context_support;
 220         u32 ir_context_mask;     /* unoccupied IR contexts */
 221         struct iso_context *ir_context_list;
 222         u64 mc_channels; /* channels in use by the multichannel IR context */
 223         bool mc_allocated;
 224
 225         __be32    *config_rom;
 226         dma_addr_t config_rom_bus;
 227         __be32    *next_config_rom;
 228         dma_addr_t next_config_rom_bus;
 229         __be32     next_header;
 230
 231         __le32    *self_id_cpu;
 232         dma_addr_t self_id_bus;
 233         struct work_struct bus_reset_work;
 234
 235         u32 self_id_buffer[512];
 236 };
 237
 238 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 239 {
 240         return container_of(card, struct fw_ohci, card);
 241 }
 242
 243 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 244 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 245 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 246 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 247 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 248 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 249
 250 #define CONTEXT_RUN     0x8000
 251 #define CONTEXT_WAKE    0x1000
 252 #define CONTEXT_DEAD    0x0800
 253 #define CONTEXT_ACTIVE  0x0400
 254
 255 #define OHCI1394_MAX_AT_REQ_RETRIES     0xf
 256 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 257 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 258
 259 #define OHCI1394_REGISTER_SIZE          0x800
 260 #define OHCI1394_PCI_HCI_Control        0x40
 261 #define SELF_ID_BUF_SIZE                0x800
 262 #define OHCI_TCODE_PHY_PACKET           0x0e
 263 #define OHCI_VERSION_1_1                0x010010
 264
 265 static char ohci_driver_name[] = KBUILD_MODNAME;
 266
 267 #define PCI_DEVICE_ID_AGERE_FW643       0x5901
 268 #define PCI_DEVICE_ID_CREATIVE_SB1394   0x4001
 269 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
 270 #define PCI_DEVICE_ID_TI_TSB12LV22      0x8009
 271 #define PCI_DEVICE_ID_TI_TSB12LV26      0x8020
 272 #define PCI_DEVICE_ID_TI_TSB82AA2       0x8025
 273 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS  0x11bd
 274
 275 #define QUIRK_CYCLE_TIMER               1
 276 #define QUIRK_RESET_PACKET              2
 277 #define QUIRK_BE_HEADERS                4
 278 #define QUIRK_NO_1394A                  8
 279 #define QUIRK_NO_MSI                    16
 280 #define QUIRK_TI_SLLZ059                32
 281
 282 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
 283 static const struct {
 284         unsigned short vendor, device, revision, flags;
 285 } ohci_quirks[] = {
 286         {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
 287                 QUIRK_CYCLE_TIMER},
 288
 289         {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
 290                 QUIRK_BE_HEADERS},
 291
 292         {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
 293                 QUIRK_NO_MSI},
 294
 295         {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID,
 296                 QUIRK_RESET_PACKET},
 297
 298         {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
 299                 QUIRK_NO_MSI},
 300
 301         {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
 302                 QUIRK_CYCLE_TIMER},
 303
 304         {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
 305                 QUIRK_NO_MSI},
 306
 307         {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
 308                 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
 309
 310         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
 311                 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
 312
 313         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
 314                 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
 315
 316         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
 317                 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
 318
 319         {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
 320                 QUIRK_RESET_PACKET},
 321
 322         {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
 323                 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
 324 };
 325
 326 /* This overrides anything that was found in ohci_quirks[]. */
 327 static int param_quirks;
 328 module_param_named(quirks, param_quirks, int, 0644);
 329 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
 330         ", nonatomic cycle timer = "    __stringify(QUIRK_CYCLE_TIMER)
 331         ", reset packet generation = "  __stringify(QUIRK_RESET_PACKET)
 332         ", AR/selfID endianess = "      __stringify(QUIRK_BE_HEADERS)
 333         ", no 1394a enhancements = "    __stringify(QUIRK_NO_1394A)
 334         ", disable MSI = "              __stringify(QUIRK_NO_MSI)
 335         ", TI SLLZ059 erratum = "       __stringify(QUIRK_TI_SLLZ059)
 336         ")");
 337
 338 #define OHCI_PARAM_DEBUG_AT_AR          1
 339 #define OHCI_PARAM_DEBUG_SELFIDS        2
 340 #define OHCI_PARAM_DEBUG_IRQS           4
 341 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
 342
 343 static int param_debug;
 344 module_param_named(debug, param_debug, int, 0644);
 345 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
 346         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
 347         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
 348         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
 349         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
 350         ", or a combination, or all = -1)");
 351
 352 static void log_irqs(struct fw_ohci *ohci, u32 evt)
 353 {
 354         if (likely(!(param_debug &
 355                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
 356                 return;
 357
 358         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
 359             !(evt & OHCI1394_busReset))
 360                 return;
 361
 362         dev_notice(ohci->card.device,
 363             "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
 364             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
 365             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
 366             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
 367             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
 368             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
 369             evt & OHCI1394_isochRx              ? " IR"                 : "",
 370             evt & OHCI1394_isochTx              ? " IT"                 : "",
 371             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
 372             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
 373             evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
 374             evt & OHCI1394_cycleInconsistent    ? " cycleInconsistent"  : "",
 375             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
 376             evt & OHCI1394_unrecoverableError   ? " unrecoverableError" : "",
 377             evt & OHCI1394_busReset             ? " busReset"           : "",
 378             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
 379                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
 380                     OHCI1394_respTxComplete | OHCI1394_isochRx |
 381                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
 382                     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
 383                     OHCI1394_cycleInconsistent |
 384                     OHCI1394_regAccessFail | OHCI1394_busReset)
 385                                                 ? " ?"                  : "");
 386 }
 387
 388 static const char *speed[] = {
 389         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
 390 };
 391 static const char *power[] = {
 392         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
 393         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
 394 };
 395 static const char port[] = { '.', '-', 'p', 'c', };
 396
 397 static char _p(u32 *s, int shift)
 398 {
 399         return port[*s >> shift & 3];
 400 }
 401
 402 static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count)
 403 {
 404         u32 *s;
 405
 406         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
 407                 return;
 408
 409         dev_notice(ohci->card.device,
 410                    "%d selfIDs, generation %d, local node ID %04x\n",
 411                    self_id_count, generation, ohci->node_id);
 412
 413         for (s = ohci->self_id_buffer; self_id_count--; ++s)
 414                 if ((*s & 1 << 23) == 0)
 415                         dev_notice(ohci->card.device,
 416                             "selfID 0: %08x, phy %d [%c%c%c] "
 417                             "%s gc=%d %s %s%s%s\n",
 418                             *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
 419                             speed[*s >> 14 & 3], *s >> 16 & 63,
 420                             power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
 421                             *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
 422                 else
 423                         dev_notice(ohci->card.device,
 424                             "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
 425                             *s, *s >> 24 & 63,
 426                             _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
 427                             _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
 428 }
 429
 430 static const char *evts[] = {
 431         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
 432         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
 433         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
 434         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
 435         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
 436         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
 437         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
 438         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
 439         [0x10] = "-reserved-",          [0x11] = "ack_complete",
 440         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
 441         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
 442         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
 443         [0x18] = "-reserved-",          [0x19] = "-reserved-",
 444         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
 445         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
 446         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
 447         [0x20] = "pending/cancelled",
 448 };
 449 static const char *tcodes[] = {
 450         [0x0] = "QW req",               [0x1] = "BW req",
 451         [0x2] = "W resp",               [0x3] = "-reserved-",
 452         [0x4] = "QR req",               [0x5] = "BR req",
 453         [0x6] = "QR resp",              [0x7] = "BR resp",
 454         [0x8] = "cycle start",          [0x9] = "Lk req",
 455         [0xa] = "async stream packet",  [0xb] = "Lk resp",
 456         [0xc] = "-reserved-",           [0xd] = "-reserved-",
 457         [0xe] = "link internal",        [0xf] = "-reserved-",
 458 };
 459
 460 static void log_ar_at_event(struct fw_ohci *ohci,
 461                             char dir, int speed, u32 *header, int evt)
 462 {
 463         int tcode = header[0] >> 4 & 0xf;
 464         char specific[12];
 465
 466         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
 467                 return;
 468
 469         if (unlikely(evt >= ARRAY_SIZE(evts)))
 470                         evt = 0x1f;
 471
 472         if (evt == OHCI1394_evt_bus_reset) {
 473                 dev_notice(ohci->card.device,
 474                            "A%c evt_bus_reset, generation %d\n",
 475                            dir, (header[2] >> 16) & 0xff);
 476                 return;
 477         }
 478
 479         switch (tcode) {
 480         case 0x0: case 0x6: case 0x8:
 481                 snprintf(specific, sizeof(specific), " = %08x",
 482                          be32_to_cpu((__force __be32)header[3]));
 483                 break;
 484         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
 485                 snprintf(specific, sizeof(specific), " %x,%x",
 486                          header[3] >> 16, header[3] & 0xffff);
 487                 break;
 488         default:
 489                 specific[0] = '\0';
 490         }
 491
 492         switch (tcode) {
 493         case 0xa:
 494                 dev_notice(ohci->card.device,
 495                            "A%c %s, %s\n",
 496                            dir, evts[evt], tcodes[tcode]);
 497                 break;
 498         case 0xe:
 499                 dev_notice(ohci->card.device,
 500                            "A%c %s, PHY %08x %08x\n",
 501                            dir, evts[evt], header[1], header[2]);
 502                 break;
 503         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
 504                 dev_notice(ohci->card.device,
 505                            "A%c spd %x tl %02x, "
 506                            "%04x -> %04x, %s, "
 507                            "%s, %04x%08x%s\n",
 508                            dir, speed, header[0] >> 10 & 0x3f,
 509                            header[1] >> 16, header[0] >> 16, evts[evt],
 510                            tcodes[tcode], header[1] & 0xffff, header[2], specific);
 511                 break;
 512         default:
 513                 dev_notice(ohci->card.device,
 514                            "A%c spd %x tl %02x, "
 515                            "%04x -> %04x, %s, "
 516                            "%s%s\n",
 517                            dir, speed, header[0] >> 10 & 0x3f,
 518                            header[1] >> 16, header[0] >> 16, evts[evt],
 519                            tcodes[tcode], specific);
 520         }
 521 }
 522
 523 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 524 {
 525         writel(data, ohci->registers + offset);
 526 }
 527
 528 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 529 {
 530         return readl(ohci->registers + offset);
 531 }
 532
 533 static inline void flush_writes(const struct fw_ohci *ohci)
 534 {
 535         /* Do a dummy read to flush writes. */
 536         reg_read(ohci, OHCI1394_Version);
 537 }
 538
 539 /*
 540  * Beware!  read_phy_reg(), write_phy_reg(), update_phy_reg(), and
 541  * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
 542  * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
 543  * directly.  Exceptions are intrinsically serialized contexts like pci_probe.
 544  */
 545 static int read_phy_reg(struct fw_ohci *ohci, int addr)
 546 {
 547         u32 val;
 548         int i;
 549
 550         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 551         for (i = 0; i < 3 + 100; i++) {
 552                 val = reg_read(ohci, OHCI1394_PhyControl);
 553                 if (!~val)
 554                         return -ENODEV; /* Card was ejected. */
 555
 556                 if (val & OHCI1394_PhyControl_ReadDone)
 557                         return OHCI1394_PhyControl_ReadData(val);
 558
 559                 /*
 560                  * Try a few times without waiting.  Sleeping is necessary
 561                  * only when the link/PHY interface is busy.
 562                  */
 563                 if (i >= 3)
 564                         msleep(1);
 565         }
 566         dev_err(ohci->card.device, "failed to read phy reg\n");
 567
 568         return -EBUSY;
 569 }
 570
 571 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
 572 {
 573         int i;
 574
 575         reg_write(ohci, OHCI1394_PhyControl,
 576                   OHCI1394_PhyControl_Write(addr, val));
 577         for (i = 0; i < 3 + 100; i++) {
 578                 val = reg_read(ohci, OHCI1394_PhyControl);
 579                 if (!~val)
 580                         return -ENODEV; /* Card was ejected. */
 581
 582                 if (!(val & OHCI1394_PhyControl_WritePending))
 583                         return 0;
 584
 585                 if (i >= 3)
 586                         msleep(1);
 587         }
 588         dev_err(ohci->card.device, "failed to write phy reg\n");
 589
 590         return -EBUSY;
 591 }
 592
 593 static int update_phy_reg(struct fw_ohci *ohci, int addr,
 594                           int clear_bits, int set_bits)
 595 {
 596         int ret = read_phy_reg(ohci, addr);
 597         if (ret < 0)
 598                 return ret;
 599
 600         /*
 601          * The interrupt status bits are cleared by writing a one bit.
 602          * Avoid clearing them unless explicitly requested in set_bits.
 603          */
 604         if (addr == 5)
 605                 clear_bits |= PHY_INT_STATUS_BITS;
 606
 607         return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
 608 }
 609
 610 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
 611 {
 612         int ret;
 613
 614         ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
 615         if (ret < 0)
 616                 return ret;
 617
 618         return read_phy_reg(ohci, addr);
 619 }
 620
 621 static int ohci_read_phy_reg(struct fw_card *card, int addr)
 622 {
 623         struct fw_ohci *ohci = fw_ohci(card);
 624         int ret;
 625
 626         mutex_lock(&ohci->phy_reg_mutex);
 627         ret = read_phy_reg(ohci, addr);
 628         mutex_unlock(&ohci->phy_reg_mutex);
 629
 630         return ret;
 631 }
 632
 633 static int ohci_update_phy_reg(struct fw_card *card, int addr,
 634                                int clear_bits, int set_bits)
 635 {
 636         struct fw_ohci *ohci = fw_ohci(card);
 637         int ret;
 638
 639         mutex_lock(&ohci->phy_reg_mutex);
 640         ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
 641         mutex_unlock(&ohci->phy_reg_mutex);
 642
 643         return ret;
 644 }
 645
 646 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
 647 {
 648         return page_private(ctx->pages[i]);
 649 }
 650
 651 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
 652 {
 653         struct descriptor *d;
 654
 655         d = &ctx->descriptors[index];
 656         d->branch_address  &= cpu_to_le32(~0xf);
 657         d->res_count       =  cpu_to_le16(PAGE_SIZE);
 658         d->transfer_status =  0;
 659
 660         wmb(); /* finish init of new descriptors before branch_address update */
 661         d = &ctx->descriptors[ctx->last_buffer_index];
 662         d->branch_address  |= cpu_to_le32(1);
 663
 664         ctx->last_buffer_index = index;
 665
 666         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 667 }
 668
 669 static void ar_context_release(struct ar_context *ctx)
 670 {
 671         unsigned int i;
 672
 673         if (ctx->buffer)
 674                 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
 675
 676         for (i = 0; i < AR_BUFFERS; i++)
 677                 if (ctx->pages[i]) {
 678                         dma_unmap_page(ctx->ohci->card.device,
 679                                        ar_buffer_bus(ctx, i),
 680                                        PAGE_SIZE, DMA_FROM_DEVICE);
 681                         __free_page(ctx->pages[i]);
 682                 }
 683 }
 684
 685 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
 686 {
 687         struct fw_ohci *ohci = ctx->ohci;
 688
 689         if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
 690                 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
 691                 flush_writes(ohci);
 692
 693                 dev_err(ohci->card.device, "AR error: %s; DMA stopped\n",
 694                         error_msg);
 695         }
 696         /* FIXME: restart? */
 697 }
 698
 699 static inline unsigned int ar_next_buffer_index(unsigned int index)
 700 {
 701         return (index + 1) % AR_BUFFERS;
 702 }
 703
 704 static inline unsigned int ar_prev_buffer_index(unsigned int index)
 705 {
 706         return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
 707 }
 708
 709 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
 710 {
 711         return ar_next_buffer_index(ctx->last_buffer_index);
 712 }
 713
 714 /*
 715  * We search for the buffer that contains the last AR packet DMA data written
 716  * by the controller.
 717  */
 718 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
 719                                                  unsigned int *buffer_offset)
 720 {
 721         unsigned int i, next_i, last = ctx->last_buffer_index;
 722         __le16 res_count, next_res_count;
 723
 724         i = ar_first_buffer_index(ctx);
 725         res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
 726
 727         /* A buffer that is not yet completely filled must be the last one. */
 728         while (i != last && res_count == 0) {
 729
 730                 /* Peek at the next descriptor. */
 731                 next_i = ar_next_buffer_index(i);
 732                 rmb(); /* read descriptors in order */
 733                 next_res_count = ACCESS_ONCE(
 734                                 ctx->descriptors[next_i].res_count);
 735                 /*
 736                  * If the next descriptor is still empty, we must stop at this
 737                  * descriptor.
 738                  */
 739                 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
 740                         /*
 741                          * The exception is when the DMA data for one packet is
 742                          * split over three buffers; in this case, the middle
 743                          * buffer's descriptor might be never updated by the
 744                          * controller and look still empty, and we have to peek
 745                          * at the third one.
 746                          */
 747                         if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
 748                                 next_i = ar_next_buffer_index(next_i);
 749                                 rmb();
 750                                 next_res_count = ACCESS_ONCE(
 751                                         ctx->descriptors[next_i].res_count);
 752                                 if (next_res_count != cpu_to_le16(PAGE_SIZE))
 753                                         goto next_buffer_is_active;
 754                         }
 755
 756                         break;
 757                 }
 758
 759 next_buffer_is_active:
 760                 i = next_i;
 761                 res_count = next_res_count;
 762         }
 763
 764         rmb(); /* read res_count before the DMA data */
 765
 766         *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
 767         if (*buffer_offset > PAGE_SIZE) {
 768                 *buffer_offset = 0;
 769                 ar_context_abort(ctx, "corrupted descriptor");
 770         }
 771
 772         return i;
 773 }
 774
 775 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
 776                                     unsigned int end_buffer_index,
 777                                     unsigned int end_buffer_offset)
 778 {
 779         unsigned int i;
 780
 781         i = ar_first_buffer_index(ctx);
 782         while (i != end_buffer_index) {
 783                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 784                                         ar_buffer_bus(ctx, i),
 785                                         PAGE_SIZE, DMA_FROM_DEVICE);
 786                 i = ar_next_buffer_index(i);
 787         }
 788         if (end_buffer_offset > 0)
 789                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 790                                         ar_buffer_bus(ctx, i),
 791                                         end_buffer_offset, DMA_FROM_DEVICE);
 792 }
 793
 794 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
 795 #define cond_le32_to_cpu(v) \
 796         (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
 797 #else
 798 #define cond_le32_to_cpu(v) le32_to_cpu(v)
 799 #endif
 800
 801 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 802 {
 803         struct fw_ohci *ohci = ctx->ohci;
 804         struct fw_packet p;
 805         u32 status, length, tcode;
 806         int evt;
 807
 808         p.header[0] = cond_le32_to_cpu(buffer[0]);
 809         p.header[1] = cond_le32_to_cpu(buffer[1]);
 810         p.header[2] = cond_le32_to_cpu(buffer[2]);
 811
 812         tcode = (p.header[0] >> 4) & 0x0f;
 813         switch (tcode) {
 814         case TCODE_WRITE_QUADLET_REQUEST:
 815         case TCODE_READ_QUADLET_RESPONSE:
 816                 p.header[3] = (__force __u32) buffer[3];
 817                 p.header_length = 16;
 818                 p.payload_length = 0;
 819                 break;
 820
 821         case TCODE_READ_BLOCK_REQUEST :
 822                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 823                 p.header_length = 16;
 824                 p.payload_length = 0;
 825                 break;
 826
 827         case TCODE_WRITE_BLOCK_REQUEST:
 828         case TCODE_READ_BLOCK_RESPONSE:
 829         case TCODE_LOCK_REQUEST:
 830         case TCODE_LOCK_RESPONSE:
 831                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 832                 p.header_length = 16;
 833                 p.payload_length = p.header[3] >> 16;
 834                 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
 835                         ar_context_abort(ctx, "invalid packet length");
 836                         return NULL;
 837                 }
 838                 break;
 839
 840         case TCODE_WRITE_RESPONSE:
 841         case TCODE_READ_QUADLET_REQUEST:
 842         case OHCI_TCODE_PHY_PACKET:
 843                 p.header_length = 12;
 844                 p.payload_length = 0;
 845                 break;
 846
 847         default:
 848                 ar_context_abort(ctx, "invalid tcode");
 849                 return NULL;
 850         }
 851
 852         p.payload = (void *) buffer + p.header_length;
 853
 854         /* FIXME: What to do about evt_* errors? */
 855         length = (p.header_length + p.payload_length + 3) / 4;
 856         status = cond_le32_to_cpu(buffer[length]);
 857         evt    = (status >> 16) & 0x1f;
 858
 859         p.ack        = evt - 16;
 860         p.speed      = (status >> 21) & 0x7;
 861         p.timestamp  = status & 0xffff;
 862         p.generation = ohci->request_generation;
 863
 864         log_ar_at_event(ohci, 'R', p.speed, p.header, evt);
 865
 866         /*
 867          * Several controllers, notably from NEC and VIA, forget to
 868          * write ack_complete status at PHY packet reception.
 869          */
 870         if (evt == OHCI1394_evt_no_status &&
 871             (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
 872                 p.ack = ACK_COMPLETE;
 873
 874         /*
 875          * The OHCI bus reset handler synthesizes a PHY packet with
 876          * the new generation number when a bus reset happens (see
 877          * section 8.4.2.3).  This helps us determine when a request
 878          * was received and make sure we send the response in the same
 879          * generation.  We only need this for requests; for responses
 880          * we use the unique tlabel for finding the matching
 881          * request.
 882          *
 883          * Alas some chips sometimes emit bus reset packets with a
 884          * wrong generation.  We set the correct generation for these
 885          * at a slightly incorrect time (in bus_reset_work).
 886          */
 887         if (evt == OHCI1394_evt_bus_reset) {
 888                 if (!(ohci->quirks & QUIRK_RESET_PACKET))
 889                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
 890         } else if (ctx == &ohci->ar_request_ctx) {
 891                 fw_core_handle_request(&ohci->card, &p);
 892         } else {
 893                 fw_core_handle_response(&ohci->card, &p);
 894         }
 895
 896         return buffer + length + 1;
 897 }
 898
 899 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
 900 {
 901         void *next;
 902
 903         while (p < end) {
 904                 next = handle_ar_packet(ctx, p);
 905                 if (!next)
 906                         return p;
 907                 p = next;
 908         }
 909
 910         return p;
 911 }
 912
 913 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
 914 {
 915         unsigned int i;
 916
 917         i = ar_first_buffer_index(ctx);
 918         while (i != end_buffer) {
 919                 dma_sync_single_for_device(ctx->ohci->card.device,
 920                                            ar_buffer_bus(ctx, i),
 921                                            PAGE_SIZE, DMA_FROM_DEVICE);
 922                 ar_context_link_page(ctx, i);
 923                 i = ar_next_buffer_index(i);
 924         }
 925 }
 926
 927 static void ar_context_tasklet(unsigned long data)
 928 {
 929         struct ar_context *ctx = (struct ar_context *)data;
 930         unsigned int end_buffer_index, end_buffer_offset;
 931         void *p, *end;
 932
 933         p = ctx->pointer;
 934         if (!p)
 935                 return;
 936
 937         end_buffer_index = ar_search_last_active_buffer(ctx,
 938                                                         &end_buffer_offset);
 939         ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
 940         end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
 941
 942         if (end_buffer_index < ar_first_buffer_index(ctx)) {
 943                 /*
 944                  * The filled part of the overall buffer wraps around; handle
 945                  * all packets up to the buffer end here.  If the last packet
 946                  * wraps around, its tail will be visible after the buffer end
 947                  * because the buffer start pages are mapped there again.
 948                  */
 949                 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
 950                 p = handle_ar_packets(ctx, p, buffer_end);
 951                 if (p < buffer_end)
 952                         goto error;
 953                 /* adjust p to point back into the actual buffer */
 954                 p -= AR_BUFFERS * PAGE_SIZE;
 955         }
 956
 957         p = handle_ar_packets(ctx, p, end);
 958         if (p != end) {
 959                 if (p > end)
 960                         ar_context_abort(ctx, "inconsistent descriptor");
 961                 goto error;
 962         }
 963
 964         ctx->pointer = p;
 965         ar_recycle_buffers(ctx, end_buffer_index);
 966
 967         return;
 968
 969 error:
 970         ctx->pointer = NULL;
 971 }
 972
 973 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
 974                            unsigned int descriptors_offset, u32 regs)
 975 {
 976         unsigned int i;
 977         dma_addr_t dma_addr;
 978         struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
 979         struct descriptor *d;
 980
 981         ctx->regs        = regs;
 982         ctx->ohci        = ohci;
 983         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 984
 985         for (i = 0; i < AR_BUFFERS; i++) {
 986                 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
 987                 if (!ctx->pages[i])
 988                         goto out_of_memory;
 989                 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
 990                                         0, PAGE_SIZE, DMA_FROM_DEVICE);
 991                 if (dma_mapping_error(ohci->card.device, dma_addr)) {
 992                         __free_page(ctx->pages[i]);
 993                         ctx->pages[i] = NULL;
 994                         goto out_of_memory;
 995                 }
 996                 set_page_private(ctx->pages[i], dma_addr);
 997         }
 998
 999         for (i = 0; i < AR_BUFFERS; i++)
1000                 pages[i]              = ctx->pages[i];
1001         for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
1002                 pages[AR_BUFFERS + i] = ctx->pages[i];
1003         ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
1004                                  -1, PAGE_KERNEL);
1005         if (!ctx->buffer)
1006                 goto out_of_memory;
1007
1008         ctx->descriptors     = ohci->misc_buffer     + descriptors_offset;
1009         ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
1010
1011         for (i = 0; i < AR_BUFFERS; i++) {
1012                 d = &ctx->descriptors[i];
1013                 d->req_count      = cpu_to_le16(PAGE_SIZE);
1014                 d->control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
1015                                                 DESCRIPTOR_STATUS |
1016                                                 DESCRIPTOR_BRANCH_ALWAYS);
1017                 d->data_address   = cpu_to_le32(ar_buffer_bus(ctx, i));
1018                 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
1019                         ar_next_buffer_index(i) * sizeof(struct descriptor));
1020         }
1021
1022         return 0;
1023
1024 out_of_memory:
1025         ar_context_release(ctx);
1026
1027         return -ENOMEM;
1028 }
1029
1030 static void ar_context_run(struct ar_context *ctx)
1031 {
1032         unsigned int i;
1033
1034         for (i = 0; i < AR_BUFFERS; i++)
1035                 ar_context_link_page(ctx, i);
1036
1037         ctx->pointer = ctx->buffer;
1038
1039         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1040         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1041 }
1042
1043 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1044 {
1045         __le16 branch;
1046
1047         branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
1048
1049         /* figure out which descriptor the branch address goes in */
1050         if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
1051                 return d;
1052         else
1053                 return d + z - 1;
1054 }
1055
1056 static void context_tasklet(unsigned long data)
1057 {
1058         struct context *ctx = (struct context *) data;
1059         struct descriptor *d, *last;
1060         u32 address;
1061         int z;
1062         struct descriptor_buffer *desc;
1063
1064         desc = list_entry(ctx->buffer_list.next,
1065                         struct descriptor_buffer, list);
1066         last = ctx->last;
1067         while (last->branch_address != 0) {
1068                 struct descriptor_buffer *old_desc = desc;
1069                 address = le32_to_cpu(last->branch_address);
1070                 z = address & 0xf;
1071                 address &= ~0xf;
1072                 ctx->current_bus = address;
1073
1074                 /* If the branch address points to a buffer outside of the
1075                  * current buffer, advance to the next buffer. */
1076                 if (address < desc->buffer_bus ||
1077                                 address >= desc->buffer_bus + desc->used)
1078                         desc = list_entry(desc->list.next,
1079                                         struct descriptor_buffer, list);
1080                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1081                 last = find_branch_descriptor(d, z);
1082
1083                 if (!ctx->callback(ctx, d, last))
1084                         break;
1085
1086                 if (old_desc != desc) {
1087                         /* If we've advanced to the next buffer, move the
1088                          * previous buffer to the free list. */
1089                         unsigned long flags;
1090                         old_desc->used = 0;
1091                         spin_lock_irqsave(&ctx->ohci->lock, flags);
1092                         list_move_tail(&old_desc->list, &ctx->buffer_list);
1093                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1094                 }
1095                 ctx->last = last;
1096         }
1097 }
1098
1099 /*
1100  * Allocate a new buffer and add it to the list of free buffers for this
1101  * context.  Must be called with ohci->lock held.
1102  */
1103 static int context_add_buffer(struct context *ctx)
1104 {
1105         struct descriptor_buffer *desc;
1106         dma_addr_t uninitialized_var(bus_addr);
1107         int offset;
1108
1109         /*
1110          * 16MB of descriptors should be far more than enough for any DMA
1111          * program.  This will catch run-away userspace or DoS attacks.
1112          */
1113         if (ctx->total_allocation >= 16*1024*1024)
1114                 return -ENOMEM;
1115
1116         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1117                         &bus_addr, GFP_ATOMIC);
1118         if (!desc)
1119                 return -ENOMEM;
1120
1121         offset = (void *)&desc->buffer - (void *)desc;
1122         desc->buffer_size = PAGE_SIZE - offset;
1123         desc->buffer_bus = bus_addr + offset;
1124         desc->used = 0;
1125
1126         list_add_tail(&desc->list, &ctx->buffer_list);
1127         ctx->total_allocation += PAGE_SIZE;
1128
1129         return 0;
1130 }
1131
1132 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1133                         u32 regs, descriptor_callback_t callback)
1134 {
1135         ctx->ohci = ohci;
1136         ctx->regs = regs;
1137         ctx->total_allocation = 0;
1138
1139         INIT_LIST_HEAD(&ctx->buffer_list);
1140         if (context_add_buffer(ctx) < 0)
1141                 return -ENOMEM;
1142
1143         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1144                         struct descriptor_buffer, list);
1145
1146         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1147         ctx->callback = callback;
1148
1149         /*
1150          * We put a dummy descriptor in the buffer that has a NULL
1151          * branch address and looks like it's been sent.  That way we
1152          * have a descriptor to append DMA programs to.
1153          */
1154         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1155         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1156         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1157         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1158         ctx->last = ctx->buffer_tail->buffer;
1159         ctx->prev = ctx->buffer_tail->buffer;
1160
1161         return 0;
1162 }
1163
1164 static void context_release(struct context *ctx)
1165 {
1166         struct fw_card *card = &ctx->ohci->card;
1167         struct descriptor_buffer *desc, *tmp;
1168
1169         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1170                 dma_free_coherent(card->device, PAGE_SIZE, desc,
1171                         desc->buffer_bus -
1172                         ((void *)&desc->buffer - (void *)desc));
1173 }
1174
1175 /* Must be called with ohci->lock held */
1176 static struct descriptor *context_get_descriptors(struct context *ctx,
1177                                                   int z, dma_addr_t *d_bus)
1178 {
1179         struct descriptor *d = NULL;
1180         struct descriptor_buffer *desc = ctx->buffer_tail;
1181
1182         if (z * sizeof(*d) > desc->buffer_size)
1183                 return NULL;
1184
1185         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1186                 /* No room for the descriptor in this buffer, so advance to the
1187                  * next one. */
1188
1189                 if (desc->list.next == &ctx->buffer_list) {
1190                         /* If there is no free buffer next in the list,
1191                          * allocate one. */
1192                         if (context_add_buffer(ctx) < 0)
1193                                 return NULL;
1194                 }
1195                 desc = list_entry(desc->list.next,
1196                                 struct descriptor_buffer, list);
1197                 ctx->buffer_tail = desc;
1198         }
1199
1200         d = desc->buffer + desc->used / sizeof(*d);
1201         memset(d, 0, z * sizeof(*d));
1202         *d_bus = desc->buffer_bus + desc->used;
1203
1204         return d;
1205 }
1206
1207 static void context_run(struct context *ctx, u32 extra)
1208 {
1209         struct fw_ohci *ohci = ctx->ohci;
1210
1211         reg_write(ohci, COMMAND_PTR(ctx->regs),
1212                   le32_to_cpu(ctx->last->branch_address));
1213         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1214         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1215         ctx->running = true;
1216         flush_writes(ohci);
1217 }
1218
1219 static void context_append(struct context *ctx,
1220                            struct descriptor *d, int z, int extra)
1221 {
1222         dma_addr_t d_bus;
1223         struct descriptor_buffer *desc = ctx->buffer_tail;
1224
1225         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1226
1227         desc->used += (z + extra) * sizeof(*d);
1228
1229         wmb(); /* finish init of new descriptors before branch_address update */
1230         ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1231         ctx->prev = find_branch_descriptor(d, z);
1232 }
1233
1234 static void context_stop(struct context *ctx)
1235 {
1236         struct fw_ohci *ohci = ctx->ohci;
1237         u32 reg;
1238         int i;
1239
1240         reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1241         ctx->running = false;
1242
1243         for (i = 0; i < 1000; i++) {
1244                 reg = reg_read(ohci, CONTROL_SET(ctx->regs));
1245                 if ((reg & CONTEXT_ACTIVE) == 0)
1246                         return;
1247
1248                 if (i)
1249                         udelay(10);
1250         }
1251         dev_err(ohci->card.device, "DMA context still active (0x%08x)\n", reg);
1252 }
1253
1254 struct driver_data {
1255         u8 inline_data[8];
1256         struct fw_packet *packet;
1257 };
1258
1259 /*
1260  * This function apppends a packet to the DMA queue for transmission.
1261  * Must always be called with the ochi->lock held to ensure proper
1262  * generation handling and locking around packet queue manipulation.
1263  */
1264 static int at_context_queue_packet(struct context *ctx,
1265                                    struct fw_packet *packet)
1266 {
1267         struct fw_ohci *ohci = ctx->ohci;
1268         dma_addr_t d_bus, uninitialized_var(payload_bus);
1269         struct driver_data *driver_data;
1270         struct descriptor *d, *last;
1271         __le32 *header;
1272         int z, tcode;
1273
1274         d = context_get_descriptors(ctx, 4, &d_bus);
1275         if (d == NULL) {
1276                 packet->ack = RCODE_SEND_ERROR;
1277                 return -1;
1278         }
1279
1280         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1281         d[0].res_count = cpu_to_le16(packet->timestamp);
1282
1283         /*
1284          * The DMA format for asyncronous link packets is different
1285          * from the IEEE1394 layout, so shift the fields around
1286          * accordingly.
1287          */
1288
1289         tcode = (packet->header[0] >> 4) & 0x0f;
1290         header = (__le32 *) &d[1];
1291         switch (tcode) {
1292         case TCODE_WRITE_QUADLET_REQUEST:
1293         case TCODE_WRITE_BLOCK_REQUEST:
1294         case TCODE_WRITE_RESPONSE:
1295         case TCODE_READ_QUADLET_REQUEST:
1296         case TCODE_READ_BLOCK_REQUEST:
1297         case TCODE_READ_QUADLET_RESPONSE:
1298         case TCODE_READ_BLOCK_RESPONSE:
1299         case TCODE_LOCK_REQUEST:
1300         case TCODE_LOCK_RESPONSE:
1301                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1302                                         (packet->speed << 16));
1303                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1304                                         (packet->header[0] & 0xffff0000));
1305                 header[2] = cpu_to_le32(packet->header[2]);
1306
1307                 if (TCODE_IS_BLOCK_PACKET(tcode))
1308                         header[3] = cpu_to_le32(packet->header[3]);
1309                 else
1310                         header[3] = (__force __le32) packet->header[3];
1311
1312                 d[0].req_count = cpu_to_le16(packet->header_length);
1313                 break;
1314
1315         case TCODE_LINK_INTERNAL:
1316                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1317                                         (packet->speed << 16));
1318                 header[1] = cpu_to_le32(packet->header[1]);
1319                 header[2] = cpu_to_le32(packet->header[2]);
1320                 d[0].req_count = cpu_to_le16(12);
1321
1322                 if (is_ping_packet(&packet->header[1]))
1323                         d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1324                 break;
1325
1326         case TCODE_STREAM_DATA:
1327                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1328                                         (packet->speed << 16));
1329                 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1330                 d[0].req_count = cpu_to_le16(8);
1331                 break;
1332
1333         default:
1334                 /* BUG(); */
1335                 packet->ack = RCODE_SEND_ERROR;
1336                 return -1;
1337         }
1338
1339         BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
1340         driver_data = (struct driver_data *) &d[3];
1341         driver_data->packet = packet;
1342         packet->driver_data = driver_data;
1343
1344         if (packet->payload_length > 0) {
1345                 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1346                         payload_bus = dma_map_single(ohci->card.device,
1347                                                      packet->payload,
1348                                                      packet->payload_length,
1349                                                      DMA_TO_DEVICE);
1350                         if (dma_mapping_error(ohci->card.device, payload_bus)) {
1351                                 packet->ack = RCODE_SEND_ERROR;
1352                                 return -1;
1353                         }
1354                         packet->payload_bus     = payload_bus;
1355                         packet->payload_mapped  = true;
1356                 } else {
1357                         memcpy(driver_data->inline_data, packet->payload,
1358                                packet->payload_length);
1359                         payload_bus = d_bus + 3 * sizeof(*d);
1360                 }
1361
1362                 d[2].req_count    = cpu_to_le16(packet->payload_length);
1363                 d[2].data_address = cpu_to_le32(payload_bus);
1364                 last = &d[2];
1365                 z = 3;
1366         } else {
1367                 last = &d[0];
1368                 z = 2;
1369         }
1370
1371         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1372                                      DESCRIPTOR_IRQ_ALWAYS |
1373                                      DESCRIPTOR_BRANCH_ALWAYS);
1374
1375         /* FIXME: Document how the locking works. */
1376         if (ohci->generation != packet->generation) {
1377                 if (packet->payload_mapped)
1378                         dma_unmap_single(ohci->card.device, payload_bus,
1379                                          packet->payload_length, DMA_TO_DEVICE);
1380                 packet->ack = RCODE_GENERATION;
1381                 return -1;
1382         }
1383
1384         context_append(ctx, d, z, 4 - z);
1385
1386         if (ctx->running)
1387                 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1388         else
1389                 context_run(ctx, 0);
1390
1391         return 0;
1392 }
1393
1394 static void at_context_flush(struct context *ctx)
1395 {
1396         tasklet_disable(&ctx->tasklet);
1397
1398         ctx->flushing = true;
1399         context_tasklet((unsigned long)ctx);
1400         ctx->flushing = false;
1401
1402         tasklet_enable(&ctx->tasklet);
1403 }
1404
1405 static int handle_at_packet(struct context *context,
1406                             struct descriptor *d,
1407                             struct descriptor *last)
1408 {
1409         struct driver_data *driver_data;
1410         struct fw_packet *packet;
1411         struct fw_ohci *ohci = context->ohci;
1412         int evt;
1413
1414         if (last->transfer_status == 0 && !context->flushing)
1415                 /* This descriptor isn't done yet, stop iteration. */
1416                 return 0;
1417
1418         driver_data = (struct driver_data *) &d[3];
1419         packet = driver_data->packet;
1420         if (packet == NULL)
1421                 /* This packet was cancelled, just continue. */
1422                 return 1;
1423
1424         if (packet->payload_mapped)
1425                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1426                                  packet->payload_length, DMA_TO_DEVICE);
1427
1428         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1429         packet->timestamp = le16_to_cpu(last->res_count);
1430
1431         log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt);
1432
1433         switch (evt) {
1434         case OHCI1394_evt_timeout:
1435                 /* Async response transmit timed out. */
1436                 packet->ack = RCODE_CANCELLED;
1437                 break;
1438
1439         case OHCI1394_evt_flushed:
1440                 /*
1441                  * The packet was flushed should give same error as
1442                  * when we try to use a stale generation count.
1443                  */
1444                 packet->ack = RCODE_GENERATION;
1445                 break;
1446
1447         case OHCI1394_evt_missing_ack:
1448                 if (context->flushing)
1449                         packet->ack = RCODE_GENERATION;
1450                 else {
1451                         /*
1452                          * Using a valid (current) generation count, but the
1453                          * node is not on the bus or not sending acks.
1454                          */
1455                         packet->ack = RCODE_NO_ACK;
1456                 }
1457                 break;
1458
1459         case ACK_COMPLETE + 0x10:
1460         case ACK_PENDING + 0x10:
1461         case ACK_BUSY_X + 0x10:
1462         case ACK_BUSY_A + 0x10:
1463         case ACK_BUSY_B + 0x10:
1464         case ACK_DATA_ERROR + 0x10:
1465         case ACK_TYPE_ERROR + 0x10:
1466                 packet->ack = evt - 0x10;
1467                 break;
1468
1469         case OHCI1394_evt_no_status:
1470                 if (context->flushing) {
1471                         packet->ack = RCODE_GENERATION;
1472                         break;
1473                 }
1474                 /* fall through */
1475
1476         default:
1477                 packet->ack = RCODE_SEND_ERROR;
1478                 break;
1479         }
1480
1481         packet->callback(packet, &ohci->card, packet->ack);
1482
1483         return 1;
1484 }
1485
1486 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1487 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1488 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1489 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1490 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1491
1492 static void handle_local_rom(struct fw_ohci *ohci,
1493                              struct fw_packet *packet, u32 csr)
1494 {
1495         struct fw_packet response;
1496         int tcode, length, i;
1497
1498         tcode = HEADER_GET_TCODE(packet->header[0]);
1499         if (TCODE_IS_BLOCK_PACKET(tcode))
1500                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1501         else
1502                 length = 4;
1503
1504         i = csr - CSR_CONFIG_ROM;
1505         if (i + length > CONFIG_ROM_SIZE) {
1506                 fw_fill_response(&response, packet->header,
1507                                  RCODE_ADDRESS_ERROR, NULL, 0);
1508         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1509                 fw_fill_response(&response, packet->header,
1510                                  RCODE_TYPE_ERROR, NULL, 0);
1511         } else {
1512                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1513                                  (void *) ohci->config_rom + i, length);
1514         }
1515
1516         fw_core_handle_response(&ohci->card, &response);
1517 }
1518
1519 static void handle_local_lock(struct fw_ohci *ohci,
1520                               struct fw_packet *packet, u32 csr)
1521 {
1522         struct fw_packet response;
1523         int tcode, length, ext_tcode, sel, try;
1524         __be32 *payload, lock_old;
1525         u32 lock_arg, lock_data;
1526
1527         tcode = HEADER_GET_TCODE(packet->header[0]);
1528         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1529         payload = packet->payload;
1530         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1531
1532         if (tcode == TCODE_LOCK_REQUEST &&
1533             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1534                 lock_arg = be32_to_cpu(payload[0]);
1535                 lock_data = be32_to_cpu(payload[1]);
1536         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1537                 lock_arg = 0;
1538                 lock_data = 0;
1539         } else {
1540                 fw_fill_response(&response, packet->header,
1541                                  RCODE_TYPE_ERROR, NULL, 0);
1542                 goto out;
1543         }
1544
1545         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1546         reg_write(ohci, OHCI1394_CSRData, lock_data);
1547         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1548         reg_write(ohci, OHCI1394_CSRControl, sel);
1549
1550         for (try = 0; try < 20; try++)
1551                 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1552                         lock_old = cpu_to_be32(reg_read(ohci,
1553                                                         OHCI1394_CSRData));
1554                         fw_fill_response(&response, packet->header,
1555                                          RCODE_COMPLETE,
1556                                          &lock_old, sizeof(lock_old));
1557                         goto out;
1558                 }
1559
1560         dev_err(ohci->card.device, "swap not done (CSR lock timeout)\n");
1561         fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1562
1563  out:
1564         fw_core_handle_response(&ohci->card, &response);
1565 }
1566
1567 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1568 {
1569         u64 offset, csr;
1570
1571         if (ctx == &ctx->ohci->at_request_ctx) {
1572                 packet->ack = ACK_PENDING;
1573                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1574         }
1575
1576         offset =
1577                 ((unsigned long long)
1578                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1579                 packet->header[2];
1580         csr = offset - CSR_REGISTER_BASE;
1581
1582         /* Handle config rom reads. */
1583         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1584                 handle_local_rom(ctx->ohci, packet, csr);
1585         else switch (csr) {
1586         case CSR_BUS_MANAGER_ID:
1587         case CSR_BANDWIDTH_AVAILABLE:
1588         case CSR_CHANNELS_AVAILABLE_HI:
1589         case CSR_CHANNELS_AVAILABLE_LO:
1590                 handle_local_lock(ctx->ohci, packet, csr);
1591                 break;
1592         default:
1593                 if (ctx == &ctx->ohci->at_request_ctx)
1594                         fw_core_handle_request(&ctx->ohci->card, packet);
1595                 else
1596                         fw_core_handle_response(&ctx->ohci->card, packet);
1597                 break;
1598         }
1599
1600         if (ctx == &ctx->ohci->at_response_ctx) {
1601                 packet->ack = ACK_COMPLETE;
1602                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1603         }
1604 }
1605
1606 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1607 {
1608         unsigned long flags;
1609         int ret;
1610
1611         spin_lock_irqsave(&ctx->ohci->lock, flags);
1612
1613         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1614             ctx->ohci->generation == packet->generation) {
1615                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1616                 handle_local_request(ctx, packet);
1617                 return;
1618         }
1619
1620         ret = at_context_queue_packet(ctx, packet);
1621         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1622
1623         if (ret < 0)
1624                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1625
1626 }
1627
1628 static void detect_dead_context(struct fw_ohci *ohci,
1629                                 const char *name, unsigned int regs)
1630 {
1631         u32 ctl;
1632
1633         ctl = reg_read(ohci, CONTROL_SET(regs));
1634         if (ctl & CONTEXT_DEAD)
1635                 dev_err(ohci->card.device,
1636                         "DMA context %s has stopped, error code: %s\n",
1637                         name, evts[ctl & 0x1f]);
1638 }
1639
1640 static void handle_dead_contexts(struct fw_ohci *ohci)
1641 {
1642         unsigned int i;
1643         char name[8];
1644
1645         detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1646         detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1647         detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1648         detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1649         for (i = 0; i < 32; ++i) {
1650                 if (!(ohci->it_context_support & (1 << i)))
1651                         continue;
1652                 sprintf(name, "IT%u", i);
1653                 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1654         }
1655         for (i = 0; i < 32; ++i) {
1656                 if (!(ohci->ir_context_support & (1 << i)))
1657                         continue;
1658                 sprintf(name, "IR%u", i);
1659                 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1660         }
1661         /* TODO: maybe try to flush and restart the dead contexts */
1662 }
1663
1664 static u32 cycle_timer_ticks(u32 cycle_timer)
1665 {
1666         u32 ticks;
1667
1668         ticks = cycle_timer & 0xfff;
1669         ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1670         ticks += (3072 * 8000) * (cycle_timer >> 25);
1671
1672         return ticks;
1673 }
1674
1675 /*
1676  * Some controllers exhibit one or more of the following bugs when updating the
1677  * iso cycle timer register:
1678  *  - When the lowest six bits are wrapping around to zero, a read that happens
1679  *    at the same time will return garbage in the lowest ten bits.
1680  *  - When the cycleOffset field wraps around to zero, the cycleCount field is
1681  *    not incremented for about 60 ns.
1682  *  - Occasionally, the entire register reads zero.
1683  *
1684  * To catch these, we read the register three times and ensure that the
1685  * difference between each two consecutive reads is approximately the same, i.e.
1686  * less than twice the other.  Furthermore, any negative difference indicates an
1687  * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1688  * execute, so we have enough precision to compute the ratio of the differences.)
1689  */
1690 static u32 get_cycle_time(struct fw_ohci *ohci)
1691 {
1692         u32 c0, c1, c2;
1693         u32 t0, t1, t2;
1694         s32 diff01, diff12;
1695         int i;
1696
1697         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1698
1699         if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1700                 i = 0;
1701                 c1 = c2;
1702                 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1703                 do {
1704                         c0 = c1;
1705                         c1 = c2;
1706                         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1707                         t0 = cycle_timer_ticks(c0);
1708                         t1 = cycle_timer_ticks(c1);
1709                         t2 = cycle_timer_ticks(c2);
1710                         diff01 = t1 - t0;
1711                         diff12 = t2 - t1;
1712                 } while ((diff01 <= 0 || diff12 <= 0 ||
1713                           diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1714                          && i++ < 20);
1715         }
1716
1717         return c2;
1718 }
1719
1720 /*
1721  * This function has to be called at least every 64 seconds.  The bus_time
1722  * field stores not only the upper 25 bits of the BUS_TIME register but also
1723  * the most significant bit of the cycle timer in bit 6 so that we can detect
1724  * changes in this bit.
1725  */
1726 static u32 update_bus_time(struct fw_ohci *ohci)
1727 {
1728         u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1729
1730         if (unlikely(!ohci->bus_time_running)) {
1731                 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds);
1732                 ohci->bus_time = (lower_32_bits(get_seconds()) & ~0x7f) |
1733                                  (cycle_time_seconds & 0x40);
1734                 ohci->bus_time_running = true;
1735         }
1736
1737         if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1738                 ohci->bus_time += 0x40;
1739
1740         return ohci->bus_time | cycle_time_seconds;
1741 }
1742
1743 static int get_status_for_port(struct fw_ohci *ohci, int port_index)
1744 {
1745         int reg;
1746
1747         mutex_lock(&ohci->phy_reg_mutex);
1748         reg = write_phy_reg(ohci, 7, port_index);
1749         if (reg >= 0)
1750                 reg = read_phy_reg(ohci, 8);
1751         mutex_unlock(&ohci->phy_reg_mutex);
1752         if (reg < 0)
1753                 return reg;
1754
1755         switch (reg & 0x0f) {
1756         case 0x06:
1757                 return 2;       /* is child node (connected to parent node) */
1758         case 0x0e:
1759                 return 3;       /* is parent node (connected to child node) */
1760         }
1761         return 1;               /* not connected */
1762 }
1763
1764 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
1765         int self_id_count)
1766 {
1767         int i;
1768         u32 entry;
1769
1770         for (i = 0; i < self_id_count; i++) {
1771                 entry = ohci->self_id_buffer[i];
1772                 if ((self_id & 0xff000000) == (entry & 0xff000000))
1773                         return -1;
1774                 if ((self_id & 0xff000000) < (entry & 0xff000000))
1775                         return i;
1776         }
1777         return i;
1778 }
1779
1780 /*
1781  * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
1782  * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
1783  * Construct the selfID from phy register contents.
1784  * FIXME:  How to determine the selfID.i flag?
1785  */
1786 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
1787 {
1788         int reg, i, pos, status;
1789         /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
1790         u32 self_id = 0x8040c800;
1791
1792         reg = reg_read(ohci, OHCI1394_NodeID);
1793         if (!(reg & OHCI1394_NodeID_idValid)) {
1794                 dev_notice(ohci->card.device,
1795                            "node ID not valid, new bus reset in progress\n");
1796                 return -EBUSY;
1797         }
1798         self_id |= ((reg & 0x3f) << 24); /* phy ID */
1799
1800         reg = ohci_read_phy_reg(&ohci->card, 4);
1801         if (reg < 0)
1802                 return reg;
1803         self_id |= ((reg & 0x07) << 8); /* power class */
1804
1805         reg = ohci_read_phy_reg(&ohci->card, 1);
1806         if (reg < 0)
1807                 return reg;
1808         self_id |= ((reg & 0x3f) << 16); /* gap count */
1809
1810         for (i = 0; i < 3; i++) {
1811                 status = get_status_for_port(ohci, i);
1812                 if (status < 0)
1813                         return status;
1814                 self_id |= ((status & 0x3) << (6 - (i * 2)));
1815         }
1816
1817         pos = get_self_id_pos(ohci, self_id, self_id_count);
1818         if (pos >= 0) {
1819                 memmove(&(ohci->self_id_buffer[pos+1]),
1820                         &(ohci->self_id_buffer[pos]),
1821                         (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
1822                 ohci->self_id_buffer[pos] = self_id;
1823                 self_id_count++;
1824         }
1825         return self_id_count;
1826 }
1827
1828 static void bus_reset_work(struct work_struct *work)
1829 {
1830         struct fw_ohci *ohci =
1831                 container_of(work, struct fw_ohci, bus_reset_work);
1832         int self_id_count, generation, new_generation, i, j;
1833         u32 reg;
1834         void *free_rom = NULL;
1835         dma_addr_t free_rom_bus = 0;
1836         bool is_new_root;
1837
1838         reg = reg_read(ohci, OHCI1394_NodeID);
1839         if (!(reg & OHCI1394_NodeID_idValid)) {
1840                 dev_notice(ohci->card.device,
1841                            "node ID not valid, new bus reset in progress\n");
1842                 return;
1843         }
1844         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1845                 dev_notice(ohci->card.device, "malconfigured bus\n");
1846                 return;
1847         }
1848         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1849                                OHCI1394_NodeID_nodeNumber);
1850
1851         is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1852         if (!(ohci->is_root && is_new_root))
1853                 reg_write(ohci, OHCI1394_LinkControlSet,
1854                           OHCI1394_LinkControl_cycleMaster);
1855         ohci->is_root = is_new_root;
1856
1857         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1858         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1859                 dev_notice(ohci->card.device, "inconsistent self IDs\n");
1860                 return;
1861         }
1862         /*
1863          * The count in the SelfIDCount register is the number of
1864          * bytes in the self ID receive buffer.  Since we also receive
1865          * the inverted quadlets and a header quadlet, we shift one
1866          * bit extra to get the actual number of self IDs.
1867          */
1868         self_id_count = (reg >> 3) & 0xff;
1869
1870         if (self_id_count > 252) {
1871                 dev_notice(ohci->card.device, "inconsistent self IDs\n");
1872                 return;
1873         }
1874
1875         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1876         rmb();
1877
1878         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1879                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1880                         /*
1881                          * If the invalid data looks like a cycle start packet,
1882                          * it's likely to be the result of the cycle master
1883                          * having a wrong gap count.  In this case, the self IDs
1884                          * so far are valid and should be processed so that the
1885                          * bus manager can then correct the gap count.
1886                          */
1887                         if (cond_le32_to_cpu(ohci->self_id_cpu[i])
1888                                                         == 0xffff008f) {
1889                                 dev_notice(ohci->card.device,
1890                                            "ignoring spurious self IDs\n");
1891                                 self_id_count = j;
1892                                 break;
1893                         } else {
1894                                 dev_notice(ohci->card.device,
1895                                            "inconsistent self IDs\n");
1896                                 return;
1897                         }
1898                 }
1899                 ohci->self_id_buffer[j] =
1900                                 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1901         }
1902
1903         if (ohci->quirks & QUIRK_TI_SLLZ059) {
1904                 self_id_count = find_and_insert_self_id(ohci, self_id_count);
1905                 if (self_id_count < 0) {
1906                         dev_notice(ohci->card.device,
1907                                    "could not construct local self ID\n");
1908                         return;
1909                 }
1910         }
1911
1912         if (self_id_count == 0) {
1913                 dev_notice(ohci->card.device, "inconsistent self IDs\n");
1914                 return;
1915         }
1916         rmb();
1917
1918         /*
1919          * Check the consistency of the self IDs we just read.  The
1920          * problem we face is that a new bus reset can start while we
1921          * read out the self IDs from the DMA buffer. If this happens,
1922          * the DMA buffer will be overwritten with new self IDs and we
1923          * will read out inconsistent data.  The OHCI specification
1924          * (section 11.2) recommends a technique similar to
1925          * linux/seqlock.h, where we remember the generation of the
1926          * self IDs in the buffer before reading them out and compare
1927          * it to the current generation after reading them out.  If
1928          * the two generations match we know we have a consistent set
1929          * of self IDs.
1930          */
1931
1932         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1933         if (new_generation != generation) {
1934                 dev_notice(ohci->card.device,
1935                            "new bus reset, discarding self ids\n");
1936                 return;
1937         }
1938
1939         /* FIXME: Document how the locking works. */
1940         spin_lock_irq(&ohci->lock);
1941
1942         ohci->generation = -1; /* prevent AT packet queueing */
1943         context_stop(&ohci->at_request_ctx);
1944         context_stop(&ohci->at_response_ctx);
1945
1946         spin_unlock_irq(&ohci->lock);
1947
1948         /*
1949          * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
1950          * packets in the AT queues and software needs to drain them.
1951          * Some OHCI 1.1 controllers (JMicron) apparently require this too.
1952          */
1953         at_context_flush(&ohci->at_request_ctx);
1954         at_context_flush(&ohci->at_response_ctx);
1955
1956         spin_lock_irq(&ohci->lock);
1957
1958         ohci->generation = generation;
1959         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1960
1961         if (ohci->quirks & QUIRK_RESET_PACKET)
1962                 ohci->request_generation = generation;
1963
1964         /*
1965          * This next bit is unrelated to the AT context stuff but we
1966          * have to do it under the spinlock also.  If a new config rom
1967          * was set up before this reset, the old one is now no longer
1968          * in use and we can free it. Update the config rom pointers
1969          * to point to the current config rom and clear the
1970          * next_config_rom pointer so a new update can take place.
1971          */
1972
1973         if (ohci->next_config_rom != NULL) {
1974                 if (ohci->next_config_rom != ohci->config_rom) {
1975                         free_rom      = ohci->config_rom;
1976                         free_rom_bus  = ohci->config_rom_bus;
1977                 }
1978                 ohci->config_rom      = ohci->next_config_rom;
1979                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
1980                 ohci->next_config_rom = NULL;
1981
1982                 /*
1983                  * Restore config_rom image and manually update
1984                  * config_rom registers.  Writing the header quadlet
1985                  * will indicate that the config rom is ready, so we
1986                  * do that last.
1987                  */
1988                 reg_write(ohci, OHCI1394_BusOptions,
1989                           be32_to_cpu(ohci->config_rom[2]));
1990                 ohci->config_rom[0] = ohci->next_header;
1991                 reg_write(ohci, OHCI1394_ConfigROMhdr,
1992                           be32_to_cpu(ohci->next_header));
1993         }
1994
1995 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1996         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1997         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1998 #endif
1999
2000         spin_unlock_irq(&ohci->lock);
2001
2002         if (free_rom)
2003                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2004                                   free_rom, free_rom_bus);
2005
2006         log_selfids(ohci, generation, self_id_count);
2007
2008         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
2009                                  self_id_count, ohci->self_id_buffer,
2010                                  ohci->csr_state_setclear_abdicate);
2011         ohci->csr_state_setclear_abdicate = false;
2012 }
2013
2014 static irqreturn_t irq_handler(int irq, void *data)
2015 {
2016         struct fw_ohci *ohci = data;
2017         u32 event, iso_event;
2018         int i;
2019
2020         event = reg_read(ohci, OHCI1394_IntEventClear);
2021
2022         if (!event || !~event)
2023                 return IRQ_NONE;
2024
2025         /*
2026          * busReset and postedWriteErr must not be cleared yet
2027          * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
2028          */
2029         reg_write(ohci, OHCI1394_IntEventClear,
2030                   event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
2031         log_irqs(ohci, event);
2032
2033         if (event & OHCI1394_selfIDComplete)
2034                 queue_work(fw_workqueue, &ohci->bus_reset_work);
2035
2036         if (event & OHCI1394_RQPkt)
2037                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
2038
2039         if (event & OHCI1394_RSPkt)
2040                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
2041
2042         if (event & OHCI1394_reqTxComplete)
2043                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
2044
2045         if (event & OHCI1394_respTxComplete)
2046                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
2047
2048         if (event & OHCI1394_isochRx) {
2049                 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
2050                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2051
2052                 while (iso_event) {
2053                         i = ffs(iso_event) - 1;
2054                         tasklet_schedule(
2055                                 &ohci->ir_context_list[i].context.tasklet);
2056                         iso_event &= ~(1 << i);
2057                 }
2058         }
2059
2060         if (event & OHCI1394_isochTx) {
2061                 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
2062                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
2063
2064                 while (iso_event) {
2065                         i = ffs(iso_event) - 1;
2066                         tasklet_schedule(
2067                                 &ohci->it_context_list[i].context.tasklet);
2068                         iso_event &= ~(1 << i);
2069                 }
2070         }
2071
2072         if (unlikely(event & OHCI1394_regAccessFail))
2073                 dev_err(ohci->card.device, "register access failure\n");
2074
2075         if (unlikely(event & OHCI1394_postedWriteErr)) {
2076                 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
2077                 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
2078                 reg_write(ohci, OHCI1394_IntEventClear,
2079                           OHCI1394_postedWriteErr);
2080                 if (printk_ratelimit())
2081                         dev_err(ohci->card.device, "PCI posted write error\n");
2082         }
2083
2084         if (unlikely(event & OHCI1394_cycleTooLong)) {
2085                 if (printk_ratelimit())
2086                         dev_notice(ohci->card.device,
2087                                    "isochronous cycle too long\n");
2088                 reg_write(ohci, OHCI1394_LinkControlSet,
2089                           OHCI1394_LinkControl_cycleMaster);
2090         }
2091
2092         if (unlikely(event & OHCI1394_cycleInconsistent)) {
2093                 /*
2094                  * We need to clear this event bit in order to make
2095                  * cycleMatch isochronous I/O work.  In theory we should
2096                  * stop active cycleMatch iso contexts now and restart
2097                  * them at least two cycles later.  (FIXME?)
2098                  */
2099                 if (printk_ratelimit())
2100                         dev_notice(ohci->card.device,
2101                                    "isochronous cycle inconsistent\n");
2102         }
2103
2104         if (unlikely(event & OHCI1394_unrecoverableError))
2105                 handle_dead_contexts(ohci);
2106
2107         if (event & OHCI1394_cycle64Seconds) {
2108                 spin_lock(&ohci->lock);
2109                 update_bus_time(ohci);
2110                 spin_unlock(&ohci->lock);
2111         } else
2112                 flush_writes(ohci);
2113
2114         return IRQ_HANDLED;
2115 }
2116
2117 static int software_reset(struct fw_ohci *ohci)
2118 {
2119         u32 val;
2120         int i;
2121
2122         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
2123         for (i = 0; i < 500; i++) {
2124                 val = reg_read(ohci, OHCI1394_HCControlSet);
2125                 if (!~val)
2126                         return -ENODEV; /* Card was ejected. */
2127
2128                 if (!(val & OHCI1394_HCControl_softReset))
2129                         return 0;
2130
2131                 msleep(1);
2132         }
2133
2134         return -EBUSY;
2135 }
2136
2137 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
2138 {
2139         size_t size = length * 4;
2140
2141         memcpy(dest, src, size);
2142         if (size < CONFIG_ROM_SIZE)
2143                 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
2144 }
2145
2146 static int configure_1394a_enhancements(struct fw_ohci *ohci)
2147 {
2148         bool enable_1394a;
2149         int ret, clear, set, offset;
2150
2151         /* Check if the driver should configure link and PHY. */
2152         if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2153               OHCI1394_HCControl_programPhyEnable))
2154                 return 0;
2155
2156         /* Paranoia: check whether the PHY supports 1394a, too. */
2157         enable_1394a = false;
2158         ret = read_phy_reg(ohci, 2);
2159         if (ret < 0)
2160                 return ret;
2161         if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2162                 ret = read_paged_phy_reg(ohci, 1, 8);
2163                 if (ret < 0)
2164                         return ret;
2165                 if (ret >= 1)
2166                         enable_1394a = true;
2167         }
2168
2169         if (ohci->quirks & QUIRK_NO_1394A)
2170                 enable_1394a = false;
2171
2172         /* Configure PHY and link consistently. */
2173         if (enable_1394a) {
2174                 clear = 0;
2175                 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2176         } else {
2177                 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2178                 set = 0;
2179         }
2180         ret = update_phy_reg(ohci, 5, clear, set);
2181         if (ret < 0)
2182                 return ret;
2183
2184         if (enable_1394a)
2185                 offset = OHCI1394_HCControlSet;
2186         else
2187                 offset = OHCI1394_HCControlClear;
2188         reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2189
2190         /* Clean up: configuration has been taken care of. */
2191         reg_write(ohci, OHCI1394_HCControlClear,
2192                   OHCI1394_HCControl_programPhyEnable);
2193
2194         return 0;
2195 }
2196
2197 static int probe_tsb41ba3d(struct fw_ohci *ohci)
2198 {
2199         /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
2200         static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
2201         int reg, i;
2202
2203         reg = read_phy_reg(ohci, 2);
2204         if (reg < 0)
2205                 return reg;
2206         if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
2207                 return 0;
2208
2209         for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
2210                 reg = read_paged_phy_reg(ohci, 1, i + 10);
2211                 if (reg < 0)
2212                         return reg;
2213                 if (reg != id[i])
2214                         return 0;
2215         }
2216         return 1;
2217 }
2218
2219 static int ohci_enable(struct fw_card *card,
2220                        const __be32 *config_rom, size_t length)
2221 {
2222         struct fw_ohci *ohci = fw_ohci(card);
2223         struct pci_dev *dev = to_pci_dev(card->device);
2224         u32 lps, version, irqs;
2225         int i, ret;
2226
2227         if (software_reset(ohci)) {
2228                 dev_err(card->device, "failed to reset ohci card\n");
2229                 return -EBUSY;
2230         }
2231
2232         /*
2233          * Now enable LPS, which we need in order to start accessing
2234          * most of the registers.  In fact, on some cards (ALI M5251),
2235          * accessing registers in the SClk domain without LPS enabled
2236          * will lock up the machine.  Wait 50msec to make sure we have
2237          * full link enabled.  However, with some cards (well, at least
2238          * a JMicron PCIe card), we have to try again sometimes.
2239          */
2240         reg_write(ohci, OHCI1394_HCControlSet,
2241                   OHCI1394_HCControl_LPS |
2242                   OHCI1394_HCControl_postedWriteEnable);
2243         flush_writes(ohci);
2244
2245         for (lps = 0, i = 0; !lps && i < 3; i++) {
2246                 msleep(50);
2247                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2248                       OHCI1394_HCControl_LPS;
2249         }
2250
2251         if (!lps) {
2252                 dev_err(card->device, "failed to set Link Power Status\n");
2253                 return -EIO;
2254         }
2255
2256         if (ohci->quirks & QUIRK_TI_SLLZ059) {
2257                 ret = probe_tsb41ba3d(ohci);
2258                 if (ret < 0)
2259                         return ret;
2260                 if (ret)
2261                         dev_notice(card->device, "local TSB41BA3D phy\n");
2262                 else
2263                         ohci->quirks &= ~QUIRK_TI_SLLZ059;
2264         }
2265
2266         reg_write(ohci, OHCI1394_HCControlClear,
2267                   OHCI1394_HCControl_noByteSwapData);
2268
2269         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2270         reg_write(ohci, OHCI1394_LinkControlSet,
2271                   OHCI1394_LinkControl_cycleTimerEnable |
2272                   OHCI1394_LinkControl_cycleMaster);
2273
2274         reg_write(ohci, OHCI1394_ATRetries,
2275                   OHCI1394_MAX_AT_REQ_RETRIES |
2276                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2277                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2278                   (200 << 16));
2279
2280         ohci->bus_time_running = false;
2281
2282         for (i = 0; i < 32; i++)
2283                 if (ohci->ir_context_support & (1 << i))
2284                         reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i),
2285                                   IR_CONTEXT_MULTI_CHANNEL_MODE);
2286
2287         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2288         if (version >= OHCI_VERSION_1_1) {
2289                 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2290                           0xfffffffe);
2291                 card->broadcast_channel_auto_allocated = true;
2292         }
2293
2294         /* Get implemented bits of the priority arbitration request counter. */
2295         reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2296         ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2297         reg_write(ohci, OHCI1394_FairnessControl, 0);
2298         card->priority_budget_implemented = ohci->pri_req_max != 0;
2299
2300         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2301         reg_write(ohci, OHCI1394_IntEventClear, ~0);
2302         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2303
2304         ret = configure_1394a_enhancements(ohci);
2305         if (ret < 0)
2306                 return ret;
2307
2308         /* Activate link_on bit and contender bit in our self ID packets.*/
2309         ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2310         if (ret < 0)
2311                 return ret;
2312
2313         /*
2314          * When the link is not yet enabled, the atomic config rom
2315          * update mechanism described below in ohci_set_config_rom()
2316          * is not active.  We have to update ConfigRomHeader and
2317          * BusOptions manually, and the write to ConfigROMmap takes
2318          * effect immediately.  We tie this to the enabling of the
2319          * link, so we have a valid config rom before enabling - the
2320          * OHCI requires that ConfigROMhdr and BusOptions have valid
2321          * values before enabling.
2322          *
2323          * However, when the ConfigROMmap is written, some controllers
2324          * always read back quadlets 0 and 2 from the config rom to
2325          * the ConfigRomHeader and BusOptions registers on bus reset.
2326          * They shouldn't do that in this initial case where the link
2327          * isn't enabled.  This means we have to use the same
2328          * workaround here, setting the bus header to 0 and then write
2329          * the right values in the bus reset tasklet.
2330          */
2331
2332         if (config_rom) {
2333                 ohci->next_config_rom =
2334                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2335                                            &ohci->next_config_rom_bus,
2336                                            GFP_KERNEL);
2337                 if (ohci->next_config_rom == NULL)
2338                         return -ENOMEM;
2339
2340                 copy_config_rom(ohci->next_config_rom, config_rom, length);
2341         } else {
2342                 /*
2343                  * In the suspend case, config_rom is NULL, which
2344                  * means that we just reuse the old config rom.
2345                  */
2346                 ohci->next_config_rom = ohci->config_rom;
2347                 ohci->next_config_rom_bus = ohci->config_rom_bus;
2348         }
2349
2350         ohci->next_header = ohci->next_config_rom[0];
2351         ohci->next_config_rom[0] = 0;
2352         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2353         reg_write(ohci, OHCI1394_BusOptions,
2354                   be32_to_cpu(ohci->next_config_rom[2]));
2355         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2356
2357         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2358
2359         if (!(ohci->quirks & QUIRK_NO_MSI))
2360                 pci_enable_msi(dev);
2361         if (request_irq(dev->irq, irq_handler,
2362                         pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
2363                         ohci_driver_name, ohci)) {
2364                 dev_err(card->device, "failed to allocate interrupt %d\n",
2365                         dev->irq);
2366                 pci_disable_msi(dev);
2367
2368                 if (config_rom) {
2369                         dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2370                                           ohci->next_config_rom,
2371                                           ohci->next_config_rom_bus);
2372                         ohci->next_config_rom = NULL;
2373                 }
2374                 return -EIO;
2375         }
2376
2377         irqs =  OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2378                 OHCI1394_RQPkt | OHCI1394_RSPkt |
2379                 OHCI1394_isochTx | OHCI1394_isochRx |
2380                 OHCI1394_postedWriteErr |
2381                 OHCI1394_selfIDComplete |
2382                 OHCI1394_regAccessFail |
2383                 OHCI1394_cycleInconsistent |
2384                 OHCI1394_unrecoverableError |
2385                 OHCI1394_cycleTooLong |
2386                 OHCI1394_masterIntEnable;
2387         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2388                 irqs |= OHCI1394_busReset;
2389         reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2390
2391         reg_write(ohci, OHCI1394_HCControlSet,
2392                   OHCI1394_HCControl_linkEnable |
2393                   OHCI1394_HCControl_BIBimageValid);
2394
2395         reg_write(ohci, OHCI1394_LinkControlSet,
2396                   OHCI1394_LinkControl_rcvSelfID |
2397                   OHCI1394_LinkControl_rcvPhyPkt);
2398
2399         ar_context_run(&ohci->ar_request_ctx);
2400         ar_context_run(&ohci->ar_response_ctx);
2401
2402         flush_writes(ohci);
2403
2404         /* We are ready to go, reset bus to finish initialization. */
2405         fw_schedule_bus_reset(&ohci->card, false, true);
2406
2407         return 0;
2408 }
2409
2410 static int ohci_set_config_rom(struct fw_card *card,
2411                                const __be32 *config_rom, size_t length)
2412 {
2413         struct fw_ohci *ohci;
2414         __be32 *next_config_rom;
2415         dma_addr_t uninitialized_var(next_config_rom_bus);
2416
2417         ohci = fw_ohci(card);
2418
2419         /*
2420          * When the OHCI controller is enabled, the config rom update
2421          * mechanism is a bit tricky, but easy enough to use.  See
2422          * section 5.5.6 in the OHCI specification.
2423          *
2424          * The OHCI controller caches the new config rom address in a
2425          * shadow register (ConfigROMmapNext) and needs a bus reset
2426          * for the changes to take place.  When the bus reset is
2427          * detected, the controller loads the new values for the
2428          * ConfigRomHeader and BusOptions registers from the specified
2429          * config rom and loads ConfigROMmap from the ConfigROMmapNext
2430          * shadow register. All automatically and atomically.
2431          *
2432          * Now, there's a twist to this story.  The automatic load of
2433          * ConfigRomHeader and BusOptions doesn't honor the
2434          * noByteSwapData bit, so with a be32 config rom, the
2435          * controller will load be32 values in to these registers
2436          * during the atomic update, even on litte endian
2437          * architectures.  The workaround we use is to put a 0 in the
2438          * header quadlet; 0 is endian agnostic and means that the
2439          * config rom isn't ready yet.  In the bus reset tasklet we
2440          * then set up the real values for the two registers.
2441          *
2442          * We use ohci->lock to avoid racing with the code that sets
2443          * ohci->next_config_rom to NULL (see bus_reset_work).
2444          */
2445
2446         next_config_rom =
2447                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2448                                    &next_config_rom_bus, GFP_KERNEL);
2449         if (next_config_rom == NULL)
2450                 return -ENOMEM;
2451
2452         spin_lock_irq(&ohci->lock);
2453
2454         /*
2455          * If there is not an already pending config_rom update,
2456          * push our new allocation into the ohci->next_config_rom
2457          * and then mark the local variable as null so that we
2458          * won't deallocate the new buffer.
2459          *
2460          * OTOH, if there is a pending config_rom update, just
2461          * use that buffer with the new config_rom data, and
2462          * let this routine free the unused DMA allocation.
2463          */
2464
2465         if (ohci->next_config_rom == NULL) {
2466                 ohci->next_config_rom = next_config_rom;
2467                 ohci->next_config_rom_bus = next_config_rom_bus;
2468                 next_config_rom = NULL;
2469         }
2470
2471         copy_config_rom(ohci->next_config_rom, config_rom, length);
2472
2473         ohci->next_header = config_rom[0];
2474         ohci->next_config_rom[0] = 0;
2475
2476         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2477
2478         spin_unlock_irq(&ohci->lock);
2479
2480         /* If we didn't use the DMA allocation, delete it. */
2481         if (next_config_rom != NULL)
2482                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2483                                   next_config_rom, next_config_rom_bus);
2484
2485         /*
2486          * Now initiate a bus reset to have the changes take
2487          * effect. We clean up the old config rom memory and DMA
2488          * mappings in the bus reset tasklet, since the OHCI
2489          * controller could need to access it before the bus reset
2490          * takes effect.
2491          */
2492
2493         fw_schedule_bus_reset(&ohci->card, true, true);
2494
2495         return 0;
2496 }
2497
2498 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2499 {
2500         struct fw_ohci *ohci = fw_ohci(card);
2501
2502         at_context_transmit(&ohci->at_request_ctx, packet);
2503 }
2504
2505 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2506 {
2507         struct fw_ohci *ohci = fw_ohci(card);
2508
2509         at_context_transmit(&ohci->at_response_ctx, packet);
2510 }
2511
2512 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2513 {
2514         struct fw_ohci *ohci = fw_ohci(card);
2515         struct context *ctx = &ohci->at_request_ctx;
2516         struct driver_data *driver_data = packet->driver_data;
2517         int ret = -ENOENT;
2518
2519         tasklet_disable(&ctx->tasklet);
2520
2521         if (packet->ack != 0)
2522                 goto out;
2523
2524         if (packet->payload_mapped)
2525                 dma_unmap_single(ohci->card.device, packet->payload_bus,
2526                                  packet->payload_length, DMA_TO_DEVICE);
2527
2528         log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20);
2529         driver_data->packet = NULL;
2530         packet->ack = RCODE_CANCELLED;
2531         packet->callback(packet, &ohci->card, packet->ack);
2532         ret = 0;
2533  out:
2534         tasklet_enable(&ctx->tasklet);
2535
2536         return ret;
2537 }
2538
2539 static int ohci_enable_phys_dma(struct fw_card *card,
2540                                 int node_id, int generation)
2541 {
2542 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2543         return 0;
2544 #else
2545         struct fw_ohci *ohci = fw_ohci(card);
2546         unsigned long flags;
2547         int n, ret = 0;
2548
2549         /*
2550          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
2551          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
2552          */
2553
2554         spin_lock_irqsave(&ohci->lock, flags);
2555
2556         if (ohci->generation != generation) {
2557                 ret = -ESTALE;
2558                 goto out;
2559         }
2560
2561         /*
2562          * Note, if the node ID contains a non-local bus ID, physical DMA is
2563          * enabled for _all_ nodes on remote buses.
2564          */
2565
2566         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2567         if (n < 32)
2568                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2569         else
2570                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2571
2572         flush_writes(ohci);
2573  out:
2574         spin_unlock_irqrestore(&ohci->lock, flags);
2575
2576         return ret;
2577 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2578 }
2579
2580 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2581 {
2582         struct fw_ohci *ohci = fw_ohci(card);
2583         unsigned long flags;
2584         u32 value;
2585
2586         switch (csr_offset) {
2587         case CSR_STATE_CLEAR:
2588         case CSR_STATE_SET:
2589                 if (ohci->is_root &&
2590                     (reg_read(ohci, OHCI1394_LinkControlSet) &
2591                      OHCI1394_LinkControl_cycleMaster))
2592                         value = CSR_STATE_BIT_CMSTR;
2593                 else
2594                         value = 0;
2595                 if (ohci->csr_state_setclear_abdicate)
2596                         value |= CSR_STATE_BIT_ABDICATE;
2597
2598                 return value;
2599
2600         case CSR_NODE_IDS:
2601                 return reg_read(ohci, OHCI1394_NodeID) << 16;
2602
2603         case CSR_CYCLE_TIME:
2604                 return get_cycle_time(ohci);
2605
2606         case CSR_BUS_TIME:
2607                 /*
2608                  * We might be called just after the cycle timer has wrapped
2609                  * around but just before the cycle64Seconds handler, so we
2610                  * better check here, too, if the bus time needs to be updated.
2611                  */
2612                 spin_lock_irqsave(&ohci->lock, flags);
2613                 value = update_bus_time(ohci);
2614                 spin_unlock_irqrestore(&ohci->lock, flags);
2615                 return value;
2616
2617         case CSR_BUSY_TIMEOUT:
2618                 value = reg_read(ohci, OHCI1394_ATRetries);
2619                 return (value >> 4) & 0x0ffff00f;
2620
2621         case CSR_PRIORITY_BUDGET:
2622                 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2623                         (ohci->pri_req_max << 8);
2624
2625         default:
2626                 WARN_ON(1);
2627                 return 0;
2628         }
2629 }
2630
2631 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2632 {
2633         struct fw_ohci *ohci = fw_ohci(card);
2634         unsigned long flags;
2635
2636         switch (csr_offset) {
2637         case CSR_STATE_CLEAR:
2638                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2639                         reg_write(ohci, OHCI1394_LinkControlClear,
2640                                   OHCI1394_LinkControl_cycleMaster);
2641                         flush_writes(ohci);
2642                 }
2643                 if (value & CSR_STATE_BIT_ABDICATE)
2644                         ohci->csr_state_setclear_abdicate = false;
2645                 break;
2646
2647         case CSR_STATE_SET:
2648                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2649                         reg_write(ohci, OHCI1394_LinkControlSet,
2650                                   OHCI1394_LinkControl_cycleMaster);
2651                         flush_writes(ohci);
2652                 }
2653                 if (value & CSR_STATE_BIT_ABDICATE)
2654                         ohci->csr_state_setclear_abdicate = true;
2655                 break;
2656
2657         case CSR_NODE_IDS:
2658                 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2659                 flush_writes(ohci);
2660                 break;
2661
2662         case CSR_CYCLE_TIME:
2663                 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2664                 reg_write(ohci, OHCI1394_IntEventSet,
2665                           OHCI1394_cycleInconsistent);
2666                 flush_writes(ohci);
2667                 break;
2668
2669         case CSR_BUS_TIME:
2670                 spin_lock_irqsave(&ohci->lock, flags);
2671                 ohci->bus_time = (update_bus_time(ohci) & 0x40) |
2672                                  (value & ~0x7f);
2673                 spin_unlock_irqrestore(&ohci->lock, flags);
2674                 break;
2675
2676         case CSR_BUSY_TIMEOUT:
2677                 value = (value & 0xf) | ((value & 0xf) << 4) |
2678                         ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2679                 reg_write(ohci, OHCI1394_ATRetries, value);
2680                 flush_writes(ohci);
2681                 break;
2682
2683         case CSR_PRIORITY_BUDGET:
2684                 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2685                 flush_writes(ohci);
2686                 break;
2687
2688         default:
2689                 WARN_ON(1);
2690                 break;
2691         }
2692 }
2693
2694 static void flush_iso_completions(struct iso_context *ctx)
2695 {
2696         ctx->base.callback.sc(&ctx->base, ctx->last_timestamp,
2697                               ctx->header_length, ctx->header,
2698                               ctx->base.callback_data);
2699         ctx->header_length = 0;
2700 }
2701
2702 static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr)
2703 {
2704         u32 *ctx_hdr;
2705
2706         if (ctx->header_length + ctx->base.header_size > PAGE_SIZE)
2707                 flush_iso_completions(ctx);
2708
2709         ctx_hdr = ctx->header + ctx->header_length;
2710         ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]);
2711
2712         /*
2713          * The two iso header quadlets are byteswapped to little
2714          * endian by the controller, but we want to present them
2715          * as big endian for consistency with the bus endianness.
2716          */
2717         if (ctx->base.header_size > 0)
2718                 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */
2719         if (ctx->base.header_size > 4)
2720                 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */
2721         if (ctx->base.header_size > 8)
2722                 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8);
2723         ctx->header_length += ctx->base.header_size;
2724 }
2725
2726 static int handle_ir_packet_per_buffer(struct context *context,
2727                                        struct descriptor *d,
2728                                        struct descriptor *last)
2729 {
2730         struct iso_context *ctx =
2731                 container_of(context, struct iso_context, context);
2732         struct descriptor *pd;
2733         u32 buffer_dma;
2734
2735         for (pd = d; pd <= last; pd++)
2736                 if (pd->transfer_status)
2737                         break;
2738         if (pd > last)
2739                 /* Descriptor(s) not done yet, stop iteration */
2740                 return 0;
2741
2742         while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
2743                 d++;
2744                 buffer_dma = le32_to_cpu(d->data_address);
2745                 dma_sync_single_range_for_cpu(context->ohci->card.device,
2746                                               buffer_dma & PAGE_MASK,
2747                                               buffer_dma & ~PAGE_MASK,
2748                                               le16_to_cpu(d->req_count),
2749                                               DMA_FROM_DEVICE);
2750         }
2751
2752         copy_iso_headers(ctx, (u32 *) (last + 1));
2753
2754         if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2755                 flush_iso_completions(ctx);
2756
2757         return 1;
2758 }
2759
2760 /* d == last because each descriptor block is only a single descriptor. */
2761 static int handle_ir_buffer_fill(struct context *context,
2762                                  struct descriptor *d,
2763                                  struct descriptor *last)
2764 {
2765         struct iso_context *ctx =
2766                 container_of(context, struct iso_context, context);
2767         unsigned int req_count, res_count, completed;
2768         u32 buffer_dma;
2769
2770         req_count = le16_to_cpu(last->req_count);
2771         res_count = le16_to_cpu(ACCESS_ONCE(last->res_count));
2772         completed = req_count - res_count;
2773         buffer_dma = le32_to_cpu(last->data_address);
2774
2775         if (completed > 0) {
2776                 ctx->mc_buffer_bus = buffer_dma;
2777                 ctx->mc_completed = completed;
2778         }
2779
2780         if (res_count != 0)
2781                 /* Descriptor(s) not done yet, stop iteration */
2782                 return 0;
2783
2784         dma_sync_single_range_for_cpu(context->ohci->card.device,
2785                                       buffer_dma & PAGE_MASK,
2786                                       buffer_dma & ~PAGE_MASK,
2787                                       completed, DMA_FROM_DEVICE);
2788
2789         if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) {
2790                 ctx->base.callback.mc(&ctx->base,
2791                                       buffer_dma + completed,
2792                                       ctx->base.callback_data);
2793                 ctx->mc_completed = 0;
2794         }
2795
2796         return 1;
2797 }
2798
2799 static void flush_ir_buffer_fill(struct iso_context *ctx)
2800 {
2801         dma_sync_single_range_for_cpu(ctx->context.ohci->card.device,
2802                                       ctx->mc_buffer_bus & PAGE_MASK,
2803                                       ctx->mc_buffer_bus & ~PAGE_MASK,
2804                                       ctx->mc_completed, DMA_FROM_DEVICE);
2805
2806         ctx->base.callback.mc(&ctx->base,
2807                               ctx->mc_buffer_bus + ctx->mc_completed,
2808                               ctx->base.callback_data);
2809         ctx->mc_completed = 0;
2810 }
2811
2812 static inline void sync_it_packet_for_cpu(struct context *context,
2813                                           struct descriptor *pd)
2814 {
2815         __le16 control;
2816         u32 buffer_dma;
2817
2818         /* only packets beginning with OUTPUT_MORE* have data buffers */
2819         if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2820                 return;
2821
2822         /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
2823         pd += 2;
2824
2825         /*
2826          * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
2827          * data buffer is in the context program's coherent page and must not
2828          * be synced.
2829          */
2830         if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
2831             (context->current_bus          & PAGE_MASK)) {
2832                 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2833                         return;
2834                 pd++;
2835         }
2836
2837         do {
2838                 buffer_dma = le32_to_cpu(pd->data_address);
2839                 dma_sync_single_range_for_cpu(context->ohci->card.device,
2840                                               buffer_dma & PAGE_MASK,
2841                                               buffer_dma & ~PAGE_MASK,
2842                                               le16_to_cpu(pd->req_count),
2843                                               DMA_TO_DEVICE);
2844                 control = pd->control;
2845                 pd++;
2846         } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
2847 }
2848
2849 static int handle_it_packet(struct context *context,
2850                             struct descriptor *d,
2851                             struct descriptor *last)
2852 {
2853         struct iso_context *ctx =
2854                 container_of(context, struct iso_context, context);
2855         struct descriptor *pd;
2856         __be32 *ctx_hdr;
2857
2858         for (pd = d; pd <= last; pd++)
2859                 if (pd->transfer_status)
2860                         break;
2861         if (pd > last)
2862                 /* Descriptor(s) not done yet, stop iteration */
2863                 return 0;
2864
2865         sync_it_packet_for_cpu(context, d);
2866
2867         if (ctx->header_length + 4 > PAGE_SIZE)
2868                 flush_iso_completions(ctx);
2869
2870         ctx_hdr = ctx->header + ctx->header_length;
2871         ctx->last_timestamp = le16_to_cpu(last->res_count);
2872         /* Present this value as big-endian to match the receive code */
2873         *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) |
2874                                le16_to_cpu(pd->res_count));
2875         ctx->header_length += 4;
2876
2877         if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2878                 flush_iso_completions(ctx);
2879
2880         return 1;
2881 }
2882
2883 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2884 {
2885         u32 hi = channels >> 32, lo = channels;
2886
2887         reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2888         reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2889         reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2890         reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2891         mmiowb();
2892         ohci->mc_channels = channels;
2893 }
2894
2895 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2896                                 int type, int channel, size_t header_size)
2897 {
2898         struct fw_ohci *ohci = fw_ohci(card);
2899         struct iso_context *uninitialized_var(ctx);
2900         descriptor_callback_t uninitialized_var(callback);
2901         u64 *uninitialized_var(channels);
2902         u32 *uninitialized_var(mask), uninitialized_var(regs);
2903         int index, ret = -EBUSY;
2904
2905         spin_lock_irq(&ohci->lock);
2906
2907         switch (type) {
2908         case FW_ISO_CONTEXT_TRANSMIT:
2909                 mask     = &ohci->it_context_mask;
2910                 callback = handle_it_packet;
2911                 index    = ffs(*mask) - 1;
2912                 if (index >= 0) {
2913                         *mask &= ~(1 << index);
2914                         regs = OHCI1394_IsoXmitContextBase(index);
2915                         ctx  = &ohci->it_context_list[index];
2916                 }
2917                 break;
2918
2919         case FW_ISO_CONTEXT_RECEIVE:
2920                 channels = &ohci->ir_context_channels;
2921                 mask     = &ohci->ir_context_mask;
2922                 callback = handle_ir_packet_per_buffer;
2923                 index    = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2924                 if (index >= 0) {
2925                         *channels &= ~(1ULL << channel);
2926                         *mask     &= ~(1 << index);
2927                         regs = OHCI1394_IsoRcvContextBase(index);
2928                         ctx  = &ohci->ir_context_list[index];
2929                 }
2930                 break;
2931
2932         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2933                 mask     = &ohci->ir_context_mask;
2934                 callback = handle_ir_buffer_fill;
2935                 index    = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2936                 if (index >= 0) {
2937                         ohci->mc_allocated = true;
2938                         *mask &= ~(1 << index);
2939                         regs = OHCI1394_IsoRcvContextBase(index);
2940                         ctx  = &ohci->ir_context_list[index];
2941                 }
2942                 break;
2943
2944         default:
2945                 index = -1;
2946                 ret = -ENOSYS;
2947         }
2948
2949         spin_unlock_irq(&ohci->lock);
2950
2951         if (index < 0)
2952                 return ERR_PTR(ret);
2953
2954         memset(ctx, 0, sizeof(*ctx));
2955         ctx->header_length = 0;
2956         ctx->header = (void *) __get_free_page(GFP_KERNEL);
2957         if (ctx->header == NULL) {
2958                 ret = -ENOMEM;
2959                 goto out;
2960         }
2961         ret = context_init(&ctx->context, ohci, regs, callback);
2962         if (ret < 0)
2963                 goto out_with_header;
2964
2965         if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) {
2966                 set_multichannel_mask(ohci, 0);
2967                 ctx->mc_completed = 0;
2968         }
2969
2970         return &ctx->base;
2971
2972  out_with_header:
2973         free_page((unsigned long)ctx->header);
2974  out:
2975         spin_lock_irq(&ohci->lock);
2976
2977         switch (type) {
2978         case FW_ISO_CONTEXT_RECEIVE:
2979                 *channels |= 1ULL << channel;
2980                 break;
2981
2982         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2983                 ohci->mc_allocated = false;
2984                 break;
2985         }
2986         *mask |= 1 << index;
2987
2988         spin_unlock_irq(&ohci->lock);
2989
2990         return ERR_PTR(ret);
2991 }
2992
2993 static int ohci_start_iso(struct fw_iso_context *base,
2994                           s32 cycle, u32 sync, u32 tags)
2995 {
2996         struct iso_context *ctx = container_of(base, struct iso_context, base);
2997         struct fw_ohci *ohci = ctx->context.ohci;
2998         u32 control = IR_CONTEXT_ISOCH_HEADER, match;
2999         int index;
3000
3001         /* the controller cannot start without any queued packets */
3002         if (ctx->context.last->branch_address == 0)
3003                 return -ENODATA;
3004
3005         switch (ctx->base.type) {
3006         case FW_ISO_CONTEXT_TRANSMIT:
3007                 index = ctx - ohci->it_context_list;
3008                 match = 0;
3009                 if (cycle >= 0)
3010                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
3011                                 (cycle & 0x7fff) << 16;
3012
3013                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
3014                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
3015                 context_run(&ctx->context, match);
3016                 break;
3017
3018         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3019                 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
3020                 /* fall through */
3021         case FW_ISO_CONTEXT_RECEIVE:
3022                 index = ctx - ohci->ir_context_list;
3023                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
3024                 if (cycle >= 0) {
3025                         match |= (cycle & 0x07fff) << 12;
3026                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
3027                 }
3028
3029                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
3030                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
3031                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
3032                 context_run(&ctx->context, control);
3033
3034                 ctx->sync = sync;
3035                 ctx->tags = tags;
3036
3037                 break;
3038         }
3039
3040         return 0;
3041 }
3042
3043 static int ohci_stop_iso(struct fw_iso_context *base)
3044 {
3045         struct fw_ohci *ohci = fw_ohci(base->card);
3046         struct iso_context *ctx = container_of(base, struct iso_context, base);
3047         int index;
3048
3049         switch (ctx->base.type) {
3050         case FW_ISO_CONTEXT_TRANSMIT:
3051                 index = ctx - ohci->it_context_list;
3052                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
3053                 break;
3054
3055         case FW_ISO_CONTEXT_RECEIVE:
3056         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3057                 index = ctx - ohci->ir_context_list;
3058                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
3059                 break;
3060         }
3061         flush_writes(ohci);
3062         context_stop(&ctx->context);
3063         tasklet_kill(&ctx->context.tasklet);
3064
3065         return 0;
3066 }
3067
3068 static void ohci_free_iso_context(struct fw_iso_context *base)
3069 {
3070         struct fw_ohci *ohci = fw_ohci(base->card);
3071         struct iso_context *ctx = container_of(base, struct iso_context, base);
3072         unsigned long flags;
3073         int index;
3074
3075         ohci_stop_iso(base);
3076         context_release(&ctx->context);
3077         free_page((unsigned long)ctx->header);
3078
3079         spin_lock_irqsave(&ohci->lock, flags);
3080
3081         switch (base->type) {
3082         case FW_ISO_CONTEXT_TRANSMIT:
3083                 index = ctx - ohci->it_context_list;
3084                 ohci->it_context_mask |= 1 << index;
3085                 break;
3086
3087         case FW_ISO_CONTEXT_RECEIVE:
3088                 index = ctx - ohci->ir_context_list;
3089                 ohci->ir_context_mask |= 1 << index;
3090                 ohci->ir_context_channels |= 1ULL << base->channel;
3091                 break;
3092
3093         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3094                 index = ctx - ohci->ir_context_list;
3095                 ohci->ir_context_mask |= 1 << index;
3096                 ohci->ir_context_channels |= ohci->mc_channels;
3097                 ohci->mc_channels = 0;
3098                 ohci->mc_allocated = false;
3099                 break;
3100         }
3101
3102         spin_unlock_irqrestore(&ohci->lock, flags);
3103 }
3104
3105 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
3106 {
3107         struct fw_ohci *ohci = fw_ohci(base->card);
3108         unsigned long flags;
3109         int ret;
3110
3111         switch (base->type) {
3112         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3113
3114                 spin_lock_irqsave(&ohci->lock, flags);
3115
3116                 /* Don't allow multichannel to grab other contexts' channels. */
3117                 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
3118                         *channels = ohci->ir_context_channels;
3119                         ret = -EBUSY;
3120                 } else {
3121                         set_multichannel_mask(ohci, *channels);
3122                         ret = 0;
3123                 }
3124
3125                 spin_unlock_irqrestore(&ohci->lock, flags);
3126
3127                 break;
3128         default:
3129                 ret = -EINVAL;
3130         }
3131
3132         return ret;
3133 }
3134
3135 #ifdef CONFIG_PM
3136 static void ohci_resume_iso_dma(struct fw_ohci *ohci)
3137 {
3138         int i;
3139         struct iso_context *ctx;
3140
3141         for (i = 0 ; i < ohci->n_ir ; i++) {
3142                 ctx = &ohci->ir_context_list[i];
3143                 if (ctx->context.running)
3144                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3145         }
3146
3147         for (i = 0 ; i < ohci->n_it ; i++) {
3148                 ctx = &ohci->it_context_list[i];
3149                 if (ctx->context.running)
3150                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3151         }
3152 }
3153 #endif
3154
3155 static int queue_iso_transmit(struct iso_context *ctx,
3156                               struct fw_iso_packet *packet,
3157                               struct fw_iso_buffer *buffer,
3158                               unsigned long payload)
3159 {
3160         struct descriptor *d, *last, *pd;
3161         struct fw_iso_packet *p;
3162         __le32 *header;
3163         dma_addr_t d_bus, page_bus;
3164         u32 z, header_z, payload_z, irq;
3165         u32 payload_index, payload_end_index, next_page_index;
3166         int page, end_page, i, length, offset;
3167
3168         p = packet;
3169         payload_index = payload;
3170
3171         if (p->skip)
3172                 z = 1;
3173         else
3174                 z = 2;
3175         if (p->header_length > 0)
3176                 z++;
3177
3178         /* Determine the first page the payload isn't contained in. */
3179         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
3180         if (p->payload_length > 0)
3181                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
3182         else
3183                 payload_z = 0;
3184
3185         z += payload_z;
3186
3187         /* Get header size in number of descriptors. */
3188         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
3189
3190         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
3191         if (d == NULL)
3192                 return -ENOMEM;
3193
3194         if (!p->skip) {
3195                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
3196                 d[0].req_count = cpu_to_le16(8);
3197                 /*
3198                  * Link the skip address to this descriptor itself.  This causes
3199                  * a context to skip a cycle whenever lost cycles or FIFO
3200                  * overruns occur, without dropping the data.  The application
3201                  * should then decide whether this is an error condition or not.
3202                  * FIXME:  Make the context's cycle-lost behaviour configurable?
3203                  */
3204                 d[0].branch_address = cpu_to_le32(d_bus | z);
3205
3206                 header = (__le32 *) &d[1];
3207                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
3208                                         IT_HEADER_TAG(p->tag) |
3209                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
3210                                         IT_HEADER_CHANNEL(ctx->base.channel) |
3211                                         IT_HEADER_SPEED(ctx->base.speed));
3212                 header[1] =
3213                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
3214                                                           p->payload_length));
3215         }
3216
3217         if (p->header_length > 0) {
3218                 d[2].req_count    = cpu_to_le16(p->header_length);
3219                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
3220                 memcpy(&d[z], p->header, p->header_length);
3221         }
3222
3223         pd = d + z - payload_z;
3224         payload_end_index = payload_index + p->payload_length;
3225         for (i = 0; i < payload_z; i++) {
3226                 page               = payload_index >> PAGE_SHIFT;
3227                 offset             = payload_index & ~PAGE_MASK;
3228                 next_page_index    = (page + 1) << PAGE_SHIFT;
3229                 length             =
3230                         min(next_page_index, payload_end_index) - payload_index;
3231                 pd[i].req_count    = cpu_to_le16(length);
3232
3233                 page_bus = page_private(buffer->pages[page]);
3234                 pd[i].data_address = cpu_to_le32(page_bus + offset);
3235
3236                 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3237                                                  page_bus, offset, length,
3238                                                  DMA_TO_DEVICE);
3239
3240                 payload_index += length;
3241         }
3242
3243         if (p->interrupt)
3244                 irq = DESCRIPTOR_IRQ_ALWAYS;
3245         else
3246                 irq = DESCRIPTOR_NO_IRQ;
3247
3248         last = z == 2 ? d : d + z - 1;
3249         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
3250                                      DESCRIPTOR_STATUS |
3251                                      DESCRIPTOR_BRANCH_ALWAYS |
3252                                      irq);
3253
3254         context_append(&ctx->context, d, z, header_z);
3255
3256         return 0;
3257 }
3258
3259 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
3260                                        struct fw_iso_packet *packet,
3261                                        struct fw_iso_buffer *buffer,
3262                                        unsigned long payload)
3263 {
3264         struct device *device = ctx->context.ohci->card.device;
3265         struct descriptor *d, *pd;
3266         dma_addr_t d_bus, page_bus;
3267         u32 z, header_z, rest;
3268         int i, j, length;
3269         int page, offset, packet_count, header_size, payload_per_buffer;
3270
3271         /*
3272          * The OHCI controller puts the isochronous header and trailer in the
3273          * buffer, so we need at least 8 bytes.
3274          */
3275         packet_count = packet->header_length / ctx->base.header_size;
3276         header_size  = max(ctx->base.header_size, (size_t)8);
3277
3278         /* Get header size in number of descriptors. */
3279         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3280         page     = payload >> PAGE_SHIFT;
3281         offset   = payload & ~PAGE_MASK;
3282         payload_per_buffer = packet->payload_length / packet_count;
3283
3284         for (i = 0; i < packet_count; i++) {
3285                 /* d points to the header descriptor */
3286                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
3287                 d = context_get_descriptors(&ctx->context,
3288                                 z + header_z, &d_bus);
3289                 if (d == NULL)
3290                         return -ENOMEM;
3291
3292                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
3293                                               DESCRIPTOR_INPUT_MORE);
3294                 if (packet->skip && i == 0)
3295                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3296                 d->req_count    = cpu_to_le16(header_size);
3297                 d->res_count    = d->req_count;
3298                 d->transfer_status = 0;
3299                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3300
3301                 rest = payload_per_buffer;
3302                 pd = d;
3303                 for (j = 1; j < z; j++) {
3304                         pd++;
3305                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3306                                                   DESCRIPTOR_INPUT_MORE);
3307
3308                         if (offset + rest < PAGE_SIZE)
3309                                 length = rest;
3310                         else
3311                                 length = PAGE_SIZE - offset;
3312                         pd->req_count = cpu_to_le16(length);
3313                         pd->res_count = pd->req_count;
3314                         pd->transfer_status = 0;
3315
3316                         page_bus = page_private(buffer->pages[page]);
3317                         pd->data_address = cpu_to_le32(page_bus + offset);
3318
3319                         dma_sync_single_range_for_device(device, page_bus,
3320                                                          offset, length,
3321                                                          DMA_FROM_DEVICE);
3322
3323                         offset = (offset + length) & ~PAGE_MASK;
3324                         rest -= length;
3325                         if (offset == 0)
3326                                 page++;
3327                 }
3328                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3329                                           DESCRIPTOR_INPUT_LAST |
3330                                           DESCRIPTOR_BRANCH_ALWAYS);
3331                 if (packet->interrupt && i == packet_count - 1)
3332                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3333
3334                 context_append(&ctx->context, d, z, header_z);
3335         }
3336
3337         return 0;
3338 }
3339
3340 static int queue_iso_buffer_fill(struct iso_context *ctx,
3341                                  struct fw_iso_packet *packet,
3342                                  struct fw_iso_buffer *buffer,
3343                                  unsigned long payload)
3344 {
3345         struct descriptor *d;
3346         dma_addr_t d_bus, page_bus;
3347         int page, offset, rest, z, i, length;
3348
3349         page   = payload >> PAGE_SHIFT;
3350         offset = payload & ~PAGE_MASK;
3351         rest   = packet->payload_length;
3352
3353         /* We need one descriptor for each page in the buffer. */
3354         z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3355
3356         if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3357                 return -EFAULT;
3358
3359         for (i = 0; i < z; i++) {
3360                 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3361                 if (d == NULL)
3362                         return -ENOMEM;
3363
3364                 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3365                                          DESCRIPTOR_BRANCH_ALWAYS);
3366                 if (packet->skip && i == 0)
3367                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3368                 if (packet->interrupt && i == z - 1)
3369                         d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3370
3371                 if (offset + rest < PAGE_SIZE)
3372                         length = rest;
3373                 else
3374                         length = PAGE_SIZE - offset;
3375                 d->req_count = cpu_to_le16(length);
3376                 d->res_count = d->req_count;
3377                 d->transfer_status = 0;
3378
3379                 page_bus = page_private(buffer->pages[page]);
3380                 d->data_address = cpu_to_le32(page_bus + offset);
3381
3382                 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3383                                                  page_bus, offset, length,
3384                                                  DMA_FROM_DEVICE);
3385
3386                 rest -= length;
3387                 offset = 0;
3388                 page++;
3389
3390                 context_append(&ctx->context, d, 1, 0);
3391         }
3392
3393         return 0;
3394 }
3395
3396 static int ohci_queue_iso(struct fw_iso_context *base,
3397                           struct fw_iso_packet *packet,
3398                           struct fw_iso_buffer *buffer,
3399                           unsigned long payload)
3400 {
3401         struct iso_context *ctx = container_of(base, struct iso_context, base);
3402         unsigned long flags;
3403         int ret = -ENOSYS;
3404
3405         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
3406         switch (base->type) {
3407         case FW_ISO_CONTEXT_TRANSMIT:
3408                 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3409                 break;
3410         case FW_ISO_CONTEXT_RECEIVE:
3411                 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3412                 break;
3413         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3414                 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3415                 break;
3416         }
3417         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3418
3419         return ret;
3420 }
3421
3422 static void ohci_flush_queue_iso(struct fw_iso_context *base)
3423 {
3424         struct context *ctx =
3425                         &container_of(base, struct iso_context, base)->context;
3426
3427         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
3428 }
3429
3430 static int ohci_flush_iso_completions(struct fw_iso_context *base)
3431 {
3432         struct iso_context *ctx = container_of(base, struct iso_context, base);
3433         int ret = 0;
3434
3435         tasklet_disable(&ctx->context.tasklet);
3436
3437         if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) {
3438                 context_tasklet((unsigned long)&ctx->context);
3439
3440                 switch (base->type) {
3441                 case FW_ISO_CONTEXT_TRANSMIT:
3442                 case FW_ISO_CONTEXT_RECEIVE:
3443                         if (ctx->header_length != 0)
3444                                 flush_iso_completions(ctx);
3445                         break;
3446                 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3447                         if (ctx->mc_completed != 0)
3448                                 flush_ir_buffer_fill(ctx);
3449                         break;
3450                 default:
3451                         ret = -ENOSYS;
3452                 }
3453
3454                 clear_bit_unlock(0, &ctx->flushing_completions);
3455                 smp_mb__after_clear_bit();
3456         }
3457
3458         tasklet_enable(&ctx->context.tasklet);
3459
3460         return ret;
3461 }
3462
3463 static const struct fw_card_driver ohci_driver = {
3464         .enable                 = ohci_enable,
3465         .read_phy_reg           = ohci_read_phy_reg,
3466         .update_phy_reg         = ohci_update_phy_reg,
3467         .set_config_rom         = ohci_set_config_rom,
3468         .send_request           = ohci_send_request,
3469         .send_response          = ohci_send_response,
3470         .cancel_packet          = ohci_cancel_packet,
3471         .enable_phys_dma        = ohci_enable_phys_dma,
3472         .read_csr               = ohci_read_csr,
3473         .write_csr              = ohci_write_csr,
3474
3475         .allocate_iso_context   = ohci_allocate_iso_context,
3476         .free_iso_context       = ohci_free_iso_context,
3477         .set_iso_channels       = ohci_set_iso_channels,
3478         .queue_iso              = ohci_queue_iso,
3479         .flush_queue_iso        = ohci_flush_queue_iso,
3480         .flush_iso_completions  = ohci_flush_iso_completions,
3481         .start_iso              = ohci_start_iso,
3482         .stop_iso               = ohci_stop_iso,
3483 };
3484
3485 #ifdef CONFIG_PPC_PMAC
3486 static void pmac_ohci_on(struct pci_dev *dev)
3487 {
3488         if (machine_is(powermac)) {
3489                 struct device_node *ofn = pci_device_to_OF_node(dev);
3490
3491                 if (ofn) {
3492                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3493                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3494                 }
3495         }
3496 }
3497
3498 static void pmac_ohci_off(struct pci_dev *dev)
3499 {
3500         if (machine_is(powermac)) {
3501                 struct device_node *ofn = pci_device_to_OF_node(dev);
3502
3503                 if (ofn) {
3504                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3505                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3506                 }
3507         }
3508 }
3509 #else
3510 static inline void pmac_ohci_on(struct pci_dev *dev) {}
3511 static inline void pmac_ohci_off(struct pci_dev *dev) {}
3512 #endif /* CONFIG_PPC_PMAC */
3513
3514 static int __devinit pci_probe(struct pci_dev *dev,
3515                                const struct pci_device_id *ent)
3516 {
3517         struct fw_ohci *ohci;
3518         u32 bus_options, max_receive, link_speed, version;
3519         u64 guid;
3520         int i, err;
3521         size_t size;
3522
3523         if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
3524                 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
3525                 return -ENOSYS;
3526         }
3527
3528         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3529         if (ohci == NULL) {
3530                 err = -ENOMEM;
3531                 goto fail;
3532         }
3533
3534         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3535
3536         pmac_ohci_on(dev);
3537
3538         err = pci_enable_device(dev);
3539         if (err) {
3540                 dev_err(&dev->dev, "failed to enable OHCI hardware\n");
3541                 goto fail_free;
3542         }
3543
3544         pci_set_master(dev);
3545         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3546         pci_set_drvdata(dev, ohci);
3547
3548         spin_lock_init(&ohci->lock);
3549         mutex_init(&ohci->phy_reg_mutex);
3550
3551         INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
3552
3553         if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) ||
3554             pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) {
3555                 dev_err(&dev->dev, "invalid MMIO resource\n");
3556                 err = -ENXIO;
3557                 goto fail_disable;
3558         }
3559
3560         err = pci_request_region(dev, 0, ohci_driver_name);
3561         if (err) {
3562                 dev_err(&dev->dev, "MMIO resource unavailable\n");
3563                 goto fail_disable;
3564         }
3565
3566         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3567         if (ohci->registers == NULL) {
3568                 dev_err(&dev->dev, "failed to remap registers\n");
3569                 err = -ENXIO;
3570                 goto fail_iomem;
3571         }
3572
3573         for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3574                 if ((ohci_quirks[i].vendor == dev->vendor) &&
3575                     (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3576                      ohci_quirks[i].device == dev->device) &&
3577                     (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3578                      ohci_quirks[i].revision >= dev->revision)) {
3579                         ohci->quirks = ohci_quirks[i].flags;
3580                         break;
3581                 }
3582         if (param_quirks)
3583                 ohci->quirks = param_quirks;
3584
3585         /*
3586          * Because dma_alloc_coherent() allocates at least one page,
3587          * we save space by using a common buffer for the AR request/
3588          * response descriptors and the self IDs buffer.
3589          */
3590         BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3591         BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3592         ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3593                                                PAGE_SIZE,
3594                                                &ohci->misc_buffer_bus,
3595                                                GFP_KERNEL);
3596         if (!ohci->misc_buffer) {
3597                 err = -ENOMEM;
3598                 goto fail_iounmap;
3599         }
3600
3601         err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3602                               OHCI1394_AsReqRcvContextControlSet);
3603         if (err < 0)
3604                 goto fail_misc_buf;
3605
3606         err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3607                               OHCI1394_AsRspRcvContextControlSet);
3608         if (err < 0)
3609                 goto fail_arreq_ctx;
3610
3611         err = context_init(&ohci->at_request_ctx, ohci,
3612                            OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3613         if (err < 0)
3614                 goto fail_arrsp_ctx;
3615
3616         err = context_init(&ohci->at_response_ctx, ohci,
3617                            OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3618         if (err < 0)
3619                 goto fail_atreq_ctx;
3620
3621         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3622         ohci->ir_context_channels = ~0ULL;
3623         ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3624         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3625         ohci->ir_context_mask = ohci->ir_context_support;
3626         ohci->n_ir = hweight32(ohci->ir_context_mask);
3627         size = sizeof(struct iso_context) * ohci->n_ir;
3628         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3629
3630         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3631         ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3632         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3633         ohci->it_context_mask = ohci->it_context_support;
3634         ohci->n_it = hweight32(ohci->it_context_mask);
3635         size = sizeof(struct iso_context) * ohci->n_it;
3636         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3637
3638         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3639                 err = -ENOMEM;
3640                 goto fail_contexts;
3641         }
3642
3643         ohci->self_id_cpu = ohci->misc_buffer     + PAGE_SIZE/2;
3644         ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3645
3646         bus_options = reg_read(ohci, OHCI1394_BusOptions);
3647         max_receive = (bus_options >> 12) & 0xf;
3648         link_speed = bus_options & 0x7;
3649         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3650                 reg_read(ohci, OHCI1394_GUIDLo);
3651
3652         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3653         if (err)
3654                 goto fail_contexts;
3655
3656         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3657         dev_notice(&dev->dev,
3658                   "added OHCI v%x.%x device as card %d, "
3659                   "%d IR + %d IT contexts, quirks 0x%x\n",
3660                   version >> 16, version & 0xff, ohci->card.index,
3661                   ohci->n_ir, ohci->n_it, ohci->quirks);
3662
3663         return 0;
3664
3665  fail_contexts:
3666         kfree(ohci->ir_context_list);
3667         kfree(ohci->it_context_list);
3668         context_release(&ohci->at_response_ctx);
3669  fail_atreq_ctx:
3670         context_release(&ohci->at_request_ctx);
3671  fail_arrsp_ctx:
3672         ar_context_release(&ohci->ar_response_ctx);
3673  fail_arreq_ctx:
3674         ar_context_release(&ohci->ar_request_ctx);
3675  fail_misc_buf:
3676         dma_free_coherent(ohci->card.device, PAGE_SIZE,
3677                           ohci->misc_buffer, ohci->misc_buffer_bus);
3678  fail_iounmap:
3679         pci_iounmap(dev, ohci->registers);
3680  fail_iomem:
3681         pci_release_region(dev, 0);
3682  fail_disable:
3683         pci_disable_device(dev);
3684  fail_free:
3685         kfree(ohci);
3686         pmac_ohci_off(dev);
3687  fail:
3688         if (err == -ENOMEM)
3689                 dev_err(&dev->dev, "out of memory\n");
3690
3691         return err;
3692 }
3693
3694 static void pci_remove(struct pci_dev *dev)
3695 {
3696         struct fw_ohci *ohci;
3697
3698         ohci = pci_get_drvdata(dev);
3699         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3700         flush_writes(ohci);
3701         cancel_work_sync(&ohci->bus_reset_work);
3702         fw_core_remove_card(&ohci->card);
3703
3704         /*
3705          * FIXME: Fail all pending packets here, now that the upper
3706          * layers can't queue any more.
3707          */
3708
3709         software_reset(ohci);
3710         free_irq(dev->irq, ohci);
3711
3712         if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3713                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3714                                   ohci->next_config_rom, ohci->next_config_rom_bus);
3715         if (ohci->config_rom)
3716                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3717                                   ohci->config_rom, ohci->config_rom_bus);
3718         ar_context_release(&ohci->ar_request_ctx);
3719         ar_context_release(&ohci->ar_response_ctx);
3720         dma_free_coherent(ohci->card.device, PAGE_SIZE,
3721                           ohci->misc_buffer, ohci->misc_buffer_bus);
3722         context_release(&ohci->at_request_ctx);
3723         context_release(&ohci->at_response_ctx);
3724         kfree(ohci->it_context_list);
3725         kfree(ohci->ir_context_list);
3726         pci_disable_msi(dev);
3727         pci_iounmap(dev, ohci->registers);
3728         pci_release_region(dev, 0);
3729         pci_disable_device(dev);
3730         kfree(ohci);
3731         pmac_ohci_off(dev);
3732
3733         dev_notice(&dev->dev, "removed fw-ohci device\n");
3734 }
3735
3736 #ifdef CONFIG_PM
3737 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3738 {
3739         struct fw_ohci *ohci = pci_get_drvdata(dev);
3740         int err;
3741
3742         software_reset(ohci);
3743         free_irq(dev->irq, ohci);
3744         pci_disable_msi(dev);
3745         err = pci_save_state(dev);
3746         if (err) {
3747                 dev_err(&dev->dev, "pci_save_state failed\n");
3748                 return err;
3749         }
3750         err = pci_set_power_state(dev, pci_choose_state(dev, state));
3751         if (err)
3752                 dev_err(&dev->dev, "pci_set_power_state failed with %d\n", err);
3753         pmac_ohci_off(dev);
3754
3755         return 0;
3756 }
3757
3758 static int pci_resume(struct pci_dev *dev)
3759 {
3760         struct fw_ohci *ohci = pci_get_drvdata(dev);
3761         int err;
3762
3763         pmac_ohci_on(dev);
3764         pci_set_power_state(dev, PCI_D0);
3765         pci_restore_state(dev);
3766         err = pci_enable_device(dev);
3767         if (err) {
3768                 dev_err(&dev->dev, "pci_enable_device failed\n");
3769                 return err;
3770         }
3771
3772         /* Some systems don't setup GUID register on resume from ram  */
3773         if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3774                                         !reg_read(ohci, OHCI1394_GUIDHi)) {
3775                 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3776                 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3777         }
3778
3779         err = ohci_enable(&ohci->card, NULL, 0);
3780         if (err)
3781                 return err;
3782
3783         ohci_resume_iso_dma(ohci);
3784
3785         return 0;
3786 }
3787 #endif
3788
3789 static const struct pci_device_id pci_table[] = {
3790         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3791         { }
3792 };
3793
3794 MODULE_DEVICE_TABLE(pci, pci_table);
3795
3796 static struct pci_driver fw_ohci_pci_driver = {
3797         .name           = ohci_driver_name,
3798         .id_table       = pci_table,
3799         .probe          = pci_probe,
3800         .remove         = pci_remove,
3801 #ifdef CONFIG_PM
3802         .resume         = pci_resume,
3803         .suspend        = pci_suspend,
3804 #endif
3805 };
3806
3807 module_pci_driver(fw_ohci_pci_driver);
3808
3809 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3810 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3811 MODULE_LICENSE("GPL");
3812
3813 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3814 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3815 MODULE_ALIAS("ohci1394");
3816 #endif