2 * Driver for OHCI 1394 controllers
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/bug.h>
22 #include <linux/compiler.h>
23 #include <linux/delay.h>
24 #include <linux/device.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/firewire.h>
27 #include <linux/firewire-constants.h>
28 #include <linux/gfp.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
32 #include <linux/kernel.h>
33 #include <linux/list.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/mutex.h>
38 #include <linux/pci.h>
39 #include <linux/pci_ids.h>
40 #include <linux/spinlock.h>
41 #include <linux/string.h>
43 #include <asm/byteorder.h>
45 #include <asm/system.h>
47 #ifdef CONFIG_PPC_PMAC
48 #include <asm/pmac_feature.h>
54 #define DESCRIPTOR_OUTPUT_MORE 0
55 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
56 #define DESCRIPTOR_INPUT_MORE (2 << 12)
57 #define DESCRIPTOR_INPUT_LAST (3 << 12)
58 #define DESCRIPTOR_STATUS (1 << 11)
59 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
60 #define DESCRIPTOR_PING (1 << 7)
61 #define DESCRIPTOR_YY (1 << 6)
62 #define DESCRIPTOR_NO_IRQ (0 << 4)
63 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
64 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
65 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
66 #define DESCRIPTOR_WAIT (3 << 0)
72 __le32 branch_address;
74 __le16 transfer_status;
75 } __attribute__((aligned(16)));
77 #define CONTROL_SET(regs) (regs)
78 #define CONTROL_CLEAR(regs) ((regs) + 4)
79 #define COMMAND_PTR(regs) ((regs) + 12)
80 #define CONTEXT_MATCH(regs) ((regs) + 16)
83 struct descriptor descriptor;
84 struct ar_buffer *next;
90 struct ar_buffer *current_buffer;
91 struct ar_buffer *last_buffer;
94 struct tasklet_struct tasklet;
99 typedef int (*descriptor_callback_t)(struct context *ctx,
100 struct descriptor *d,
101 struct descriptor *last);
104 * A buffer that contains a block of DMA-able coherent memory used for
105 * storing a portion of a DMA descriptor program.
107 struct descriptor_buffer {
108 struct list_head list;
109 dma_addr_t buffer_bus;
112 struct descriptor buffer[0];
116 struct fw_ohci *ohci;
118 int total_allocation;
121 * List of page-sized buffers for storing DMA descriptors.
122 * Head of list contains buffers in use and tail of list contains
125 struct list_head buffer_list;
128 * Pointer to a buffer inside buffer_list that contains the tail
129 * end of the current DMA program.
131 struct descriptor_buffer *buffer_tail;
134 * The descriptor containing the branch address of the first
135 * descriptor that has not yet been filled by the device.
137 struct descriptor *last;
140 * The last descriptor in the DMA program. It contains the branch
141 * address that must be updated upon appending a new descriptor.
143 struct descriptor *prev;
145 descriptor_callback_t callback;
147 struct tasklet_struct tasklet;
150 #define IT_HEADER_SY(v) ((v) << 0)
151 #define IT_HEADER_TCODE(v) ((v) << 4)
152 #define IT_HEADER_CHANNEL(v) ((v) << 8)
153 #define IT_HEADER_TAG(v) ((v) << 14)
154 #define IT_HEADER_SPEED(v) ((v) << 16)
155 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
158 struct fw_iso_context base;
159 struct context context;
162 size_t header_length;
165 #define CONFIG_ROM_SIZE 1024
170 __iomem char *registers;
173 int request_generation; /* for timestamping incoming requests */
175 unsigned int pri_req_max;
178 bool csr_state_setclear_abdicate;
181 * Spinlock for accessing fw_ohci data. Never call out of
182 * this driver with this lock held.
186 struct mutex phy_reg_mutex;
188 struct ar_context ar_request_ctx;
189 struct ar_context ar_response_ctx;
190 struct context at_request_ctx;
191 struct context at_response_ctx;
194 struct iso_context *it_context_list;
195 u64 ir_context_channels;
197 struct iso_context *ir_context_list;
200 dma_addr_t config_rom_bus;
201 __be32 *next_config_rom;
202 dma_addr_t next_config_rom_bus;
206 dma_addr_t self_id_bus;
207 struct tasklet_struct bus_reset_tasklet;
209 u32 self_id_buffer[512];
212 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
214 return container_of(card, struct fw_ohci, card);
217 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
218 #define IR_CONTEXT_BUFFER_FILL 0x80000000
219 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
220 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
221 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
222 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
224 #define CONTEXT_RUN 0x8000
225 #define CONTEXT_WAKE 0x1000
226 #define CONTEXT_DEAD 0x0800
227 #define CONTEXT_ACTIVE 0x0400
229 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
230 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
231 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
233 #define OHCI1394_REGISTER_SIZE 0x800
234 #define OHCI_LOOP_COUNT 500
235 #define OHCI1394_PCI_HCI_Control 0x40
236 #define SELF_ID_BUF_SIZE 0x800
237 #define OHCI_TCODE_PHY_PACKET 0x0e
238 #define OHCI_VERSION_1_1 0x010010
240 static char ohci_driver_name[] = KBUILD_MODNAME;
242 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
243 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
245 #define QUIRK_CYCLE_TIMER 1
246 #define QUIRK_RESET_PACKET 2
247 #define QUIRK_BE_HEADERS 4
248 #define QUIRK_NO_1394A 8
249 #define QUIRK_NO_MSI 16
251 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
252 static const struct {
253 unsigned short vendor, device, flags;
255 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, QUIRK_CYCLE_TIMER |
258 {PCI_VENDOR_ID_TI, PCI_ANY_ID, QUIRK_RESET_PACKET},
259 {PCI_VENDOR_ID_AL, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
260 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, QUIRK_NO_MSI},
261 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
262 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
263 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, QUIRK_BE_HEADERS},
266 /* This overrides anything that was found in ohci_quirks[]. */
267 static int param_quirks;
268 module_param_named(quirks, param_quirks, int, 0644);
269 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
270 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
271 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
272 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
273 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
274 ", disable MSI = " __stringify(QUIRK_NO_MSI)
277 #define OHCI_PARAM_DEBUG_AT_AR 1
278 #define OHCI_PARAM_DEBUG_SELFIDS 2
279 #define OHCI_PARAM_DEBUG_IRQS 4
280 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
282 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
284 static int param_debug;
285 module_param_named(debug, param_debug, int, 0644);
286 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
287 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
288 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
289 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
290 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
291 ", or a combination, or all = -1)");
293 static void log_irqs(u32 evt)
295 if (likely(!(param_debug &
296 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
299 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
300 !(evt & OHCI1394_busReset))
303 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
304 evt & OHCI1394_selfIDComplete ? " selfID" : "",
305 evt & OHCI1394_RQPkt ? " AR_req" : "",
306 evt & OHCI1394_RSPkt ? " AR_resp" : "",
307 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
308 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
309 evt & OHCI1394_isochRx ? " IR" : "",
310 evt & OHCI1394_isochTx ? " IT" : "",
311 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
312 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
313 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
314 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
315 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
316 evt & OHCI1394_busReset ? " busReset" : "",
317 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
318 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
319 OHCI1394_respTxComplete | OHCI1394_isochRx |
320 OHCI1394_isochTx | OHCI1394_postedWriteErr |
321 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
322 OHCI1394_cycleInconsistent |
323 OHCI1394_regAccessFail | OHCI1394_busReset)
327 static const char *speed[] = {
328 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
330 static const char *power[] = {
331 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
332 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
334 static const char port[] = { '.', '-', 'p', 'c', };
336 static char _p(u32 *s, int shift)
338 return port[*s >> shift & 3];
341 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
343 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
346 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
347 self_id_count, generation, node_id);
349 for (; self_id_count--; ++s)
350 if ((*s & 1 << 23) == 0)
351 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
352 "%s gc=%d %s %s%s%s\n",
353 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
354 speed[*s >> 14 & 3], *s >> 16 & 63,
355 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
356 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
358 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
360 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
361 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
364 static const char *evts[] = {
365 [0x00] = "evt_no_status", [0x01] = "-reserved-",
366 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
367 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
368 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
369 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
370 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
371 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
372 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
373 [0x10] = "-reserved-", [0x11] = "ack_complete",
374 [0x12] = "ack_pending ", [0x13] = "-reserved-",
375 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
376 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
377 [0x18] = "-reserved-", [0x19] = "-reserved-",
378 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
379 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
380 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
381 [0x20] = "pending/cancelled",
383 static const char *tcodes[] = {
384 [0x0] = "QW req", [0x1] = "BW req",
385 [0x2] = "W resp", [0x3] = "-reserved-",
386 [0x4] = "QR req", [0x5] = "BR req",
387 [0x6] = "QR resp", [0x7] = "BR resp",
388 [0x8] = "cycle start", [0x9] = "Lk req",
389 [0xa] = "async stream packet", [0xb] = "Lk resp",
390 [0xc] = "-reserved-", [0xd] = "-reserved-",
391 [0xe] = "link internal", [0xf] = "-reserved-",
393 static const char *phys[] = {
394 [0x0] = "phy config packet", [0x1] = "link-on packet",
395 [0x2] = "self-id packet", [0x3] = "-reserved-",
398 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
400 int tcode = header[0] >> 4 & 0xf;
403 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
406 if (unlikely(evt >= ARRAY_SIZE(evts)))
409 if (evt == OHCI1394_evt_bus_reset) {
410 fw_notify("A%c evt_bus_reset, generation %d\n",
411 dir, (header[2] >> 16) & 0xff);
415 if (header[0] == ~header[1]) {
416 fw_notify("A%c %s, %s, %08x\n",
417 dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
422 case 0x0: case 0x6: case 0x8:
423 snprintf(specific, sizeof(specific), " = %08x",
424 be32_to_cpu((__force __be32)header[3]));
426 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
427 snprintf(specific, sizeof(specific), " %x,%x",
428 header[3] >> 16, header[3] & 0xffff);
436 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
438 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
439 fw_notify("A%c spd %x tl %02x, "
442 dir, speed, header[0] >> 10 & 0x3f,
443 header[1] >> 16, header[0] >> 16, evts[evt],
444 tcodes[tcode], header[1] & 0xffff, header[2], specific);
447 fw_notify("A%c spd %x tl %02x, "
450 dir, speed, header[0] >> 10 & 0x3f,
451 header[1] >> 16, header[0] >> 16, evts[evt],
452 tcodes[tcode], specific);
458 #define param_debug 0
459 static inline void log_irqs(u32 evt) {}
460 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
461 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
463 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
465 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
467 writel(data, ohci->registers + offset);
470 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
472 return readl(ohci->registers + offset);
475 static inline void flush_writes(const struct fw_ohci *ohci)
477 /* Do a dummy read to flush writes. */
478 reg_read(ohci, OHCI1394_Version);
481 static int read_phy_reg(struct fw_ohci *ohci, int addr)
486 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
487 for (i = 0; i < 3 + 100; i++) {
488 val = reg_read(ohci, OHCI1394_PhyControl);
489 if (val & OHCI1394_PhyControl_ReadDone)
490 return OHCI1394_PhyControl_ReadData(val);
493 * Try a few times without waiting. Sleeping is necessary
494 * only when the link/PHY interface is busy.
499 fw_error("failed to read phy reg\n");
504 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
508 reg_write(ohci, OHCI1394_PhyControl,
509 OHCI1394_PhyControl_Write(addr, val));
510 for (i = 0; i < 3 + 100; i++) {
511 val = reg_read(ohci, OHCI1394_PhyControl);
512 if (!(val & OHCI1394_PhyControl_WritePending))
518 fw_error("failed to write phy reg\n");
523 static int update_phy_reg(struct fw_ohci *ohci, int addr,
524 int clear_bits, int set_bits)
526 int ret = read_phy_reg(ohci, addr);
531 * The interrupt status bits are cleared by writing a one bit.
532 * Avoid clearing them unless explicitly requested in set_bits.
535 clear_bits |= PHY_INT_STATUS_BITS;
537 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
540 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
544 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
548 return read_phy_reg(ohci, addr);
551 static int ohci_read_phy_reg(struct fw_card *card, int addr)
553 struct fw_ohci *ohci = fw_ohci(card);
556 mutex_lock(&ohci->phy_reg_mutex);
557 ret = read_phy_reg(ohci, addr);
558 mutex_unlock(&ohci->phy_reg_mutex);
563 static int ohci_update_phy_reg(struct fw_card *card, int addr,
564 int clear_bits, int set_bits)
566 struct fw_ohci *ohci = fw_ohci(card);
569 mutex_lock(&ohci->phy_reg_mutex);
570 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
571 mutex_unlock(&ohci->phy_reg_mutex);
576 static int ar_context_add_page(struct ar_context *ctx)
578 struct device *dev = ctx->ohci->card.device;
579 struct ar_buffer *ab;
580 dma_addr_t uninitialized_var(ab_bus);
583 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
588 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
589 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
591 DESCRIPTOR_BRANCH_ALWAYS);
592 offset = offsetof(struct ar_buffer, data);
593 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
594 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
595 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
596 ab->descriptor.branch_address = 0;
598 wmb(); /* finish init of new descriptors before branch_address update */
599 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
600 ctx->last_buffer->next = ab;
601 ctx->last_buffer = ab;
603 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
604 flush_writes(ctx->ohci);
609 static void ar_context_release(struct ar_context *ctx)
611 struct ar_buffer *ab, *ab_next;
615 for (ab = ctx->current_buffer; ab; ab = ab_next) {
617 offset = offsetof(struct ar_buffer, data);
618 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
619 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
624 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
625 #define cond_le32_to_cpu(v) \
626 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
628 #define cond_le32_to_cpu(v) le32_to_cpu(v)
631 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
633 struct fw_ohci *ohci = ctx->ohci;
635 u32 status, length, tcode;
638 p.header[0] = cond_le32_to_cpu(buffer[0]);
639 p.header[1] = cond_le32_to_cpu(buffer[1]);
640 p.header[2] = cond_le32_to_cpu(buffer[2]);
642 tcode = (p.header[0] >> 4) & 0x0f;
644 case TCODE_WRITE_QUADLET_REQUEST:
645 case TCODE_READ_QUADLET_RESPONSE:
646 p.header[3] = (__force __u32) buffer[3];
647 p.header_length = 16;
648 p.payload_length = 0;
651 case TCODE_READ_BLOCK_REQUEST :
652 p.header[3] = cond_le32_to_cpu(buffer[3]);
653 p.header_length = 16;
654 p.payload_length = 0;
657 case TCODE_WRITE_BLOCK_REQUEST:
658 case TCODE_READ_BLOCK_RESPONSE:
659 case TCODE_LOCK_REQUEST:
660 case TCODE_LOCK_RESPONSE:
661 p.header[3] = cond_le32_to_cpu(buffer[3]);
662 p.header_length = 16;
663 p.payload_length = p.header[3] >> 16;
666 case TCODE_WRITE_RESPONSE:
667 case TCODE_READ_QUADLET_REQUEST:
668 case OHCI_TCODE_PHY_PACKET:
669 p.header_length = 12;
670 p.payload_length = 0;
674 /* FIXME: Stop context, discard everything, and restart? */
676 p.payload_length = 0;
679 p.payload = (void *) buffer + p.header_length;
681 /* FIXME: What to do about evt_* errors? */
682 length = (p.header_length + p.payload_length + 3) / 4;
683 status = cond_le32_to_cpu(buffer[length]);
684 evt = (status >> 16) & 0x1f;
687 p.speed = (status >> 21) & 0x7;
688 p.timestamp = status & 0xffff;
689 p.generation = ohci->request_generation;
691 log_ar_at_event('R', p.speed, p.header, evt);
694 * The OHCI bus reset handler synthesizes a phy packet with
695 * the new generation number when a bus reset happens (see
696 * section 8.4.2.3). This helps us determine when a request
697 * was received and make sure we send the response in the same
698 * generation. We only need this for requests; for responses
699 * we use the unique tlabel for finding the matching
702 * Alas some chips sometimes emit bus reset packets with a
703 * wrong generation. We set the correct generation for these
704 * at a slightly incorrect time (in bus_reset_tasklet).
706 if (evt == OHCI1394_evt_bus_reset) {
707 if (!(ohci->quirks & QUIRK_RESET_PACKET))
708 ohci->request_generation = (p.header[2] >> 16) & 0xff;
709 } else if (ctx == &ohci->ar_request_ctx) {
710 fw_core_handle_request(&ohci->card, &p);
712 fw_core_handle_response(&ohci->card, &p);
715 return buffer + length + 1;
718 static void ar_context_tasklet(unsigned long data)
720 struct ar_context *ctx = (struct ar_context *)data;
721 struct fw_ohci *ohci = ctx->ohci;
722 struct ar_buffer *ab;
723 struct descriptor *d;
726 ab = ctx->current_buffer;
729 if (d->res_count == 0) {
730 size_t size, rest, offset;
731 dma_addr_t start_bus;
735 * This descriptor is finished and we may have a
736 * packet split across this and the next buffer. We
737 * reuse the page for reassembling the split packet.
740 offset = offsetof(struct ar_buffer, data);
742 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
746 size = buffer + PAGE_SIZE - ctx->pointer;
747 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
748 memmove(buffer, ctx->pointer, size);
749 memcpy(buffer + size, ab->data, rest);
750 ctx->current_buffer = ab;
751 ctx->pointer = (void *) ab->data + rest;
752 end = buffer + size + rest;
755 buffer = handle_ar_packet(ctx, buffer);
757 dma_free_coherent(ohci->card.device, PAGE_SIZE,
759 ar_context_add_page(ctx);
761 buffer = ctx->pointer;
763 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
766 buffer = handle_ar_packet(ctx, buffer);
770 static int ar_context_init(struct ar_context *ctx,
771 struct fw_ohci *ohci, u32 regs)
777 ctx->last_buffer = &ab;
778 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
780 ar_context_add_page(ctx);
781 ar_context_add_page(ctx);
782 ctx->current_buffer = ab.next;
783 ctx->pointer = ctx->current_buffer->data;
788 static void ar_context_run(struct ar_context *ctx)
790 struct ar_buffer *ab = ctx->current_buffer;
794 offset = offsetof(struct ar_buffer, data);
795 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
797 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
798 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
799 flush_writes(ctx->ohci);
802 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
806 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
807 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
809 /* figure out which descriptor the branch address goes in */
810 if (z == 2 && (b == 3 || key == 2))
816 static void context_tasklet(unsigned long data)
818 struct context *ctx = (struct context *) data;
819 struct descriptor *d, *last;
822 struct descriptor_buffer *desc;
824 desc = list_entry(ctx->buffer_list.next,
825 struct descriptor_buffer, list);
827 while (last->branch_address != 0) {
828 struct descriptor_buffer *old_desc = desc;
829 address = le32_to_cpu(last->branch_address);
833 /* If the branch address points to a buffer outside of the
834 * current buffer, advance to the next buffer. */
835 if (address < desc->buffer_bus ||
836 address >= desc->buffer_bus + desc->used)
837 desc = list_entry(desc->list.next,
838 struct descriptor_buffer, list);
839 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
840 last = find_branch_descriptor(d, z);
842 if (!ctx->callback(ctx, d, last))
845 if (old_desc != desc) {
846 /* If we've advanced to the next buffer, move the
847 * previous buffer to the free list. */
850 spin_lock_irqsave(&ctx->ohci->lock, flags);
851 list_move_tail(&old_desc->list, &ctx->buffer_list);
852 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
859 * Allocate a new buffer and add it to the list of free buffers for this
860 * context. Must be called with ohci->lock held.
862 static int context_add_buffer(struct context *ctx)
864 struct descriptor_buffer *desc;
865 dma_addr_t uninitialized_var(bus_addr);
869 * 16MB of descriptors should be far more than enough for any DMA
870 * program. This will catch run-away userspace or DoS attacks.
872 if (ctx->total_allocation >= 16*1024*1024)
875 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
876 &bus_addr, GFP_ATOMIC);
880 offset = (void *)&desc->buffer - (void *)desc;
881 desc->buffer_size = PAGE_SIZE - offset;
882 desc->buffer_bus = bus_addr + offset;
885 list_add_tail(&desc->list, &ctx->buffer_list);
886 ctx->total_allocation += PAGE_SIZE;
891 static int context_init(struct context *ctx, struct fw_ohci *ohci,
892 u32 regs, descriptor_callback_t callback)
896 ctx->total_allocation = 0;
898 INIT_LIST_HEAD(&ctx->buffer_list);
899 if (context_add_buffer(ctx) < 0)
902 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
903 struct descriptor_buffer, list);
905 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
906 ctx->callback = callback;
909 * We put a dummy descriptor in the buffer that has a NULL
910 * branch address and looks like it's been sent. That way we
911 * have a descriptor to append DMA programs to.
913 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
914 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
915 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
916 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
917 ctx->last = ctx->buffer_tail->buffer;
918 ctx->prev = ctx->buffer_tail->buffer;
923 static void context_release(struct context *ctx)
925 struct fw_card *card = &ctx->ohci->card;
926 struct descriptor_buffer *desc, *tmp;
928 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
929 dma_free_coherent(card->device, PAGE_SIZE, desc,
931 ((void *)&desc->buffer - (void *)desc));
934 /* Must be called with ohci->lock held */
935 static struct descriptor *context_get_descriptors(struct context *ctx,
936 int z, dma_addr_t *d_bus)
938 struct descriptor *d = NULL;
939 struct descriptor_buffer *desc = ctx->buffer_tail;
941 if (z * sizeof(*d) > desc->buffer_size)
944 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
945 /* No room for the descriptor in this buffer, so advance to the
948 if (desc->list.next == &ctx->buffer_list) {
949 /* If there is no free buffer next in the list,
951 if (context_add_buffer(ctx) < 0)
954 desc = list_entry(desc->list.next,
955 struct descriptor_buffer, list);
956 ctx->buffer_tail = desc;
959 d = desc->buffer + desc->used / sizeof(*d);
960 memset(d, 0, z * sizeof(*d));
961 *d_bus = desc->buffer_bus + desc->used;
966 static void context_run(struct context *ctx, u32 extra)
968 struct fw_ohci *ohci = ctx->ohci;
970 reg_write(ohci, COMMAND_PTR(ctx->regs),
971 le32_to_cpu(ctx->last->branch_address));
972 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
973 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
977 static void context_append(struct context *ctx,
978 struct descriptor *d, int z, int extra)
981 struct descriptor_buffer *desc = ctx->buffer_tail;
983 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
985 desc->used += (z + extra) * sizeof(*d);
987 wmb(); /* finish init of new descriptors before branch_address update */
988 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
989 ctx->prev = find_branch_descriptor(d, z);
991 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
992 flush_writes(ctx->ohci);
995 static void context_stop(struct context *ctx)
1000 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1001 flush_writes(ctx->ohci);
1003 for (i = 0; i < 10; i++) {
1004 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1005 if ((reg & CONTEXT_ACTIVE) == 0)
1010 fw_error("Error: DMA context still active (0x%08x)\n", reg);
1013 struct driver_data {
1014 struct fw_packet *packet;
1018 * This function apppends a packet to the DMA queue for transmission.
1019 * Must always be called with the ochi->lock held to ensure proper
1020 * generation handling and locking around packet queue manipulation.
1022 static int at_context_queue_packet(struct context *ctx,
1023 struct fw_packet *packet)
1025 struct fw_ohci *ohci = ctx->ohci;
1026 dma_addr_t d_bus, uninitialized_var(payload_bus);
1027 struct driver_data *driver_data;
1028 struct descriptor *d, *last;
1033 d = context_get_descriptors(ctx, 4, &d_bus);
1035 packet->ack = RCODE_SEND_ERROR;
1039 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1040 d[0].res_count = cpu_to_le16(packet->timestamp);
1043 * The DMA format for asyncronous link packets is different
1044 * from the IEEE1394 layout, so shift the fields around
1045 * accordingly. If header_length is 8, it's a PHY packet, to
1046 * which we need to prepend an extra quadlet.
1049 header = (__le32 *) &d[1];
1050 switch (packet->header_length) {
1053 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1054 (packet->speed << 16));
1055 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1056 (packet->header[0] & 0xffff0000));
1057 header[2] = cpu_to_le32(packet->header[2]);
1059 tcode = (packet->header[0] >> 4) & 0x0f;
1060 if (TCODE_IS_BLOCK_PACKET(tcode))
1061 header[3] = cpu_to_le32(packet->header[3]);
1063 header[3] = (__force __le32) packet->header[3];
1065 d[0].req_count = cpu_to_le16(packet->header_length);
1069 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1070 (packet->speed << 16));
1071 header[1] = cpu_to_le32(packet->header[0]);
1072 header[2] = cpu_to_le32(packet->header[1]);
1073 d[0].req_count = cpu_to_le16(12);
1075 if (is_ping_packet(packet->header))
1076 d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1080 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1081 (packet->speed << 16));
1082 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1083 d[0].req_count = cpu_to_le16(8);
1088 packet->ack = RCODE_SEND_ERROR;
1092 driver_data = (struct driver_data *) &d[3];
1093 driver_data->packet = packet;
1094 packet->driver_data = driver_data;
1096 if (packet->payload_length > 0) {
1098 dma_map_single(ohci->card.device, packet->payload,
1099 packet->payload_length, DMA_TO_DEVICE);
1100 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1101 packet->ack = RCODE_SEND_ERROR;
1104 packet->payload_bus = payload_bus;
1105 packet->payload_mapped = true;
1107 d[2].req_count = cpu_to_le16(packet->payload_length);
1108 d[2].data_address = cpu_to_le32(payload_bus);
1116 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1117 DESCRIPTOR_IRQ_ALWAYS |
1118 DESCRIPTOR_BRANCH_ALWAYS);
1121 * If the controller and packet generations don't match, we need to
1122 * bail out and try again. If IntEvent.busReset is set, the AT context
1123 * is halted, so appending to the context and trying to run it is
1124 * futile. Most controllers do the right thing and just flush the AT
1125 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1126 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1127 * up stalling out. So we just bail out in software and try again
1128 * later, and everyone is happy.
1129 * FIXME: Document how the locking works.
1131 if (ohci->generation != packet->generation ||
1132 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1133 if (packet->payload_mapped)
1134 dma_unmap_single(ohci->card.device, payload_bus,
1135 packet->payload_length, DMA_TO_DEVICE);
1136 packet->ack = RCODE_GENERATION;
1140 context_append(ctx, d, z, 4 - z);
1142 /* If the context isn't already running, start it up. */
1143 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1144 if ((reg & CONTEXT_RUN) == 0)
1145 context_run(ctx, 0);
1150 static int handle_at_packet(struct context *context,
1151 struct descriptor *d,
1152 struct descriptor *last)
1154 struct driver_data *driver_data;
1155 struct fw_packet *packet;
1156 struct fw_ohci *ohci = context->ohci;
1159 if (last->transfer_status == 0)
1160 /* This descriptor isn't done yet, stop iteration. */
1163 driver_data = (struct driver_data *) &d[3];
1164 packet = driver_data->packet;
1166 /* This packet was cancelled, just continue. */
1169 if (packet->payload_mapped)
1170 dma_unmap_single(ohci->card.device, packet->payload_bus,
1171 packet->payload_length, DMA_TO_DEVICE);
1173 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1174 packet->timestamp = le16_to_cpu(last->res_count);
1176 log_ar_at_event('T', packet->speed, packet->header, evt);
1179 case OHCI1394_evt_timeout:
1180 /* Async response transmit timed out. */
1181 packet->ack = RCODE_CANCELLED;
1184 case OHCI1394_evt_flushed:
1186 * The packet was flushed should give same error as
1187 * when we try to use a stale generation count.
1189 packet->ack = RCODE_GENERATION;
1192 case OHCI1394_evt_missing_ack:
1194 * Using a valid (current) generation count, but the
1195 * node is not on the bus or not sending acks.
1197 packet->ack = RCODE_NO_ACK;
1200 case ACK_COMPLETE + 0x10:
1201 case ACK_PENDING + 0x10:
1202 case ACK_BUSY_X + 0x10:
1203 case ACK_BUSY_A + 0x10:
1204 case ACK_BUSY_B + 0x10:
1205 case ACK_DATA_ERROR + 0x10:
1206 case ACK_TYPE_ERROR + 0x10:
1207 packet->ack = evt - 0x10;
1211 packet->ack = RCODE_SEND_ERROR;
1215 packet->callback(packet, &ohci->card, packet->ack);
1220 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1221 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1222 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1223 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1224 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1226 static void handle_local_rom(struct fw_ohci *ohci,
1227 struct fw_packet *packet, u32 csr)
1229 struct fw_packet response;
1230 int tcode, length, i;
1232 tcode = HEADER_GET_TCODE(packet->header[0]);
1233 if (TCODE_IS_BLOCK_PACKET(tcode))
1234 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1238 i = csr - CSR_CONFIG_ROM;
1239 if (i + length > CONFIG_ROM_SIZE) {
1240 fw_fill_response(&response, packet->header,
1241 RCODE_ADDRESS_ERROR, NULL, 0);
1242 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1243 fw_fill_response(&response, packet->header,
1244 RCODE_TYPE_ERROR, NULL, 0);
1246 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1247 (void *) ohci->config_rom + i, length);
1250 fw_core_handle_response(&ohci->card, &response);
1253 static void handle_local_lock(struct fw_ohci *ohci,
1254 struct fw_packet *packet, u32 csr)
1256 struct fw_packet response;
1257 int tcode, length, ext_tcode, sel;
1258 __be32 *payload, lock_old;
1259 u32 lock_arg, lock_data;
1261 tcode = HEADER_GET_TCODE(packet->header[0]);
1262 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1263 payload = packet->payload;
1264 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1266 if (tcode == TCODE_LOCK_REQUEST &&
1267 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1268 lock_arg = be32_to_cpu(payload[0]);
1269 lock_data = be32_to_cpu(payload[1]);
1270 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1274 fw_fill_response(&response, packet->header,
1275 RCODE_TYPE_ERROR, NULL, 0);
1279 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1280 reg_write(ohci, OHCI1394_CSRData, lock_data);
1281 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1282 reg_write(ohci, OHCI1394_CSRControl, sel);
1284 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1285 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1287 fw_notify("swap not done yet\n");
1289 fw_fill_response(&response, packet->header,
1290 RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1292 fw_core_handle_response(&ohci->card, &response);
1295 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1300 if (ctx == &ctx->ohci->at_request_ctx) {
1301 packet->ack = ACK_PENDING;
1302 packet->callback(packet, &ctx->ohci->card, packet->ack);
1306 ((unsigned long long)
1307 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1309 csr = offset - CSR_REGISTER_BASE;
1311 /* Handle config rom reads. */
1312 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1313 handle_local_rom(ctx->ohci, packet, csr);
1315 case CSR_BUS_MANAGER_ID:
1316 case CSR_BANDWIDTH_AVAILABLE:
1317 case CSR_CHANNELS_AVAILABLE_HI:
1318 case CSR_CHANNELS_AVAILABLE_LO:
1319 handle_local_lock(ctx->ohci, packet, csr);
1322 if (ctx == &ctx->ohci->at_request_ctx)
1323 fw_core_handle_request(&ctx->ohci->card, packet);
1325 fw_core_handle_response(&ctx->ohci->card, packet);
1329 if (ctx == &ctx->ohci->at_response_ctx) {
1330 packet->ack = ACK_COMPLETE;
1331 packet->callback(packet, &ctx->ohci->card, packet->ack);
1335 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1337 unsigned long flags;
1340 spin_lock_irqsave(&ctx->ohci->lock, flags);
1342 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1343 ctx->ohci->generation == packet->generation) {
1344 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1345 handle_local_request(ctx, packet);
1349 ret = at_context_queue_packet(ctx, packet);
1350 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1353 packet->callback(packet, &ctx->ohci->card, packet->ack);
1357 static u32 cycle_timer_ticks(u32 cycle_timer)
1361 ticks = cycle_timer & 0xfff;
1362 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1363 ticks += (3072 * 8000) * (cycle_timer >> 25);
1369 * Some controllers exhibit one or more of the following bugs when updating the
1370 * iso cycle timer register:
1371 * - When the lowest six bits are wrapping around to zero, a read that happens
1372 * at the same time will return garbage in the lowest ten bits.
1373 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1374 * not incremented for about 60 ns.
1375 * - Occasionally, the entire register reads zero.
1377 * To catch these, we read the register three times and ensure that the
1378 * difference between each two consecutive reads is approximately the same, i.e.
1379 * less than twice the other. Furthermore, any negative difference indicates an
1380 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1381 * execute, so we have enough precision to compute the ratio of the differences.)
1383 static u32 get_cycle_time(struct fw_ohci *ohci)
1390 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1392 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1395 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1399 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1400 t0 = cycle_timer_ticks(c0);
1401 t1 = cycle_timer_ticks(c1);
1402 t2 = cycle_timer_ticks(c2);
1405 } while ((diff01 <= 0 || diff12 <= 0 ||
1406 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1414 * This function has to be called at least every 64 seconds. The bus_time
1415 * field stores not only the upper 25 bits of the BUS_TIME register but also
1416 * the most significant bit of the cycle timer in bit 6 so that we can detect
1417 * changes in this bit.
1419 static u32 update_bus_time(struct fw_ohci *ohci)
1421 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1423 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1424 ohci->bus_time += 0x40;
1426 return ohci->bus_time | cycle_time_seconds;
1429 static void bus_reset_tasklet(unsigned long data)
1431 struct fw_ohci *ohci = (struct fw_ohci *)data;
1432 int self_id_count, i, j, reg;
1433 int generation, new_generation;
1434 unsigned long flags;
1435 void *free_rom = NULL;
1436 dma_addr_t free_rom_bus = 0;
1439 reg = reg_read(ohci, OHCI1394_NodeID);
1440 if (!(reg & OHCI1394_NodeID_idValid)) {
1441 fw_notify("node ID not valid, new bus reset in progress\n");
1444 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1445 fw_notify("malconfigured bus\n");
1448 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1449 OHCI1394_NodeID_nodeNumber);
1451 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1452 if (!(ohci->is_root && is_new_root))
1453 reg_write(ohci, OHCI1394_LinkControlSet,
1454 OHCI1394_LinkControl_cycleMaster);
1455 ohci->is_root = is_new_root;
1457 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1458 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1459 fw_notify("inconsistent self IDs\n");
1463 * The count in the SelfIDCount register is the number of
1464 * bytes in the self ID receive buffer. Since we also receive
1465 * the inverted quadlets and a header quadlet, we shift one
1466 * bit extra to get the actual number of self IDs.
1468 self_id_count = (reg >> 3) & 0xff;
1469 if (self_id_count == 0 || self_id_count > 252) {
1470 fw_notify("inconsistent self IDs\n");
1473 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1476 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1477 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1478 fw_notify("inconsistent self IDs\n");
1481 ohci->self_id_buffer[j] =
1482 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1487 * Check the consistency of the self IDs we just read. The
1488 * problem we face is that a new bus reset can start while we
1489 * read out the self IDs from the DMA buffer. If this happens,
1490 * the DMA buffer will be overwritten with new self IDs and we
1491 * will read out inconsistent data. The OHCI specification
1492 * (section 11.2) recommends a technique similar to
1493 * linux/seqlock.h, where we remember the generation of the
1494 * self IDs in the buffer before reading them out and compare
1495 * it to the current generation after reading them out. If
1496 * the two generations match we know we have a consistent set
1500 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1501 if (new_generation != generation) {
1502 fw_notify("recursive bus reset detected, "
1503 "discarding self ids\n");
1507 /* FIXME: Document how the locking works. */
1508 spin_lock_irqsave(&ohci->lock, flags);
1510 ohci->generation = generation;
1511 context_stop(&ohci->at_request_ctx);
1512 context_stop(&ohci->at_response_ctx);
1513 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1515 if (ohci->quirks & QUIRK_RESET_PACKET)
1516 ohci->request_generation = generation;
1519 * This next bit is unrelated to the AT context stuff but we
1520 * have to do it under the spinlock also. If a new config rom
1521 * was set up before this reset, the old one is now no longer
1522 * in use and we can free it. Update the config rom pointers
1523 * to point to the current config rom and clear the
1524 * next_config_rom pointer so a new udpate can take place.
1527 if (ohci->next_config_rom != NULL) {
1528 if (ohci->next_config_rom != ohci->config_rom) {
1529 free_rom = ohci->config_rom;
1530 free_rom_bus = ohci->config_rom_bus;
1532 ohci->config_rom = ohci->next_config_rom;
1533 ohci->config_rom_bus = ohci->next_config_rom_bus;
1534 ohci->next_config_rom = NULL;
1537 * Restore config_rom image and manually update
1538 * config_rom registers. Writing the header quadlet
1539 * will indicate that the config rom is ready, so we
1542 reg_write(ohci, OHCI1394_BusOptions,
1543 be32_to_cpu(ohci->config_rom[2]));
1544 ohci->config_rom[0] = ohci->next_header;
1545 reg_write(ohci, OHCI1394_ConfigROMhdr,
1546 be32_to_cpu(ohci->next_header));
1549 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1550 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1551 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1554 spin_unlock_irqrestore(&ohci->lock, flags);
1557 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1558 free_rom, free_rom_bus);
1560 log_selfids(ohci->node_id, generation,
1561 self_id_count, ohci->self_id_buffer);
1563 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1564 self_id_count, ohci->self_id_buffer,
1565 ohci->csr_state_setclear_abdicate);
1566 ohci->csr_state_setclear_abdicate = false;
1569 static irqreturn_t irq_handler(int irq, void *data)
1571 struct fw_ohci *ohci = data;
1572 u32 event, iso_event;
1575 event = reg_read(ohci, OHCI1394_IntEventClear);
1577 if (!event || !~event)
1580 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1581 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1584 if (event & OHCI1394_selfIDComplete)
1585 tasklet_schedule(&ohci->bus_reset_tasklet);
1587 if (event & OHCI1394_RQPkt)
1588 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1590 if (event & OHCI1394_RSPkt)
1591 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1593 if (event & OHCI1394_reqTxComplete)
1594 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1596 if (event & OHCI1394_respTxComplete)
1597 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1599 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1600 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1603 i = ffs(iso_event) - 1;
1604 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1605 iso_event &= ~(1 << i);
1608 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1609 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1612 i = ffs(iso_event) - 1;
1613 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1614 iso_event &= ~(1 << i);
1617 if (unlikely(event & OHCI1394_regAccessFail))
1618 fw_error("Register access failure - "
1619 "please notify linux1394-devel@lists.sf.net\n");
1621 if (unlikely(event & OHCI1394_postedWriteErr))
1622 fw_error("PCI posted write error\n");
1624 if (unlikely(event & OHCI1394_cycleTooLong)) {
1625 if (printk_ratelimit())
1626 fw_notify("isochronous cycle too long\n");
1627 reg_write(ohci, OHCI1394_LinkControlSet,
1628 OHCI1394_LinkControl_cycleMaster);
1631 if (unlikely(event & OHCI1394_cycleInconsistent)) {
1633 * We need to clear this event bit in order to make
1634 * cycleMatch isochronous I/O work. In theory we should
1635 * stop active cycleMatch iso contexts now and restart
1636 * them at least two cycles later. (FIXME?)
1638 if (printk_ratelimit())
1639 fw_notify("isochronous cycle inconsistent\n");
1642 if (event & OHCI1394_cycle64Seconds) {
1643 spin_lock(&ohci->lock);
1644 update_bus_time(ohci);
1645 spin_unlock(&ohci->lock);
1651 static int software_reset(struct fw_ohci *ohci)
1655 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1657 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1658 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1659 OHCI1394_HCControl_softReset) == 0)
1667 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1669 size_t size = length * 4;
1671 memcpy(dest, src, size);
1672 if (size < CONFIG_ROM_SIZE)
1673 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1676 static int configure_1394a_enhancements(struct fw_ohci *ohci)
1679 int ret, clear, set, offset;
1681 /* Check if the driver should configure link and PHY. */
1682 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
1683 OHCI1394_HCControl_programPhyEnable))
1686 /* Paranoia: check whether the PHY supports 1394a, too. */
1687 enable_1394a = false;
1688 ret = read_phy_reg(ohci, 2);
1691 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
1692 ret = read_paged_phy_reg(ohci, 1, 8);
1696 enable_1394a = true;
1699 if (ohci->quirks & QUIRK_NO_1394A)
1700 enable_1394a = false;
1702 /* Configure PHY and link consistently. */
1705 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1707 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1710 ret = update_phy_reg(ohci, 5, clear, set);
1715 offset = OHCI1394_HCControlSet;
1717 offset = OHCI1394_HCControlClear;
1718 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
1720 /* Clean up: configuration has been taken care of. */
1721 reg_write(ohci, OHCI1394_HCControlClear,
1722 OHCI1394_HCControl_programPhyEnable);
1727 static int ohci_enable(struct fw_card *card,
1728 const __be32 *config_rom, size_t length)
1730 struct fw_ohci *ohci = fw_ohci(card);
1731 struct pci_dev *dev = to_pci_dev(card->device);
1732 u32 lps, seconds, version, irqs;
1735 if (software_reset(ohci)) {
1736 fw_error("Failed to reset ohci card.\n");
1741 * Now enable LPS, which we need in order to start accessing
1742 * most of the registers. In fact, on some cards (ALI M5251),
1743 * accessing registers in the SClk domain without LPS enabled
1744 * will lock up the machine. Wait 50msec to make sure we have
1745 * full link enabled. However, with some cards (well, at least
1746 * a JMicron PCIe card), we have to try again sometimes.
1748 reg_write(ohci, OHCI1394_HCControlSet,
1749 OHCI1394_HCControl_LPS |
1750 OHCI1394_HCControl_postedWriteEnable);
1753 for (lps = 0, i = 0; !lps && i < 3; i++) {
1755 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1756 OHCI1394_HCControl_LPS;
1760 fw_error("Failed to set Link Power Status\n");
1764 reg_write(ohci, OHCI1394_HCControlClear,
1765 OHCI1394_HCControl_noByteSwapData);
1767 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1768 reg_write(ohci, OHCI1394_LinkControlSet,
1769 OHCI1394_LinkControl_rcvSelfID |
1770 OHCI1394_LinkControl_rcvPhyPkt |
1771 OHCI1394_LinkControl_cycleTimerEnable |
1772 OHCI1394_LinkControl_cycleMaster);
1774 reg_write(ohci, OHCI1394_ATRetries,
1775 OHCI1394_MAX_AT_REQ_RETRIES |
1776 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1777 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
1780 seconds = lower_32_bits(get_seconds());
1781 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
1782 ohci->bus_time = seconds & ~0x3f;
1784 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
1785 if (version >= OHCI_VERSION_1_1) {
1786 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
1788 card->broadcast_channel_auto_allocated = true;
1791 /* Get implemented bits of the priority arbitration request counter. */
1792 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
1793 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
1794 reg_write(ohci, OHCI1394_FairnessControl, 0);
1795 card->priority_budget_implemented = ohci->pri_req_max != 0;
1797 ar_context_run(&ohci->ar_request_ctx);
1798 ar_context_run(&ohci->ar_response_ctx);
1800 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1801 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1802 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1804 ret = configure_1394a_enhancements(ohci);
1808 /* Activate link_on bit and contender bit in our self ID packets.*/
1809 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
1814 * When the link is not yet enabled, the atomic config rom
1815 * update mechanism described below in ohci_set_config_rom()
1816 * is not active. We have to update ConfigRomHeader and
1817 * BusOptions manually, and the write to ConfigROMmap takes
1818 * effect immediately. We tie this to the enabling of the
1819 * link, so we have a valid config rom before enabling - the
1820 * OHCI requires that ConfigROMhdr and BusOptions have valid
1821 * values before enabling.
1823 * However, when the ConfigROMmap is written, some controllers
1824 * always read back quadlets 0 and 2 from the config rom to
1825 * the ConfigRomHeader and BusOptions registers on bus reset.
1826 * They shouldn't do that in this initial case where the link
1827 * isn't enabled. This means we have to use the same
1828 * workaround here, setting the bus header to 0 and then write
1829 * the right values in the bus reset tasklet.
1833 ohci->next_config_rom =
1834 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1835 &ohci->next_config_rom_bus,
1837 if (ohci->next_config_rom == NULL)
1840 copy_config_rom(ohci->next_config_rom, config_rom, length);
1843 * In the suspend case, config_rom is NULL, which
1844 * means that we just reuse the old config rom.
1846 ohci->next_config_rom = ohci->config_rom;
1847 ohci->next_config_rom_bus = ohci->config_rom_bus;
1850 ohci->next_header = ohci->next_config_rom[0];
1851 ohci->next_config_rom[0] = 0;
1852 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1853 reg_write(ohci, OHCI1394_BusOptions,
1854 be32_to_cpu(ohci->next_config_rom[2]));
1855 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1857 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1859 if (!(ohci->quirks & QUIRK_NO_MSI))
1860 pci_enable_msi(dev);
1861 if (request_irq(dev->irq, irq_handler,
1862 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
1863 ohci_driver_name, ohci)) {
1864 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
1865 pci_disable_msi(dev);
1866 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1867 ohci->config_rom, ohci->config_rom_bus);
1871 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1872 OHCI1394_RQPkt | OHCI1394_RSPkt |
1873 OHCI1394_isochTx | OHCI1394_isochRx |
1874 OHCI1394_postedWriteErr |
1875 OHCI1394_selfIDComplete |
1876 OHCI1394_regAccessFail |
1877 OHCI1394_cycle64Seconds |
1878 OHCI1394_cycleInconsistent | OHCI1394_cycleTooLong |
1879 OHCI1394_masterIntEnable;
1880 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1881 irqs |= OHCI1394_busReset;
1882 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
1884 reg_write(ohci, OHCI1394_HCControlSet,
1885 OHCI1394_HCControl_linkEnable |
1886 OHCI1394_HCControl_BIBimageValid);
1889 /* We are ready to go, reset bus to finish initialization. */
1890 fw_schedule_bus_reset(&ohci->card, false, true);
1895 static int ohci_set_config_rom(struct fw_card *card,
1896 const __be32 *config_rom, size_t length)
1898 struct fw_ohci *ohci;
1899 unsigned long flags;
1901 __be32 *next_config_rom;
1902 dma_addr_t uninitialized_var(next_config_rom_bus);
1904 ohci = fw_ohci(card);
1907 * When the OHCI controller is enabled, the config rom update
1908 * mechanism is a bit tricky, but easy enough to use. See
1909 * section 5.5.6 in the OHCI specification.
1911 * The OHCI controller caches the new config rom address in a
1912 * shadow register (ConfigROMmapNext) and needs a bus reset
1913 * for the changes to take place. When the bus reset is
1914 * detected, the controller loads the new values for the
1915 * ConfigRomHeader and BusOptions registers from the specified
1916 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1917 * shadow register. All automatically and atomically.
1919 * Now, there's a twist to this story. The automatic load of
1920 * ConfigRomHeader and BusOptions doesn't honor the
1921 * noByteSwapData bit, so with a be32 config rom, the
1922 * controller will load be32 values in to these registers
1923 * during the atomic update, even on litte endian
1924 * architectures. The workaround we use is to put a 0 in the
1925 * header quadlet; 0 is endian agnostic and means that the
1926 * config rom isn't ready yet. In the bus reset tasklet we
1927 * then set up the real values for the two registers.
1929 * We use ohci->lock to avoid racing with the code that sets
1930 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1934 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1935 &next_config_rom_bus, GFP_KERNEL);
1936 if (next_config_rom == NULL)
1939 spin_lock_irqsave(&ohci->lock, flags);
1941 if (ohci->next_config_rom == NULL) {
1942 ohci->next_config_rom = next_config_rom;
1943 ohci->next_config_rom_bus = next_config_rom_bus;
1945 copy_config_rom(ohci->next_config_rom, config_rom, length);
1947 ohci->next_header = config_rom[0];
1948 ohci->next_config_rom[0] = 0;
1950 reg_write(ohci, OHCI1394_ConfigROMmap,
1951 ohci->next_config_rom_bus);
1955 spin_unlock_irqrestore(&ohci->lock, flags);
1958 * Now initiate a bus reset to have the changes take
1959 * effect. We clean up the old config rom memory and DMA
1960 * mappings in the bus reset tasklet, since the OHCI
1961 * controller could need to access it before the bus reset
1965 fw_schedule_bus_reset(&ohci->card, true, true);
1967 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1968 next_config_rom, next_config_rom_bus);
1973 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1975 struct fw_ohci *ohci = fw_ohci(card);
1977 at_context_transmit(&ohci->at_request_ctx, packet);
1980 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1982 struct fw_ohci *ohci = fw_ohci(card);
1984 at_context_transmit(&ohci->at_response_ctx, packet);
1987 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1989 struct fw_ohci *ohci = fw_ohci(card);
1990 struct context *ctx = &ohci->at_request_ctx;
1991 struct driver_data *driver_data = packet->driver_data;
1994 tasklet_disable(&ctx->tasklet);
1996 if (packet->ack != 0)
1999 if (packet->payload_mapped)
2000 dma_unmap_single(ohci->card.device, packet->payload_bus,
2001 packet->payload_length, DMA_TO_DEVICE);
2003 log_ar_at_event('T', packet->speed, packet->header, 0x20);
2004 driver_data->packet = NULL;
2005 packet->ack = RCODE_CANCELLED;
2006 packet->callback(packet, &ohci->card, packet->ack);
2009 tasklet_enable(&ctx->tasklet);
2014 static int ohci_enable_phys_dma(struct fw_card *card,
2015 int node_id, int generation)
2017 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2020 struct fw_ohci *ohci = fw_ohci(card);
2021 unsigned long flags;
2025 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2026 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2029 spin_lock_irqsave(&ohci->lock, flags);
2031 if (ohci->generation != generation) {
2037 * Note, if the node ID contains a non-local bus ID, physical DMA is
2038 * enabled for _all_ nodes on remote buses.
2041 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2043 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2045 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2049 spin_unlock_irqrestore(&ohci->lock, flags);
2052 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2055 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2057 struct fw_ohci *ohci = fw_ohci(card);
2058 unsigned long flags;
2061 switch (csr_offset) {
2062 case CSR_STATE_CLEAR:
2064 if (ohci->is_root &&
2065 (reg_read(ohci, OHCI1394_LinkControlSet) &
2066 OHCI1394_LinkControl_cycleMaster))
2067 value = CSR_STATE_BIT_CMSTR;
2070 if (ohci->csr_state_setclear_abdicate)
2071 value |= CSR_STATE_BIT_ABDICATE;
2076 return reg_read(ohci, OHCI1394_NodeID) << 16;
2078 case CSR_CYCLE_TIME:
2079 return get_cycle_time(ohci);
2083 * We might be called just after the cycle timer has wrapped
2084 * around but just before the cycle64Seconds handler, so we
2085 * better check here, too, if the bus time needs to be updated.
2087 spin_lock_irqsave(&ohci->lock, flags);
2088 value = update_bus_time(ohci);
2089 spin_unlock_irqrestore(&ohci->lock, flags);
2092 case CSR_BUSY_TIMEOUT:
2093 value = reg_read(ohci, OHCI1394_ATRetries);
2094 return (value >> 4) & 0x0ffff00f;
2096 case CSR_PRIORITY_BUDGET:
2097 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2098 (ohci->pri_req_max << 8);
2106 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2108 struct fw_ohci *ohci = fw_ohci(card);
2109 unsigned long flags;
2111 switch (csr_offset) {
2112 case CSR_STATE_CLEAR:
2113 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2114 reg_write(ohci, OHCI1394_LinkControlClear,
2115 OHCI1394_LinkControl_cycleMaster);
2118 if (value & CSR_STATE_BIT_ABDICATE)
2119 ohci->csr_state_setclear_abdicate = false;
2123 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2124 reg_write(ohci, OHCI1394_LinkControlSet,
2125 OHCI1394_LinkControl_cycleMaster);
2128 if (value & CSR_STATE_BIT_ABDICATE)
2129 ohci->csr_state_setclear_abdicate = true;
2133 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2137 case CSR_CYCLE_TIME:
2138 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2139 reg_write(ohci, OHCI1394_IntEventSet,
2140 OHCI1394_cycleInconsistent);
2145 spin_lock_irqsave(&ohci->lock, flags);
2146 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2147 spin_unlock_irqrestore(&ohci->lock, flags);
2150 case CSR_BUSY_TIMEOUT:
2151 value = (value & 0xf) | ((value & 0xf) << 4) |
2152 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2153 reg_write(ohci, OHCI1394_ATRetries, value);
2157 case CSR_PRIORITY_BUDGET:
2158 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2168 static void copy_iso_headers(struct iso_context *ctx, void *p)
2170 int i = ctx->header_length;
2172 if (i + ctx->base.header_size > PAGE_SIZE)
2176 * The iso header is byteswapped to little endian by
2177 * the controller, but the remaining header quadlets
2178 * are big endian. We want to present all the headers
2179 * as big endian, so we have to swap the first quadlet.
2181 if (ctx->base.header_size > 0)
2182 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2183 if (ctx->base.header_size > 4)
2184 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2185 if (ctx->base.header_size > 8)
2186 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2187 ctx->header_length += ctx->base.header_size;
2190 static int handle_ir_packet_per_buffer(struct context *context,
2191 struct descriptor *d,
2192 struct descriptor *last)
2194 struct iso_context *ctx =
2195 container_of(context, struct iso_context, context);
2196 struct descriptor *pd;
2200 for (pd = d; pd <= last; pd++) {
2201 if (pd->transfer_status)
2205 /* Descriptor(s) not done yet, stop iteration */
2209 copy_iso_headers(ctx, p);
2211 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2212 ir_header = (__le32 *) p;
2213 ctx->base.callback(&ctx->base,
2214 le32_to_cpu(ir_header[0]) & 0xffff,
2215 ctx->header_length, ctx->header,
2216 ctx->base.callback_data);
2217 ctx->header_length = 0;
2223 static int handle_it_packet(struct context *context,
2224 struct descriptor *d,
2225 struct descriptor *last)
2227 struct iso_context *ctx =
2228 container_of(context, struct iso_context, context);
2230 struct descriptor *pd;
2232 for (pd = d; pd <= last; pd++)
2233 if (pd->transfer_status)
2236 /* Descriptor(s) not done yet, stop iteration */
2239 i = ctx->header_length;
2240 if (i + 4 < PAGE_SIZE) {
2241 /* Present this value as big-endian to match the receive code */
2242 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2243 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2244 le16_to_cpu(pd->res_count));
2245 ctx->header_length += 4;
2247 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2248 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
2249 ctx->header_length, ctx->header,
2250 ctx->base.callback_data);
2251 ctx->header_length = 0;
2256 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2257 int type, int channel, size_t header_size)
2259 struct fw_ohci *ohci = fw_ohci(card);
2260 struct iso_context *ctx, *list;
2261 descriptor_callback_t callback;
2262 u64 *channels, dont_care = ~0ULL;
2264 unsigned long flags;
2265 int index, ret = -ENOMEM;
2267 if (type == FW_ISO_CONTEXT_TRANSMIT) {
2268 channels = &dont_care;
2269 mask = &ohci->it_context_mask;
2270 list = ohci->it_context_list;
2271 callback = handle_it_packet;
2273 channels = &ohci->ir_context_channels;
2274 mask = &ohci->ir_context_mask;
2275 list = ohci->ir_context_list;
2276 callback = handle_ir_packet_per_buffer;
2279 spin_lock_irqsave(&ohci->lock, flags);
2280 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2282 *channels &= ~(1ULL << channel);
2283 *mask &= ~(1 << index);
2285 spin_unlock_irqrestore(&ohci->lock, flags);
2288 return ERR_PTR(-EBUSY);
2290 if (type == FW_ISO_CONTEXT_TRANSMIT)
2291 regs = OHCI1394_IsoXmitContextBase(index);
2293 regs = OHCI1394_IsoRcvContextBase(index);
2296 memset(ctx, 0, sizeof(*ctx));
2297 ctx->header_length = 0;
2298 ctx->header = (void *) __get_free_page(GFP_KERNEL);
2299 if (ctx->header == NULL)
2302 ret = context_init(&ctx->context, ohci, regs, callback);
2304 goto out_with_header;
2309 free_page((unsigned long)ctx->header);
2311 spin_lock_irqsave(&ohci->lock, flags);
2312 *mask |= 1 << index;
2313 spin_unlock_irqrestore(&ohci->lock, flags);
2315 return ERR_PTR(ret);
2318 static int ohci_start_iso(struct fw_iso_context *base,
2319 s32 cycle, u32 sync, u32 tags)
2321 struct iso_context *ctx = container_of(base, struct iso_context, base);
2322 struct fw_ohci *ohci = ctx->context.ohci;
2326 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2327 index = ctx - ohci->it_context_list;
2330 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2331 (cycle & 0x7fff) << 16;
2333 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2334 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2335 context_run(&ctx->context, match);
2337 index = ctx - ohci->ir_context_list;
2338 control = IR_CONTEXT_ISOCH_HEADER;
2339 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2341 match |= (cycle & 0x07fff) << 12;
2342 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2345 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2346 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2347 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2348 context_run(&ctx->context, control);
2354 static int ohci_stop_iso(struct fw_iso_context *base)
2356 struct fw_ohci *ohci = fw_ohci(base->card);
2357 struct iso_context *ctx = container_of(base, struct iso_context, base);
2360 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2361 index = ctx - ohci->it_context_list;
2362 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2364 index = ctx - ohci->ir_context_list;
2365 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2368 context_stop(&ctx->context);
2373 static void ohci_free_iso_context(struct fw_iso_context *base)
2375 struct fw_ohci *ohci = fw_ohci(base->card);
2376 struct iso_context *ctx = container_of(base, struct iso_context, base);
2377 unsigned long flags;
2380 ohci_stop_iso(base);
2381 context_release(&ctx->context);
2382 free_page((unsigned long)ctx->header);
2384 spin_lock_irqsave(&ohci->lock, flags);
2386 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2387 index = ctx - ohci->it_context_list;
2388 ohci->it_context_mask |= 1 << index;
2390 index = ctx - ohci->ir_context_list;
2391 ohci->ir_context_mask |= 1 << index;
2392 ohci->ir_context_channels |= 1ULL << base->channel;
2395 spin_unlock_irqrestore(&ohci->lock, flags);
2398 static int ohci_queue_iso_transmit(struct fw_iso_context *base,
2399 struct fw_iso_packet *packet,
2400 struct fw_iso_buffer *buffer,
2401 unsigned long payload)
2403 struct iso_context *ctx = container_of(base, struct iso_context, base);
2404 struct descriptor *d, *last, *pd;
2405 struct fw_iso_packet *p;
2407 dma_addr_t d_bus, page_bus;
2408 u32 z, header_z, payload_z, irq;
2409 u32 payload_index, payload_end_index, next_page_index;
2410 int page, end_page, i, length, offset;
2413 payload_index = payload;
2419 if (p->header_length > 0)
2422 /* Determine the first page the payload isn't contained in. */
2423 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2424 if (p->payload_length > 0)
2425 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2431 /* Get header size in number of descriptors. */
2432 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2434 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2439 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2440 d[0].req_count = cpu_to_le16(8);
2442 * Link the skip address to this descriptor itself. This causes
2443 * a context to skip a cycle whenever lost cycles or FIFO
2444 * overruns occur, without dropping the data. The application
2445 * should then decide whether this is an error condition or not.
2446 * FIXME: Make the context's cycle-lost behaviour configurable?
2448 d[0].branch_address = cpu_to_le32(d_bus | z);
2450 header = (__le32 *) &d[1];
2451 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2452 IT_HEADER_TAG(p->tag) |
2453 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2454 IT_HEADER_CHANNEL(ctx->base.channel) |
2455 IT_HEADER_SPEED(ctx->base.speed));
2457 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2458 p->payload_length));
2461 if (p->header_length > 0) {
2462 d[2].req_count = cpu_to_le16(p->header_length);
2463 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2464 memcpy(&d[z], p->header, p->header_length);
2467 pd = d + z - payload_z;
2468 payload_end_index = payload_index + p->payload_length;
2469 for (i = 0; i < payload_z; i++) {
2470 page = payload_index >> PAGE_SHIFT;
2471 offset = payload_index & ~PAGE_MASK;
2472 next_page_index = (page + 1) << PAGE_SHIFT;
2474 min(next_page_index, payload_end_index) - payload_index;
2475 pd[i].req_count = cpu_to_le16(length);
2477 page_bus = page_private(buffer->pages[page]);
2478 pd[i].data_address = cpu_to_le32(page_bus + offset);
2480 payload_index += length;
2484 irq = DESCRIPTOR_IRQ_ALWAYS;
2486 irq = DESCRIPTOR_NO_IRQ;
2488 last = z == 2 ? d : d + z - 1;
2489 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2491 DESCRIPTOR_BRANCH_ALWAYS |
2494 context_append(&ctx->context, d, z, header_z);
2499 static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2500 struct fw_iso_packet *packet,
2501 struct fw_iso_buffer *buffer,
2502 unsigned long payload)
2504 struct iso_context *ctx = container_of(base, struct iso_context, base);
2505 struct descriptor *d, *pd;
2506 struct fw_iso_packet *p = packet;
2507 dma_addr_t d_bus, page_bus;
2508 u32 z, header_z, rest;
2510 int page, offset, packet_count, header_size, payload_per_buffer;
2513 * The OHCI controller puts the isochronous header and trailer in the
2514 * buffer, so we need at least 8 bytes.
2516 packet_count = p->header_length / ctx->base.header_size;
2517 header_size = max(ctx->base.header_size, (size_t)8);
2519 /* Get header size in number of descriptors. */
2520 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2521 page = payload >> PAGE_SHIFT;
2522 offset = payload & ~PAGE_MASK;
2523 payload_per_buffer = p->payload_length / packet_count;
2525 for (i = 0; i < packet_count; i++) {
2526 /* d points to the header descriptor */
2527 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2528 d = context_get_descriptors(&ctx->context,
2529 z + header_z, &d_bus);
2533 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2534 DESCRIPTOR_INPUT_MORE);
2535 if (p->skip && i == 0)
2536 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2537 d->req_count = cpu_to_le16(header_size);
2538 d->res_count = d->req_count;
2539 d->transfer_status = 0;
2540 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2542 rest = payload_per_buffer;
2544 for (j = 1; j < z; j++) {
2546 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2547 DESCRIPTOR_INPUT_MORE);
2549 if (offset + rest < PAGE_SIZE)
2552 length = PAGE_SIZE - offset;
2553 pd->req_count = cpu_to_le16(length);
2554 pd->res_count = pd->req_count;
2555 pd->transfer_status = 0;
2557 page_bus = page_private(buffer->pages[page]);
2558 pd->data_address = cpu_to_le32(page_bus + offset);
2560 offset = (offset + length) & ~PAGE_MASK;
2565 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2566 DESCRIPTOR_INPUT_LAST |
2567 DESCRIPTOR_BRANCH_ALWAYS);
2568 if (p->interrupt && i == packet_count - 1)
2569 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2571 context_append(&ctx->context, d, z, header_z);
2577 static int ohci_queue_iso(struct fw_iso_context *base,
2578 struct fw_iso_packet *packet,
2579 struct fw_iso_buffer *buffer,
2580 unsigned long payload)
2582 struct iso_context *ctx = container_of(base, struct iso_context, base);
2583 unsigned long flags;
2586 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2587 if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2588 ret = ohci_queue_iso_transmit(base, packet, buffer, payload);
2590 ret = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2592 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2597 static const struct fw_card_driver ohci_driver = {
2598 .enable = ohci_enable,
2599 .read_phy_reg = ohci_read_phy_reg,
2600 .update_phy_reg = ohci_update_phy_reg,
2601 .set_config_rom = ohci_set_config_rom,
2602 .send_request = ohci_send_request,
2603 .send_response = ohci_send_response,
2604 .cancel_packet = ohci_cancel_packet,
2605 .enable_phys_dma = ohci_enable_phys_dma,
2606 .read_csr = ohci_read_csr,
2607 .write_csr = ohci_write_csr,
2609 .allocate_iso_context = ohci_allocate_iso_context,
2610 .free_iso_context = ohci_free_iso_context,
2611 .queue_iso = ohci_queue_iso,
2612 .start_iso = ohci_start_iso,
2613 .stop_iso = ohci_stop_iso,
2616 #ifdef CONFIG_PPC_PMAC
2617 static void pmac_ohci_on(struct pci_dev *dev)
2619 if (machine_is(powermac)) {
2620 struct device_node *ofn = pci_device_to_OF_node(dev);
2623 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2624 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2629 static void pmac_ohci_off(struct pci_dev *dev)
2631 if (machine_is(powermac)) {
2632 struct device_node *ofn = pci_device_to_OF_node(dev);
2635 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2636 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2641 static inline void pmac_ohci_on(struct pci_dev *dev) {}
2642 static inline void pmac_ohci_off(struct pci_dev *dev) {}
2643 #endif /* CONFIG_PPC_PMAC */
2645 static int __devinit pci_probe(struct pci_dev *dev,
2646 const struct pci_device_id *ent)
2648 struct fw_ohci *ohci;
2649 u32 bus_options, max_receive, link_speed, version, link_enh;
2651 int i, err, n_ir, n_it;
2654 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2660 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2664 err = pci_enable_device(dev);
2666 fw_error("Failed to enable OHCI hardware\n");
2670 pci_set_master(dev);
2671 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2672 pci_set_drvdata(dev, ohci);
2674 spin_lock_init(&ohci->lock);
2675 mutex_init(&ohci->phy_reg_mutex);
2677 tasklet_init(&ohci->bus_reset_tasklet,
2678 bus_reset_tasklet, (unsigned long)ohci);
2680 err = pci_request_region(dev, 0, ohci_driver_name);
2682 fw_error("MMIO resource unavailable\n");
2686 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2687 if (ohci->registers == NULL) {
2688 fw_error("Failed to remap registers\n");
2693 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
2694 if (ohci_quirks[i].vendor == dev->vendor &&
2695 (ohci_quirks[i].device == dev->device ||
2696 ohci_quirks[i].device == (unsigned short)PCI_ANY_ID)) {
2697 ohci->quirks = ohci_quirks[i].flags;
2701 ohci->quirks = param_quirks;
2703 /* TI OHCI-Lynx and compatible: set recommended configuration bits. */
2704 if (dev->vendor == PCI_VENDOR_ID_TI) {
2705 pci_read_config_dword(dev, PCI_CFG_TI_LinkEnh, &link_enh);
2707 /* adjust latency of ATx FIFO: use 1.7 KB threshold */
2708 link_enh &= ~TI_LinkEnh_atx_thresh_mask;
2709 link_enh |= TI_LinkEnh_atx_thresh_1_7K;
2711 /* use priority arbitration for asynchronous responses */
2712 link_enh |= TI_LinkEnh_enab_unfair;
2714 /* required for aPhyEnhanceEnable to work */
2715 link_enh |= TI_LinkEnh_enab_accel;
2717 pci_write_config_dword(dev, PCI_CFG_TI_LinkEnh, link_enh);
2720 ar_context_init(&ohci->ar_request_ctx, ohci,
2721 OHCI1394_AsReqRcvContextControlSet);
2723 ar_context_init(&ohci->ar_response_ctx, ohci,
2724 OHCI1394_AsRspRcvContextControlSet);
2726 context_init(&ohci->at_request_ctx, ohci,
2727 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2729 context_init(&ohci->at_response_ctx, ohci,
2730 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2732 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2733 ohci->ir_context_channels = ~0ULL;
2734 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2735 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2736 n_ir = hweight32(ohci->ir_context_mask);
2737 size = sizeof(struct iso_context) * n_ir;
2738 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2740 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2741 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2742 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2743 n_it = hweight32(ohci->it_context_mask);
2744 size = sizeof(struct iso_context) * n_it;
2745 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2747 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2752 /* self-id dma buffer allocation */
2753 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2757 if (ohci->self_id_cpu == NULL) {
2762 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2763 max_receive = (bus_options >> 12) & 0xf;
2764 link_speed = bus_options & 0x7;
2765 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2766 reg_read(ohci, OHCI1394_GUIDLo);
2768 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2772 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2773 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
2774 "%d IR + %d IT contexts, quirks 0x%x\n",
2775 dev_name(&dev->dev), version >> 16, version & 0xff,
2776 n_ir, n_it, ohci->quirks);
2781 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2782 ohci->self_id_cpu, ohci->self_id_bus);
2784 kfree(ohci->ir_context_list);
2785 kfree(ohci->it_context_list);
2786 context_release(&ohci->at_response_ctx);
2787 context_release(&ohci->at_request_ctx);
2788 ar_context_release(&ohci->ar_response_ctx);
2789 ar_context_release(&ohci->ar_request_ctx);
2790 pci_iounmap(dev, ohci->registers);
2792 pci_release_region(dev, 0);
2794 pci_disable_device(dev);
2800 fw_error("Out of memory\n");
2805 static void pci_remove(struct pci_dev *dev)
2807 struct fw_ohci *ohci;
2809 ohci = pci_get_drvdata(dev);
2810 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2812 fw_core_remove_card(&ohci->card);
2815 * FIXME: Fail all pending packets here, now that the upper
2816 * layers can't queue any more.
2819 software_reset(ohci);
2820 free_irq(dev->irq, ohci);
2822 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
2823 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2824 ohci->next_config_rom, ohci->next_config_rom_bus);
2825 if (ohci->config_rom)
2826 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2827 ohci->config_rom, ohci->config_rom_bus);
2828 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2829 ohci->self_id_cpu, ohci->self_id_bus);
2830 ar_context_release(&ohci->ar_request_ctx);
2831 ar_context_release(&ohci->ar_response_ctx);
2832 context_release(&ohci->at_request_ctx);
2833 context_release(&ohci->at_response_ctx);
2834 kfree(ohci->it_context_list);
2835 kfree(ohci->ir_context_list);
2836 pci_disable_msi(dev);
2837 pci_iounmap(dev, ohci->registers);
2838 pci_release_region(dev, 0);
2839 pci_disable_device(dev);
2843 fw_notify("Removed fw-ohci device.\n");
2847 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2849 struct fw_ohci *ohci = pci_get_drvdata(dev);
2852 software_reset(ohci);
2853 free_irq(dev->irq, ohci);
2854 pci_disable_msi(dev);
2855 err = pci_save_state(dev);
2857 fw_error("pci_save_state failed\n");
2860 err = pci_set_power_state(dev, pci_choose_state(dev, state));
2862 fw_error("pci_set_power_state failed with %d\n", err);
2868 static int pci_resume(struct pci_dev *dev)
2870 struct fw_ohci *ohci = pci_get_drvdata(dev);
2874 pci_set_power_state(dev, PCI_D0);
2875 pci_restore_state(dev);
2876 err = pci_enable_device(dev);
2878 fw_error("pci_enable_device failed\n");
2882 return ohci_enable(&ohci->card, NULL, 0);
2886 static const struct pci_device_id pci_table[] = {
2887 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2891 MODULE_DEVICE_TABLE(pci, pci_table);
2893 static struct pci_driver fw_ohci_pci_driver = {
2894 .name = ohci_driver_name,
2895 .id_table = pci_table,
2897 .remove = pci_remove,
2899 .resume = pci_resume,
2900 .suspend = pci_suspend,
2904 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2905 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2906 MODULE_LICENSE("GPL");
2908 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2909 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2910 MODULE_ALIAS("ohci1394");
2913 static int __init fw_ohci_init(void)
2915 return pci_register_driver(&fw_ohci_pci_driver);
2918 static void __exit fw_ohci_cleanup(void)
2920 pci_unregister_driver(&fw_ohci_pci_driver);
2923 module_init(fw_ohci_init);
2924 module_exit(fw_ohci_cleanup);