1 /* Intel i7 core/Nehalem Memory Controller kernel module
3 * This driver supports yhe memory controllers found on the Intel
4 * processor families i7core, i7core 7xx/8xx, i5core, Xeon 35xx,
5 * Xeon 55xx and Xeon 56xx also known as Nehalem, Nehalem-EP, Lynnfield
8 * This file may be distributed under the terms of the
9 * GNU General Public License version 2 only.
11 * Copyright (c) 2009-2010 by:
12 * Mauro Carvalho Chehab <mchehab@redhat.com>
14 * Red Hat Inc. http://www.redhat.com
16 * Forked and adapted from the i5400_edac driver
18 * Based on the following public Intel datasheets:
19 * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor
20 * Datasheet, Volume 2:
21 * http://download.intel.com/design/processor/datashts/320835.pdf
22 * Intel Xeon Processor 5500 Series Datasheet Volume 2
23 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
25 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/pci_ids.h>
32 #include <linux/slab.h>
33 #include <linux/delay.h>
34 #include <linux/edac.h>
35 #include <linux/mmzone.h>
36 #include <linux/edac_mce.h>
37 #include <linux/smp.h>
38 #include <asm/processor.h>
40 #include "edac_core.h"
43 * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core
44 * registers start at bus 255, and are not reported by BIOS.
45 * We currently find devices with only 2 sockets. In order to support more QPI
46 * Quick Path Interconnect, just increment this number.
48 #define MAX_SOCKET_BUSES 2
52 * Alter this version for the module when modifications are made
54 #define I7CORE_REVISION " Ver: 1.0.0 " __DATE__
55 #define EDAC_MOD_STR "i7core_edac"
60 #define i7core_printk(level, fmt, arg...) \
61 edac_printk(level, "i7core", fmt, ##arg)
63 #define i7core_mc_printk(mci, level, fmt, arg...) \
64 edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg)
67 * i7core Memory Controller Registers
70 /* OFFSETS for Device 0 Function 0 */
72 #define MC_CFG_CONTROL 0x90
74 /* OFFSETS for Device 3 Function 0 */
76 #define MC_CONTROL 0x48
77 #define MC_STATUS 0x4c
78 #define MC_MAX_DOD 0x64
81 * OFFSETS for Device 3 Function 4, as inicated on Xeon 5500 datasheet:
82 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
85 #define MC_TEST_ERR_RCV1 0x60
86 #define DIMM2_COR_ERR(r) ((r) & 0x7fff)
88 #define MC_TEST_ERR_RCV0 0x64
89 #define DIMM1_COR_ERR(r) (((r) >> 16) & 0x7fff)
90 #define DIMM0_COR_ERR(r) ((r) & 0x7fff)
92 /* OFFSETS for Device 3 Function 2, as inicated on Xeon 5500 datasheet */
93 #define MC_COR_ECC_CNT_0 0x80
94 #define MC_COR_ECC_CNT_1 0x84
95 #define MC_COR_ECC_CNT_2 0x88
96 #define MC_COR_ECC_CNT_3 0x8c
97 #define MC_COR_ECC_CNT_4 0x90
98 #define MC_COR_ECC_CNT_5 0x94
100 #define DIMM_TOP_COR_ERR(r) (((r) >> 16) & 0x7fff)
101 #define DIMM_BOT_COR_ERR(r) ((r) & 0x7fff)
104 /* OFFSETS for Devices 4,5 and 6 Function 0 */
106 #define MC_CHANNEL_DIMM_INIT_PARAMS 0x58
107 #define THREE_DIMMS_PRESENT (1 << 24)
108 #define SINGLE_QUAD_RANK_PRESENT (1 << 23)
109 #define QUAD_RANK_PRESENT (1 << 22)
110 #define REGISTERED_DIMM (1 << 15)
112 #define MC_CHANNEL_MAPPER 0x60
113 #define RDLCH(r, ch) ((((r) >> (3 + (ch * 6))) & 0x07) - 1)
114 #define WRLCH(r, ch) ((((r) >> (ch * 6)) & 0x07) - 1)
116 #define MC_CHANNEL_RANK_PRESENT 0x7c
117 #define RANK_PRESENT_MASK 0xffff
119 #define MC_CHANNEL_ADDR_MATCH 0xf0
120 #define MC_CHANNEL_ERROR_MASK 0xf8
121 #define MC_CHANNEL_ERROR_INJECT 0xfc
122 #define INJECT_ADDR_PARITY 0x10
123 #define INJECT_ECC 0x08
124 #define MASK_CACHELINE 0x06
125 #define MASK_FULL_CACHELINE 0x06
126 #define MASK_MSB32_CACHELINE 0x04
127 #define MASK_LSB32_CACHELINE 0x02
128 #define NO_MASK_CACHELINE 0x00
129 #define REPEAT_EN 0x01
131 /* OFFSETS for Devices 4,5 and 6 Function 1 */
133 #define MC_DOD_CH_DIMM0 0x48
134 #define MC_DOD_CH_DIMM1 0x4c
135 #define MC_DOD_CH_DIMM2 0x50
136 #define RANKOFFSET_MASK ((1 << 12) | (1 << 11) | (1 << 10))
137 #define RANKOFFSET(x) ((x & RANKOFFSET_MASK) >> 10)
138 #define DIMM_PRESENT_MASK (1 << 9)
139 #define DIMM_PRESENT(x) (((x) & DIMM_PRESENT_MASK) >> 9)
140 #define MC_DOD_NUMBANK_MASK ((1 << 8) | (1 << 7))
141 #define MC_DOD_NUMBANK(x) (((x) & MC_DOD_NUMBANK_MASK) >> 7)
142 #define MC_DOD_NUMRANK_MASK ((1 << 6) | (1 << 5))
143 #define MC_DOD_NUMRANK(x) (((x) & MC_DOD_NUMRANK_MASK) >> 5)
144 #define MC_DOD_NUMROW_MASK ((1 << 4) | (1 << 3) | (1 << 2))
145 #define MC_DOD_NUMROW(x) (((x) & MC_DOD_NUMROW_MASK) >> 2)
146 #define MC_DOD_NUMCOL_MASK 3
147 #define MC_DOD_NUMCOL(x) ((x) & MC_DOD_NUMCOL_MASK)
149 #define MC_RANK_PRESENT 0x7c
151 #define MC_SAG_CH_0 0x80
152 #define MC_SAG_CH_1 0x84
153 #define MC_SAG_CH_2 0x88
154 #define MC_SAG_CH_3 0x8c
155 #define MC_SAG_CH_4 0x90
156 #define MC_SAG_CH_5 0x94
157 #define MC_SAG_CH_6 0x98
158 #define MC_SAG_CH_7 0x9c
160 #define MC_RIR_LIMIT_CH_0 0x40
161 #define MC_RIR_LIMIT_CH_1 0x44
162 #define MC_RIR_LIMIT_CH_2 0x48
163 #define MC_RIR_LIMIT_CH_3 0x4C
164 #define MC_RIR_LIMIT_CH_4 0x50
165 #define MC_RIR_LIMIT_CH_5 0x54
166 #define MC_RIR_LIMIT_CH_6 0x58
167 #define MC_RIR_LIMIT_CH_7 0x5C
168 #define MC_RIR_LIMIT_MASK ((1 << 10) - 1)
170 #define MC_RIR_WAY_CH 0x80
171 #define MC_RIR_WAY_OFFSET_MASK (((1 << 14) - 1) & ~0x7)
172 #define MC_RIR_WAY_RANK_MASK 0x7
179 #define MAX_DIMMS 3 /* Max DIMMS per channel */
180 #define MAX_MCR_FUNC 4
181 #define MAX_CHAN_FUNC 3
191 struct i7core_inject {
198 /* Error address mask */
199 int channel, dimm, rank, bank, page, col;
202 struct i7core_channel {
207 struct pci_id_descr {
214 struct pci_id_table {
215 struct pci_id_descr *descr;
220 struct list_head list;
222 struct pci_dev **pdev;
224 struct mem_ctl_info *mci;
228 struct pci_dev *pci_noncore;
229 struct pci_dev *pci_mcr[MAX_MCR_FUNC + 1];
230 struct pci_dev *pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1];
232 struct i7core_dev *i7core_dev;
234 struct i7core_info info;
235 struct i7core_inject inject;
236 struct i7core_channel channel[NUM_CHANS];
238 int channels; /* Number of active channels */
240 int ce_count_available;
241 int csrow_map[NUM_CHANS][MAX_DIMMS];
243 /* ECC corrected errors counts per udimm */
244 unsigned long udimm_ce_count[MAX_DIMMS];
245 int udimm_last_ce_count[MAX_DIMMS];
246 /* ECC corrected errors counts per rdimm */
247 unsigned long rdimm_ce_count[NUM_CHANS][MAX_DIMMS];
248 int rdimm_last_ce_count[NUM_CHANS][MAX_DIMMS];
250 unsigned int is_registered;
253 struct edac_mce edac_mce;
255 /* Fifo double buffers */
256 struct mce mce_entry[MCE_LOG_LEN];
257 struct mce mce_outentry[MCE_LOG_LEN];
259 /* Fifo in/out counters */
260 unsigned mce_in, mce_out;
262 /* Count indicator to show errors not got */
263 unsigned mce_overrun;
267 static LIST_HEAD(i7core_edac_list);
268 static DEFINE_MUTEX(i7core_edac_lock);
270 #define PCI_DESCR(device, function, device_id) \
272 .func = (function), \
273 .dev_id = (device_id)
275 struct pci_id_descr pci_dev_descr_i7core_nehalem[] = {
276 /* Memory controller */
277 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) },
278 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) },
279 /* Exists only for RDIMM */
280 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS), .optional = 1 },
281 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },
284 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) },
285 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) },
286 { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) },
287 { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC) },
290 { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) },
291 { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) },
292 { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) },
293 { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC) },
296 { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) },
297 { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
298 { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
299 { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC) },
301 /* Generic Non-core registers */
303 * This is the PCI device on i7core and on Xeon 35xx (8086:2c41)
304 * On Xeon 55xx, however, it has a different id (8086:2c40). So,
305 * the probing code needs to test for the other address in case of
306 * failure of this one
308 { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NONCORE) },
312 struct pci_id_descr pci_dev_descr_lynnfield[] = {
313 { PCI_DESCR( 3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR) },
314 { PCI_DESCR( 3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD) },
315 { PCI_DESCR( 3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST) },
317 { PCI_DESCR( 4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL) },
318 { PCI_DESCR( 4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR) },
319 { PCI_DESCR( 4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK) },
320 { PCI_DESCR( 4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC) },
322 { PCI_DESCR( 5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL) },
323 { PCI_DESCR( 5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR) },
324 { PCI_DESCR( 5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK) },
325 { PCI_DESCR( 5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC) },
328 * This is the PCI device has an alternate address on some
329 * processors like Core i7 860
331 { PCI_DESCR( 0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE) },
334 struct pci_id_descr pci_dev_descr_i7core_westmere[] = {
335 /* Memory controller */
336 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2) },
337 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2) },
338 /* Exists only for RDIMM */
339 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2), .optional = 1 },
340 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2) },
343 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2) },
344 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2) },
345 { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2) },
346 { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2) },
349 { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2) },
350 { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2) },
351 { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2) },
352 { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2) },
355 { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2) },
356 { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2) },
357 { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2) },
358 { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2) },
360 /* Generic Non-core registers */
361 { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2) },
365 #define PCI_ID_TABLE_ENTRY(A) { A, ARRAY_SIZE(A) }
366 struct pci_id_table pci_dev_table[] = {
367 PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_nehalem),
368 PCI_ID_TABLE_ENTRY(pci_dev_descr_lynnfield),
369 PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_westmere),
373 * pci_device_id table for which devices we are looking for
375 static const struct pci_device_id i7core_pci_tbl[] __devinitdata = {
376 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},
377 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0)},
378 {0,} /* 0 terminated list. */
381 static struct edac_pci_ctl_info *i7core_pci;
383 /****************************************************************************
384 Anciliary status routines
385 ****************************************************************************/
387 /* MC_CONTROL bits */
388 #define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch)))
389 #define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1))
392 #define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4))
393 #define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch))
395 /* MC_MAX_DOD read functions */
396 static inline int numdimms(u32 dimms)
398 return (dimms & 0x3) + 1;
401 static inline int numrank(u32 rank)
403 static int ranks[4] = { 1, 2, 4, -EINVAL };
405 return ranks[rank & 0x3];
408 static inline int numbank(u32 bank)
410 static int banks[4] = { 4, 8, 16, -EINVAL };
412 return banks[bank & 0x3];
415 static inline int numrow(u32 row)
417 static int rows[8] = {
418 1 << 12, 1 << 13, 1 << 14, 1 << 15,
419 1 << 16, -EINVAL, -EINVAL, -EINVAL,
422 return rows[row & 0x7];
425 static inline int numcol(u32 col)
427 static int cols[8] = {
428 1 << 10, 1 << 11, 1 << 12, -EINVAL,
430 return cols[col & 0x3];
433 static struct i7core_dev *get_i7core_dev(u8 socket)
435 struct i7core_dev *i7core_dev;
437 list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
438 if (i7core_dev->socket == socket)
445 /****************************************************************************
446 Memory check routines
447 ****************************************************************************/
448 static struct pci_dev *get_pdev_slot_func(u8 socket, unsigned slot,
451 struct i7core_dev *i7core_dev = get_i7core_dev(socket);
457 for (i = 0; i < i7core_dev->n_devs; i++) {
458 if (!i7core_dev->pdev[i])
461 if (PCI_SLOT(i7core_dev->pdev[i]->devfn) == slot &&
462 PCI_FUNC(i7core_dev->pdev[i]->devfn) == func) {
463 return i7core_dev->pdev[i];
471 * i7core_get_active_channels() - gets the number of channels and csrows
472 * @socket: Quick Path Interconnect socket
473 * @channels: Number of channels that will be returned
474 * @csrows: Number of csrows found
476 * Since EDAC core needs to know in advance the number of available channels
477 * and csrows, in order to allocate memory for csrows/channels, it is needed
478 * to run two similar steps. At the first step, implemented on this function,
479 * it checks the number of csrows/channels present at one socket.
480 * this is used in order to properly allocate the size of mci components.
482 * It should be noticed that none of the current available datasheets explain
483 * or even mention how csrows are seen by the memory controller. So, we need
484 * to add a fake description for csrows.
485 * So, this driver is attributing one DIMM memory for one csrow.
487 static int i7core_get_active_channels(u8 socket, unsigned *channels,
490 struct pci_dev *pdev = NULL;
497 pdev = get_pdev_slot_func(socket, 3, 0);
499 i7core_printk(KERN_ERR, "Couldn't find socket %d fn 3.0!!!\n",
504 /* Device 3 function 0 reads */
505 pci_read_config_dword(pdev, MC_STATUS, &status);
506 pci_read_config_dword(pdev, MC_CONTROL, &control);
508 for (i = 0; i < NUM_CHANS; i++) {
510 /* Check if the channel is active */
511 if (!(control & (1 << (8 + i))))
514 /* Check if the channel is disabled */
515 if (status & (1 << i))
518 pdev = get_pdev_slot_func(socket, i + 4, 1);
520 i7core_printk(KERN_ERR, "Couldn't find socket %d "
525 /* Devices 4-6 function 1 */
526 pci_read_config_dword(pdev,
527 MC_DOD_CH_DIMM0, &dimm_dod[0]);
528 pci_read_config_dword(pdev,
529 MC_DOD_CH_DIMM1, &dimm_dod[1]);
530 pci_read_config_dword(pdev,
531 MC_DOD_CH_DIMM2, &dimm_dod[2]);
535 for (j = 0; j < 3; j++) {
536 if (!DIMM_PRESENT(dimm_dod[j]))
542 debugf0("Number of active channels on socket %d: %d\n",
548 static int get_dimm_config(struct mem_ctl_info *mci, int *csrow)
550 struct i7core_pvt *pvt = mci->pvt_info;
551 struct csrow_info *csr;
552 struct pci_dev *pdev;
554 unsigned long last_page = 0;
558 /* Get data from the MC register, function 0 */
559 pdev = pvt->pci_mcr[0];
563 /* Device 3 function 0 reads */
564 pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control);
565 pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status);
566 pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod);
567 pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map);
569 debugf0("QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n",
570 pvt->i7core_dev->socket, pvt->info.mc_control, pvt->info.mc_status,
571 pvt->info.max_dod, pvt->info.ch_map);
573 if (ECC_ENABLED(pvt)) {
574 debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4);
576 mode = EDAC_S8ECD8ED;
578 mode = EDAC_S4ECD4ED;
580 debugf0("ECC disabled\n");
584 /* FIXME: need to handle the error codes */
585 debugf0("DOD Max limits: DIMMS: %d, %d-ranked, %d-banked "
587 numdimms(pvt->info.max_dod),
588 numrank(pvt->info.max_dod >> 2),
589 numbank(pvt->info.max_dod >> 4),
590 numrow(pvt->info.max_dod >> 6),
591 numcol(pvt->info.max_dod >> 9));
593 for (i = 0; i < NUM_CHANS; i++) {
594 u32 data, dimm_dod[3], value[8];
596 if (!pvt->pci_ch[i][0])
599 if (!CH_ACTIVE(pvt, i)) {
600 debugf0("Channel %i is not active\n", i);
603 if (CH_DISABLED(pvt, i)) {
604 debugf0("Channel %i is disabled\n", i);
608 /* Devices 4-6 function 0 */
609 pci_read_config_dword(pvt->pci_ch[i][0],
610 MC_CHANNEL_DIMM_INIT_PARAMS, &data);
612 pvt->channel[i].ranks = (data & QUAD_RANK_PRESENT) ?
615 if (data & REGISTERED_DIMM)
620 if (data & THREE_DIMMS_PRESENT)
621 pvt->channel[i].dimms = 3;
622 else if (data & SINGLE_QUAD_RANK_PRESENT)
623 pvt->channel[i].dimms = 1;
625 pvt->channel[i].dimms = 2;
628 /* Devices 4-6 function 1 */
629 pci_read_config_dword(pvt->pci_ch[i][1],
630 MC_DOD_CH_DIMM0, &dimm_dod[0]);
631 pci_read_config_dword(pvt->pci_ch[i][1],
632 MC_DOD_CH_DIMM1, &dimm_dod[1]);
633 pci_read_config_dword(pvt->pci_ch[i][1],
634 MC_DOD_CH_DIMM2, &dimm_dod[2]);
636 debugf0("Ch%d phy rd%d, wr%d (0x%08x): "
637 "%d ranks, %cDIMMs\n",
639 RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
641 pvt->channel[i].ranks,
642 (data & REGISTERED_DIMM) ? 'R' : 'U');
644 for (j = 0; j < 3; j++) {
645 u32 banks, ranks, rows, cols;
648 if (!DIMM_PRESENT(dimm_dod[j]))
651 banks = numbank(MC_DOD_NUMBANK(dimm_dod[j]));
652 ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j]));
653 rows = numrow(MC_DOD_NUMROW(dimm_dod[j]));
654 cols = numcol(MC_DOD_NUMCOL(dimm_dod[j]));
656 /* DDR3 has 8 I/O banks */
657 size = (rows * cols * banks * ranks) >> (20 - 3);
659 pvt->channel[i].dimms++;
661 debugf0("\tdimm %d %d Mb offset: %x, "
662 "bank: %d, rank: %d, row: %#x, col: %#x\n",
664 RANKOFFSET(dimm_dod[j]),
665 banks, ranks, rows, cols);
668 npages = size >> (PAGE_SHIFT - 20);
670 npages = size << (20 - PAGE_SHIFT);
673 csr = &mci->csrows[*csrow];
674 csr->first_page = last_page + 1;
676 csr->last_page = last_page;
677 csr->nr_pages = npages;
681 csr->csrow_idx = *csrow;
682 csr->nr_channels = 1;
684 csr->channels[0].chan_idx = i;
685 csr->channels[0].ce_count = 0;
687 pvt->csrow_map[i][j] = *csrow;
697 csr->dtype = DEV_X16;
700 csr->dtype = DEV_UNKNOWN;
703 csr->edac_mode = mode;
709 pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
710 pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]);
711 pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]);
712 pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]);
713 pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]);
714 pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);
715 pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);
716 pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);
717 debugf1("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
718 for (j = 0; j < 8; j++)
719 debugf1("\t\t%#x\t%#x\t%#x\n",
720 (value[j] >> 27) & 0x1,
721 (value[j] >> 24) & 0x7,
722 (value[j] && ((1 << 24) - 1)));
728 /****************************************************************************
729 Error insertion routines
730 ****************************************************************************/
732 /* The i7core has independent error injection features per channel.
733 However, to have a simpler code, we don't allow enabling error injection
734 on more than one channel.
735 Also, since a change at an inject parameter will be applied only at enable,
736 we're disabling error injection on all write calls to the sysfs nodes that
737 controls the error code injection.
739 static int disable_inject(struct mem_ctl_info *mci)
741 struct i7core_pvt *pvt = mci->pvt_info;
743 pvt->inject.enable = 0;
745 if (!pvt->pci_ch[pvt->inject.channel][0])
748 pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
749 MC_CHANNEL_ERROR_INJECT, 0);
755 * i7core inject inject.section
757 * accept and store error injection inject.section value
758 * bit 0 - refers to the lower 32-byte half cacheline
759 * bit 1 - refers to the upper 32-byte half cacheline
761 static ssize_t i7core_inject_section_store(struct mem_ctl_info *mci,
762 const char *data, size_t count)
764 struct i7core_pvt *pvt = mci->pvt_info;
768 if (pvt->inject.enable)
771 rc = strict_strtoul(data, 10, &value);
772 if ((rc < 0) || (value > 3))
775 pvt->inject.section = (u32) value;
779 static ssize_t i7core_inject_section_show(struct mem_ctl_info *mci,
782 struct i7core_pvt *pvt = mci->pvt_info;
783 return sprintf(data, "0x%08x\n", pvt->inject.section);
789 * accept and store error injection inject.section value
790 * bit 0 - repeat enable - Enable error repetition
791 * bit 1 - inject ECC error
792 * bit 2 - inject parity error
794 static ssize_t i7core_inject_type_store(struct mem_ctl_info *mci,
795 const char *data, size_t count)
797 struct i7core_pvt *pvt = mci->pvt_info;
801 if (pvt->inject.enable)
804 rc = strict_strtoul(data, 10, &value);
805 if ((rc < 0) || (value > 7))
808 pvt->inject.type = (u32) value;
812 static ssize_t i7core_inject_type_show(struct mem_ctl_info *mci,
815 struct i7core_pvt *pvt = mci->pvt_info;
816 return sprintf(data, "0x%08x\n", pvt->inject.type);
820 * i7core_inject_inject.eccmask_store
822 * The type of error (UE/CE) will depend on the inject.eccmask value:
823 * Any bits set to a 1 will flip the corresponding ECC bit
824 * Correctable errors can be injected by flipping 1 bit or the bits within
825 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
826 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
827 * uncorrectable error to be injected.
829 static ssize_t i7core_inject_eccmask_store(struct mem_ctl_info *mci,
830 const char *data, size_t count)
832 struct i7core_pvt *pvt = mci->pvt_info;
836 if (pvt->inject.enable)
839 rc = strict_strtoul(data, 10, &value);
843 pvt->inject.eccmask = (u32) value;
847 static ssize_t i7core_inject_eccmask_show(struct mem_ctl_info *mci,
850 struct i7core_pvt *pvt = mci->pvt_info;
851 return sprintf(data, "0x%08x\n", pvt->inject.eccmask);
857 * The type of error (UE/CE) will depend on the inject.eccmask value:
858 * Any bits set to a 1 will flip the corresponding ECC bit
859 * Correctable errors can be injected by flipping 1 bit or the bits within
860 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
861 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
862 * uncorrectable error to be injected.
865 #define DECLARE_ADDR_MATCH(param, limit) \
866 static ssize_t i7core_inject_store_##param( \
867 struct mem_ctl_info *mci, \
868 const char *data, size_t count) \
870 struct i7core_pvt *pvt; \
874 debugf1("%s()\n", __func__); \
875 pvt = mci->pvt_info; \
877 if (pvt->inject.enable) \
878 disable_inject(mci); \
880 if (!strcasecmp(data, "any") || !strcasecmp(data, "any\n"))\
883 rc = strict_strtoul(data, 10, &value); \
884 if ((rc < 0) || (value >= limit)) \
888 pvt->inject.param = value; \
893 static ssize_t i7core_inject_show_##param( \
894 struct mem_ctl_info *mci, \
897 struct i7core_pvt *pvt; \
899 pvt = mci->pvt_info; \
900 debugf1("%s() pvt=%p\n", __func__, pvt); \
901 if (pvt->inject.param < 0) \
902 return sprintf(data, "any\n"); \
904 return sprintf(data, "%d\n", pvt->inject.param);\
907 #define ATTR_ADDR_MATCH(param) \
911 .mode = (S_IRUGO | S_IWUSR) \
913 .show = i7core_inject_show_##param, \
914 .store = i7core_inject_store_##param, \
917 DECLARE_ADDR_MATCH(channel, 3);
918 DECLARE_ADDR_MATCH(dimm, 3);
919 DECLARE_ADDR_MATCH(rank, 4);
920 DECLARE_ADDR_MATCH(bank, 32);
921 DECLARE_ADDR_MATCH(page, 0x10000);
922 DECLARE_ADDR_MATCH(col, 0x4000);
924 static int write_and_test(struct pci_dev *dev, int where, u32 val)
929 debugf0("setting pci %02x:%02x.%x reg=%02x value=%08x\n",
930 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
933 for (count = 0; count < 10; count++) {
936 pci_write_config_dword(dev, where, val);
937 pci_read_config_dword(dev, where, &read);
943 i7core_printk(KERN_ERR, "Error during set pci %02x:%02x.%x reg=%02x "
944 "write=%08x. Read=%08x\n",
945 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
952 * This routine prepares the Memory Controller for error injection.
953 * The error will be injected when some process tries to write to the
954 * memory that matches the given criteria.
955 * The criteria can be set in terms of a mask where dimm, rank, bank, page
956 * and col can be specified.
957 * A -1 value for any of the mask items will make the MCU to ignore
958 * that matching criteria for error injection.
960 * It should be noticed that the error will only happen after a write operation
961 * on a memory that matches the condition. if REPEAT_EN is not enabled at
962 * inject mask, then it will produce just one error. Otherwise, it will repeat
963 * until the injectmask would be cleaned.
965 * FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD
966 * is reliable enough to check if the MC is using the
967 * three channels. However, this is not clear at the datasheet.
969 static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
970 const char *data, size_t count)
972 struct i7core_pvt *pvt = mci->pvt_info;
978 if (!pvt->pci_ch[pvt->inject.channel][0])
981 rc = strict_strtoul(data, 10, &enable);
986 pvt->inject.enable = 1;
992 /* Sets pvt->inject.dimm mask */
993 if (pvt->inject.dimm < 0)
996 if (pvt->channel[pvt->inject.channel].dimms > 2)
997 mask |= (pvt->inject.dimm & 0x3LL) << 35;
999 mask |= (pvt->inject.dimm & 0x1LL) << 36;
1002 /* Sets pvt->inject.rank mask */
1003 if (pvt->inject.rank < 0)
1006 if (pvt->channel[pvt->inject.channel].dimms > 2)
1007 mask |= (pvt->inject.rank & 0x1LL) << 34;
1009 mask |= (pvt->inject.rank & 0x3LL) << 34;
1012 /* Sets pvt->inject.bank mask */
1013 if (pvt->inject.bank < 0)
1016 mask |= (pvt->inject.bank & 0x15LL) << 30;
1018 /* Sets pvt->inject.page mask */
1019 if (pvt->inject.page < 0)
1022 mask |= (pvt->inject.page & 0xffff) << 14;
1024 /* Sets pvt->inject.column mask */
1025 if (pvt->inject.col < 0)
1028 mask |= (pvt->inject.col & 0x3fff);
1032 * bits 1-2: MASK_HALF_CACHELINE
1034 * bit 4: INJECT_ADDR_PARITY
1037 injectmask = (pvt->inject.type & 1) |
1038 (pvt->inject.section & 0x3) << 1 |
1039 (pvt->inject.type & 0x6) << (3 - 1);
1041 /* Unlock writes to registers - this register is write only */
1042 pci_write_config_dword(pvt->pci_noncore,
1043 MC_CFG_CONTROL, 0x2);
1045 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1046 MC_CHANNEL_ADDR_MATCH, mask);
1047 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1048 MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L);
1050 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1051 MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);
1053 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1054 MC_CHANNEL_ERROR_INJECT, injectmask);
1057 * This is something undocumented, based on my tests
1058 * Without writing 8 to this register, errors aren't injected. Not sure
1061 pci_write_config_dword(pvt->pci_noncore,
1064 debugf0("Error inject addr match 0x%016llx, ecc 0x%08x,"
1066 mask, pvt->inject.eccmask, injectmask);
1072 static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci,
1075 struct i7core_pvt *pvt = mci->pvt_info;
1078 if (!pvt->pci_ch[pvt->inject.channel][0])
1081 pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
1082 MC_CHANNEL_ERROR_INJECT, &injectmask);
1084 debugf0("Inject error read: 0x%018x\n", injectmask);
1086 if (injectmask & 0x0c)
1087 pvt->inject.enable = 1;
1089 return sprintf(data, "%d\n", pvt->inject.enable);
1092 #define DECLARE_COUNTER(param) \
1093 static ssize_t i7core_show_counter_##param( \
1094 struct mem_ctl_info *mci, \
1097 struct i7core_pvt *pvt = mci->pvt_info; \
1099 debugf1("%s() \n", __func__); \
1100 if (!pvt->ce_count_available || (pvt->is_registered)) \
1101 return sprintf(data, "data unavailable\n"); \
1102 return sprintf(data, "%lu\n", \
1103 pvt->udimm_ce_count[param]); \
1106 #define ATTR_COUNTER(param) \
1109 .name = __stringify(udimm##param), \
1110 .mode = (S_IRUGO | S_IWUSR) \
1112 .show = i7core_show_counter_##param \
1124 static struct mcidev_sysfs_attribute i7core_addrmatch_attrs[] = {
1125 ATTR_ADDR_MATCH(channel),
1126 ATTR_ADDR_MATCH(dimm),
1127 ATTR_ADDR_MATCH(rank),
1128 ATTR_ADDR_MATCH(bank),
1129 ATTR_ADDR_MATCH(page),
1130 ATTR_ADDR_MATCH(col),
1131 { .attr = { .name = NULL } }
1134 static struct mcidev_sysfs_group i7core_inject_addrmatch = {
1135 .name = "inject_addrmatch",
1136 .mcidev_attr = i7core_addrmatch_attrs,
1139 static struct mcidev_sysfs_attribute i7core_udimm_counters_attrs[] = {
1145 static struct mcidev_sysfs_group i7core_udimm_counters = {
1146 .name = "all_channel_counts",
1147 .mcidev_attr = i7core_udimm_counters_attrs,
1150 static struct mcidev_sysfs_attribute i7core_sysfs_attrs[] = {
1153 .name = "inject_section",
1154 .mode = (S_IRUGO | S_IWUSR)
1156 .show = i7core_inject_section_show,
1157 .store = i7core_inject_section_store,
1160 .name = "inject_type",
1161 .mode = (S_IRUGO | S_IWUSR)
1163 .show = i7core_inject_type_show,
1164 .store = i7core_inject_type_store,
1167 .name = "inject_eccmask",
1168 .mode = (S_IRUGO | S_IWUSR)
1170 .show = i7core_inject_eccmask_show,
1171 .store = i7core_inject_eccmask_store,
1173 .grp = &i7core_inject_addrmatch,
1176 .name = "inject_enable",
1177 .mode = (S_IRUGO | S_IWUSR)
1179 .show = i7core_inject_enable_show,
1180 .store = i7core_inject_enable_store,
1182 { .attr = { .name = NULL } }, /* Reserved for udimm counters */
1183 { .attr = { .name = NULL } }
1186 /****************************************************************************
1187 Device initialization routines: put/get, init/exit
1188 ****************************************************************************/
1191 * i7core_put_devices 'put' all the devices that we have
1192 * reserved via 'get'
1194 static void i7core_put_devices(struct i7core_dev *i7core_dev)
1198 debugf0(__FILE__ ": %s()\n", __func__);
1199 for (i = 0; i < i7core_dev->n_devs; i++) {
1200 struct pci_dev *pdev = i7core_dev->pdev[i];
1203 debugf0("Removing dev %02x:%02x.%d\n",
1205 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1208 kfree(i7core_dev->pdev);
1209 list_del(&i7core_dev->list);
1213 static void i7core_put_all_devices(void)
1215 struct i7core_dev *i7core_dev, *tmp;
1217 list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list)
1218 i7core_put_devices(i7core_dev);
1221 static void __init i7core_xeon_pci_fixup(struct pci_id_table *table)
1223 struct pci_dev *pdev = NULL;
1226 * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core pci buses
1227 * aren't announced by acpi. So, we need to use a legacy scan probing
1230 while (table && table->descr) {
1231 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, table->descr[0].dev_id, NULL);
1232 if (unlikely(!pdev)) {
1233 for (i = 0; i < MAX_SOCKET_BUSES; i++)
1234 pcibios_scan_specific_bus(255-i);
1241 static unsigned i7core_pci_lastbus(void)
1243 int last_bus = 0, bus;
1244 struct pci_bus *b = NULL;
1246 while ((b = pci_find_next_bus(b)) != NULL) {
1248 debugf0("Found bus %d\n", bus);
1253 debugf0("Last bus %d\n", last_bus);
1259 * i7core_get_devices Find and perform 'get' operation on the MCH's
1260 * device/functions we want to reference for this driver
1262 * Need to 'get' device 16 func 1 and func 2
1264 int i7core_get_onedevice(struct pci_dev **prev, int devno,
1265 struct pci_id_descr *dev_descr, unsigned n_devs,
1268 struct i7core_dev *i7core_dev;
1270 struct pci_dev *pdev = NULL;
1274 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1275 dev_descr->dev_id, *prev);
1278 * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core regs
1279 * is at addr 8086:2c40, instead of 8086:2c41. So, we need
1280 * to probe for the alternate address in case of failure
1282 if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_I7_NONCORE && !pdev)
1283 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1284 PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT, *prev);
1286 if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE && !pdev)
1287 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1288 PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT,
1297 if (dev_descr->optional)
1303 i7core_printk(KERN_INFO,
1304 "Device not found: dev %02x.%d PCI ID %04x:%04x\n",
1305 dev_descr->dev, dev_descr->func,
1306 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1308 /* End of list, leave */
1311 bus = pdev->bus->number;
1313 socket = last_bus - bus;
1315 i7core_dev = get_i7core_dev(socket);
1317 i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL);
1320 i7core_dev->pdev = kzalloc(sizeof(*i7core_dev->pdev) * n_devs,
1322 if (!i7core_dev->pdev) {
1326 i7core_dev->socket = socket;
1327 i7core_dev->n_devs = n_devs;
1328 list_add_tail(&i7core_dev->list, &i7core_edac_list);
1331 if (i7core_dev->pdev[devno]) {
1332 i7core_printk(KERN_ERR,
1333 "Duplicated device for "
1334 "dev %02x:%02x.%d PCI ID %04x:%04x\n",
1335 bus, dev_descr->dev, dev_descr->func,
1336 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1341 i7core_dev->pdev[devno] = pdev;
1344 if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev ||
1345 PCI_FUNC(pdev->devfn) != dev_descr->func)) {
1346 i7core_printk(KERN_ERR,
1347 "Device PCI ID %04x:%04x "
1348 "has dev %02x:%02x.%d instead of dev %02x:%02x.%d\n",
1349 PCI_VENDOR_ID_INTEL, dev_descr->dev_id,
1350 bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1351 bus, dev_descr->dev, dev_descr->func);
1355 /* Be sure that the device is enabled */
1356 if (unlikely(pci_enable_device(pdev) < 0)) {
1357 i7core_printk(KERN_ERR,
1359 "dev %02x:%02x.%d PCI ID %04x:%04x\n",
1360 bus, dev_descr->dev, dev_descr->func,
1361 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1365 debugf0("Detected socket %d dev %02x:%02x.%d PCI ID %04x:%04x\n",
1366 socket, bus, dev_descr->dev,
1368 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1375 static int i7core_get_devices(struct pci_id_table *table)
1377 int i, rc, last_bus;
1378 struct pci_dev *pdev = NULL;
1379 struct pci_id_descr *dev_descr;
1381 last_bus = i7core_pci_lastbus();
1383 while (table && table->descr) {
1384 dev_descr = table->descr;
1385 for (i = 0; i < table->n_devs; i++) {
1388 rc = i7core_get_onedevice(&pdev, i,
1397 i7core_put_all_devices();
1409 static int mci_bind_devs(struct mem_ctl_info *mci,
1410 struct i7core_dev *i7core_dev)
1412 struct i7core_pvt *pvt = mci->pvt_info;
1413 struct pci_dev *pdev;
1416 /* Associates i7core_dev and mci for future usage */
1417 pvt->i7core_dev = i7core_dev;
1418 i7core_dev->mci = mci;
1420 pvt->is_registered = 0;
1421 for (i = 0; i < i7core_dev->n_devs; i++) {
1422 pdev = i7core_dev->pdev[i];
1426 func = PCI_FUNC(pdev->devfn);
1427 slot = PCI_SLOT(pdev->devfn);
1429 if (unlikely(func > MAX_MCR_FUNC))
1431 pvt->pci_mcr[func] = pdev;
1432 } else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) {
1433 if (unlikely(func > MAX_CHAN_FUNC))
1435 pvt->pci_ch[slot - 4][func] = pdev;
1436 } else if (!slot && !func)
1437 pvt->pci_noncore = pdev;
1441 debugf0("Associated fn %d.%d, dev = %p, socket %d\n",
1442 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1443 pdev, i7core_dev->socket);
1445 if (PCI_SLOT(pdev->devfn) == 3 &&
1446 PCI_FUNC(pdev->devfn) == 2)
1447 pvt->is_registered = 1;
1451 * Add extra nodes to count errors on udimm
1452 * For registered memory, this is not needed, since the counters
1453 * are already displayed at the standard locations
1455 if (!pvt->is_registered)
1456 i7core_sysfs_attrs[ARRAY_SIZE(i7core_sysfs_attrs)-2].grp =
1457 &i7core_udimm_counters;
1462 i7core_printk(KERN_ERR, "Device %d, function %d "
1463 "is out of the expected range\n",
1468 /****************************************************************************
1469 Error check routines
1470 ****************************************************************************/
1471 static void i7core_rdimm_update_csrow(struct mem_ctl_info *mci,
1472 int chan, int dimm, int add)
1475 struct i7core_pvt *pvt = mci->pvt_info;
1476 int row = pvt->csrow_map[chan][dimm], i;
1478 for (i = 0; i < add; i++) {
1479 msg = kasprintf(GFP_KERNEL, "Corrected error "
1480 "(Socket=%d channel=%d dimm=%d)",
1481 pvt->i7core_dev->socket, chan, dimm);
1483 edac_mc_handle_fbd_ce(mci, row, 0, msg);
1488 static void i7core_rdimm_update_ce_count(struct mem_ctl_info *mci,
1489 int chan, int new0, int new1, int new2)
1491 struct i7core_pvt *pvt = mci->pvt_info;
1492 int add0 = 0, add1 = 0, add2 = 0;
1493 /* Updates CE counters if it is not the first time here */
1494 if (pvt->ce_count_available) {
1495 /* Updates CE counters */
1497 add2 = new2 - pvt->rdimm_last_ce_count[chan][2];
1498 add1 = new1 - pvt->rdimm_last_ce_count[chan][1];
1499 add0 = new0 - pvt->rdimm_last_ce_count[chan][0];
1503 pvt->rdimm_ce_count[chan][2] += add2;
1507 pvt->rdimm_ce_count[chan][1] += add1;
1511 pvt->rdimm_ce_count[chan][0] += add0;
1513 pvt->ce_count_available = 1;
1515 /* Store the new values */
1516 pvt->rdimm_last_ce_count[chan][2] = new2;
1517 pvt->rdimm_last_ce_count[chan][1] = new1;
1518 pvt->rdimm_last_ce_count[chan][0] = new0;
1520 /*updated the edac core */
1522 i7core_rdimm_update_csrow(mci, chan, 0, add0);
1524 i7core_rdimm_update_csrow(mci, chan, 1, add1);
1526 i7core_rdimm_update_csrow(mci, chan, 2, add2);
1530 static void i7core_rdimm_check_mc_ecc_err(struct mem_ctl_info *mci)
1532 struct i7core_pvt *pvt = mci->pvt_info;
1534 int i, new0, new1, new2;
1536 /*Read DEV 3: FUN 2: MC_COR_ECC_CNT regs directly*/
1537 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0,
1539 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1,
1541 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2,
1543 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3,
1545 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4,
1547 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5,
1549 for (i = 0 ; i < 3; i++) {
1550 debugf3("MC_COR_ECC_CNT%d = 0x%x; MC_COR_ECC_CNT%d = 0x%x\n",
1551 (i * 2), rcv[i][0], (i * 2) + 1, rcv[i][1]);
1552 /*if the channel has 3 dimms*/
1553 if (pvt->channel[i].dimms > 2) {
1554 new0 = DIMM_BOT_COR_ERR(rcv[i][0]);
1555 new1 = DIMM_TOP_COR_ERR(rcv[i][0]);
1556 new2 = DIMM_BOT_COR_ERR(rcv[i][1]);
1558 new0 = DIMM_TOP_COR_ERR(rcv[i][0]) +
1559 DIMM_BOT_COR_ERR(rcv[i][0]);
1560 new1 = DIMM_TOP_COR_ERR(rcv[i][1]) +
1561 DIMM_BOT_COR_ERR(rcv[i][1]);
1565 i7core_rdimm_update_ce_count(mci, i, new0, new1, new2);
1569 /* This function is based on the device 3 function 4 registers as described on:
1570 * Intel Xeon Processor 5500 Series Datasheet Volume 2
1571 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
1572 * also available at:
1573 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
1575 static void i7core_udimm_check_mc_ecc_err(struct mem_ctl_info *mci)
1577 struct i7core_pvt *pvt = mci->pvt_info;
1579 int new0, new1, new2;
1581 if (!pvt->pci_mcr[4]) {
1582 debugf0("%s MCR registers not found\n", __func__);
1586 /* Corrected test errors */
1587 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1);
1588 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0);
1590 /* Store the new values */
1591 new2 = DIMM2_COR_ERR(rcv1);
1592 new1 = DIMM1_COR_ERR(rcv0);
1593 new0 = DIMM0_COR_ERR(rcv0);
1595 /* Updates CE counters if it is not the first time here */
1596 if (pvt->ce_count_available) {
1597 /* Updates CE counters */
1598 int add0, add1, add2;
1600 add2 = new2 - pvt->udimm_last_ce_count[2];
1601 add1 = new1 - pvt->udimm_last_ce_count[1];
1602 add0 = new0 - pvt->udimm_last_ce_count[0];
1606 pvt->udimm_ce_count[2] += add2;
1610 pvt->udimm_ce_count[1] += add1;
1614 pvt->udimm_ce_count[0] += add0;
1616 if (add0 | add1 | add2)
1617 i7core_printk(KERN_ERR, "New Corrected error(s): "
1618 "dimm0: +%d, dimm1: +%d, dimm2 +%d\n",
1621 pvt->ce_count_available = 1;
1623 /* Store the new values */
1624 pvt->udimm_last_ce_count[2] = new2;
1625 pvt->udimm_last_ce_count[1] = new1;
1626 pvt->udimm_last_ce_count[0] = new0;
1630 * According with tables E-11 and E-12 of chapter E.3.3 of Intel 64 and IA-32
1631 * Architectures Software Developer’s Manual Volume 3B.
1632 * Nehalem are defined as family 0x06, model 0x1a
1634 * The MCA registers used here are the following ones:
1635 * struct mce field MCA Register
1636 * m->status MSR_IA32_MC8_STATUS
1637 * m->addr MSR_IA32_MC8_ADDR
1638 * m->misc MSR_IA32_MC8_MISC
1639 * In the case of Nehalem, the error information is masked at .status and .misc
1642 static void i7core_mce_output_error(struct mem_ctl_info *mci,
1645 struct i7core_pvt *pvt = mci->pvt_info;
1646 char *type, *optype, *err, *msg;
1647 unsigned long error = m->status & 0x1ff0000l;
1648 u32 optypenum = (m->status >> 4) & 0x07;
1649 u32 core_err_cnt = (m->status >> 38) && 0x7fff;
1650 u32 dimm = (m->misc >> 16) & 0x3;
1651 u32 channel = (m->misc >> 18) & 0x3;
1652 u32 syndrome = m->misc >> 32;
1653 u32 errnum = find_first_bit(&error, 32);
1656 if (m->mcgstatus & 1)
1661 switch (optypenum) {
1663 optype = "generic undef request";
1666 optype = "read error";
1669 optype = "write error";
1672 optype = "addr/cmd error";
1675 optype = "scrubbing error";
1678 optype = "reserved";
1684 err = "read ECC error";
1687 err = "RAS ECC error";
1690 err = "write parity error";
1693 err = "redundacy loss";
1699 err = "memory range error";
1702 err = "RTID out of range";
1705 err = "address parity error";
1708 err = "byte enable parity error";
1714 /* FIXME: should convert addr into bank and rank information */
1715 msg = kasprintf(GFP_ATOMIC,
1716 "%s (addr = 0x%08llx, cpu=%d, Dimm=%d, Channel=%d, "
1717 "syndrome=0x%08x, count=%d, Err=%08llx:%08llx (%s: %s))\n",
1718 type, (long long) m->addr, m->cpu, dimm, channel,
1719 syndrome, core_err_cnt, (long long)m->status,
1720 (long long)m->misc, optype, err);
1724 csrow = pvt->csrow_map[channel][dimm];
1726 /* Call the helper to output message */
1727 if (m->mcgstatus & 1)
1728 edac_mc_handle_fbd_ue(mci, csrow, 0,
1729 0 /* FIXME: should be channel here */, msg);
1730 else if (!pvt->is_registered)
1731 edac_mc_handle_fbd_ce(mci, csrow,
1732 0 /* FIXME: should be channel here */, msg);
1738 * i7core_check_error Retrieve and process errors reported by the
1739 * hardware. Called by the Core module.
1741 static void i7core_check_error(struct mem_ctl_info *mci)
1743 struct i7core_pvt *pvt = mci->pvt_info;
1749 * MCE first step: Copy all mce errors into a temporary buffer
1750 * We use a double buffering here, to reduce the risk of
1754 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
1757 goto check_ce_error;
1759 m = pvt->mce_outentry;
1760 if (pvt->mce_in + count > MCE_LOG_LEN) {
1761 unsigned l = MCE_LOG_LEN - pvt->mce_in;
1763 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
1769 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
1771 pvt->mce_in += count;
1774 if (pvt->mce_overrun) {
1775 i7core_printk(KERN_ERR, "Lost %d memory errors\n",
1778 pvt->mce_overrun = 0;
1782 * MCE second step: parse errors and display
1784 for (i = 0; i < count; i++)
1785 i7core_mce_output_error(mci, &pvt->mce_outentry[i]);
1788 * Now, let's increment CE error counts
1791 if (!pvt->is_registered)
1792 i7core_udimm_check_mc_ecc_err(mci);
1794 i7core_rdimm_check_mc_ecc_err(mci);
1798 * i7core_mce_check_error Replicates mcelog routine to get errors
1799 * This routine simply queues mcelog errors, and
1800 * return. The error itself should be handled later
1801 * by i7core_check_error.
1802 * WARNING: As this routine should be called at NMI time, extra care should
1803 * be taken to avoid deadlocks, and to be as fast as possible.
1805 static int i7core_mce_check_error(void *priv, struct mce *mce)
1807 struct mem_ctl_info *mci = priv;
1808 struct i7core_pvt *pvt = mci->pvt_info;
1811 * Just let mcelog handle it if the error is
1812 * outside the memory controller
1814 if (((mce->status & 0xffff) >> 7) != 1)
1817 /* Bank 8 registers are the only ones that we know how to handle */
1822 /* Only handle if it is the right mc controller */
1823 if (cpu_data(mce->cpu).phys_proc_id != pvt->i7core_dev->socket)
1828 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
1834 /* Copy memory error at the ringbuffer */
1835 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
1837 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
1839 /* Handle fatal errors immediately */
1840 if (mce->mcgstatus & 1)
1841 i7core_check_error(mci);
1843 /* Advice mcelog that the error were handled */
1847 static int i7core_register_mci(struct i7core_dev *i7core_dev,
1848 int num_channels, int num_csrows)
1850 struct mem_ctl_info *mci;
1851 struct i7core_pvt *pvt;
1855 /* allocate a new MC control structure */
1856 mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels,
1857 i7core_dev->socket);
1861 debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
1863 /* record ptr to the generic device */
1864 mci->dev = &i7core_dev->pdev[0]->dev;
1866 pvt = mci->pvt_info;
1867 memset(pvt, 0, sizeof(*pvt));
1870 * FIXME: how to handle RDDR3 at MCI level? It is possible to have
1871 * Mixed RDDR3/UDDR3 with Nehalem, provided that they are on different
1874 mci->mtype_cap = MEM_FLAG_DDR3;
1875 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1876 mci->edac_cap = EDAC_FLAG_NONE;
1877 mci->mod_name = "i7core_edac.c";
1878 mci->mod_ver = I7CORE_REVISION;
1879 mci->ctl_name = kasprintf(GFP_KERNEL, "i7 core #%d",
1880 i7core_dev->socket);
1881 mci->dev_name = pci_name(i7core_dev->pdev[0]);
1882 mci->ctl_page_to_phys = NULL;
1883 mci->mc_driver_sysfs_attributes = i7core_sysfs_attrs;
1884 /* Set the function pointer to an actual operation function */
1885 mci->edac_check = i7core_check_error;
1887 /* Store pci devices at mci for faster access */
1888 rc = mci_bind_devs(mci, i7core_dev);
1889 if (unlikely(rc < 0))
1892 /* Get dimm basic config */
1893 get_dimm_config(mci, &csrow);
1895 /* add this new MC control structure to EDAC's list of MCs */
1896 if (unlikely(edac_mc_add_mc(mci))) {
1897 debugf0("MC: " __FILE__
1898 ": %s(): failed edac_mc_add_mc()\n", __func__);
1899 /* FIXME: perhaps some code should go here that disables error
1900 * reporting if we just enabled it
1907 /* allocating generic PCI control info */
1908 i7core_pci = edac_pci_create_generic_ctl(&i7core_dev->pdev[0]->dev,
1910 if (unlikely(!i7core_pci)) {
1912 "%s(): Unable to create PCI control\n",
1915 "%s(): PCI error report via EDAC not setup\n",
1919 /* Default error mask is any memory */
1920 pvt->inject.channel = 0;
1921 pvt->inject.dimm = -1;
1922 pvt->inject.rank = -1;
1923 pvt->inject.bank = -1;
1924 pvt->inject.page = -1;
1925 pvt->inject.col = -1;
1927 /* Registers on edac_mce in order to receive memory errors */
1928 pvt->edac_mce.priv = mci;
1929 pvt->edac_mce.check_error = i7core_mce_check_error;
1931 rc = edac_mce_register(&pvt->edac_mce);
1932 if (unlikely(rc < 0)) {
1933 debugf0("MC: " __FILE__
1934 ": %s(): failed edac_mce_register()\n", __func__);
1944 * i7core_probe Probe for ONE instance of device to see if it is
1947 * 0 for FOUND a device
1948 * < 0 for error code
1951 static int probed = 0;
1953 static int __devinit i7core_probe(struct pci_dev *pdev,
1954 const struct pci_device_id *id)
1957 struct i7core_dev *i7core_dev;
1959 /* get the pci devices we want to reserve for our use */
1960 mutex_lock(&i7core_edac_lock);
1963 * All memory controllers are allocated at the first pass.
1965 if (unlikely(probed >= 1)) {
1966 mutex_unlock(&i7core_edac_lock);
1971 rc = i7core_get_devices(pci_dev_table);
1972 if (unlikely(rc < 0))
1975 list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
1979 /* Check the number of active and not disabled channels */
1980 rc = i7core_get_active_channels(i7core_dev->socket,
1981 &channels, &csrows);
1982 if (unlikely(rc < 0))
1985 rc = i7core_register_mci(i7core_dev, channels, csrows);
1986 if (unlikely(rc < 0))
1990 i7core_printk(KERN_INFO, "Driver loaded.\n");
1992 mutex_unlock(&i7core_edac_lock);
1996 i7core_put_all_devices();
1998 mutex_unlock(&i7core_edac_lock);
2003 * i7core_remove destructor for one instance of device
2006 static void __devexit i7core_remove(struct pci_dev *pdev)
2008 struct mem_ctl_info *mci;
2009 struct i7core_dev *i7core_dev, *tmp;
2011 debugf0(__FILE__ ": %s()\n", __func__);
2014 edac_pci_release_generic_ctl(i7core_pci);
2017 * we have a trouble here: pdev value for removal will be wrong, since
2018 * it will point to the X58 register used to detect that the machine
2019 * is a Nehalem or upper design. However, due to the way several PCI
2020 * devices are grouped together to provide MC functionality, we need
2021 * to use a different method for releasing the devices
2024 mutex_lock(&i7core_edac_lock);
2025 list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) {
2026 mci = edac_mc_del_mc(&i7core_dev->pdev[0]->dev);
2028 struct i7core_pvt *pvt = mci->pvt_info;
2030 i7core_dev = pvt->i7core_dev;
2031 edac_mce_unregister(&pvt->edac_mce);
2032 kfree(mci->ctl_name);
2034 i7core_put_devices(i7core_dev);
2036 i7core_printk(KERN_ERR,
2037 "Couldn't find mci for socket %d\n",
2038 i7core_dev->socket);
2043 mutex_unlock(&i7core_edac_lock);
2046 MODULE_DEVICE_TABLE(pci, i7core_pci_tbl);
2049 * i7core_driver pci_driver structure for this module
2052 static struct pci_driver i7core_driver = {
2053 .name = "i7core_edac",
2054 .probe = i7core_probe,
2055 .remove = __devexit_p(i7core_remove),
2056 .id_table = i7core_pci_tbl,
2060 * i7core_init Module entry function
2061 * Try to initialize this module for its devices
2063 static int __init i7core_init(void)
2067 debugf2("MC: " __FILE__ ": %s()\n", __func__);
2069 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
2072 i7core_xeon_pci_fixup(pci_dev_table);
2074 pci_rc = pci_register_driver(&i7core_driver);
2079 i7core_printk(KERN_ERR, "Failed to register device with error %d.\n",
2086 * i7core_exit() Module exit function
2087 * Unregister the driver
2089 static void __exit i7core_exit(void)
2091 debugf2("MC: " __FILE__ ": %s()\n", __func__);
2092 pci_unregister_driver(&i7core_driver);
2095 module_init(i7core_init);
2096 module_exit(i7core_exit);
2098 MODULE_LICENSE("GPL");
2099 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
2100 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
2101 MODULE_DESCRIPTION("MC Driver for Intel i7 Core memory controllers - "
2104 module_param(edac_op_state, int, 0444);
2105 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");