1 /* Intel 7 core Memory Controller kernel module (Nehalem)
3 * This file may be distributed under the terms of the
4 * GNU General Public License version 2 only.
6 * Copyright (c) 2009 by:
7 * Mauro Carvalho Chehab <mchehab@redhat.com>
9 * Red Hat Inc. http://www.redhat.com
11 * Forked and adapted from the i5400_edac driver
13 * Based on the following public Intel datasheets:
14 * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor
15 * Datasheet, Volume 2:
16 * http://download.intel.com/design/processor/datashts/320835.pdf
17 * Intel Xeon Processor 5500 Series Datasheet Volume 2
18 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
20 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/pci.h>
26 #include <linux/pci_ids.h>
27 #include <linux/slab.h>
28 #include <linux/edac.h>
29 #include <linux/mmzone.h>
30 #include <linux/edac_mce.h>
31 #include <linux/smp.h>
32 #include <asm/processor.h>
34 #include "edac_core.h"
37 * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core
38 * registers start at bus 255, and are not reported by BIOS.
39 * We currently find devices with only 2 sockets. In order to support more QPI
40 * Quick Path Interconnect, just increment this number.
42 #define MAX_SOCKET_BUSES 2
46 * Alter this version for the module when modifications are made
48 #define I7CORE_REVISION " Ver: 1.0.0 " __DATE__
49 #define EDAC_MOD_STR "i7core_edac"
54 #define i7core_printk(level, fmt, arg...) \
55 edac_printk(level, "i7core", fmt, ##arg)
57 #define i7core_mc_printk(mci, level, fmt, arg...) \
58 edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg)
61 * i7core Memory Controller Registers
64 /* OFFSETS for Device 0 Function 0 */
66 #define MC_CFG_CONTROL 0x90
68 /* OFFSETS for Device 3 Function 0 */
70 #define MC_CONTROL 0x48
71 #define MC_STATUS 0x4c
72 #define MC_MAX_DOD 0x64
75 * OFFSETS for Device 3 Function 4, as inicated on Xeon 5500 datasheet:
76 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
79 #define MC_TEST_ERR_RCV1 0x60
80 #define DIMM2_COR_ERR(r) ((r) & 0x7fff)
82 #define MC_TEST_ERR_RCV0 0x64
83 #define DIMM1_COR_ERR(r) (((r) >> 16) & 0x7fff)
84 #define DIMM0_COR_ERR(r) ((r) & 0x7fff)
86 /* OFFSETS for Device 3 Function 2, as inicated on Xeon 5500 datasheet */
87 #define MC_COR_ECC_CNT_0 0x80
88 #define MC_COR_ECC_CNT_1 0x84
89 #define MC_COR_ECC_CNT_2 0x88
90 #define MC_COR_ECC_CNT_3 0x8c
91 #define MC_COR_ECC_CNT_4 0x90
92 #define MC_COR_ECC_CNT_5 0x94
94 #define DIMM_TOP_COR_ERR(r) (((r) >> 16) & 0x7fff)
95 #define DIMM_BOT_COR_ERR(r) ((r) & 0x7fff)
98 /* OFFSETS for Devices 4,5 and 6 Function 0 */
100 #define MC_CHANNEL_DIMM_INIT_PARAMS 0x58
101 #define THREE_DIMMS_PRESENT (1 << 24)
102 #define SINGLE_QUAD_RANK_PRESENT (1 << 23)
103 #define QUAD_RANK_PRESENT (1 << 22)
104 #define REGISTERED_DIMM (1 << 15)
106 #define MC_CHANNEL_MAPPER 0x60
107 #define RDLCH(r, ch) ((((r) >> (3 + (ch * 6))) & 0x07) - 1)
108 #define WRLCH(r, ch) ((((r) >> (ch * 6)) & 0x07) - 1)
110 #define MC_CHANNEL_RANK_PRESENT 0x7c
111 #define RANK_PRESENT_MASK 0xffff
113 #define MC_CHANNEL_ADDR_MATCH 0xf0
114 #define MC_CHANNEL_ERROR_MASK 0xf8
115 #define MC_CHANNEL_ERROR_INJECT 0xfc
116 #define INJECT_ADDR_PARITY 0x10
117 #define INJECT_ECC 0x08
118 #define MASK_CACHELINE 0x06
119 #define MASK_FULL_CACHELINE 0x06
120 #define MASK_MSB32_CACHELINE 0x04
121 #define MASK_LSB32_CACHELINE 0x02
122 #define NO_MASK_CACHELINE 0x00
123 #define REPEAT_EN 0x01
125 /* OFFSETS for Devices 4,5 and 6 Function 1 */
127 #define MC_DOD_CH_DIMM0 0x48
128 #define MC_DOD_CH_DIMM1 0x4c
129 #define MC_DOD_CH_DIMM2 0x50
130 #define RANKOFFSET_MASK ((1 << 12) | (1 << 11) | (1 << 10))
131 #define RANKOFFSET(x) ((x & RANKOFFSET_MASK) >> 10)
132 #define DIMM_PRESENT_MASK (1 << 9)
133 #define DIMM_PRESENT(x) (((x) & DIMM_PRESENT_MASK) >> 9)
134 #define MC_DOD_NUMBANK_MASK ((1 << 8) | (1 << 7))
135 #define MC_DOD_NUMBANK(x) (((x) & MC_DOD_NUMBANK_MASK) >> 7)
136 #define MC_DOD_NUMRANK_MASK ((1 << 6) | (1 << 5))
137 #define MC_DOD_NUMRANK(x) (((x) & MC_DOD_NUMRANK_MASK) >> 5)
138 #define MC_DOD_NUMROW_MASK ((1 << 4) | (1 << 3) | (1 << 2))
139 #define MC_DOD_NUMROW(x) (((x) & MC_DOD_NUMROW_MASK) >> 2)
140 #define MC_DOD_NUMCOL_MASK 3
141 #define MC_DOD_NUMCOL(x) ((x) & MC_DOD_NUMCOL_MASK)
143 #define MC_RANK_PRESENT 0x7c
145 #define MC_SAG_CH_0 0x80
146 #define MC_SAG_CH_1 0x84
147 #define MC_SAG_CH_2 0x88
148 #define MC_SAG_CH_3 0x8c
149 #define MC_SAG_CH_4 0x90
150 #define MC_SAG_CH_5 0x94
151 #define MC_SAG_CH_6 0x98
152 #define MC_SAG_CH_7 0x9c
154 #define MC_RIR_LIMIT_CH_0 0x40
155 #define MC_RIR_LIMIT_CH_1 0x44
156 #define MC_RIR_LIMIT_CH_2 0x48
157 #define MC_RIR_LIMIT_CH_3 0x4C
158 #define MC_RIR_LIMIT_CH_4 0x50
159 #define MC_RIR_LIMIT_CH_5 0x54
160 #define MC_RIR_LIMIT_CH_6 0x58
161 #define MC_RIR_LIMIT_CH_7 0x5C
162 #define MC_RIR_LIMIT_MASK ((1 << 10) - 1)
164 #define MC_RIR_WAY_CH 0x80
165 #define MC_RIR_WAY_OFFSET_MASK (((1 << 14) - 1) & ~0x7)
166 #define MC_RIR_WAY_RANK_MASK 0x7
173 #define MAX_DIMMS 3 /* Max DIMMS per channel */
174 #define MAX_MCR_FUNC 4
175 #define MAX_CHAN_FUNC 3
185 struct i7core_inject {
192 /* Error address mask */
193 int channel, dimm, rank, bank, page, col;
196 struct i7core_channel {
201 struct pci_id_descr {
208 struct list_head list;
210 struct pci_dev **pdev;
211 struct mem_ctl_info *mci;
215 struct pci_dev *pci_noncore;
216 struct pci_dev *pci_mcr[MAX_MCR_FUNC + 1];
217 struct pci_dev *pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1];
219 struct i7core_dev *i7core_dev;
221 struct i7core_info info;
222 struct i7core_inject inject;
223 struct i7core_channel channel[NUM_CHANS];
225 int channels; /* Number of active channels */
227 int ce_count_available;
228 int csrow_map[NUM_CHANS][MAX_DIMMS];
230 /* ECC corrected errors counts per udimm */
231 unsigned long udimm_ce_count[MAX_DIMMS];
232 int udimm_last_ce_count[MAX_DIMMS];
233 /* ECC corrected errors counts per rdimm */
234 unsigned long rdimm_ce_count[NUM_CHANS][MAX_DIMMS];
235 int rdimm_last_ce_count[NUM_CHANS][MAX_DIMMS];
237 unsigned int is_registered;
240 struct edac_mce edac_mce;
242 /* Fifo double buffers */
243 struct mce mce_entry[MCE_LOG_LEN];
244 struct mce mce_outentry[MCE_LOG_LEN];
246 /* Fifo in/out counters */
247 unsigned mce_in, mce_out;
249 /* Count indicator to show errors not got */
250 unsigned mce_overrun;
254 static LIST_HEAD(i7core_edac_list);
255 static DEFINE_MUTEX(i7core_edac_lock);
257 #define PCI_DESCR(device, function, device_id) \
259 .func = (function), \
260 .dev_id = (device_id)
262 struct pci_id_descr pci_dev_descr[] = {
263 /* Memory controller */
264 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) },
265 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) },
266 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS) }, /* if RDIMM */
267 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },
270 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) },
271 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) },
272 { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) },
273 { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC) },
276 { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) },
277 { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) },
278 { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) },
279 { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC) },
282 { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) },
283 { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
284 { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
285 { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC) },
287 /* Generic Non-core registers */
289 * This is the PCI device on i7core and on Xeon 35xx (8086:2c41)
290 * On Xeon 55xx, however, it has a different id (8086:2c40). So,
291 * the probing code needs to test for the other address in case of
292 * failure of this one
294 { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NONCORE) },
297 #define N_DEVS ARRAY_SIZE(pci_dev_descr)
300 * pci_device_id table for which devices we are looking for
302 static const struct pci_device_id i7core_pci_tbl[] __devinitdata = {
303 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},
304 {0,} /* 0 terminated list. */
307 static struct edac_pci_ctl_info *i7core_pci;
309 /****************************************************************************
310 Anciliary status routines
311 ****************************************************************************/
313 /* MC_CONTROL bits */
314 #define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch)))
315 #define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1))
318 #define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4))
319 #define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch))
321 /* MC_MAX_DOD read functions */
322 static inline int numdimms(u32 dimms)
324 return (dimms & 0x3) + 1;
327 static inline int numrank(u32 rank)
329 static int ranks[4] = { 1, 2, 4, -EINVAL };
331 return ranks[rank & 0x3];
334 static inline int numbank(u32 bank)
336 static int banks[4] = { 4, 8, 16, -EINVAL };
338 return banks[bank & 0x3];
341 static inline int numrow(u32 row)
343 static int rows[8] = {
344 1 << 12, 1 << 13, 1 << 14, 1 << 15,
345 1 << 16, -EINVAL, -EINVAL, -EINVAL,
348 return rows[row & 0x7];
351 static inline int numcol(u32 col)
353 static int cols[8] = {
354 1 << 10, 1 << 11, 1 << 12, -EINVAL,
356 return cols[col & 0x3];
359 static struct i7core_dev *get_i7core_dev(u8 socket)
361 struct i7core_dev *i7core_dev;
363 list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
364 if (i7core_dev->socket == socket)
371 /****************************************************************************
372 Memory check routines
373 ****************************************************************************/
374 static struct pci_dev *get_pdev_slot_func(u8 socket, unsigned slot,
377 struct i7core_dev *i7core_dev = get_i7core_dev(socket);
383 for (i = 0; i < N_DEVS; i++) {
384 if (!i7core_dev->pdev[i])
387 if (PCI_SLOT(i7core_dev->pdev[i]->devfn) == slot &&
388 PCI_FUNC(i7core_dev->pdev[i]->devfn) == func) {
389 return i7core_dev->pdev[i];
397 * i7core_get_active_channels() - gets the number of channels and csrows
398 * @socket: Quick Path Interconnect socket
399 * @channels: Number of channels that will be returned
400 * @csrows: Number of csrows found
402 * Since EDAC core needs to know in advance the number of available channels
403 * and csrows, in order to allocate memory for csrows/channels, it is needed
404 * to run two similar steps. At the first step, implemented on this function,
405 * it checks the number of csrows/channels present at one socket.
406 * this is used in order to properly allocate the size of mci components.
408 * It should be noticed that none of the current available datasheets explain
409 * or even mention how csrows are seen by the memory controller. So, we need
410 * to add a fake description for csrows.
411 * So, this driver is attributing one DIMM memory for one csrow.
413 static int i7core_get_active_channels(u8 socket, unsigned *channels,
416 struct pci_dev *pdev = NULL;
423 pdev = get_pdev_slot_func(socket, 3, 0);
425 i7core_printk(KERN_ERR, "Couldn't find socket %d fn 3.0!!!\n",
430 /* Device 3 function 0 reads */
431 pci_read_config_dword(pdev, MC_STATUS, &status);
432 pci_read_config_dword(pdev, MC_CONTROL, &control);
434 for (i = 0; i < NUM_CHANS; i++) {
436 /* Check if the channel is active */
437 if (!(control & (1 << (8 + i))))
440 /* Check if the channel is disabled */
441 if (status & (1 << i))
444 pdev = get_pdev_slot_func(socket, i + 4, 1);
446 i7core_printk(KERN_ERR, "Couldn't find socket %d "
451 /* Devices 4-6 function 1 */
452 pci_read_config_dword(pdev,
453 MC_DOD_CH_DIMM0, &dimm_dod[0]);
454 pci_read_config_dword(pdev,
455 MC_DOD_CH_DIMM1, &dimm_dod[1]);
456 pci_read_config_dword(pdev,
457 MC_DOD_CH_DIMM2, &dimm_dod[2]);
461 for (j = 0; j < 3; j++) {
462 if (!DIMM_PRESENT(dimm_dod[j]))
468 debugf0("Number of active channels on socket %d: %d\n",
474 static int get_dimm_config(struct mem_ctl_info *mci, int *csrow)
476 struct i7core_pvt *pvt = mci->pvt_info;
477 struct csrow_info *csr;
478 struct pci_dev *pdev;
480 unsigned long last_page = 0;
484 /* Get data from the MC register, function 0 */
485 pdev = pvt->pci_mcr[0];
489 /* Device 3 function 0 reads */
490 pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control);
491 pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status);
492 pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod);
493 pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map);
495 debugf0("QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n",
496 pvt->i7core_dev->socket, pvt->info.mc_control, pvt->info.mc_status,
497 pvt->info.max_dod, pvt->info.ch_map);
499 if (ECC_ENABLED(pvt)) {
500 debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4);
502 mode = EDAC_S8ECD8ED;
504 mode = EDAC_S4ECD4ED;
506 debugf0("ECC disabled\n");
510 /* FIXME: need to handle the error codes */
511 debugf0("DOD Max limits: DIMMS: %d, %d-ranked, %d-banked "
513 numdimms(pvt->info.max_dod),
514 numrank(pvt->info.max_dod >> 2),
515 numbank(pvt->info.max_dod >> 4),
516 numrow(pvt->info.max_dod >> 6),
517 numcol(pvt->info.max_dod >> 9));
519 for (i = 0; i < NUM_CHANS; i++) {
520 u32 data, dimm_dod[3], value[8];
522 if (!CH_ACTIVE(pvt, i)) {
523 debugf0("Channel %i is not active\n", i);
526 if (CH_DISABLED(pvt, i)) {
527 debugf0("Channel %i is disabled\n", i);
531 /* Devices 4-6 function 0 */
532 pci_read_config_dword(pvt->pci_ch[i][0],
533 MC_CHANNEL_DIMM_INIT_PARAMS, &data);
535 pvt->channel[i].ranks = (data & QUAD_RANK_PRESENT) ?
538 if (data & REGISTERED_DIMM)
543 if (data & THREE_DIMMS_PRESENT)
544 pvt->channel[i].dimms = 3;
545 else if (data & SINGLE_QUAD_RANK_PRESENT)
546 pvt->channel[i].dimms = 1;
548 pvt->channel[i].dimms = 2;
551 /* Devices 4-6 function 1 */
552 pci_read_config_dword(pvt->pci_ch[i][1],
553 MC_DOD_CH_DIMM0, &dimm_dod[0]);
554 pci_read_config_dword(pvt->pci_ch[i][1],
555 MC_DOD_CH_DIMM1, &dimm_dod[1]);
556 pci_read_config_dword(pvt->pci_ch[i][1],
557 MC_DOD_CH_DIMM2, &dimm_dod[2]);
559 debugf0("Ch%d phy rd%d, wr%d (0x%08x): "
560 "%d ranks, %cDIMMs\n",
562 RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
564 pvt->channel[i].ranks,
565 (data & REGISTERED_DIMM) ? 'R' : 'U');
567 for (j = 0; j < 3; j++) {
568 u32 banks, ranks, rows, cols;
571 if (!DIMM_PRESENT(dimm_dod[j]))
574 banks = numbank(MC_DOD_NUMBANK(dimm_dod[j]));
575 ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j]));
576 rows = numrow(MC_DOD_NUMROW(dimm_dod[j]));
577 cols = numcol(MC_DOD_NUMCOL(dimm_dod[j]));
579 /* DDR3 has 8 I/O banks */
580 size = (rows * cols * banks * ranks) >> (20 - 3);
582 pvt->channel[i].dimms++;
584 debugf0("\tdimm %d %d Mb offset: %x, "
585 "bank: %d, rank: %d, row: %#x, col: %#x\n",
587 RANKOFFSET(dimm_dod[j]),
588 banks, ranks, rows, cols);
591 npages = size >> (PAGE_SHIFT - 20);
593 npages = size << (20 - PAGE_SHIFT);
596 csr = &mci->csrows[*csrow];
597 csr->first_page = last_page + 1;
599 csr->last_page = last_page;
600 csr->nr_pages = npages;
604 csr->csrow_idx = *csrow;
605 csr->nr_channels = 1;
607 csr->channels[0].chan_idx = i;
608 csr->channels[0].ce_count = 0;
610 pvt->csrow_map[i][j] = *csrow;
620 csr->dtype = DEV_X16;
623 csr->dtype = DEV_UNKNOWN;
626 csr->edac_mode = mode;
632 pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
633 pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]);
634 pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]);
635 pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]);
636 pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]);
637 pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);
638 pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);
639 pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);
640 debugf1("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
641 for (j = 0; j < 8; j++)
642 debugf1("\t\t%#x\t%#x\t%#x\n",
643 (value[j] >> 27) & 0x1,
644 (value[j] >> 24) & 0x7,
645 (value[j] && ((1 << 24) - 1)));
651 /****************************************************************************
652 Error insertion routines
653 ****************************************************************************/
655 /* The i7core has independent error injection features per channel.
656 However, to have a simpler code, we don't allow enabling error injection
657 on more than one channel.
658 Also, since a change at an inject parameter will be applied only at enable,
659 we're disabling error injection on all write calls to the sysfs nodes that
660 controls the error code injection.
662 static int disable_inject(struct mem_ctl_info *mci)
664 struct i7core_pvt *pvt = mci->pvt_info;
666 pvt->inject.enable = 0;
668 if (!pvt->pci_ch[pvt->inject.channel][0])
671 pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
672 MC_CHANNEL_ERROR_INJECT, 0);
678 * i7core inject inject.section
680 * accept and store error injection inject.section value
681 * bit 0 - refers to the lower 32-byte half cacheline
682 * bit 1 - refers to the upper 32-byte half cacheline
684 static ssize_t i7core_inject_section_store(struct mem_ctl_info *mci,
685 const char *data, size_t count)
687 struct i7core_pvt *pvt = mci->pvt_info;
691 if (pvt->inject.enable)
694 rc = strict_strtoul(data, 10, &value);
695 if ((rc < 0) || (value > 3))
698 pvt->inject.section = (u32) value;
702 static ssize_t i7core_inject_section_show(struct mem_ctl_info *mci,
705 struct i7core_pvt *pvt = mci->pvt_info;
706 return sprintf(data, "0x%08x\n", pvt->inject.section);
712 * accept and store error injection inject.section value
713 * bit 0 - repeat enable - Enable error repetition
714 * bit 1 - inject ECC error
715 * bit 2 - inject parity error
717 static ssize_t i7core_inject_type_store(struct mem_ctl_info *mci,
718 const char *data, size_t count)
720 struct i7core_pvt *pvt = mci->pvt_info;
724 if (pvt->inject.enable)
727 rc = strict_strtoul(data, 10, &value);
728 if ((rc < 0) || (value > 7))
731 pvt->inject.type = (u32) value;
735 static ssize_t i7core_inject_type_show(struct mem_ctl_info *mci,
738 struct i7core_pvt *pvt = mci->pvt_info;
739 return sprintf(data, "0x%08x\n", pvt->inject.type);
743 * i7core_inject_inject.eccmask_store
745 * The type of error (UE/CE) will depend on the inject.eccmask value:
746 * Any bits set to a 1 will flip the corresponding ECC bit
747 * Correctable errors can be injected by flipping 1 bit or the bits within
748 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
749 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
750 * uncorrectable error to be injected.
752 static ssize_t i7core_inject_eccmask_store(struct mem_ctl_info *mci,
753 const char *data, size_t count)
755 struct i7core_pvt *pvt = mci->pvt_info;
759 if (pvt->inject.enable)
762 rc = strict_strtoul(data, 10, &value);
766 pvt->inject.eccmask = (u32) value;
770 static ssize_t i7core_inject_eccmask_show(struct mem_ctl_info *mci,
773 struct i7core_pvt *pvt = mci->pvt_info;
774 return sprintf(data, "0x%08x\n", pvt->inject.eccmask);
780 * The type of error (UE/CE) will depend on the inject.eccmask value:
781 * Any bits set to a 1 will flip the corresponding ECC bit
782 * Correctable errors can be injected by flipping 1 bit or the bits within
783 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
784 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
785 * uncorrectable error to be injected.
788 #define DECLARE_ADDR_MATCH(param, limit) \
789 static ssize_t i7core_inject_store_##param( \
790 struct mem_ctl_info *mci, \
791 const char *data, size_t count) \
793 struct i7core_pvt *pvt; \
797 debugf1("%s()\n", __func__); \
798 pvt = mci->pvt_info; \
800 if (pvt->inject.enable) \
801 disable_inject(mci); \
803 if (!strcasecmp(data, "any") || !strcasecmp(data, "any\n"))\
806 rc = strict_strtoul(data, 10, &value); \
807 if ((rc < 0) || (value >= limit)) \
811 pvt->inject.param = value; \
816 static ssize_t i7core_inject_show_##param( \
817 struct mem_ctl_info *mci, \
820 struct i7core_pvt *pvt; \
822 pvt = mci->pvt_info; \
823 debugf1("%s() pvt=%p\n", __func__, pvt); \
824 if (pvt->inject.param < 0) \
825 return sprintf(data, "any\n"); \
827 return sprintf(data, "%d\n", pvt->inject.param);\
830 #define ATTR_ADDR_MATCH(param) \
834 .mode = (S_IRUGO | S_IWUSR) \
836 .show = i7core_inject_show_##param, \
837 .store = i7core_inject_store_##param, \
840 DECLARE_ADDR_MATCH(channel, 3);
841 DECLARE_ADDR_MATCH(dimm, 3);
842 DECLARE_ADDR_MATCH(rank, 4);
843 DECLARE_ADDR_MATCH(bank, 32);
844 DECLARE_ADDR_MATCH(page, 0x10000);
845 DECLARE_ADDR_MATCH(col, 0x4000);
847 static int write_and_test(struct pci_dev *dev, int where, u32 val)
852 debugf0("setting pci %02x:%02x.%x reg=%02x value=%08x\n",
853 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
856 for (count = 0; count < 10; count++) {
859 pci_write_config_dword(dev, where, val);
860 pci_read_config_dword(dev, where, &read);
866 i7core_printk(KERN_ERR, "Error during set pci %02x:%02x.%x reg=%02x "
867 "write=%08x. Read=%08x\n",
868 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
875 * This routine prepares the Memory Controller for error injection.
876 * The error will be injected when some process tries to write to the
877 * memory that matches the given criteria.
878 * The criteria can be set in terms of a mask where dimm, rank, bank, page
879 * and col can be specified.
880 * A -1 value for any of the mask items will make the MCU to ignore
881 * that matching criteria for error injection.
883 * It should be noticed that the error will only happen after a write operation
884 * on a memory that matches the condition. if REPEAT_EN is not enabled at
885 * inject mask, then it will produce just one error. Otherwise, it will repeat
886 * until the injectmask would be cleaned.
888 * FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD
889 * is reliable enough to check if the MC is using the
890 * three channels. However, this is not clear at the datasheet.
892 static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
893 const char *data, size_t count)
895 struct i7core_pvt *pvt = mci->pvt_info;
901 if (!pvt->pci_ch[pvt->inject.channel][0])
904 rc = strict_strtoul(data, 10, &enable);
909 pvt->inject.enable = 1;
915 /* Sets pvt->inject.dimm mask */
916 if (pvt->inject.dimm < 0)
919 if (pvt->channel[pvt->inject.channel].dimms > 2)
920 mask |= (pvt->inject.dimm & 0x3L) << 35;
922 mask |= (pvt->inject.dimm & 0x1L) << 36;
925 /* Sets pvt->inject.rank mask */
926 if (pvt->inject.rank < 0)
929 if (pvt->channel[pvt->inject.channel].dimms > 2)
930 mask |= (pvt->inject.rank & 0x1L) << 34;
932 mask |= (pvt->inject.rank & 0x3L) << 34;
935 /* Sets pvt->inject.bank mask */
936 if (pvt->inject.bank < 0)
939 mask |= (pvt->inject.bank & 0x15L) << 30;
941 /* Sets pvt->inject.page mask */
942 if (pvt->inject.page < 0)
945 mask |= (pvt->inject.page & 0xffffL) << 14;
947 /* Sets pvt->inject.column mask */
948 if (pvt->inject.col < 0)
951 mask |= (pvt->inject.col & 0x3fffL);
955 * bits 1-2: MASK_HALF_CACHELINE
957 * bit 4: INJECT_ADDR_PARITY
960 injectmask = (pvt->inject.type & 1) |
961 (pvt->inject.section & 0x3) << 1 |
962 (pvt->inject.type & 0x6) << (3 - 1);
964 /* Unlock writes to registers - this register is write only */
965 pci_write_config_dword(pvt->pci_noncore,
966 MC_CFG_CONTROL, 0x2);
968 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
969 MC_CHANNEL_ADDR_MATCH, mask);
970 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
971 MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L);
973 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
974 MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);
976 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
977 MC_CHANNEL_ERROR_INJECT, injectmask);
980 * This is something undocumented, based on my tests
981 * Without writing 8 to this register, errors aren't injected. Not sure
984 pci_write_config_dword(pvt->pci_noncore,
987 debugf0("Error inject addr match 0x%016llx, ecc 0x%08x,"
989 mask, pvt->inject.eccmask, injectmask);
995 static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci,
998 struct i7core_pvt *pvt = mci->pvt_info;
1001 pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
1002 MC_CHANNEL_ERROR_INJECT, &injectmask);
1004 debugf0("Inject error read: 0x%018x\n", injectmask);
1006 if (injectmask & 0x0c)
1007 pvt->inject.enable = 1;
1009 return sprintf(data, "%d\n", pvt->inject.enable);
1012 #define DECLARE_COUNTER(param) \
1013 static ssize_t i7core_show_counter_##param( \
1014 struct mem_ctl_info *mci, \
1017 struct i7core_pvt *pvt = mci->pvt_info; \
1019 debugf1("%s() \n", __func__); \
1020 if (!pvt->ce_count_available || (pvt->is_registered)) \
1021 return sprintf(data, "data unavailable\n"); \
1022 return sprintf(data, "%lu\n", \
1023 pvt->udimm_ce_count[param]); \
1026 #define ATTR_COUNTER(param) \
1029 .name = __stringify(udimm##param), \
1030 .mode = (S_IRUGO | S_IWUSR) \
1032 .show = i7core_show_counter_##param \
1044 static struct mcidev_sysfs_attribute i7core_addrmatch_attrs[] = {
1045 ATTR_ADDR_MATCH(channel),
1046 ATTR_ADDR_MATCH(dimm),
1047 ATTR_ADDR_MATCH(rank),
1048 ATTR_ADDR_MATCH(bank),
1049 ATTR_ADDR_MATCH(page),
1050 ATTR_ADDR_MATCH(col),
1051 { .attr = { .name = NULL } }
1054 static struct mcidev_sysfs_group i7core_inject_addrmatch = {
1055 .name = "inject_addrmatch",
1056 .mcidev_attr = i7core_addrmatch_attrs,
1059 static struct mcidev_sysfs_attribute i7core_udimm_counters_attrs[] = {
1065 static struct mcidev_sysfs_group i7core_udimm_counters = {
1066 .name = "all_channel_counts",
1067 .mcidev_attr = i7core_udimm_counters_attrs,
1070 static struct mcidev_sysfs_attribute i7core_sysfs_attrs[] = {
1073 .name = "inject_section",
1074 .mode = (S_IRUGO | S_IWUSR)
1076 .show = i7core_inject_section_show,
1077 .store = i7core_inject_section_store,
1080 .name = "inject_type",
1081 .mode = (S_IRUGO | S_IWUSR)
1083 .show = i7core_inject_type_show,
1084 .store = i7core_inject_type_store,
1087 .name = "inject_eccmask",
1088 .mode = (S_IRUGO | S_IWUSR)
1090 .show = i7core_inject_eccmask_show,
1091 .store = i7core_inject_eccmask_store,
1093 .grp = &i7core_inject_addrmatch,
1096 .name = "inject_enable",
1097 .mode = (S_IRUGO | S_IWUSR)
1099 .show = i7core_inject_enable_show,
1100 .store = i7core_inject_enable_store,
1102 { .attr = { .name = NULL } }, /* Reserved for udimm counters */
1103 { .attr = { .name = NULL } }
1106 /****************************************************************************
1107 Device initialization routines: put/get, init/exit
1108 ****************************************************************************/
1111 * i7core_put_devices 'put' all the devices that we have
1112 * reserved via 'get'
1114 static void i7core_put_devices(struct i7core_dev *i7core_dev)
1118 debugf0(__FILE__ ": %s()\n", __func__);
1119 for (i = 0; i < N_DEVS; i++) {
1120 struct pci_dev *pdev = i7core_dev->pdev[i];
1123 debugf0("Removing dev %02x:%02x.%d\n",
1125 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1128 kfree(i7core_dev->pdev);
1129 list_del(&i7core_dev->list);
1133 static void i7core_put_all_devices(void)
1135 struct i7core_dev *i7core_dev, *tmp;
1137 list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list)
1138 i7core_put_devices(i7core_dev);
1141 static void i7core_xeon_pci_fixup(void)
1143 struct pci_dev *pdev = NULL;
1146 * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core pci buses
1147 * aren't announced by acpi. So, we need to use a legacy scan probing
1150 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1151 pci_dev_descr[0].dev_id, NULL);
1152 if (unlikely(!pdev)) {
1153 for (i = 0; i < MAX_SOCKET_BUSES; i++)
1154 pcibios_scan_specific_bus(255-i);
1159 * i7core_get_devices Find and perform 'get' operation on the MCH's
1160 * device/functions we want to reference for this driver
1162 * Need to 'get' device 16 func 1 and func 2
1164 int i7core_get_onedevice(struct pci_dev **prev, int devno)
1166 struct i7core_dev *i7core_dev;
1168 struct pci_dev *pdev = NULL;
1172 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1173 pci_dev_descr[devno].dev_id, *prev);
1176 * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core regs
1177 * is at addr 8086:2c40, instead of 8086:2c41. So, we need
1178 * to probe for the alternate address in case of failure
1180 if (pci_dev_descr[devno].dev_id == PCI_DEVICE_ID_INTEL_I7_NONCORE && !pdev)
1181 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1182 PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT, *prev);
1191 * Dev 3 function 2 only exists on chips with RDIMMs
1192 * so, it is ok to not found it
1194 if ((pci_dev_descr[devno].dev == 3) && (pci_dev_descr[devno].func == 2)) {
1199 i7core_printk(KERN_ERR,
1200 "Device not found: dev %02x.%d PCI ID %04x:%04x\n",
1201 pci_dev_descr[devno].dev, pci_dev_descr[devno].func,
1202 PCI_VENDOR_ID_INTEL, pci_dev_descr[devno].dev_id);
1204 /* End of list, leave */
1207 bus = pdev->bus->number;
1214 i7core_dev = get_i7core_dev(socket);
1216 i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL);
1219 i7core_dev->pdev = kzalloc(sizeof(*i7core_dev->pdev) * N_DEVS,
1221 if (!i7core_dev->pdev)
1223 i7core_dev->socket = socket;
1224 list_add_tail(&i7core_dev->list, &i7core_edac_list);
1227 if (i7core_dev->pdev[devno]) {
1228 i7core_printk(KERN_ERR,
1229 "Duplicated device for "
1230 "dev %02x:%02x.%d PCI ID %04x:%04x\n",
1231 bus, pci_dev_descr[devno].dev, pci_dev_descr[devno].func,
1232 PCI_VENDOR_ID_INTEL, pci_dev_descr[devno].dev_id);
1237 i7core_dev->pdev[devno] = pdev;
1240 if (unlikely(PCI_SLOT(pdev->devfn) != pci_dev_descr[devno].dev ||
1241 PCI_FUNC(pdev->devfn) != pci_dev_descr[devno].func)) {
1242 i7core_printk(KERN_ERR,
1243 "Device PCI ID %04x:%04x "
1244 "has dev %02x:%02x.%d instead of dev %02x:%02x.%d\n",
1245 PCI_VENDOR_ID_INTEL, pci_dev_descr[devno].dev_id,
1246 bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1247 bus, pci_dev_descr[devno].dev, pci_dev_descr[devno].func);
1251 /* Be sure that the device is enabled */
1252 if (unlikely(pci_enable_device(pdev) < 0)) {
1253 i7core_printk(KERN_ERR,
1255 "dev %02x:%02x.%d PCI ID %04x:%04x\n",
1256 bus, pci_dev_descr[devno].dev, pci_dev_descr[devno].func,
1257 PCI_VENDOR_ID_INTEL, pci_dev_descr[devno].dev_id);
1261 debugf0("Detected socket %d dev %02x:%02x.%d PCI ID %04x:%04x\n",
1262 socket, bus, pci_dev_descr[devno].dev,
1263 pci_dev_descr[devno].func,
1264 PCI_VENDOR_ID_INTEL, pci_dev_descr[devno].dev_id);
1271 static int i7core_get_devices(void)
1274 struct pci_dev *pdev = NULL;
1276 for (i = 0; i < N_DEVS; i++) {
1279 if (i7core_get_onedevice(&pdev, i) < 0) {
1280 i7core_put_all_devices();
1289 static int mci_bind_devs(struct mem_ctl_info *mci,
1290 struct i7core_dev *i7core_dev)
1292 struct i7core_pvt *pvt = mci->pvt_info;
1293 struct pci_dev *pdev;
1296 /* Associates i7core_dev and mci for future usage */
1297 pvt->i7core_dev = i7core_dev;
1298 i7core_dev->mci = mci;
1300 pvt->is_registered = 0;
1301 for (i = 0; i < N_DEVS; i++) {
1302 pdev = i7core_dev->pdev[i];
1306 func = PCI_FUNC(pdev->devfn);
1307 slot = PCI_SLOT(pdev->devfn);
1309 if (unlikely(func > MAX_MCR_FUNC))
1311 pvt->pci_mcr[func] = pdev;
1312 } else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) {
1313 if (unlikely(func > MAX_CHAN_FUNC))
1315 pvt->pci_ch[slot - 4][func] = pdev;
1316 } else if (!slot && !func)
1317 pvt->pci_noncore = pdev;
1321 debugf0("Associated fn %d.%d, dev = %p, socket %d\n",
1322 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1323 pdev, i7core_dev->socket);
1325 if (PCI_SLOT(pdev->devfn) == 3 &&
1326 PCI_FUNC(pdev->devfn) == 2)
1327 pvt->is_registered = 1;
1331 * Add extra nodes to count errors on udimm
1332 * For registered memory, this is not needed, since the counters
1333 * are already displayed at the standard locations
1335 if (!pvt->is_registered)
1336 i7core_sysfs_attrs[ARRAY_SIZE(i7core_sysfs_attrs)-2].grp =
1337 &i7core_udimm_counters;
1342 i7core_printk(KERN_ERR, "Device %d, function %d "
1343 "is out of the expected range\n",
1348 /****************************************************************************
1349 Error check routines
1350 ****************************************************************************/
1351 static void i7core_rdimm_update_csrow(struct mem_ctl_info *mci,
1352 int chan, int dimm, int add)
1355 struct i7core_pvt *pvt = mci->pvt_info;
1356 int row = pvt->csrow_map[chan][dimm], i;
1358 for (i = 0; i < add; i++) {
1359 msg = kasprintf(GFP_KERNEL, "Corrected error "
1360 "(Socket=%d channel=%d dimm=%d)",
1361 pvt->i7core_dev->socket, chan, dimm);
1363 edac_mc_handle_fbd_ce(mci, row, 0, msg);
1368 static void i7core_rdimm_update_ce_count(struct mem_ctl_info *mci,
1369 int chan, int new0, int new1, int new2)
1371 struct i7core_pvt *pvt = mci->pvt_info;
1372 int add0 = 0, add1 = 0, add2 = 0;
1373 /* Updates CE counters if it is not the first time here */
1374 if (pvt->ce_count_available) {
1375 /* Updates CE counters */
1377 add2 = new2 - pvt->rdimm_last_ce_count[chan][2];
1378 add1 = new1 - pvt->rdimm_last_ce_count[chan][1];
1379 add0 = new0 - pvt->rdimm_last_ce_count[chan][0];
1383 pvt->rdimm_ce_count[chan][2] += add2;
1387 pvt->rdimm_ce_count[chan][1] += add1;
1391 pvt->rdimm_ce_count[chan][0] += add0;
1393 pvt->ce_count_available = 1;
1395 /* Store the new values */
1396 pvt->rdimm_last_ce_count[chan][2] = new2;
1397 pvt->rdimm_last_ce_count[chan][1] = new1;
1398 pvt->rdimm_last_ce_count[chan][0] = new0;
1400 /*updated the edac core */
1402 i7core_rdimm_update_csrow(mci, chan, 0, add0);
1404 i7core_rdimm_update_csrow(mci, chan, 1, add1);
1406 i7core_rdimm_update_csrow(mci, chan, 2, add2);
1410 static void i7core_rdimm_check_mc_ecc_err(struct mem_ctl_info *mci)
1412 struct i7core_pvt *pvt = mci->pvt_info;
1414 int i, new0, new1, new2;
1416 /*Read DEV 3: FUN 2: MC_COR_ECC_CNT regs directly*/
1417 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0,
1419 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1,
1421 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2,
1423 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3,
1425 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4,
1427 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5,
1429 for (i = 0 ; i < 3; i++) {
1430 debugf3("MC_COR_ECC_CNT%d = 0x%x; MC_COR_ECC_CNT%d = 0x%x\n",
1431 (i * 2), rcv[i][0], (i * 2) + 1, rcv[i][1]);
1432 /*if the channel has 3 dimms*/
1433 if (pvt->channel[i].dimms > 2) {
1434 new0 = DIMM_BOT_COR_ERR(rcv[i][0]);
1435 new1 = DIMM_TOP_COR_ERR(rcv[i][0]);
1436 new2 = DIMM_BOT_COR_ERR(rcv[i][1]);
1438 new0 = DIMM_TOP_COR_ERR(rcv[i][0]) +
1439 DIMM_BOT_COR_ERR(rcv[i][0]);
1440 new1 = DIMM_TOP_COR_ERR(rcv[i][1]) +
1441 DIMM_BOT_COR_ERR(rcv[i][1]);
1445 i7core_rdimm_update_ce_count(mci, i, new0, new1, new2);
1449 /* This function is based on the device 3 function 4 registers as described on:
1450 * Intel Xeon Processor 5500 Series Datasheet Volume 2
1451 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
1452 * also available at:
1453 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
1455 static void i7core_udimm_check_mc_ecc_err(struct mem_ctl_info *mci)
1457 struct i7core_pvt *pvt = mci->pvt_info;
1459 int new0, new1, new2;
1461 if (!pvt->pci_mcr[4]) {
1462 debugf0("%s MCR registers not found\n", __func__);
1466 /* Corrected test errors */
1467 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1);
1468 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0);
1470 /* Store the new values */
1471 new2 = DIMM2_COR_ERR(rcv1);
1472 new1 = DIMM1_COR_ERR(rcv0);
1473 new0 = DIMM0_COR_ERR(rcv0);
1475 /* Updates CE counters if it is not the first time here */
1476 if (pvt->ce_count_available) {
1477 /* Updates CE counters */
1478 int add0, add1, add2;
1480 add2 = new2 - pvt->udimm_last_ce_count[2];
1481 add1 = new1 - pvt->udimm_last_ce_count[1];
1482 add0 = new0 - pvt->udimm_last_ce_count[0];
1486 pvt->udimm_ce_count[2] += add2;
1490 pvt->udimm_ce_count[1] += add1;
1494 pvt->udimm_ce_count[0] += add0;
1496 if (add0 | add1 | add2)
1497 i7core_printk(KERN_ERR, "New Corrected error(s): "
1498 "dimm0: +%d, dimm1: +%d, dimm2 +%d\n",
1501 pvt->ce_count_available = 1;
1503 /* Store the new values */
1504 pvt->udimm_last_ce_count[2] = new2;
1505 pvt->udimm_last_ce_count[1] = new1;
1506 pvt->udimm_last_ce_count[0] = new0;
1510 * According with tables E-11 and E-12 of chapter E.3.3 of Intel 64 and IA-32
1511 * Architectures Software Developer’s Manual Volume 3B.
1512 * Nehalem are defined as family 0x06, model 0x1a
1514 * The MCA registers used here are the following ones:
1515 * struct mce field MCA Register
1516 * m->status MSR_IA32_MC8_STATUS
1517 * m->addr MSR_IA32_MC8_ADDR
1518 * m->misc MSR_IA32_MC8_MISC
1519 * In the case of Nehalem, the error information is masked at .status and .misc
1522 static void i7core_mce_output_error(struct mem_ctl_info *mci,
1525 struct i7core_pvt *pvt = mci->pvt_info;
1526 char *type, *optype, *err, *msg;
1527 unsigned long error = m->status & 0x1ff0000l;
1528 u32 optypenum = (m->status >> 4) & 0x07;
1529 u32 core_err_cnt = (m->status >> 38) && 0x7fff;
1530 u32 dimm = (m->misc >> 16) & 0x3;
1531 u32 channel = (m->misc >> 18) & 0x3;
1532 u32 syndrome = m->misc >> 32;
1533 u32 errnum = find_first_bit(&error, 32);
1536 if (m->mcgstatus & 1)
1541 switch (optypenum) {
1543 optype = "generic undef request";
1546 optype = "read error";
1549 optype = "write error";
1552 optype = "addr/cmd error";
1555 optype = "scrubbing error";
1558 optype = "reserved";
1564 err = "read ECC error";
1567 err = "RAS ECC error";
1570 err = "write parity error";
1573 err = "redundacy loss";
1579 err = "memory range error";
1582 err = "RTID out of range";
1585 err = "address parity error";
1588 err = "byte enable parity error";
1594 /* FIXME: should convert addr into bank and rank information */
1595 msg = kasprintf(GFP_ATOMIC,
1596 "%s (addr = 0x%08llx, cpu=%d, Dimm=%d, Channel=%d, "
1597 "syndrome=0x%08x, count=%d, Err=%08llx:%08llx (%s: %s))\n",
1598 type, (long long) m->addr, m->cpu, dimm, channel,
1599 syndrome, core_err_cnt, (long long)m->status,
1600 (long long)m->misc, optype, err);
1604 csrow = pvt->csrow_map[channel][dimm];
1606 /* Call the helper to output message */
1607 if (m->mcgstatus & 1)
1608 edac_mc_handle_fbd_ue(mci, csrow, 0,
1609 0 /* FIXME: should be channel here */, msg);
1610 else if (!pvt->is_registered)
1611 edac_mc_handle_fbd_ce(mci, csrow,
1612 0 /* FIXME: should be channel here */, msg);
1618 * i7core_check_error Retrieve and process errors reported by the
1619 * hardware. Called by the Core module.
1621 static void i7core_check_error(struct mem_ctl_info *mci)
1623 struct i7core_pvt *pvt = mci->pvt_info;
1629 * MCE first step: Copy all mce errors into a temporary buffer
1630 * We use a double buffering here, to reduce the risk of
1634 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
1639 m = pvt->mce_outentry;
1640 if (pvt->mce_in + count > MCE_LOG_LEN) {
1641 unsigned l = MCE_LOG_LEN - pvt->mce_in;
1643 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
1649 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
1651 pvt->mce_in += count;
1654 if (pvt->mce_overrun) {
1655 i7core_printk(KERN_ERR, "Lost %d memory errors\n",
1658 pvt->mce_overrun = 0;
1662 * MCE second step: parse errors and display
1664 for (i = 0; i < count; i++)
1665 i7core_mce_output_error(mci, &pvt->mce_outentry[i]);
1668 * Now, let's increment CE error counts
1670 if (!pvt->is_registered)
1671 i7core_udimm_check_mc_ecc_err(mci);
1673 i7core_rdimm_check_mc_ecc_err(mci);
1677 * i7core_mce_check_error Replicates mcelog routine to get errors
1678 * This routine simply queues mcelog errors, and
1679 * return. The error itself should be handled later
1680 * by i7core_check_error.
1681 * WARNING: As this routine should be called at NMI time, extra care should
1682 * be taken to avoid deadlocks, and to be as fast as possible.
1684 static int i7core_mce_check_error(void *priv, struct mce *mce)
1686 struct mem_ctl_info *mci = priv;
1687 struct i7core_pvt *pvt = mci->pvt_info;
1690 * Just let mcelog handle it if the error is
1691 * outside the memory controller
1693 if (((mce->status & 0xffff) >> 7) != 1)
1696 /* Bank 8 registers are the only ones that we know how to handle */
1700 /* Only handle if it is the right mc controller */
1701 if (cpu_data(mce->cpu).phys_proc_id != pvt->i7core_dev->socket)
1705 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
1711 /* Copy memory error at the ringbuffer */
1712 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
1714 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
1716 /* Handle fatal errors immediately */
1717 if (mce->mcgstatus & 1)
1718 i7core_check_error(mci);
1720 /* Advice mcelog that the error were handled */
1724 static int i7core_register_mci(struct i7core_dev *i7core_dev,
1725 int num_channels, int num_csrows)
1727 struct mem_ctl_info *mci;
1728 struct i7core_pvt *pvt;
1732 /* allocate a new MC control structure */
1733 mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels,
1734 i7core_dev->socket);
1738 debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
1740 /* record ptr to the generic device */
1741 mci->dev = &i7core_dev->pdev[0]->dev;
1743 pvt = mci->pvt_info;
1744 memset(pvt, 0, sizeof(*pvt));
1747 * FIXME: how to handle RDDR3 at MCI level? It is possible to have
1748 * Mixed RDDR3/UDDR3 with Nehalem, provided that they are on different
1751 mci->mtype_cap = MEM_FLAG_DDR3;
1752 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1753 mci->edac_cap = EDAC_FLAG_NONE;
1754 mci->mod_name = "i7core_edac.c";
1755 mci->mod_ver = I7CORE_REVISION;
1756 mci->ctl_name = kasprintf(GFP_KERNEL, "i7 core #%d",
1757 i7core_dev->socket);
1758 mci->dev_name = pci_name(i7core_dev->pdev[0]);
1759 mci->ctl_page_to_phys = NULL;
1760 mci->mc_driver_sysfs_attributes = i7core_sysfs_attrs;
1761 /* Set the function pointer to an actual operation function */
1762 mci->edac_check = i7core_check_error;
1764 /* Store pci devices at mci for faster access */
1765 rc = mci_bind_devs(mci, i7core_dev);
1766 if (unlikely(rc < 0))
1769 /* Get dimm basic config */
1770 get_dimm_config(mci, &csrow);
1772 /* add this new MC control structure to EDAC's list of MCs */
1773 if (unlikely(edac_mc_add_mc(mci))) {
1774 debugf0("MC: " __FILE__
1775 ": %s(): failed edac_mc_add_mc()\n", __func__);
1776 /* FIXME: perhaps some code should go here that disables error
1777 * reporting if we just enabled it
1784 /* allocating generic PCI control info */
1785 i7core_pci = edac_pci_create_generic_ctl(&i7core_dev->pdev[0]->dev,
1787 if (unlikely(!i7core_pci)) {
1789 "%s(): Unable to create PCI control\n",
1792 "%s(): PCI error report via EDAC not setup\n",
1796 /* Default error mask is any memory */
1797 pvt->inject.channel = 0;
1798 pvt->inject.dimm = -1;
1799 pvt->inject.rank = -1;
1800 pvt->inject.bank = -1;
1801 pvt->inject.page = -1;
1802 pvt->inject.col = -1;
1804 /* Registers on edac_mce in order to receive memory errors */
1805 pvt->edac_mce.priv = mci;
1806 pvt->edac_mce.check_error = i7core_mce_check_error;
1808 rc = edac_mce_register(&pvt->edac_mce);
1809 if (unlikely(rc < 0)) {
1810 debugf0("MC: " __FILE__
1811 ": %s(): failed edac_mce_register()\n", __func__);
1820 * i7core_probe Probe for ONE instance of device to see if it is
1823 * 0 for FOUND a device
1824 * < 0 for error code
1826 static int __devinit i7core_probe(struct pci_dev *pdev,
1827 const struct pci_device_id *id)
1829 int dev_idx = id->driver_data;
1831 struct i7core_dev *i7core_dev;
1834 * All memory controllers are allocated at the first pass.
1836 if (unlikely(dev_idx >= 1))
1839 /* get the pci devices we want to reserve for our use */
1840 mutex_lock(&i7core_edac_lock);
1841 rc = i7core_get_devices();
1842 if (unlikely(rc < 0))
1845 list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
1849 /* Check the number of active and not disabled channels */
1850 rc = i7core_get_active_channels(i7core_dev->socket,
1851 &channels, &csrows);
1852 if (unlikely(rc < 0))
1855 rc = i7core_register_mci(i7core_dev, channels, csrows);
1856 if (unlikely(rc < 0))
1860 i7core_printk(KERN_INFO, "Driver loaded.\n");
1862 mutex_unlock(&i7core_edac_lock);
1866 i7core_put_all_devices();
1868 mutex_unlock(&i7core_edac_lock);
1873 * i7core_remove destructor for one instance of device
1876 static void __devexit i7core_remove(struct pci_dev *pdev)
1878 struct mem_ctl_info *mci;
1879 struct i7core_dev *i7core_dev, *tmp;
1881 debugf0(__FILE__ ": %s()\n", __func__);
1884 edac_pci_release_generic_ctl(i7core_pci);
1887 * we have a trouble here: pdev value for removal will be wrong, since
1888 * it will point to the X58 register used to detect that the machine
1889 * is a Nehalem or upper design. However, due to the way several PCI
1890 * devices are grouped together to provide MC functionality, we need
1891 * to use a different method for releasing the devices
1894 mutex_lock(&i7core_edac_lock);
1895 list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) {
1896 mci = edac_mc_del_mc(&i7core_dev->pdev[0]->dev);
1898 struct i7core_pvt *pvt = mci->pvt_info;
1900 i7core_dev = pvt->i7core_dev;
1901 edac_mce_unregister(&pvt->edac_mce);
1902 kfree(mci->ctl_name);
1904 i7core_put_devices(i7core_dev);
1906 i7core_printk(KERN_ERR,
1907 "Couldn't find mci for socket %d\n",
1908 i7core_dev->socket);
1911 mutex_unlock(&i7core_edac_lock);
1914 MODULE_DEVICE_TABLE(pci, i7core_pci_tbl);
1917 * i7core_driver pci_driver structure for this module
1920 static struct pci_driver i7core_driver = {
1921 .name = "i7core_edac",
1922 .probe = i7core_probe,
1923 .remove = __devexit_p(i7core_remove),
1924 .id_table = i7core_pci_tbl,
1928 * i7core_init Module entry function
1929 * Try to initialize this module for its devices
1931 static int __init i7core_init(void)
1935 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1937 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1940 i7core_xeon_pci_fixup();
1942 pci_rc = pci_register_driver(&i7core_driver);
1947 i7core_printk(KERN_ERR, "Failed to register device with error %d.\n",
1954 * i7core_exit() Module exit function
1955 * Unregister the driver
1957 static void __exit i7core_exit(void)
1959 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1960 pci_unregister_driver(&i7core_driver);
1963 module_init(i7core_init);
1964 module_exit(i7core_exit);
1966 MODULE_LICENSE("GPL");
1967 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
1968 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
1969 MODULE_DESCRIPTION("MC Driver for Intel i7 Core memory controllers - "
1972 module_param(edac_op_state, int, 0444);
1973 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");