3 # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
4 # Licensed and distributed under the GPL
8 bool "EDAC (Error Detection And Correction) reporting"
10 depends on X86 || PPC || TILE
12 EDAC is designed to report errors in the core system.
13 These are low-level errors that are reported in the CPU or
14 supporting chipset or other subsystems:
15 memory errors, cache errors, PCI errors, thermal throttling, etc..
16 If unsure, select 'Y'.
18 If this code is reporting problems on your system, please
19 see the EDAC project web pages for more information at:
21 <http://bluesmoke.sourceforge.net/>
25 <http://buttersideup.com/edacwiki>
27 There is also a mailing list for the EDAC project, which can
28 be found via the sourceforge page.
32 comment "Reporting subsystems"
37 This turns on debugging information for the entire EDAC
38 sub-system. You can insert module with "debug_level=x", current
39 there're four debug levels (x=0,1,2,3 from low to high).
40 Usually you should select 'N'.
42 config EDAC_DECODE_MCE
43 tristate "Decode MCEs in human-readable form (only on AMD for now)"
44 depends on CPU_SUP_AMD && X86_MCE
47 Enable this option if you want to decode Machine Check Exceptions
48 occurring on your machine in human-readable form.
50 You should definitely say Y here in case you want to decode MCEs
51 which occur really early upon boot, before the module infrastructure
55 tristate "Simple MCE injection interface over /sysfs"
56 depends on EDAC_DECODE_MCE
59 This is a simple interface to inject MCEs over /sysfs and test
60 the MCE decoding code in EDAC.
62 This is currently AMD-only.
65 tristate "Main Memory EDAC (Error Detection And Correction) reporting"
67 Some systems are able to detect and correct errors in main
68 memory. EDAC can report statistics on memory error
69 detection and correction (EDAC - or commonly referred to ECC
70 errors). EDAC will also try to decode where these errors
71 occurred so that a particular failing memory module can be
72 replaced. If unsure, select 'Y'.
75 tristate "AMD64 (Opteron, Athlon64) K8, F10h"
76 depends on EDAC_MM_EDAC && AMD_NB && X86_64 && EDAC_DECODE_MCE
78 Support for error detection and correction of DRAM ECC errors on
79 the AMD64 families of memory controllers (K8 and F10h)
81 config EDAC_AMD64_ERROR_INJECTION
82 bool "Sysfs HW Error injection facilities"
85 Recent Opterons (Family 10h and later) provide for Memory Error
86 Injection into the ECC detection circuits. The amd64_edac module
87 allows the operator/user to inject Uncorrectable and Correctable
90 When enabled, in each of the respective memory controller directories
91 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
93 - inject_section (0..3, 16-byte section of 64-byte cacheline),
94 - inject_word (0..8, 16-bit word of 16-byte section),
95 - inject_ecc_vector (hex ecc vector: select bits of inject word)
97 In addition, there are two control files, inject_read and inject_write,
98 which trigger the DRAM ECC Read and Write respectively.
101 tristate "AMD 76x (760, 762, 768)"
102 depends on EDAC_MM_EDAC && PCI && X86_32
104 Support for error detection and correction on the AMD 76x
105 series of chipsets used with the Athlon processor.
108 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
109 depends on EDAC_MM_EDAC && PCI && X86_32
111 Support for error detection and correction on the Intel
112 E7205, E7500, E7501 and E7505 server chipsets.
115 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
116 depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG
118 Support for error detection and correction on the Intel
119 E7520, E7525, E7320 server chipsets.
121 config EDAC_I82443BXGX
122 tristate "Intel 82443BX/GX (440BX/GX)"
123 depends on EDAC_MM_EDAC && PCI && X86_32
126 Support for error detection and correction on the Intel
127 82443BX/GX memory controllers (440BX/GX chipsets).
130 tristate "Intel 82875p (D82875P, E7210)"
131 depends on EDAC_MM_EDAC && PCI && X86_32
133 Support for error detection and correction on the Intel
134 DP82785P and E7210 server chipsets.
137 tristate "Intel 82975x (D82975x)"
138 depends on EDAC_MM_EDAC && PCI && X86
140 Support for error detection and correction on the Intel
141 DP82975x server chipsets.
144 tristate "Intel 3000/3010"
145 depends on EDAC_MM_EDAC && PCI && X86
147 Support for error detection and correction on the Intel
148 3000 and 3010 server chipsets.
151 tristate "Intel 3200"
152 depends on EDAC_MM_EDAC && PCI && X86 && EXPERIMENTAL
154 Support for error detection and correction on the Intel
155 3200 and 3210 server chipsets.
159 depends on EDAC_MM_EDAC && PCI && X86
161 Support for error detection and correction on the Intel
165 tristate "Intel 5400 (Seaburg) chipsets"
166 depends on EDAC_MM_EDAC && PCI && X86
168 Support for error detection and correction the Intel
169 i5400 MCH chipset (Seaburg).
172 tristate "Intel i7 Core (Nehalem) processors"
173 depends on EDAC_MM_EDAC && PCI && X86
176 Support for error detection and correction the Intel
177 i7 Core (Nehalem) Integrated Memory Controller that exists on
178 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
179 and Xeon 55xx processors.
182 tristate "Intel 82860"
183 depends on EDAC_MM_EDAC && PCI && X86_32
185 Support for error detection and correction on the Intel
189 tristate "Radisys 82600 embedded chipset"
190 depends on EDAC_MM_EDAC && PCI && X86_32
192 Support for error detection and correction on the Radisys
193 82600 embedded chipset.
196 tristate "Intel Greencreek/Blackford chipset"
197 depends on EDAC_MM_EDAC && X86 && PCI
199 Support for error detection and correction the Intel
200 Greekcreek/Blackford chipsets.
203 tristate "Intel San Clemente MCH"
204 depends on EDAC_MM_EDAC && X86 && PCI
206 Support for error detection and correction the Intel
210 tristate "Intel Clarksboro MCH"
211 depends on EDAC_MM_EDAC && X86 && PCI
213 Support for error detection and correction the Intel
214 Clarksboro MCH (Intel 7300 chipset).
217 tristate "Freescale MPC83xx / MPC85xx"
218 depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
220 Support for error detection and correction on the Freescale
221 MPC8349, MPC8560, MPC8540, MPC8548
224 tristate "Marvell MV64x60"
225 depends on EDAC_MM_EDAC && MV64X60
227 Support for error detection and correction on the Marvell
228 MV64360 and MV64460 chipsets.
231 tristate "PA Semi PWRficient"
232 depends on EDAC_MM_EDAC && PCI
233 depends on PPC_PASEMI
235 Support for error detection and correction on PA Semi
239 tristate "Cell Broadband Engine memory controller"
240 depends on EDAC_MM_EDAC && PPC_CELL_COMMON
242 Support for error detection and correction on the
243 Cell Broadband Engine internal memory controller
244 on platform without a hypervisor
247 tristate "PPC4xx IBM DDR2 Memory Controller"
248 depends on EDAC_MM_EDAC && 4xx
250 This enables support for EDAC on the ECC memory used
251 with the IBM DDR2 memory controller found in various
252 PowerPC 4xx embedded processors such as the 405EX[r],
253 440SP, 440SPe, 460EX, 460GT and 460SX.
256 tristate "AMD8131 HyperTransport PCI-X Tunnel"
257 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
259 Support for error detection and correction on the
260 AMD8131 HyperTransport PCI-X Tunnel chip.
261 Note, add more Kconfig dependency if it's adopted
262 on some machine other than Maple.
265 tristate "AMD8111 HyperTransport I/O Hub"
266 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
268 Support for error detection and correction on the
269 AMD8111 HyperTransport I/O Hub chip.
270 Note, add more Kconfig dependency if it's adopted
271 on some machine other than Maple.
274 tristate "IBM CPC925 Memory Controller (PPC970FX)"
275 depends on EDAC_MM_EDAC && PPC64
277 Support for error detection and correction on the
278 IBM CPC925 Bridge and Memory Controller, which is
279 a companion chip to the PowerPC 970 family of
283 tristate "Tilera Memory Controller"
284 depends on EDAC_MM_EDAC && TILE
287 Support for error detection and correction on the
288 Tilera memory controller.