2 * Driver for the TXx9 SoC DMA Controller
4 * Copyright (C) 2009 Atsushi Nemoto
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/dma-mapping.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/slab.h>
17 #include <linux/scatterlist.h>
20 static struct txx9dmac_chan *to_txx9dmac_chan(struct dma_chan *chan)
22 return container_of(chan, struct txx9dmac_chan, chan);
25 static struct txx9dmac_cregs __iomem *__dma_regs(const struct txx9dmac_chan *dc)
30 static struct txx9dmac_cregs32 __iomem *__dma_regs32(
31 const struct txx9dmac_chan *dc)
36 #define channel64_readq(dc, name) \
37 __raw_readq(&(__dma_regs(dc)->name))
38 #define channel64_writeq(dc, name, val) \
39 __raw_writeq((val), &(__dma_regs(dc)->name))
40 #define channel64_readl(dc, name) \
41 __raw_readl(&(__dma_regs(dc)->name))
42 #define channel64_writel(dc, name, val) \
43 __raw_writel((val), &(__dma_regs(dc)->name))
45 #define channel32_readl(dc, name) \
46 __raw_readl(&(__dma_regs32(dc)->name))
47 #define channel32_writel(dc, name, val) \
48 __raw_writel((val), &(__dma_regs32(dc)->name))
50 #define channel_readq(dc, name) channel64_readq(dc, name)
51 #define channel_writeq(dc, name, val) channel64_writeq(dc, name, val)
52 #define channel_readl(dc, name) \
54 channel64_readl(dc, name) : channel32_readl(dc, name))
55 #define channel_writel(dc, name, val) \
57 channel64_writel(dc, name, val) : channel32_writel(dc, name, val))
59 static dma_addr_t channel64_read_CHAR(const struct txx9dmac_chan *dc)
61 if (sizeof(__dma_regs(dc)->CHAR) == sizeof(u64))
62 return channel64_readq(dc, CHAR);
64 return channel64_readl(dc, CHAR);
67 static void channel64_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)
69 if (sizeof(__dma_regs(dc)->CHAR) == sizeof(u64))
70 channel64_writeq(dc, CHAR, val);
72 channel64_writel(dc, CHAR, val);
75 static void channel64_clear_CHAR(const struct txx9dmac_chan *dc)
77 #if defined(CONFIG_32BIT) && !defined(CONFIG_64BIT_PHYS_ADDR)
78 channel64_writel(dc, CHAR, 0);
79 channel64_writel(dc, __pad_CHAR, 0);
81 channel64_writeq(dc, CHAR, 0);
85 static dma_addr_t channel_read_CHAR(const struct txx9dmac_chan *dc)
88 return channel64_read_CHAR(dc);
90 return channel32_readl(dc, CHAR);
93 static void channel_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)
96 channel64_write_CHAR(dc, val);
98 channel32_writel(dc, CHAR, val);
101 static struct txx9dmac_regs __iomem *__txx9dmac_regs(
102 const struct txx9dmac_dev *ddev)
107 static struct txx9dmac_regs32 __iomem *__txx9dmac_regs32(
108 const struct txx9dmac_dev *ddev)
113 #define dma64_readl(ddev, name) \
114 __raw_readl(&(__txx9dmac_regs(ddev)->name))
115 #define dma64_writel(ddev, name, val) \
116 __raw_writel((val), &(__txx9dmac_regs(ddev)->name))
118 #define dma32_readl(ddev, name) \
119 __raw_readl(&(__txx9dmac_regs32(ddev)->name))
120 #define dma32_writel(ddev, name, val) \
121 __raw_writel((val), &(__txx9dmac_regs32(ddev)->name))
123 #define dma_readl(ddev, name) \
124 (__is_dmac64(ddev) ? \
125 dma64_readl(ddev, name) : dma32_readl(ddev, name))
126 #define dma_writel(ddev, name, val) \
127 (__is_dmac64(ddev) ? \
128 dma64_writel(ddev, name, val) : dma32_writel(ddev, name, val))
130 static struct device *chan2dev(struct dma_chan *chan)
132 return &chan->dev->device;
134 static struct device *chan2parent(struct dma_chan *chan)
136 return chan->dev->device.parent;
139 static struct txx9dmac_desc *
140 txd_to_txx9dmac_desc(struct dma_async_tx_descriptor *txd)
142 return container_of(txd, struct txx9dmac_desc, txd);
145 static dma_addr_t desc_read_CHAR(const struct txx9dmac_chan *dc,
146 const struct txx9dmac_desc *desc)
148 return is_dmac64(dc) ? desc->hwdesc.CHAR : desc->hwdesc32.CHAR;
151 static void desc_write_CHAR(const struct txx9dmac_chan *dc,
152 struct txx9dmac_desc *desc, dma_addr_t val)
155 desc->hwdesc.CHAR = val;
157 desc->hwdesc32.CHAR = val;
160 #define TXX9_DMA_MAX_COUNT 0x04000000
162 #define TXX9_DMA_INITIAL_DESC_COUNT 64
164 static struct txx9dmac_desc *txx9dmac_first_active(struct txx9dmac_chan *dc)
166 return list_entry(dc->active_list.next,
167 struct txx9dmac_desc, desc_node);
170 static struct txx9dmac_desc *txx9dmac_last_active(struct txx9dmac_chan *dc)
172 return list_entry(dc->active_list.prev,
173 struct txx9dmac_desc, desc_node);
176 static struct txx9dmac_desc *txx9dmac_first_queued(struct txx9dmac_chan *dc)
178 return list_entry(dc->queue.next, struct txx9dmac_desc, desc_node);
181 static struct txx9dmac_desc *txx9dmac_last_child(struct txx9dmac_desc *desc)
183 if (!list_empty(&desc->tx_list))
184 desc = list_entry(desc->tx_list.prev, typeof(*desc), desc_node);
188 static dma_cookie_t txx9dmac_tx_submit(struct dma_async_tx_descriptor *tx);
190 static struct txx9dmac_desc *txx9dmac_desc_alloc(struct txx9dmac_chan *dc,
193 struct txx9dmac_dev *ddev = dc->ddev;
194 struct txx9dmac_desc *desc;
196 desc = kzalloc(sizeof(*desc), flags);
199 INIT_LIST_HEAD(&desc->tx_list);
200 dma_async_tx_descriptor_init(&desc->txd, &dc->chan);
201 desc->txd.tx_submit = txx9dmac_tx_submit;
202 /* txd.flags will be overwritten in prep funcs */
203 desc->txd.flags = DMA_CTRL_ACK;
204 desc->txd.phys = dma_map_single(chan2parent(&dc->chan), &desc->hwdesc,
205 ddev->descsize, DMA_TO_DEVICE);
209 static struct txx9dmac_desc *txx9dmac_desc_get(struct txx9dmac_chan *dc)
211 struct txx9dmac_desc *desc, *_desc;
212 struct txx9dmac_desc *ret = NULL;
215 spin_lock_bh(&dc->lock);
216 list_for_each_entry_safe(desc, _desc, &dc->free_list, desc_node) {
217 if (async_tx_test_ack(&desc->txd)) {
218 list_del(&desc->desc_node);
222 dev_dbg(chan2dev(&dc->chan), "desc %p not ACKed\n", desc);
225 spin_unlock_bh(&dc->lock);
227 dev_vdbg(chan2dev(&dc->chan), "scanned %u descriptors on freelist\n",
230 ret = txx9dmac_desc_alloc(dc, GFP_ATOMIC);
232 spin_lock_bh(&dc->lock);
233 dc->descs_allocated++;
234 spin_unlock_bh(&dc->lock);
236 dev_err(chan2dev(&dc->chan),
237 "not enough descriptors available\n");
242 static void txx9dmac_sync_desc_for_cpu(struct txx9dmac_chan *dc,
243 struct txx9dmac_desc *desc)
245 struct txx9dmac_dev *ddev = dc->ddev;
246 struct txx9dmac_desc *child;
248 list_for_each_entry(child, &desc->tx_list, desc_node)
249 dma_sync_single_for_cpu(chan2parent(&dc->chan),
250 child->txd.phys, ddev->descsize,
252 dma_sync_single_for_cpu(chan2parent(&dc->chan),
253 desc->txd.phys, ddev->descsize,
258 * Move a descriptor, including any children, to the free list.
259 * `desc' must not be on any lists.
261 static void txx9dmac_desc_put(struct txx9dmac_chan *dc,
262 struct txx9dmac_desc *desc)
265 struct txx9dmac_desc *child;
267 txx9dmac_sync_desc_for_cpu(dc, desc);
269 spin_lock_bh(&dc->lock);
270 list_for_each_entry(child, &desc->tx_list, desc_node)
271 dev_vdbg(chan2dev(&dc->chan),
272 "moving child desc %p to freelist\n",
274 list_splice_init(&desc->tx_list, &dc->free_list);
275 dev_vdbg(chan2dev(&dc->chan), "moving desc %p to freelist\n",
277 list_add(&desc->desc_node, &dc->free_list);
278 spin_unlock_bh(&dc->lock);
282 /* Called with dc->lock held and bh disabled */
284 txx9dmac_assign_cookie(struct txx9dmac_chan *dc, struct txx9dmac_desc *desc)
286 dma_cookie_t cookie = dc->chan.cookie;
291 dc->chan.cookie = cookie;
292 desc->txd.cookie = cookie;
297 /*----------------------------------------------------------------------*/
299 static void txx9dmac_dump_regs(struct txx9dmac_chan *dc)
302 dev_err(chan2dev(&dc->chan),
303 " CHAR: %#llx SAR: %#llx DAR: %#llx CNTR: %#x"
304 " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n",
305 (u64)channel64_read_CHAR(dc),
306 channel64_readq(dc, SAR),
307 channel64_readq(dc, DAR),
308 channel64_readl(dc, CNTR),
309 channel64_readl(dc, SAIR),
310 channel64_readl(dc, DAIR),
311 channel64_readl(dc, CCR),
312 channel64_readl(dc, CSR));
314 dev_err(chan2dev(&dc->chan),
315 " CHAR: %#x SAR: %#x DAR: %#x CNTR: %#x"
316 " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n",
317 channel32_readl(dc, CHAR),
318 channel32_readl(dc, SAR),
319 channel32_readl(dc, DAR),
320 channel32_readl(dc, CNTR),
321 channel32_readl(dc, SAIR),
322 channel32_readl(dc, DAIR),
323 channel32_readl(dc, CCR),
324 channel32_readl(dc, CSR));
327 static void txx9dmac_reset_chan(struct txx9dmac_chan *dc)
329 channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST);
331 channel64_clear_CHAR(dc);
332 channel_writeq(dc, SAR, 0);
333 channel_writeq(dc, DAR, 0);
335 channel_writel(dc, CHAR, 0);
336 channel_writel(dc, SAR, 0);
337 channel_writel(dc, DAR, 0);
339 channel_writel(dc, CNTR, 0);
340 channel_writel(dc, SAIR, 0);
341 channel_writel(dc, DAIR, 0);
342 channel_writel(dc, CCR, 0);
346 /* Called with dc->lock held and bh disabled */
347 static void txx9dmac_dostart(struct txx9dmac_chan *dc,
348 struct txx9dmac_desc *first)
350 struct txx9dmac_slave *ds = dc->chan.private;
353 dev_vdbg(chan2dev(&dc->chan), "dostart %u %p\n",
354 first->txd.cookie, first);
355 /* ASSERT: channel is idle */
356 if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {
357 dev_err(chan2dev(&dc->chan),
358 "BUG: Attempted to start non-idle channel\n");
359 txx9dmac_dump_regs(dc);
360 /* The tasklet will hopefully advance the queue... */
365 channel64_writel(dc, CNTR, 0);
366 channel64_writel(dc, CSR, 0xffffffff);
379 channel64_writel(dc, SAIR, sai);
380 channel64_writel(dc, DAIR, dai);
381 /* All 64-bit DMAC supports SMPCHN */
382 channel64_writel(dc, CCR, dc->ccr);
383 /* Writing a non zero value to CHAR will assert XFACT */
384 channel64_write_CHAR(dc, first->txd.phys);
386 channel32_writel(dc, CNTR, 0);
387 channel32_writel(dc, CSR, 0xffffffff);
400 channel32_writel(dc, SAIR, sai);
401 channel32_writel(dc, DAIR, dai);
402 if (txx9_dma_have_SMPCHN()) {
403 channel32_writel(dc, CCR, dc->ccr);
404 /* Writing a non zero value to CHAR will assert XFACT */
405 channel32_writel(dc, CHAR, first->txd.phys);
407 channel32_writel(dc, CHAR, first->txd.phys);
408 channel32_writel(dc, CCR, dc->ccr);
413 /*----------------------------------------------------------------------*/
416 txx9dmac_descriptor_complete(struct txx9dmac_chan *dc,
417 struct txx9dmac_desc *desc)
419 dma_async_tx_callback callback;
421 struct dma_async_tx_descriptor *txd = &desc->txd;
422 struct txx9dmac_slave *ds = dc->chan.private;
424 dev_vdbg(chan2dev(&dc->chan), "descriptor %u %p complete\n",
427 dc->completed = txd->cookie;
428 callback = txd->callback;
429 param = txd->callback_param;
431 txx9dmac_sync_desc_for_cpu(dc, desc);
432 list_splice_init(&desc->tx_list, &dc->free_list);
433 list_move(&desc->desc_node, &dc->free_list);
437 if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
438 dmaaddr = is_dmac64(dc) ?
439 desc->hwdesc.DAR : desc->hwdesc32.DAR;
440 if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
441 dma_unmap_single(chan2parent(&dc->chan),
442 dmaaddr, desc->len, DMA_FROM_DEVICE);
444 dma_unmap_page(chan2parent(&dc->chan),
445 dmaaddr, desc->len, DMA_FROM_DEVICE);
447 if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
448 dmaaddr = is_dmac64(dc) ?
449 desc->hwdesc.SAR : desc->hwdesc32.SAR;
450 if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
451 dma_unmap_single(chan2parent(&dc->chan),
452 dmaaddr, desc->len, DMA_TO_DEVICE);
454 dma_unmap_page(chan2parent(&dc->chan),
455 dmaaddr, desc->len, DMA_TO_DEVICE);
460 * The API requires that no submissions are done from a
461 * callback, so we don't need to drop the lock here
465 dma_run_dependencies(txd);
468 static void txx9dmac_dequeue(struct txx9dmac_chan *dc, struct list_head *list)
470 struct txx9dmac_dev *ddev = dc->ddev;
471 struct txx9dmac_desc *desc;
472 struct txx9dmac_desc *prev = NULL;
474 BUG_ON(!list_empty(list));
476 desc = txx9dmac_first_queued(dc);
478 desc_write_CHAR(dc, prev, desc->txd.phys);
479 dma_sync_single_for_device(chan2parent(&dc->chan),
480 prev->txd.phys, ddev->descsize,
483 prev = txx9dmac_last_child(desc);
484 list_move_tail(&desc->desc_node, list);
485 /* Make chain-completion interrupt happen */
486 if ((desc->txd.flags & DMA_PREP_INTERRUPT) &&
487 !txx9dmac_chan_INTENT(dc))
489 } while (!list_empty(&dc->queue));
492 static void txx9dmac_complete_all(struct txx9dmac_chan *dc)
494 struct txx9dmac_desc *desc, *_desc;
498 * Submit queued descriptors ASAP, i.e. before we go through
499 * the completed ones.
501 list_splice_init(&dc->active_list, &list);
502 if (!list_empty(&dc->queue)) {
503 txx9dmac_dequeue(dc, &dc->active_list);
504 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
507 list_for_each_entry_safe(desc, _desc, &list, desc_node)
508 txx9dmac_descriptor_complete(dc, desc);
511 static void txx9dmac_dump_desc(struct txx9dmac_chan *dc,
512 struct txx9dmac_hwdesc *desc)
515 #ifdef TXX9_DMA_USE_SIMPLE_CHAIN
516 dev_crit(chan2dev(&dc->chan),
517 " desc: ch%#llx s%#llx d%#llx c%#x\n",
518 (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR);
520 dev_crit(chan2dev(&dc->chan),
521 " desc: ch%#llx s%#llx d%#llx c%#x"
522 " si%#x di%#x cc%#x cs%#x\n",
523 (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR,
524 desc->SAIR, desc->DAIR, desc->CCR, desc->CSR);
527 struct txx9dmac_hwdesc32 *d = (struct txx9dmac_hwdesc32 *)desc;
528 #ifdef TXX9_DMA_USE_SIMPLE_CHAIN
529 dev_crit(chan2dev(&dc->chan),
530 " desc: ch%#x s%#x d%#x c%#x\n",
531 d->CHAR, d->SAR, d->DAR, d->CNTR);
533 dev_crit(chan2dev(&dc->chan),
534 " desc: ch%#x s%#x d%#x c%#x"
535 " si%#x di%#x cc%#x cs%#x\n",
536 d->CHAR, d->SAR, d->DAR, d->CNTR,
537 d->SAIR, d->DAIR, d->CCR, d->CSR);
542 static void txx9dmac_handle_error(struct txx9dmac_chan *dc, u32 csr)
544 struct txx9dmac_desc *bad_desc;
545 struct txx9dmac_desc *child;
549 * The descriptor currently at the head of the active list is
550 * borked. Since we don't have any way to report errors, we'll
551 * just have to scream loudly and try to carry on.
553 dev_crit(chan2dev(&dc->chan), "Abnormal Chain Completion\n");
554 txx9dmac_dump_regs(dc);
556 bad_desc = txx9dmac_first_active(dc);
557 list_del_init(&bad_desc->desc_node);
559 /* Clear all error flags and try to restart the controller */
560 errors = csr & (TXX9_DMA_CSR_ABCHC |
561 TXX9_DMA_CSR_CFERR | TXX9_DMA_CSR_CHERR |
562 TXX9_DMA_CSR_DESERR | TXX9_DMA_CSR_SORERR);
563 channel_writel(dc, CSR, errors);
565 if (list_empty(&dc->active_list) && !list_empty(&dc->queue))
566 txx9dmac_dequeue(dc, &dc->active_list);
567 if (!list_empty(&dc->active_list))
568 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
570 dev_crit(chan2dev(&dc->chan),
571 "Bad descriptor submitted for DMA! (cookie: %d)\n",
572 bad_desc->txd.cookie);
573 txx9dmac_dump_desc(dc, &bad_desc->hwdesc);
574 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
575 txx9dmac_dump_desc(dc, &child->hwdesc);
576 /* Pretend the descriptor completed successfully */
577 txx9dmac_descriptor_complete(dc, bad_desc);
580 static void txx9dmac_scan_descriptors(struct txx9dmac_chan *dc)
583 struct txx9dmac_desc *desc, *_desc;
584 struct txx9dmac_desc *child;
588 chain = channel64_read_CHAR(dc);
589 csr = channel64_readl(dc, CSR);
590 channel64_writel(dc, CSR, csr);
592 chain = channel32_readl(dc, CHAR);
593 csr = channel32_readl(dc, CSR);
594 channel32_writel(dc, CSR, csr);
596 /* For dynamic chain, we should look at XFACT instead of NCHNC */
597 if (!(csr & (TXX9_DMA_CSR_XFACT | TXX9_DMA_CSR_ABCHC))) {
598 /* Everything we've submitted is done */
599 txx9dmac_complete_all(dc);
602 if (!(csr & TXX9_DMA_CSR_CHNEN))
603 chain = 0; /* last descriptor of this chain */
605 dev_vdbg(chan2dev(&dc->chan), "scan_descriptors: char=%#llx\n",
608 list_for_each_entry_safe(desc, _desc, &dc->active_list, desc_node) {
609 if (desc_read_CHAR(dc, desc) == chain) {
610 /* This one is currently in progress */
611 if (csr & TXX9_DMA_CSR_ABCHC)
616 list_for_each_entry(child, &desc->tx_list, desc_node)
617 if (desc_read_CHAR(dc, child) == chain) {
618 /* Currently in progress */
619 if (csr & TXX9_DMA_CSR_ABCHC)
625 * No descriptors so far seem to be in progress, i.e.
626 * this one must be done.
628 txx9dmac_descriptor_complete(dc, desc);
631 if (csr & TXX9_DMA_CSR_ABCHC) {
632 txx9dmac_handle_error(dc, csr);
636 dev_err(chan2dev(&dc->chan),
637 "BUG: All descriptors done, but channel not idle!\n");
639 /* Try to continue after resetting the channel... */
640 txx9dmac_reset_chan(dc);
642 if (!list_empty(&dc->queue)) {
643 txx9dmac_dequeue(dc, &dc->active_list);
644 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
648 static void txx9dmac_chan_tasklet(unsigned long data)
652 struct txx9dmac_chan *dc;
654 dc = (struct txx9dmac_chan *)data;
655 csr = channel_readl(dc, CSR);
656 dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n", csr);
658 spin_lock(&dc->lock);
659 if (csr & (TXX9_DMA_CSR_ABCHC | TXX9_DMA_CSR_NCHNC |
660 TXX9_DMA_CSR_NTRNFC))
661 txx9dmac_scan_descriptors(dc);
662 spin_unlock(&dc->lock);
668 static irqreturn_t txx9dmac_chan_interrupt(int irq, void *dev_id)
670 struct txx9dmac_chan *dc = dev_id;
672 dev_vdbg(chan2dev(&dc->chan), "interrupt: status=%#x\n",
673 channel_readl(dc, CSR));
675 tasklet_schedule(&dc->tasklet);
677 * Just disable the interrupts. We'll turn them back on in the
680 disable_irq_nosync(irq);
685 static void txx9dmac_tasklet(unsigned long data)
689 struct txx9dmac_chan *dc;
691 struct txx9dmac_dev *ddev = (struct txx9dmac_dev *)data;
695 mcr = dma_readl(ddev, MCR);
696 dev_vdbg(ddev->chan[0]->dma.dev, "tasklet: mcr=%x\n", mcr);
697 for (i = 0; i < TXX9_DMA_MAX_NR_CHANNELS; i++) {
698 if ((mcr >> (24 + i)) & 0x11) {
700 csr = channel_readl(dc, CSR);
701 dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n",
703 spin_lock(&dc->lock);
704 if (csr & (TXX9_DMA_CSR_ABCHC | TXX9_DMA_CSR_NCHNC |
705 TXX9_DMA_CSR_NTRNFC))
706 txx9dmac_scan_descriptors(dc);
707 spin_unlock(&dc->lock);
715 static irqreturn_t txx9dmac_interrupt(int irq, void *dev_id)
717 struct txx9dmac_dev *ddev = dev_id;
719 dev_vdbg(ddev->chan[0]->dma.dev, "interrupt: status=%#x\n",
720 dma_readl(ddev, MCR));
722 tasklet_schedule(&ddev->tasklet);
724 * Just disable the interrupts. We'll turn them back on in the
727 disable_irq_nosync(irq);
732 /*----------------------------------------------------------------------*/
734 static dma_cookie_t txx9dmac_tx_submit(struct dma_async_tx_descriptor *tx)
736 struct txx9dmac_desc *desc = txd_to_txx9dmac_desc(tx);
737 struct txx9dmac_chan *dc = to_txx9dmac_chan(tx->chan);
740 spin_lock_bh(&dc->lock);
741 cookie = txx9dmac_assign_cookie(dc, desc);
743 dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u %p\n",
744 desc->txd.cookie, desc);
746 list_add_tail(&desc->desc_node, &dc->queue);
747 spin_unlock_bh(&dc->lock);
752 static struct dma_async_tx_descriptor *
753 txx9dmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
754 size_t len, unsigned long flags)
756 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
757 struct txx9dmac_dev *ddev = dc->ddev;
758 struct txx9dmac_desc *desc;
759 struct txx9dmac_desc *first;
760 struct txx9dmac_desc *prev;
764 dev_vdbg(chan2dev(chan), "prep_dma_memcpy d%#llx s%#llx l%#zx f%#lx\n",
765 (u64)dest, (u64)src, len, flags);
767 if (unlikely(!len)) {
768 dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
774 for (offset = 0; offset < len; offset += xfer_count) {
775 xfer_count = min_t(size_t, len - offset, TXX9_DMA_MAX_COUNT);
777 * Workaround for ERT-TX49H2-033, ERT-TX49H3-020,
778 * ERT-TX49H4-016 (slightly conservative)
780 if (__is_dmac64(ddev)) {
781 if (xfer_count > 0x100 &&
782 (xfer_count & 0xff) >= 0xfa &&
783 (xfer_count & 0xff) <= 0xff)
786 if (xfer_count > 0x80 &&
787 (xfer_count & 0x7f) >= 0x7e &&
788 (xfer_count & 0x7f) <= 0x7f)
792 desc = txx9dmac_desc_get(dc);
794 txx9dmac_desc_put(dc, first);
798 if (__is_dmac64(ddev)) {
799 desc->hwdesc.SAR = src + offset;
800 desc->hwdesc.DAR = dest + offset;
801 desc->hwdesc.CNTR = xfer_count;
802 txx9dmac_desc_set_nosimple(ddev, desc, 8, 8,
803 dc->ccr | TXX9_DMA_CCR_XFACT);
805 desc->hwdesc32.SAR = src + offset;
806 desc->hwdesc32.DAR = dest + offset;
807 desc->hwdesc32.CNTR = xfer_count;
808 txx9dmac_desc_set_nosimple(ddev, desc, 4, 4,
809 dc->ccr | TXX9_DMA_CCR_XFACT);
813 * The descriptors on tx_list are not reachable from
814 * the dc->queue list or dc->active_list after a
815 * submit. If we put all descriptors on active_list,
816 * calling of callback on the completion will be more
822 desc_write_CHAR(dc, prev, desc->txd.phys);
823 dma_sync_single_for_device(chan2parent(&dc->chan),
824 prev->txd.phys, ddev->descsize,
826 list_add_tail(&desc->desc_node, &first->tx_list);
831 /* Trigger interrupt after last block */
832 if (flags & DMA_PREP_INTERRUPT)
833 txx9dmac_desc_set_INTENT(ddev, prev);
835 desc_write_CHAR(dc, prev, 0);
836 dma_sync_single_for_device(chan2parent(&dc->chan),
837 prev->txd.phys, ddev->descsize,
840 first->txd.flags = flags;
846 static struct dma_async_tx_descriptor *
847 txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
848 unsigned int sg_len, enum dma_data_direction direction,
851 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
852 struct txx9dmac_dev *ddev = dc->ddev;
853 struct txx9dmac_slave *ds = chan->private;
854 struct txx9dmac_desc *prev;
855 struct txx9dmac_desc *first;
857 struct scatterlist *sg;
859 dev_vdbg(chan2dev(chan), "prep_dma_slave\n");
861 BUG_ON(!ds || !ds->reg_width);
863 BUG_ON(direction != DMA_TO_DEVICE);
865 BUG_ON(direction != DMA_FROM_DEVICE);
866 if (unlikely(!sg_len))
871 for_each_sg(sgl, sg, sg_len, i) {
872 struct txx9dmac_desc *desc;
876 desc = txx9dmac_desc_get(dc);
878 txx9dmac_desc_put(dc, first);
882 mem = sg_dma_address(sg);
884 if (__is_dmac64(ddev)) {
885 if (direction == DMA_TO_DEVICE) {
886 desc->hwdesc.SAR = mem;
887 desc->hwdesc.DAR = ds->tx_reg;
889 desc->hwdesc.SAR = ds->rx_reg;
890 desc->hwdesc.DAR = mem;
892 desc->hwdesc.CNTR = sg_dma_len(sg);
894 if (direction == DMA_TO_DEVICE) {
895 desc->hwdesc32.SAR = mem;
896 desc->hwdesc32.DAR = ds->tx_reg;
898 desc->hwdesc32.SAR = ds->rx_reg;
899 desc->hwdesc32.DAR = mem;
901 desc->hwdesc32.CNTR = sg_dma_len(sg);
903 if (direction == DMA_TO_DEVICE) {
910 txx9dmac_desc_set_nosimple(ddev, desc, sai, dai,
911 dc->ccr | TXX9_DMA_CCR_XFACT);
916 desc_write_CHAR(dc, prev, desc->txd.phys);
917 dma_sync_single_for_device(chan2parent(&dc->chan),
921 list_add_tail(&desc->desc_node, &first->tx_list);
926 /* Trigger interrupt after last block */
927 if (flags & DMA_PREP_INTERRUPT)
928 txx9dmac_desc_set_INTENT(ddev, prev);
930 desc_write_CHAR(dc, prev, 0);
931 dma_sync_single_for_device(chan2parent(&dc->chan),
932 prev->txd.phys, ddev->descsize,
935 first->txd.flags = flags;
941 static void txx9dmac_terminate_all(struct dma_chan *chan)
943 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
944 struct txx9dmac_desc *desc, *_desc;
947 dev_vdbg(chan2dev(chan), "terminate_all\n");
948 spin_lock_bh(&dc->lock);
950 txx9dmac_reset_chan(dc);
952 /* active_list entries will end up before queued entries */
953 list_splice_init(&dc->queue, &list);
954 list_splice_init(&dc->active_list, &list);
956 spin_unlock_bh(&dc->lock);
958 /* Flush all pending and queued descriptors */
959 list_for_each_entry_safe(desc, _desc, &list, desc_node)
960 txx9dmac_descriptor_complete(dc, desc);
963 static enum dma_status
964 txx9dmac_is_tx_complete(struct dma_chan *chan,
966 dma_cookie_t *done, dma_cookie_t *used)
968 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
969 dma_cookie_t last_used;
970 dma_cookie_t last_complete;
973 last_complete = dc->completed;
974 last_used = chan->cookie;
976 ret = dma_async_is_complete(cookie, last_complete, last_used);
977 if (ret != DMA_SUCCESS) {
978 spin_lock_bh(&dc->lock);
979 txx9dmac_scan_descriptors(dc);
980 spin_unlock_bh(&dc->lock);
982 last_complete = dc->completed;
983 last_used = chan->cookie;
985 ret = dma_async_is_complete(cookie, last_complete, last_used);
989 *done = last_complete;
996 static void txx9dmac_chain_dynamic(struct txx9dmac_chan *dc,
997 struct txx9dmac_desc *prev)
999 struct txx9dmac_dev *ddev = dc->ddev;
1000 struct txx9dmac_desc *desc;
1003 prev = txx9dmac_last_child(prev);
1004 txx9dmac_dequeue(dc, &list);
1005 desc = list_entry(list.next, struct txx9dmac_desc, desc_node);
1006 desc_write_CHAR(dc, prev, desc->txd.phys);
1007 dma_sync_single_for_device(chan2parent(&dc->chan),
1008 prev->txd.phys, ddev->descsize,
1011 if (!(channel_readl(dc, CSR) & TXX9_DMA_CSR_CHNEN) &&
1012 channel_read_CHAR(dc) == prev->txd.phys)
1013 /* Restart chain DMA */
1014 channel_write_CHAR(dc, desc->txd.phys);
1015 list_splice_tail(&list, &dc->active_list);
1018 static void txx9dmac_issue_pending(struct dma_chan *chan)
1020 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
1022 spin_lock_bh(&dc->lock);
1024 if (!list_empty(&dc->active_list))
1025 txx9dmac_scan_descriptors(dc);
1026 if (!list_empty(&dc->queue)) {
1027 if (list_empty(&dc->active_list)) {
1028 txx9dmac_dequeue(dc, &dc->active_list);
1029 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
1030 } else if (txx9_dma_have_SMPCHN()) {
1031 struct txx9dmac_desc *prev = txx9dmac_last_active(dc);
1033 if (!(prev->txd.flags & DMA_PREP_INTERRUPT) ||
1034 txx9dmac_chan_INTENT(dc))
1035 txx9dmac_chain_dynamic(dc, prev);
1039 spin_unlock_bh(&dc->lock);
1042 static int txx9dmac_alloc_chan_resources(struct dma_chan *chan)
1044 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
1045 struct txx9dmac_slave *ds = chan->private;
1046 struct txx9dmac_desc *desc;
1049 dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");
1051 /* ASSERT: channel is idle */
1052 if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {
1053 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1057 dc->completed = chan->cookie = 1;
1059 dc->ccr = TXX9_DMA_CCR_IMMCHN | TXX9_DMA_CCR_INTENE | CCR_LE;
1060 txx9dmac_chan_set_SMPCHN(dc);
1061 if (!txx9_dma_have_SMPCHN() || (dc->ccr & TXX9_DMA_CCR_SMPCHN))
1062 dc->ccr |= TXX9_DMA_CCR_INTENC;
1063 if (chan->device->device_prep_dma_memcpy) {
1066 dc->ccr |= TXX9_DMA_CCR_XFSZ_X8;
1069 (ds->tx_reg && ds->rx_reg) || (!ds->tx_reg && !ds->rx_reg))
1071 dc->ccr |= TXX9_DMA_CCR_EXTRQ |
1072 TXX9_DMA_CCR_XFSZ(__ffs(ds->reg_width));
1073 txx9dmac_chan_set_INTENT(dc);
1076 spin_lock_bh(&dc->lock);
1077 i = dc->descs_allocated;
1078 while (dc->descs_allocated < TXX9_DMA_INITIAL_DESC_COUNT) {
1079 spin_unlock_bh(&dc->lock);
1081 desc = txx9dmac_desc_alloc(dc, GFP_KERNEL);
1083 dev_info(chan2dev(chan),
1084 "only allocated %d descriptors\n", i);
1085 spin_lock_bh(&dc->lock);
1088 txx9dmac_desc_put(dc, desc);
1090 spin_lock_bh(&dc->lock);
1091 i = ++dc->descs_allocated;
1093 spin_unlock_bh(&dc->lock);
1095 dev_dbg(chan2dev(chan),
1096 "alloc_chan_resources allocated %d descriptors\n", i);
1101 static void txx9dmac_free_chan_resources(struct dma_chan *chan)
1103 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
1104 struct txx9dmac_dev *ddev = dc->ddev;
1105 struct txx9dmac_desc *desc, *_desc;
1108 dev_dbg(chan2dev(chan), "free_chan_resources (descs allocated=%u)\n",
1109 dc->descs_allocated);
1111 /* ASSERT: channel is idle */
1112 BUG_ON(!list_empty(&dc->active_list));
1113 BUG_ON(!list_empty(&dc->queue));
1114 BUG_ON(channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT);
1116 spin_lock_bh(&dc->lock);
1117 list_splice_init(&dc->free_list, &list);
1118 dc->descs_allocated = 0;
1119 spin_unlock_bh(&dc->lock);
1121 list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1122 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
1123 dma_unmap_single(chan2parent(chan), desc->txd.phys,
1124 ddev->descsize, DMA_TO_DEVICE);
1128 dev_vdbg(chan2dev(chan), "free_chan_resources done\n");
1131 /*----------------------------------------------------------------------*/
1133 static void txx9dmac_off(struct txx9dmac_dev *ddev)
1135 dma_writel(ddev, MCR, 0);
1139 static int __init txx9dmac_chan_probe(struct platform_device *pdev)
1141 struct txx9dmac_chan_platform_data *cpdata = pdev->dev.platform_data;
1142 struct platform_device *dmac_dev = cpdata->dmac_dev;
1143 struct txx9dmac_platform_data *pdata = dmac_dev->dev.platform_data;
1144 struct txx9dmac_chan *dc;
1146 int ch = pdev->id % TXX9_DMA_MAX_NR_CHANNELS;
1149 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1153 dc->dma.dev = &pdev->dev;
1154 dc->dma.device_alloc_chan_resources = txx9dmac_alloc_chan_resources;
1155 dc->dma.device_free_chan_resources = txx9dmac_free_chan_resources;
1156 dc->dma.device_terminate_all = txx9dmac_terminate_all;
1157 dc->dma.device_is_tx_complete = txx9dmac_is_tx_complete;
1158 dc->dma.device_issue_pending = txx9dmac_issue_pending;
1159 if (pdata && pdata->memcpy_chan == ch) {
1160 dc->dma.device_prep_dma_memcpy = txx9dmac_prep_dma_memcpy;
1161 dma_cap_set(DMA_MEMCPY, dc->dma.cap_mask);
1163 dc->dma.device_prep_slave_sg = txx9dmac_prep_slave_sg;
1164 dma_cap_set(DMA_SLAVE, dc->dma.cap_mask);
1165 dma_cap_set(DMA_PRIVATE, dc->dma.cap_mask);
1168 INIT_LIST_HEAD(&dc->dma.channels);
1169 dc->ddev = platform_get_drvdata(dmac_dev);
1170 if (dc->ddev->irq < 0) {
1171 irq = platform_get_irq(pdev, 0);
1174 tasklet_init(&dc->tasklet, txx9dmac_chan_tasklet,
1177 err = devm_request_irq(&pdev->dev, dc->irq,
1178 txx9dmac_chan_interrupt, 0, dev_name(&pdev->dev), dc);
1183 dc->ddev->chan[ch] = dc;
1184 dc->chan.device = &dc->dma;
1185 list_add_tail(&dc->chan.device_node, &dc->chan.device->channels);
1186 dc->chan.cookie = dc->completed = 1;
1189 dc->ch_regs = &__txx9dmac_regs(dc->ddev)->CHAN[ch];
1191 dc->ch_regs = &__txx9dmac_regs32(dc->ddev)->CHAN[ch];
1192 spin_lock_init(&dc->lock);
1194 INIT_LIST_HEAD(&dc->active_list);
1195 INIT_LIST_HEAD(&dc->queue);
1196 INIT_LIST_HEAD(&dc->free_list);
1198 txx9dmac_reset_chan(dc);
1200 platform_set_drvdata(pdev, dc);
1202 err = dma_async_device_register(&dc->dma);
1205 dev_dbg(&pdev->dev, "TXx9 DMA Channel (dma%d%s%s)\n",
1207 dma_has_cap(DMA_MEMCPY, dc->dma.cap_mask) ? " memcpy" : "",
1208 dma_has_cap(DMA_SLAVE, dc->dma.cap_mask) ? " slave" : "");
1213 static int __exit txx9dmac_chan_remove(struct platform_device *pdev)
1215 struct txx9dmac_chan *dc = platform_get_drvdata(pdev);
1217 dma_async_device_unregister(&dc->dma);
1219 tasklet_kill(&dc->tasklet);
1220 dc->ddev->chan[pdev->id % TXX9_DMA_MAX_NR_CHANNELS] = NULL;
1224 static int __init txx9dmac_probe(struct platform_device *pdev)
1226 struct txx9dmac_platform_data *pdata = pdev->dev.platform_data;
1227 struct resource *io;
1228 struct txx9dmac_dev *ddev;
1232 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1236 ddev = devm_kzalloc(&pdev->dev, sizeof(*ddev), GFP_KERNEL);
1240 if (!devm_request_mem_region(&pdev->dev, io->start, resource_size(io),
1241 dev_name(&pdev->dev)))
1244 ddev->regs = devm_ioremap(&pdev->dev, io->start, resource_size(io));
1247 ddev->have_64bit_regs = pdata->have_64bit_regs;
1248 if (__is_dmac64(ddev))
1249 ddev->descsize = sizeof(struct txx9dmac_hwdesc);
1251 ddev->descsize = sizeof(struct txx9dmac_hwdesc32);
1253 /* force dma off, just in case */
1256 ddev->irq = platform_get_irq(pdev, 0);
1257 if (ddev->irq >= 0) {
1258 tasklet_init(&ddev->tasklet, txx9dmac_tasklet,
1259 (unsigned long)ddev);
1260 err = devm_request_irq(&pdev->dev, ddev->irq,
1261 txx9dmac_interrupt, 0, dev_name(&pdev->dev), ddev);
1266 mcr = TXX9_DMA_MCR_MSTEN | MCR_LE;
1267 if (pdata && pdata->memcpy_chan >= 0)
1268 mcr |= TXX9_DMA_MCR_FIFUM(pdata->memcpy_chan);
1269 dma_writel(ddev, MCR, mcr);
1271 platform_set_drvdata(pdev, ddev);
1275 static int __exit txx9dmac_remove(struct platform_device *pdev)
1277 struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1281 tasklet_kill(&ddev->tasklet);
1285 static void txx9dmac_shutdown(struct platform_device *pdev)
1287 struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1292 static int txx9dmac_suspend_noirq(struct device *dev)
1294 struct platform_device *pdev = to_platform_device(dev);
1295 struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1301 static int txx9dmac_resume_noirq(struct device *dev)
1303 struct platform_device *pdev = to_platform_device(dev);
1304 struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1305 struct txx9dmac_platform_data *pdata = pdev->dev.platform_data;
1308 mcr = TXX9_DMA_MCR_MSTEN | MCR_LE;
1309 if (pdata && pdata->memcpy_chan >= 0)
1310 mcr |= TXX9_DMA_MCR_FIFUM(pdata->memcpy_chan);
1311 dma_writel(ddev, MCR, mcr);
1316 static const struct dev_pm_ops txx9dmac_dev_pm_ops = {
1317 .suspend_noirq = txx9dmac_suspend_noirq,
1318 .resume_noirq = txx9dmac_resume_noirq,
1321 static struct platform_driver txx9dmac_chan_driver = {
1322 .remove = __exit_p(txx9dmac_chan_remove),
1324 .name = "txx9dmac-chan",
1328 static struct platform_driver txx9dmac_driver = {
1329 .remove = __exit_p(txx9dmac_remove),
1330 .shutdown = txx9dmac_shutdown,
1333 .pm = &txx9dmac_dev_pm_ops,
1337 static int __init txx9dmac_init(void)
1341 rc = platform_driver_probe(&txx9dmac_driver, txx9dmac_probe);
1343 rc = platform_driver_probe(&txx9dmac_chan_driver,
1344 txx9dmac_chan_probe);
1346 platform_driver_unregister(&txx9dmac_driver);
1350 module_init(txx9dmac_init);
1352 static void __exit txx9dmac_exit(void)
1354 platform_driver_unregister(&txx9dmac_chan_driver);
1355 platform_driver_unregister(&txx9dmac_driver);
1357 module_exit(txx9dmac_exit);
1359 MODULE_LICENSE("GPL");
1360 MODULE_DESCRIPTION("TXx9 DMA Controller driver");
1361 MODULE_AUTHOR("Atsushi Nemoto <anemo@mba.ocn.ne.jp>");
1362 MODULE_ALIAS("platform:txx9dmac");
1363 MODULE_ALIAS("platform:txx9dmac-chan");