2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 * Refer to drivers/dma/imx-sdma.c
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/init.h>
12 #include <linux/types.h>
14 #include <linux/interrupt.h>
15 #include <linux/clk.h>
16 #include <linux/wait.h>
17 #include <linux/sched.h>
18 #include <linux/semaphore.h>
19 #include <linux/device.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/platform_device.h>
23 #include <linux/dmaengine.h>
24 #include <linux/delay.h>
25 #include <linux/module.h>
26 #include <linux/stmp_device.h>
28 #include <linux/of_device.h>
29 #include <linux/of_dma.h>
30 #include <linux/list.h>
34 #include "dmaengine.h"
37 * NOTE: The term "PIO" throughout the mxs-dma implementation means
38 * PIO mode of mxs apbh-dma and apbx-dma. With this working mode,
39 * dma can program the controller registers of peripheral devices.
42 #define dma_is_apbh(mxs_dma) ((mxs_dma)->type == MXS_DMA_APBH)
43 #define apbh_is_old(mxs_dma) ((mxs_dma)->dev_id == IMX23_DMA)
45 #define HW_APBHX_CTRL0 0x000
46 #define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29)
47 #define BM_APBH_CTRL0_APB_BURST_EN (1 << 28)
48 #define BP_APBH_CTRL0_RESET_CHANNEL 16
49 #define HW_APBHX_CTRL1 0x010
50 #define HW_APBHX_CTRL2 0x020
51 #define HW_APBHX_CHANNEL_CTRL 0x030
52 #define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16
54 * The offset of NXTCMDAR register is different per both dma type and version,
55 * while stride for each channel is all the same 0x70.
57 #define HW_APBHX_CHn_NXTCMDAR(d, n) \
58 (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x050 : 0x110) + (n) * 0x70)
59 #define HW_APBHX_CHn_SEMA(d, n) \
60 (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x080 : 0x140) + (n) * 0x70)
61 #define HW_APBHX_CHn_BAR(d, n) \
62 (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x070 : 0x130) + (n) * 0x70)
65 * ccw bits definitions
70 * NAND_LOCK: 4 (1) - not implemented
71 * NAND_WAIT4READY: 5 (1) - not implemented
74 * HALT_ON_TERMINATE: 8 (1)
75 * TERMINATE_FLUSH: 9 (1)
76 * RESERVED: 10..11 (2)
79 #define BP_CCW_COMMAND 0
80 #define BM_CCW_COMMAND (3 << 0)
81 #define CCW_CHAIN (1 << 2)
82 #define CCW_IRQ (1 << 3)
83 #define CCW_DEC_SEM (1 << 6)
84 #define CCW_WAIT4END (1 << 7)
85 #define CCW_HALT_ON_TERM (1 << 8)
86 #define CCW_TERM_FLUSH (1 << 9)
87 #define BP_CCW_PIO_NUM 12
88 #define BM_CCW_PIO_NUM (0xf << 12)
90 #define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field)
92 #define MXS_DMA_CMD_NO_XFER 0
93 #define MXS_DMA_CMD_WRITE 1
94 #define MXS_DMA_CMD_READ 2
95 #define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */
101 #define MAX_XFER_BYTES 0xff00
103 #define MXS_PIO_WORDS 16
104 u32 pio_words[MXS_PIO_WORDS];
107 #define CCW_BLOCK_SIZE (4 * PAGE_SIZE)
108 #define NUM_CCW (int)(CCW_BLOCK_SIZE / sizeof(struct mxs_dma_ccw))
110 struct mxs_dma_chan {
111 struct mxs_dma_engine *mxs_dma;
112 struct dma_chan chan;
113 struct dma_async_tx_descriptor desc;
114 struct tasklet_struct tasklet;
115 unsigned int chan_irq;
116 struct mxs_dma_ccw *ccw;
119 enum dma_status status;
121 #define MXS_DMA_SG_LOOP (1 << 0)
124 #define MXS_DMA_CHANNELS 16
125 #define MXS_DMA_CHANNELS_MASK 0xffff
127 enum mxs_dma_devtype {
137 struct mxs_dma_engine {
138 enum mxs_dma_id dev_id;
139 enum mxs_dma_devtype type;
142 struct dma_device dma_device;
143 struct device_dma_parameters dma_parms;
144 struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS];
145 struct platform_device *pdev;
146 unsigned int nr_channels;
149 struct mxs_dma_type {
151 enum mxs_dma_devtype type;
154 static struct mxs_dma_type mxs_dma_types[] = {
157 .type = MXS_DMA_APBH,
160 .type = MXS_DMA_APBX,
163 .type = MXS_DMA_APBH,
166 .type = MXS_DMA_APBX,
170 static struct platform_device_id mxs_dma_ids[] = {
172 .name = "imx23-dma-apbh",
173 .driver_data = (kernel_ulong_t) &mxs_dma_types[0],
175 .name = "imx23-dma-apbx",
176 .driver_data = (kernel_ulong_t) &mxs_dma_types[1],
178 .name = "imx28-dma-apbh",
179 .driver_data = (kernel_ulong_t) &mxs_dma_types[2],
181 .name = "imx28-dma-apbx",
182 .driver_data = (kernel_ulong_t) &mxs_dma_types[3],
188 static const struct of_device_id mxs_dma_dt_ids[] = {
189 { .compatible = "fsl,imx23-dma-apbh", .data = &mxs_dma_ids[0], },
190 { .compatible = "fsl,imx23-dma-apbx", .data = &mxs_dma_ids[1], },
191 { .compatible = "fsl,imx28-dma-apbh", .data = &mxs_dma_ids[2], },
192 { .compatible = "fsl,imx28-dma-apbx", .data = &mxs_dma_ids[3], },
195 MODULE_DEVICE_TABLE(of, mxs_dma_dt_ids);
197 static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan)
199 return container_of(chan, struct mxs_dma_chan, chan);
202 static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan)
204 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
205 int chan_id = mxs_chan->chan.chan_id;
207 if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma))
208 writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL),
209 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
211 writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
212 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
215 static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan)
217 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
218 int chan_id = mxs_chan->chan.chan_id;
220 /* set cmd_addr up */
221 writel(mxs_chan->ccw_phys,
222 mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(mxs_dma, chan_id));
224 /* write 1 to SEMA to kick off the channel */
225 writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id));
228 static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan)
230 mxs_chan->status = DMA_COMPLETE;
233 static void mxs_dma_pause_chan(struct mxs_dma_chan *mxs_chan)
235 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
236 int chan_id = mxs_chan->chan.chan_id;
238 /* freeze the channel */
239 if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma))
241 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
244 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
246 mxs_chan->status = DMA_PAUSED;
249 static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan)
251 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
252 int chan_id = mxs_chan->chan.chan_id;
254 /* unfreeze the channel */
255 if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma))
257 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR);
260 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_CLR);
262 mxs_chan->status = DMA_IN_PROGRESS;
265 static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx)
267 return dma_cookie_assign(tx);
270 static void mxs_dma_tasklet(unsigned long data)
272 struct mxs_dma_chan *mxs_chan = (struct mxs_dma_chan *) data;
274 if (mxs_chan->desc.callback)
275 mxs_chan->desc.callback(mxs_chan->desc.callback_param);
278 static int mxs_dma_irq_to_chan(struct mxs_dma_engine *mxs_dma, int irq)
282 for (i = 0; i != mxs_dma->nr_channels; ++i)
283 if (mxs_dma->mxs_chans[i].chan_irq == irq)
289 static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
291 struct mxs_dma_engine *mxs_dma = dev_id;
292 struct mxs_dma_chan *mxs_chan;
295 int chan = mxs_dma_irq_to_chan(mxs_dma, irq);
300 /* completion status */
301 completed = readl(mxs_dma->base + HW_APBHX_CTRL1);
302 completed = (completed >> chan) & 0x1;
304 /* Clear interrupt */
306 mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR);
309 err = readl(mxs_dma->base + HW_APBHX_CTRL2);
310 err &= (1 << (MXS_DMA_CHANNELS + chan)) | (1 << chan);
313 * error status bit is in the upper 16 bits, error irq bit in the lower
314 * 16 bits. We transform it into a simpler error code:
315 * err: 0x00 = no error, 0x01 = TERMINATION, 0x02 = BUS_ERROR
317 err = (err >> (MXS_DMA_CHANNELS + chan)) + (err >> chan);
319 /* Clear error irq */
321 mxs_dma->base + HW_APBHX_CTRL2 + STMP_OFFSET_REG_CLR);
324 * When both completion and error of termination bits set at the
325 * same time, we do not take it as an error. IOW, it only becomes
326 * an error we need to handle here in case of either it's a bus
327 * error or a termination error with no completion. 0x01 is termination
328 * error, so we can subtract err & completed to get the real error case.
330 err -= err & completed;
332 mxs_chan = &mxs_dma->mxs_chans[chan];
335 dev_dbg(mxs_dma->dma_device.dev,
336 "%s: error in channel %d\n", __func__,
338 mxs_chan->status = DMA_ERROR;
339 mxs_dma_reset_chan(mxs_chan);
341 if (mxs_chan->flags & MXS_DMA_SG_LOOP)
342 mxs_chan->status = DMA_IN_PROGRESS;
344 mxs_chan->status = DMA_COMPLETE;
347 if (mxs_chan->status == DMA_COMPLETE)
348 dma_cookie_complete(&mxs_chan->desc);
350 /* schedule tasklet on this channel */
351 tasklet_schedule(&mxs_chan->tasklet);
356 static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
358 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
359 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
362 mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev,
363 CCW_BLOCK_SIZE, &mxs_chan->ccw_phys,
365 if (!mxs_chan->ccw) {
370 memset(mxs_chan->ccw, 0, CCW_BLOCK_SIZE);
372 if (mxs_chan->chan_irq != NO_IRQ) {
373 ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler,
374 0, "mxs-dma", mxs_dma);
379 ret = clk_prepare_enable(mxs_dma->clk);
383 mxs_dma_reset_chan(mxs_chan);
385 dma_async_tx_descriptor_init(&mxs_chan->desc, chan);
386 mxs_chan->desc.tx_submit = mxs_dma_tx_submit;
388 /* the descriptor is ready */
389 async_tx_ack(&mxs_chan->desc);
394 free_irq(mxs_chan->chan_irq, mxs_dma);
396 dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE,
397 mxs_chan->ccw, mxs_chan->ccw_phys);
402 static void mxs_dma_free_chan_resources(struct dma_chan *chan)
404 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
405 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
407 mxs_dma_disable_chan(mxs_chan);
409 free_irq(mxs_chan->chan_irq, mxs_dma);
411 dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE,
412 mxs_chan->ccw, mxs_chan->ccw_phys);
414 clk_disable_unprepare(mxs_dma->clk);
418 * How to use the flags for ->device_prep_slave_sg() :
419 * [1] If there is only one DMA command in the DMA chain, the code should be:
421 * ->device_prep_slave_sg(DMA_CTRL_ACK);
423 * [2] If there are two DMA commands in the DMA chain, the code should be
425 * ->device_prep_slave_sg(0);
427 * ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
429 * [3] If there are more than two DMA commands in the DMA chain, the code
432 * ->device_prep_slave_sg(0); // First
434 * ->device_prep_slave_sg(DMA_PREP_INTERRUPT [| DMA_CTRL_ACK]);
436 * ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK); // Last
439 static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
440 struct dma_chan *chan, struct scatterlist *sgl,
441 unsigned int sg_len, enum dma_transfer_direction direction,
442 unsigned long flags, void *context)
444 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
445 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
446 struct mxs_dma_ccw *ccw;
447 struct scatterlist *sg;
450 bool append = flags & DMA_PREP_INTERRUPT;
451 int idx = append ? mxs_chan->desc_count : 0;
453 if (mxs_chan->status == DMA_IN_PROGRESS && !append)
456 if (sg_len + (append ? idx : 0) > NUM_CCW) {
457 dev_err(mxs_dma->dma_device.dev,
458 "maximum number of sg exceeded: %d > %d\n",
463 mxs_chan->status = DMA_IN_PROGRESS;
467 * If the sg is prepared with append flag set, the sg
468 * will be appended to the last prepared sg.
472 ccw = &mxs_chan->ccw[idx - 1];
473 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
474 ccw->bits |= CCW_CHAIN;
475 ccw->bits &= ~CCW_IRQ;
476 ccw->bits &= ~CCW_DEC_SEM;
481 if (direction == DMA_TRANS_NONE) {
482 ccw = &mxs_chan->ccw[idx++];
485 for (j = 0; j < sg_len;)
486 ccw->pio_words[j++] = *pio++;
489 ccw->bits |= CCW_IRQ;
490 ccw->bits |= CCW_DEC_SEM;
491 if (flags & DMA_CTRL_ACK)
492 ccw->bits |= CCW_WAIT4END;
493 ccw->bits |= CCW_HALT_ON_TERM;
494 ccw->bits |= CCW_TERM_FLUSH;
495 ccw->bits |= BF_CCW(sg_len, PIO_NUM);
496 ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND);
498 for_each_sg(sgl, sg, sg_len, i) {
499 if (sg_dma_len(sg) > MAX_XFER_BYTES) {
500 dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n",
501 sg_dma_len(sg), MAX_XFER_BYTES);
505 ccw = &mxs_chan->ccw[idx++];
507 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
508 ccw->bufaddr = sg->dma_address;
509 ccw->xfer_bytes = sg_dma_len(sg);
512 ccw->bits |= CCW_CHAIN;
513 ccw->bits |= CCW_HALT_ON_TERM;
514 ccw->bits |= CCW_TERM_FLUSH;
515 ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
516 MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ,
519 if (i + 1 == sg_len) {
520 ccw->bits &= ~CCW_CHAIN;
521 ccw->bits |= CCW_IRQ;
522 ccw->bits |= CCW_DEC_SEM;
523 if (flags & DMA_CTRL_ACK)
524 ccw->bits |= CCW_WAIT4END;
528 mxs_chan->desc_count = idx;
530 return &mxs_chan->desc;
533 mxs_chan->status = DMA_ERROR;
537 static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic(
538 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
539 size_t period_len, enum dma_transfer_direction direction,
540 unsigned long flags, void *context)
542 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
543 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
544 u32 num_periods = buf_len / period_len;
547 if (mxs_chan->status == DMA_IN_PROGRESS)
550 mxs_chan->status = DMA_IN_PROGRESS;
551 mxs_chan->flags |= MXS_DMA_SG_LOOP;
553 if (num_periods > NUM_CCW) {
554 dev_err(mxs_dma->dma_device.dev,
555 "maximum number of sg exceeded: %d > %d\n",
556 num_periods, NUM_CCW);
560 if (period_len > MAX_XFER_BYTES) {
561 dev_err(mxs_dma->dma_device.dev,
562 "maximum period size exceeded: %d > %d\n",
563 period_len, MAX_XFER_BYTES);
567 while (buf < buf_len) {
568 struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i];
570 if (i + 1 == num_periods)
571 ccw->next = mxs_chan->ccw_phys;
573 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * (i + 1);
575 ccw->bufaddr = dma_addr;
576 ccw->xfer_bytes = period_len;
579 ccw->bits |= CCW_CHAIN;
580 ccw->bits |= CCW_IRQ;
581 ccw->bits |= CCW_HALT_ON_TERM;
582 ccw->bits |= CCW_TERM_FLUSH;
583 ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
584 MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND);
586 dma_addr += period_len;
591 mxs_chan->desc_count = i;
593 return &mxs_chan->desc;
596 mxs_chan->status = DMA_ERROR;
600 static int mxs_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
603 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
607 case DMA_TERMINATE_ALL:
608 mxs_dma_reset_chan(mxs_chan);
609 mxs_dma_disable_chan(mxs_chan);
612 mxs_dma_pause_chan(mxs_chan);
615 mxs_dma_resume_chan(mxs_chan);
624 static enum dma_status mxs_dma_tx_status(struct dma_chan *chan,
625 dma_cookie_t cookie, struct dma_tx_state *txstate)
627 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
628 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
631 if (mxs_chan->status == DMA_IN_PROGRESS &&
632 mxs_chan->flags & MXS_DMA_SG_LOOP) {
633 struct mxs_dma_ccw *last_ccw;
636 last_ccw = &mxs_chan->ccw[mxs_chan->desc_count - 1];
637 residue = last_ccw->xfer_bytes + last_ccw->bufaddr;
639 bar = readl(mxs_dma->base +
640 HW_APBHX_CHn_BAR(mxs_dma, chan->chan_id));
644 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
647 return mxs_chan->status;
650 static void mxs_dma_issue_pending(struct dma_chan *chan)
652 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
654 mxs_dma_enable_chan(mxs_chan);
657 static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma)
661 ret = clk_prepare_enable(mxs_dma->clk);
665 ret = stmp_reset_block(mxs_dma->base);
669 /* enable apbh burst */
670 if (dma_is_apbh(mxs_dma)) {
671 writel(BM_APBH_CTRL0_APB_BURST_EN,
672 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
673 writel(BM_APBH_CTRL0_APB_BURST8_EN,
674 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
677 /* enable irq for all the channels */
678 writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS,
679 mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET);
682 clk_disable_unprepare(mxs_dma->clk);
686 struct mxs_dma_filter_param {
687 struct device_node *of_node;
688 unsigned int chan_id;
691 static bool mxs_dma_filter_fn(struct dma_chan *chan, void *fn_param)
693 struct mxs_dma_filter_param *param = fn_param;
694 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
695 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
698 if (mxs_dma->dma_device.dev->of_node != param->of_node)
701 if (chan->chan_id != param->chan_id)
704 chan_irq = platform_get_irq(mxs_dma->pdev, param->chan_id);
708 mxs_chan->chan_irq = chan_irq;
713 static struct dma_chan *mxs_dma_xlate(struct of_phandle_args *dma_spec,
714 struct of_dma *ofdma)
716 struct mxs_dma_engine *mxs_dma = ofdma->of_dma_data;
717 dma_cap_mask_t mask = mxs_dma->dma_device.cap_mask;
718 struct mxs_dma_filter_param param;
720 if (dma_spec->args_count != 1)
723 param.of_node = ofdma->of_node;
724 param.chan_id = dma_spec->args[0];
726 if (param.chan_id >= mxs_dma->nr_channels)
729 return dma_request_channel(mask, mxs_dma_filter_fn, ¶m);
732 static int __init mxs_dma_probe(struct platform_device *pdev)
734 struct device_node *np = pdev->dev.of_node;
735 const struct platform_device_id *id_entry;
736 const struct of_device_id *of_id;
737 const struct mxs_dma_type *dma_type;
738 struct mxs_dma_engine *mxs_dma;
739 struct resource *iores;
742 mxs_dma = devm_kzalloc(&pdev->dev, sizeof(*mxs_dma), GFP_KERNEL);
746 ret = of_property_read_u32(np, "dma-channels", &mxs_dma->nr_channels);
748 dev_err(&pdev->dev, "failed to read dma-channels\n");
752 of_id = of_match_device(mxs_dma_dt_ids, &pdev->dev);
754 id_entry = of_id->data;
756 id_entry = platform_get_device_id(pdev);
758 dma_type = (struct mxs_dma_type *)id_entry->driver_data;
759 mxs_dma->type = dma_type->type;
760 mxs_dma->dev_id = dma_type->id;
762 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
763 mxs_dma->base = devm_ioremap_resource(&pdev->dev, iores);
764 if (IS_ERR(mxs_dma->base))
765 return PTR_ERR(mxs_dma->base);
767 mxs_dma->clk = devm_clk_get(&pdev->dev, NULL);
768 if (IS_ERR(mxs_dma->clk))
769 return PTR_ERR(mxs_dma->clk);
771 dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask);
772 dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask);
774 INIT_LIST_HEAD(&mxs_dma->dma_device.channels);
776 /* Initialize channel parameters */
777 for (i = 0; i < MXS_DMA_CHANNELS; i++) {
778 struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i];
780 mxs_chan->mxs_dma = mxs_dma;
781 mxs_chan->chan.device = &mxs_dma->dma_device;
782 dma_cookie_init(&mxs_chan->chan);
784 tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet,
785 (unsigned long) mxs_chan);
788 /* Add the channel to mxs_chan list */
789 list_add_tail(&mxs_chan->chan.device_node,
790 &mxs_dma->dma_device.channels);
793 ret = mxs_dma_init(mxs_dma);
797 mxs_dma->pdev = pdev;
798 mxs_dma->dma_device.dev = &pdev->dev;
800 /* mxs_dma gets 65535 bytes maximum sg size */
801 mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms;
802 dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES);
804 mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources;
805 mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources;
806 mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status;
807 mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg;
808 mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic;
809 mxs_dma->dma_device.device_control = mxs_dma_control;
810 mxs_dma->dma_device.device_issue_pending = mxs_dma_issue_pending;
812 ret = dma_async_device_register(&mxs_dma->dma_device);
814 dev_err(mxs_dma->dma_device.dev, "unable to register\n");
818 ret = of_dma_controller_register(np, mxs_dma_xlate, mxs_dma);
820 dev_err(mxs_dma->dma_device.dev,
821 "failed to register controller\n");
822 dma_async_device_unregister(&mxs_dma->dma_device);
825 dev_info(mxs_dma->dma_device.dev, "initialized\n");
830 static struct platform_driver mxs_dma_driver = {
833 .of_match_table = mxs_dma_dt_ids,
835 .id_table = mxs_dma_ids,
838 static int __init mxs_dma_module_init(void)
840 return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe);
842 subsys_initcall(mxs_dma_module_init);