2 * Copyright (C) 2007, 2008, Marvell International Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software Foundation,
15 * Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21 #include <linux/types.h>
23 #include <linux/dmaengine.h>
24 #include <linux/interrupt.h>
27 #define MV_XOR_SLOT_SIZE 64
28 #define MV_XOR_THRESHOLD 1
30 #define XOR_OPERATION_MODE_XOR 0
31 #define XOR_OPERATION_MODE_MEMCPY 2
32 #define XOR_OPERATION_MODE_MEMSET 4
33 #define XOR_DESC_SUCCESS 0x40000000
35 #define XOR_CURR_DESC(chan) (chan->mmr_base + 0x210 + (chan->idx * 4))
36 #define XOR_NEXT_DESC(chan) (chan->mmr_base + 0x200 + (chan->idx * 4))
37 #define XOR_BYTE_COUNT(chan) (chan->mmr_base + 0x220 + (chan->idx * 4))
38 #define XOR_DEST_POINTER(chan) (chan->mmr_base + 0x2B0 + (chan->idx * 4))
39 #define XOR_BLOCK_SIZE(chan) (chan->mmr_base + 0x2C0 + (chan->idx * 4))
40 #define XOR_INIT_VALUE_LOW(chan) (chan->mmr_base + 0x2E0)
41 #define XOR_INIT_VALUE_HIGH(chan) (chan->mmr_base + 0x2E4)
43 #define XOR_CONFIG(chan) (chan->mmr_base + 0x10 + (chan->idx * 4))
44 #define XOR_ACTIVATION(chan) (chan->mmr_base + 0x20 + (chan->idx * 4))
45 #define XOR_INTR_CAUSE(chan) (chan->mmr_base + 0x30)
46 #define XOR_INTR_MASK(chan) (chan->mmr_base + 0x40)
47 #define XOR_ERROR_CAUSE(chan) (chan->mmr_base + 0x50)
48 #define XOR_ERROR_ADDR(chan) (chan->mmr_base + 0x60)
49 #define XOR_INTR_MASK_VALUE 0x3F5
51 #define WINDOW_BASE(w) (0x250 + ((w) << 2))
52 #define WINDOW_SIZE(w) (0x270 + ((w) << 2))
53 #define WINDOW_REMAP_HIGH(w) (0x290 + ((w) << 2))
54 #define WINDOW_BAR_ENABLE(chan) (0x240 + ((chan) << 2))
56 struct mv_xor_shared_private {
57 void __iomem *xor_base;
58 void __iomem *xor_high_base;
63 * struct mv_xor_device - internal representation of a XOR device
64 * @pdev: Platform device
65 * @id: HW XOR Device selector
66 * @dma_desc_pool: base of DMA descriptor region (DMA address)
67 * @dma_desc_pool_virt: base of DMA descriptor region (CPU address)
68 * @common: embedded struct dma_device
70 struct mv_xor_device {
71 struct platform_device *pdev;
73 dma_addr_t dma_desc_pool;
74 void *dma_desc_pool_virt;
75 struct dma_device common;
76 struct mv_xor_shared_private *shared;
80 * struct mv_xor_chan - internal representation of a XOR channel
81 * @pending: allows batching of hardware operations
82 * @completed_cookie: identifier for the most recently completed operation
83 * @lock: serializes enqueue/dequeue operations to the descriptors pool
84 * @mmr_base: memory mapped register base
85 * @idx: the index of the xor channel
86 * @chain: device chain view of the descriptors
87 * @completed_slots: slots completed by HW but still need to be acked
88 * @device: parent device
89 * @common: common dmaengine channel object members
90 * @last_used: place holder for allocation to continue from where it left off
91 * @all_slots: complete domain of slots usable by the channel
92 * @slots_allocated: records the actual size of the descriptor slot pool
93 * @irq_tasklet: bottom half where mv_xor_slot_cleanup runs
97 dma_cookie_t completed_cookie;
98 spinlock_t lock; /* protects the descriptor slot pool */
99 void __iomem *mmr_base;
101 enum dma_transaction_type current_type;
102 struct list_head chain;
103 struct list_head completed_slots;
104 struct mv_xor_device *device;
105 struct dma_chan common;
106 struct mv_xor_desc_slot *last_used;
107 struct list_head all_slots;
109 struct tasklet_struct irq_tasklet;
111 unsigned long cleanup_time;
112 u32 current_on_last_cleanup;
113 dma_cookie_t is_complete_cookie;
118 * struct mv_xor_desc_slot - software descriptor
119 * @slot_node: node on the mv_xor_chan.all_slots list
120 * @chain_node: node on the mv_xor_chan.chain list
121 * @completed_node: node on the mv_xor_chan.completed_slots list
122 * @hw_desc: virtual address of the hardware descriptor chain
123 * @phys: hardware address of the hardware descriptor chain
124 * @group_head: first operation in a transaction
125 * @slot_cnt: total slots used in an transaction (group of operations)
126 * @slots_per_op: number of slots per operation
128 * @unmap_src_cnt: number of xor sources
129 * @unmap_len: transaction bytecount
130 * @tx_list: list of slots that make up a multi-descriptor transaction
131 * @async_tx: support for the async_tx api
132 * @xor_check_result: result of zero sum
133 * @crc32_result: result crc calculation
135 struct mv_xor_desc_slot {
136 struct list_head slot_node;
137 struct list_head chain_node;
138 struct list_head completed_node;
139 enum dma_transaction_type type;
141 struct mv_xor_desc_slot *group_head;
148 struct list_head tx_list;
149 struct dma_async_tx_descriptor async_tx;
151 u32 *xor_check_result;
155 unsigned long arrival_time;
156 struct timer_list timeout;
160 /* This structure describes XOR descriptor size 64bytes */
162 u32 status; /* descriptor execution status */
163 u32 crc32_result; /* result of CRC-32 calculation */
164 u32 desc_command; /* type of operation to be carried out */
165 u32 phy_next_desc; /* next descriptor address pointer */
166 u32 byte_count; /* size of src/dst blocks in bytes */
167 u32 phy_dest_addr; /* destination block address */
168 u32 phy_src_addr[8]; /* source block addresses */
173 #define to_mv_sw_desc(addr_hw_desc) \
174 container_of(addr_hw_desc, struct mv_xor_desc_slot, hw_desc)
176 #define mv_hw_desc_slot_idx(hw_desc, idx) \
177 ((void *)(((unsigned long)hw_desc) + ((idx) << 5)))
179 #define MV_XOR_MIN_BYTE_COUNT (128)
180 #define XOR_MAX_BYTE_COUNT ((16 * 1024 * 1024) - 1)
181 #define MV_XOR_MAX_BYTE_COUNT XOR_MAX_BYTE_COUNT