2 * drivers/dma/imx-sdma.c
4 * This file contains a driver for the Freescale Smart DMA engine
6 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
8 * Based on code from Freescale:
10 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
12 * The code contained herein is licensed under the GNU General Public
13 * License. You may obtain a copy of the GNU General Public License
14 * Version 2 or later at the following locations:
16 * http://www.opensource.org/licenses/gpl-license.html
17 * http://www.gnu.org/copyleft/gpl.html
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/types.h>
24 #include <linux/interrupt.h>
25 #include <linux/clk.h>
26 #include <linux/wait.h>
27 #include <linux/sched.h>
28 #include <linux/semaphore.h>
29 #include <linux/spinlock.h>
30 #include <linux/device.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/firmware.h>
33 #include <linux/slab.h>
34 #include <linux/platform_device.h>
35 #include <linux/dmaengine.h>
37 #include <linux/of_device.h>
38 #include <linux/module.h>
41 #include <mach/sdma.h>
43 #include <mach/hardware.h>
46 #define SDMA_H_C0PTR 0x000
47 #define SDMA_H_INTR 0x004
48 #define SDMA_H_STATSTOP 0x008
49 #define SDMA_H_START 0x00c
50 #define SDMA_H_EVTOVR 0x010
51 #define SDMA_H_DSPOVR 0x014
52 #define SDMA_H_HOSTOVR 0x018
53 #define SDMA_H_EVTPEND 0x01c
54 #define SDMA_H_DSPENBL 0x020
55 #define SDMA_H_RESET 0x024
56 #define SDMA_H_EVTERR 0x028
57 #define SDMA_H_INTRMSK 0x02c
58 #define SDMA_H_PSW 0x030
59 #define SDMA_H_EVTERRDBG 0x034
60 #define SDMA_H_CONFIG 0x038
61 #define SDMA_ONCE_ENB 0x040
62 #define SDMA_ONCE_DATA 0x044
63 #define SDMA_ONCE_INSTR 0x048
64 #define SDMA_ONCE_STAT 0x04c
65 #define SDMA_ONCE_CMD 0x050
66 #define SDMA_EVT_MIRROR 0x054
67 #define SDMA_ILLINSTADDR 0x058
68 #define SDMA_CHN0ADDR 0x05c
69 #define SDMA_ONCE_RTB 0x060
70 #define SDMA_XTRIG_CONF1 0x070
71 #define SDMA_XTRIG_CONF2 0x074
72 #define SDMA_CHNENBL0_IMX35 0x200
73 #define SDMA_CHNENBL0_IMX31 0x080
74 #define SDMA_CHNPRI_0 0x100
77 * Buffer descriptor status values.
88 * Data Node descriptor status values.
90 #define DND_END_OF_FRAME 0x80
91 #define DND_END_OF_XFER 0x40
93 #define DND_UNUSED 0x01
96 * IPCV2 descriptor status values.
98 #define BD_IPCV2_END_OF_FRAME 0x40
100 #define IPCV2_MAX_NODES 50
102 * Error bit set in the CCB status field by the SDMA,
103 * in setbd routine, in case of a transfer error
105 #define DATA_ERROR 0x10000000
108 * Buffer descriptor commands.
113 #define C0_SETCTX 0x07
114 #define C0_GETCTX 0x03
115 #define C0_SETDM 0x01
116 #define C0_SETPM 0x04
117 #define C0_GETDM 0x02
118 #define C0_GETPM 0x08
120 * Change endianness indicator in the BD command field
122 #define CHANGE_ENDIANNESS 0x80
125 * Mode/Count of data node descriptors - IPCv2
127 struct sdma_mode_count {
128 u32 count : 16; /* size of the buffer pointed by this BD */
129 u32 status : 8; /* E,R,I,C,W,D status bits stored here */
130 u32 command : 8; /* command mostlky used for channel 0 */
136 struct sdma_buffer_descriptor {
137 struct sdma_mode_count mode;
138 u32 buffer_addr; /* address of the buffer described */
139 u32 ext_buffer_addr; /* extended buffer address */
140 } __attribute__ ((packed));
143 * struct sdma_channel_control - Channel control Block
145 * @current_bd_ptr current buffer descriptor processed
146 * @base_bd_ptr first element of buffer descriptor array
147 * @unused padding. The SDMA engine expects an array of 128 byte
150 struct sdma_channel_control {
154 } __attribute__ ((packed));
157 * struct sdma_state_registers - SDMA context for a channel
159 * @pc: program counter
160 * @t: test bit: status of arithmetic & test instruction
161 * @rpc: return program counter
162 * @sf: source fault while loading data
163 * @spc: loop start program counter
164 * @df: destination fault while storing data
165 * @epc: loop end program counter
168 struct sdma_state_registers {
180 } __attribute__ ((packed));
183 * struct sdma_context_data - sdma context specific to a channel
185 * @channel_state: channel state bits
186 * @gReg: general registers
187 * @mda: burst dma destination address register
188 * @msa: burst dma source address register
189 * @ms: burst dma status register
190 * @md: burst dma data register
191 * @pda: peripheral dma destination address register
192 * @psa: peripheral dma source address register
193 * @ps: peripheral dma status register
194 * @pd: peripheral dma data register
195 * @ca: CRC polynomial register
196 * @cs: CRC accumulator register
197 * @dda: dedicated core destination address register
198 * @dsa: dedicated core source address register
199 * @ds: dedicated core status register
200 * @dd: dedicated core data register
202 struct sdma_context_data {
203 struct sdma_state_registers channel_state;
227 } __attribute__ ((packed));
229 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
234 * struct sdma_channel - housekeeping for a SDMA channel
236 * @sdma pointer to the SDMA engine for this channel
237 * @channel the channel number, matches dmaengine chan_id + 1
238 * @direction transfer type. Needed for setting SDMA script
239 * @peripheral_type Peripheral type. Needed for setting SDMA script
240 * @event_id0 aka dma request line
241 * @event_id1 for channels that use 2 events
242 * @word_size peripheral access size
243 * @buf_tail ID of the buffer that was processed
244 * @done channel completion
245 * @num_bd max NUM_BD. number of descriptors currently handling
247 struct sdma_channel {
248 struct sdma_engine *sdma;
249 unsigned int channel;
250 enum dma_transfer_direction direction;
251 enum sdma_peripheral_type peripheral_type;
252 unsigned int event_id0;
253 unsigned int event_id1;
254 enum dma_slave_buswidth word_size;
255 unsigned int buf_tail;
256 struct completion done;
258 struct sdma_buffer_descriptor *bd;
260 unsigned int pc_from_device, pc_to_device;
262 dma_addr_t per_address;
263 u32 event_mask0, event_mask1;
265 u32 shp_addr, per_addr;
266 struct dma_chan chan;
268 struct dma_async_tx_descriptor desc;
269 dma_cookie_t last_completed;
270 enum dma_status status;
271 unsigned int chn_count;
272 unsigned int chn_real_count;
275 #define IMX_DMA_SG_LOOP (1 << 0)
277 #define MAX_DMA_CHANNELS 32
278 #define MXC_SDMA_DEFAULT_PRIORITY 1
279 #define MXC_SDMA_MIN_PRIORITY 1
280 #define MXC_SDMA_MAX_PRIORITY 7
282 #define SDMA_FIRMWARE_MAGIC 0x414d4453
285 * struct sdma_firmware_header - Layout of the firmware image
288 * @version_major increased whenever layout of struct sdma_script_start_addrs
290 * @version_minor firmware minor version (for binary compatible changes)
291 * @script_addrs_start offset of struct sdma_script_start_addrs in this image
292 * @num_script_addrs Number of script addresses in this image
293 * @ram_code_start offset of SDMA ram image in this firmware image
294 * @ram_code_size size of SDMA ram image
295 * @script_addrs Stores the start address of the SDMA scripts
296 * (in SDMA memory space)
298 struct sdma_firmware_header {
302 u32 script_addrs_start;
303 u32 num_script_addrs;
309 IMX31_SDMA, /* runs on i.mx31 */
310 IMX35_SDMA, /* runs on i.mx35 and later */
315 struct device_dma_parameters dma_parms;
316 struct sdma_channel channel[MAX_DMA_CHANNELS];
317 struct sdma_channel_control *channel_control;
319 enum sdma_devtype devtype;
320 unsigned int num_events;
321 struct sdma_context_data *context;
322 dma_addr_t context_phys;
323 struct dma_device dma_device;
325 struct mutex channel_0_lock;
326 struct sdma_script_start_addrs *script_addrs;
329 static struct platform_device_id sdma_devtypes[] = {
331 .name = "imx31-sdma",
332 .driver_data = IMX31_SDMA,
334 .name = "imx35-sdma",
335 .driver_data = IMX35_SDMA,
340 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
342 static const struct of_device_id sdma_dt_ids[] = {
343 { .compatible = "fsl,imx31-sdma", .data = &sdma_devtypes[IMX31_SDMA], },
344 { .compatible = "fsl,imx35-sdma", .data = &sdma_devtypes[IMX35_SDMA], },
347 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
349 #define SDMA_H_CONFIG_DSPDMA (1 << 12) /* indicates if the DSPDMA is used */
350 #define SDMA_H_CONFIG_RTD_PINS (1 << 11) /* indicates if Real-Time Debug pins are enabled */
351 #define SDMA_H_CONFIG_ACR (1 << 4) /* indicates if AHB freq /core freq = 2 or 1 */
352 #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/
354 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
356 u32 chnenbl0 = (sdma->devtype == IMX31_SDMA ? SDMA_CHNENBL0_IMX31 :
357 SDMA_CHNENBL0_IMX35);
358 return chnenbl0 + event * 4;
361 static int sdma_config_ownership(struct sdma_channel *sdmac,
362 bool event_override, bool mcu_override, bool dsp_override)
364 struct sdma_engine *sdma = sdmac->sdma;
365 int channel = sdmac->channel;
368 if (event_override && mcu_override && dsp_override)
371 evt = __raw_readl(sdma->regs + SDMA_H_EVTOVR);
372 mcu = __raw_readl(sdma->regs + SDMA_H_HOSTOVR);
373 dsp = __raw_readl(sdma->regs + SDMA_H_DSPOVR);
376 dsp &= ~(1 << channel);
378 dsp |= (1 << channel);
381 evt &= ~(1 << channel);
383 evt |= (1 << channel);
386 mcu &= ~(1 << channel);
388 mcu |= (1 << channel);
390 __raw_writel(evt, sdma->regs + SDMA_H_EVTOVR);
391 __raw_writel(mcu, sdma->regs + SDMA_H_HOSTOVR);
392 __raw_writel(dsp, sdma->regs + SDMA_H_DSPOVR);
397 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
399 __raw_writel(1 << channel, sdma->regs + SDMA_H_START);
403 * sdma_run_channel - run a channel and wait till it's done
405 static int sdma_run_channel(struct sdma_channel *sdmac)
407 struct sdma_engine *sdma = sdmac->sdma;
408 int channel = sdmac->channel;
411 init_completion(&sdmac->done);
413 sdma_enable_channel(sdma, channel);
415 ret = wait_for_completion_timeout(&sdmac->done, HZ);
417 return ret ? 0 : -ETIMEDOUT;
420 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
423 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
428 mutex_lock(&sdma->channel_0_lock);
430 buf_virt = dma_alloc_coherent(NULL,
432 &buf_phys, GFP_KERNEL);
438 bd0->mode.command = C0_SETPM;
439 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
440 bd0->mode.count = size / 2;
441 bd0->buffer_addr = buf_phys;
442 bd0->ext_buffer_addr = address;
444 memcpy(buf_virt, buf, size);
446 ret = sdma_run_channel(&sdma->channel[0]);
448 dma_free_coherent(NULL, size, buf_virt, buf_phys);
451 mutex_unlock(&sdma->channel_0_lock);
456 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
458 struct sdma_engine *sdma = sdmac->sdma;
459 int channel = sdmac->channel;
461 u32 chnenbl = chnenbl_ofs(sdma, event);
463 val = __raw_readl(sdma->regs + chnenbl);
464 val |= (1 << channel);
465 __raw_writel(val, sdma->regs + chnenbl);
468 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
470 struct sdma_engine *sdma = sdmac->sdma;
471 int channel = sdmac->channel;
472 u32 chnenbl = chnenbl_ofs(sdma, event);
475 val = __raw_readl(sdma->regs + chnenbl);
476 val &= ~(1 << channel);
477 __raw_writel(val, sdma->regs + chnenbl);
480 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
482 struct sdma_buffer_descriptor *bd;
485 * loop mode. Iterate over descriptors, re-setup them and
486 * call callback function.
489 bd = &sdmac->bd[sdmac->buf_tail];
491 if (bd->mode.status & BD_DONE)
494 if (bd->mode.status & BD_RROR)
495 sdmac->status = DMA_ERROR;
497 sdmac->status = DMA_IN_PROGRESS;
499 bd->mode.status |= BD_DONE;
501 sdmac->buf_tail %= sdmac->num_bd;
503 if (sdmac->desc.callback)
504 sdmac->desc.callback(sdmac->desc.callback_param);
508 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
510 struct sdma_buffer_descriptor *bd;
513 sdmac->chn_real_count = 0;
515 * non loop mode. Iterate over all descriptors, collect
516 * errors and call callback function
518 for (i = 0; i < sdmac->num_bd; i++) {
521 if (bd->mode.status & (BD_DONE | BD_RROR))
523 sdmac->chn_real_count += bd->mode.count;
527 sdmac->status = DMA_ERROR;
529 sdmac->status = DMA_SUCCESS;
531 sdmac->last_completed = sdmac->desc.cookie;
532 if (sdmac->desc.callback)
533 sdmac->desc.callback(sdmac->desc.callback_param);
536 static void mxc_sdma_handle_channel(struct sdma_channel *sdmac)
538 complete(&sdmac->done);
540 /* not interested in channel 0 interrupts */
541 if (sdmac->channel == 0)
544 if (sdmac->flags & IMX_DMA_SG_LOOP)
545 sdma_handle_channel_loop(sdmac);
547 mxc_sdma_handle_channel_normal(sdmac);
550 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
552 struct sdma_engine *sdma = dev_id;
555 stat = __raw_readl(sdma->regs + SDMA_H_INTR);
556 __raw_writel(stat, sdma->regs + SDMA_H_INTR);
559 int channel = fls(stat) - 1;
560 struct sdma_channel *sdmac = &sdma->channel[channel];
562 mxc_sdma_handle_channel(sdmac);
564 stat &= ~(1 << channel);
571 * sets the pc of SDMA script according to the peripheral type
573 static void sdma_get_pc(struct sdma_channel *sdmac,
574 enum sdma_peripheral_type peripheral_type)
576 struct sdma_engine *sdma = sdmac->sdma;
577 int per_2_emi = 0, emi_2_per = 0;
579 * These are needed once we start to support transfers between
580 * two peripherals or memory-to-memory transfers
582 int per_2_per = 0, emi_2_emi = 0;
584 sdmac->pc_from_device = 0;
585 sdmac->pc_to_device = 0;
587 switch (peripheral_type) {
588 case IMX_DMATYPE_MEMORY:
589 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
591 case IMX_DMATYPE_DSP:
592 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
593 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
595 case IMX_DMATYPE_FIRI:
596 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
597 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
599 case IMX_DMATYPE_UART:
600 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
601 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
603 case IMX_DMATYPE_UART_SP:
604 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
605 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
607 case IMX_DMATYPE_ATA:
608 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
609 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
611 case IMX_DMATYPE_CSPI:
612 case IMX_DMATYPE_EXT:
613 case IMX_DMATYPE_SSI:
614 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
615 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
617 case IMX_DMATYPE_SSI_SP:
618 case IMX_DMATYPE_MMC:
619 case IMX_DMATYPE_SDHC:
620 case IMX_DMATYPE_CSPI_SP:
621 case IMX_DMATYPE_ESAI:
622 case IMX_DMATYPE_MSHC_SP:
623 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
624 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
626 case IMX_DMATYPE_ASRC:
627 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
628 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
629 per_2_per = sdma->script_addrs->per_2_per_addr;
631 case IMX_DMATYPE_MSHC:
632 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
633 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
635 case IMX_DMATYPE_CCM:
636 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
638 case IMX_DMATYPE_SPDIF:
639 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
640 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
642 case IMX_DMATYPE_IPU_MEMORY:
643 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
649 sdmac->pc_from_device = per_2_emi;
650 sdmac->pc_to_device = emi_2_per;
653 static int sdma_load_context(struct sdma_channel *sdmac)
655 struct sdma_engine *sdma = sdmac->sdma;
656 int channel = sdmac->channel;
658 struct sdma_context_data *context = sdma->context;
659 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
662 if (sdmac->direction == DMA_DEV_TO_MEM) {
663 load_address = sdmac->pc_from_device;
665 load_address = sdmac->pc_to_device;
668 if (load_address < 0)
671 dev_dbg(sdma->dev, "load_address = %d\n", load_address);
672 dev_dbg(sdma->dev, "wml = 0x%08x\n", sdmac->watermark_level);
673 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
674 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
675 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", sdmac->event_mask0);
676 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", sdmac->event_mask1);
678 mutex_lock(&sdma->channel_0_lock);
680 memset(context, 0, sizeof(*context));
681 context->channel_state.pc = load_address;
683 /* Send by context the event mask,base address for peripheral
684 * and watermark level
686 context->gReg[0] = sdmac->event_mask1;
687 context->gReg[1] = sdmac->event_mask0;
688 context->gReg[2] = sdmac->per_addr;
689 context->gReg[6] = sdmac->shp_addr;
690 context->gReg[7] = sdmac->watermark_level;
692 bd0->mode.command = C0_SETDM;
693 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
694 bd0->mode.count = sizeof(*context) / 4;
695 bd0->buffer_addr = sdma->context_phys;
696 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
698 ret = sdma_run_channel(&sdma->channel[0]);
700 mutex_unlock(&sdma->channel_0_lock);
705 static void sdma_disable_channel(struct sdma_channel *sdmac)
707 struct sdma_engine *sdma = sdmac->sdma;
708 int channel = sdmac->channel;
710 __raw_writel(1 << channel, sdma->regs + SDMA_H_STATSTOP);
711 sdmac->status = DMA_ERROR;
714 static int sdma_config_channel(struct sdma_channel *sdmac)
718 sdma_disable_channel(sdmac);
720 sdmac->event_mask0 = 0;
721 sdmac->event_mask1 = 0;
725 if (sdmac->event_id0) {
726 if (sdmac->event_id0 > 32)
728 sdma_event_enable(sdmac, sdmac->event_id0);
731 switch (sdmac->peripheral_type) {
732 case IMX_DMATYPE_DSP:
733 sdma_config_ownership(sdmac, false, true, true);
735 case IMX_DMATYPE_MEMORY:
736 sdma_config_ownership(sdmac, false, true, false);
739 sdma_config_ownership(sdmac, true, true, false);
743 sdma_get_pc(sdmac, sdmac->peripheral_type);
745 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
746 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
747 /* Handle multiple event channels differently */
748 if (sdmac->event_id1) {
749 sdmac->event_mask1 = 1 << (sdmac->event_id1 % 32);
750 if (sdmac->event_id1 > 31)
751 sdmac->watermark_level |= 1 << 31;
752 sdmac->event_mask0 = 1 << (sdmac->event_id0 % 32);
753 if (sdmac->event_id0 > 31)
754 sdmac->watermark_level |= 1 << 30;
756 sdmac->event_mask0 = 1 << sdmac->event_id0;
757 sdmac->event_mask1 = 1 << (sdmac->event_id0 - 32);
759 /* Watermark Level */
760 sdmac->watermark_level |= sdmac->watermark_level;
762 sdmac->shp_addr = sdmac->per_address;
764 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
767 ret = sdma_load_context(sdmac);
772 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
773 unsigned int priority)
775 struct sdma_engine *sdma = sdmac->sdma;
776 int channel = sdmac->channel;
778 if (priority < MXC_SDMA_MIN_PRIORITY
779 || priority > MXC_SDMA_MAX_PRIORITY) {
783 __raw_writel(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
788 static int sdma_request_channel(struct sdma_channel *sdmac)
790 struct sdma_engine *sdma = sdmac->sdma;
791 int channel = sdmac->channel;
794 sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL);
800 memset(sdmac->bd, 0, PAGE_SIZE);
802 sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
803 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
805 clk_enable(sdma->clk);
807 sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
809 init_completion(&sdmac->done);
819 static dma_cookie_t sdma_assign_cookie(struct sdma_channel *sdmac)
821 dma_cookie_t cookie = sdmac->chan.cookie;
826 sdmac->chan.cookie = cookie;
827 sdmac->desc.cookie = cookie;
832 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
834 return container_of(chan, struct sdma_channel, chan);
837 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
840 struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
843 spin_lock_irqsave(&sdmac->lock, flags);
845 cookie = sdma_assign_cookie(sdmac);
847 spin_unlock_irqrestore(&sdmac->lock, flags);
852 static int sdma_alloc_chan_resources(struct dma_chan *chan)
854 struct sdma_channel *sdmac = to_sdma_chan(chan);
855 struct imx_dma_data *data = chan->private;
861 switch (data->priority) {
865 case DMA_PRIO_MEDIUM:
874 sdmac->peripheral_type = data->peripheral_type;
875 sdmac->event_id0 = data->dma_request;
876 ret = sdma_set_channel_priority(sdmac, prio);
880 ret = sdma_request_channel(sdmac);
884 dma_async_tx_descriptor_init(&sdmac->desc, chan);
885 sdmac->desc.tx_submit = sdma_tx_submit;
886 /* txd.flags will be overwritten in prep funcs */
887 sdmac->desc.flags = DMA_CTRL_ACK;
892 static void sdma_free_chan_resources(struct dma_chan *chan)
894 struct sdma_channel *sdmac = to_sdma_chan(chan);
895 struct sdma_engine *sdma = sdmac->sdma;
897 sdma_disable_channel(sdmac);
899 if (sdmac->event_id0)
900 sdma_event_disable(sdmac, sdmac->event_id0);
901 if (sdmac->event_id1)
902 sdma_event_disable(sdmac, sdmac->event_id1);
904 sdmac->event_id0 = 0;
905 sdmac->event_id1 = 0;
907 sdma_set_channel_priority(sdmac, 0);
909 dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
911 clk_disable(sdma->clk);
914 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
915 struct dma_chan *chan, struct scatterlist *sgl,
916 unsigned int sg_len, enum dma_transfer_direction direction,
919 struct sdma_channel *sdmac = to_sdma_chan(chan);
920 struct sdma_engine *sdma = sdmac->sdma;
922 int channel = sdmac->channel;
923 struct scatterlist *sg;
925 if (sdmac->status == DMA_IN_PROGRESS)
927 sdmac->status = DMA_IN_PROGRESS;
931 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
934 sdmac->direction = direction;
935 ret = sdma_load_context(sdmac);
939 if (sg_len > NUM_BD) {
940 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
941 channel, sg_len, NUM_BD);
946 sdmac->chn_count = 0;
947 for_each_sg(sgl, sg, sg_len, i) {
948 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
951 bd->buffer_addr = sg->dma_address;
955 if (count > 0xffff) {
956 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
957 channel, count, 0xffff);
962 bd->mode.count = count;
963 sdmac->chn_count += count;
965 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
970 switch (sdmac->word_size) {
971 case DMA_SLAVE_BUSWIDTH_4_BYTES:
972 bd->mode.command = 0;
973 if (count & 3 || sg->dma_address & 3)
976 case DMA_SLAVE_BUSWIDTH_2_BYTES:
977 bd->mode.command = 2;
978 if (count & 1 || sg->dma_address & 1)
981 case DMA_SLAVE_BUSWIDTH_1_BYTE:
982 bd->mode.command = 1;
988 param = BD_DONE | BD_EXTD | BD_CONT;
990 if (i + 1 == sg_len) {
996 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
997 i, count, sg->dma_address,
998 param & BD_WRAP ? "wrap" : "",
999 param & BD_INTR ? " intr" : "");
1001 bd->mode.status = param;
1004 sdmac->num_bd = sg_len;
1005 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1007 return &sdmac->desc;
1009 sdmac->status = DMA_ERROR;
1013 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1014 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1015 size_t period_len, enum dma_transfer_direction direction)
1017 struct sdma_channel *sdmac = to_sdma_chan(chan);
1018 struct sdma_engine *sdma = sdmac->sdma;
1019 int num_periods = buf_len / period_len;
1020 int channel = sdmac->channel;
1021 int ret, i = 0, buf = 0;
1023 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1025 if (sdmac->status == DMA_IN_PROGRESS)
1028 sdmac->status = DMA_IN_PROGRESS;
1030 sdmac->flags |= IMX_DMA_SG_LOOP;
1031 sdmac->direction = direction;
1032 ret = sdma_load_context(sdmac);
1036 if (num_periods > NUM_BD) {
1037 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1038 channel, num_periods, NUM_BD);
1042 if (period_len > 0xffff) {
1043 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1044 channel, period_len, 0xffff);
1048 while (buf < buf_len) {
1049 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1052 bd->buffer_addr = dma_addr;
1054 bd->mode.count = period_len;
1056 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1058 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1059 bd->mode.command = 0;
1061 bd->mode.command = sdmac->word_size;
1063 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1064 if (i + 1 == num_periods)
1067 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
1068 i, period_len, dma_addr,
1069 param & BD_WRAP ? "wrap" : "",
1070 param & BD_INTR ? " intr" : "");
1072 bd->mode.status = param;
1074 dma_addr += period_len;
1080 sdmac->num_bd = num_periods;
1081 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1083 return &sdmac->desc;
1085 sdmac->status = DMA_ERROR;
1089 static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1092 struct sdma_channel *sdmac = to_sdma_chan(chan);
1093 struct dma_slave_config *dmaengine_cfg = (void *)arg;
1096 case DMA_TERMINATE_ALL:
1097 sdma_disable_channel(sdmac);
1099 case DMA_SLAVE_CONFIG:
1100 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1101 sdmac->per_address = dmaengine_cfg->src_addr;
1102 sdmac->watermark_level = dmaengine_cfg->src_maxburst;
1103 sdmac->word_size = dmaengine_cfg->src_addr_width;
1105 sdmac->per_address = dmaengine_cfg->dst_addr;
1106 sdmac->watermark_level = dmaengine_cfg->dst_maxburst;
1107 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1109 sdmac->direction = dmaengine_cfg->direction;
1110 return sdma_config_channel(sdmac);
1118 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1119 dma_cookie_t cookie,
1120 struct dma_tx_state *txstate)
1122 struct sdma_channel *sdmac = to_sdma_chan(chan);
1123 dma_cookie_t last_used;
1125 last_used = chan->cookie;
1127 dma_set_tx_state(txstate, sdmac->last_completed, last_used,
1128 sdmac->chn_count - sdmac->chn_real_count);
1130 return sdmac->status;
1133 static void sdma_issue_pending(struct dma_chan *chan)
1135 struct sdma_channel *sdmac = to_sdma_chan(chan);
1136 struct sdma_engine *sdma = sdmac->sdma;
1138 if (sdmac->status == DMA_IN_PROGRESS)
1139 sdma_enable_channel(sdma, sdmac->channel);
1142 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1144 static void sdma_add_scripts(struct sdma_engine *sdma,
1145 const struct sdma_script_start_addrs *addr)
1147 s32 *addr_arr = (u32 *)addr;
1148 s32 *saddr_arr = (u32 *)sdma->script_addrs;
1151 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1152 if (addr_arr[i] > 0)
1153 saddr_arr[i] = addr_arr[i];
1156 static void sdma_load_firmware(const struct firmware *fw, void *context)
1158 struct sdma_engine *sdma = context;
1159 const struct sdma_firmware_header *header;
1160 const struct sdma_script_start_addrs *addr;
1161 unsigned short *ram_code;
1164 dev_err(sdma->dev, "firmware not found\n");
1168 if (fw->size < sizeof(*header))
1171 header = (struct sdma_firmware_header *)fw->data;
1173 if (header->magic != SDMA_FIRMWARE_MAGIC)
1175 if (header->ram_code_start + header->ram_code_size > fw->size)
1178 addr = (void *)header + header->script_addrs_start;
1179 ram_code = (void *)header + header->ram_code_start;
1181 clk_enable(sdma->clk);
1182 /* download the RAM image for SDMA */
1183 sdma_load_script(sdma, ram_code,
1184 header->ram_code_size,
1185 addr->ram_code_start_addr);
1186 clk_disable(sdma->clk);
1188 sdma_add_scripts(sdma, addr);
1190 dev_info(sdma->dev, "loaded firmware %d.%d\n",
1191 header->version_major,
1192 header->version_minor);
1195 release_firmware(fw);
1198 static int __init sdma_get_firmware(struct sdma_engine *sdma,
1199 const char *fw_name)
1203 ret = request_firmware_nowait(THIS_MODULE,
1204 FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1205 GFP_KERNEL, sdma, sdma_load_firmware);
1210 static int __init sdma_init(struct sdma_engine *sdma)
1213 dma_addr_t ccb_phys;
1215 switch (sdma->devtype) {
1217 sdma->num_events = 32;
1220 sdma->num_events = 48;
1223 dev_err(sdma->dev, "Unknown sdma type %d. aborting\n",
1228 clk_enable(sdma->clk);
1230 /* Be sure SDMA has not started yet */
1231 __raw_writel(0, sdma->regs + SDMA_H_C0PTR);
1233 sdma->channel_control = dma_alloc_coherent(NULL,
1234 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1235 sizeof(struct sdma_context_data),
1236 &ccb_phys, GFP_KERNEL);
1238 if (!sdma->channel_control) {
1243 sdma->context = (void *)sdma->channel_control +
1244 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1245 sdma->context_phys = ccb_phys +
1246 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1248 /* Zero-out the CCB structures array just allocated */
1249 memset(sdma->channel_control, 0,
1250 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1252 /* disable all channels */
1253 for (i = 0; i < sdma->num_events; i++)
1254 __raw_writel(0, sdma->regs + chnenbl_ofs(sdma, i));
1256 /* All channels have priority 0 */
1257 for (i = 0; i < MAX_DMA_CHANNELS; i++)
1258 __raw_writel(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1260 ret = sdma_request_channel(&sdma->channel[0]);
1264 sdma_config_ownership(&sdma->channel[0], false, true, false);
1266 /* Set Command Channel (Channel Zero) */
1267 __raw_writel(0x4050, sdma->regs + SDMA_CHN0ADDR);
1269 /* Set bits of CONFIG register but with static context switching */
1270 /* FIXME: Check whether to set ACR bit depending on clock ratios */
1271 __raw_writel(0, sdma->regs + SDMA_H_CONFIG);
1273 __raw_writel(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1275 /* Set bits of CONFIG register with given context switching mode */
1276 __raw_writel(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
1278 /* Initializes channel's priorities */
1279 sdma_set_channel_priority(&sdma->channel[0], 7);
1281 clk_disable(sdma->clk);
1286 clk_disable(sdma->clk);
1287 dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1291 static int __init sdma_probe(struct platform_device *pdev)
1293 const struct of_device_id *of_id =
1294 of_match_device(sdma_dt_ids, &pdev->dev);
1295 struct device_node *np = pdev->dev.of_node;
1296 const char *fw_name;
1299 struct resource *iores;
1300 struct sdma_platform_data *pdata = pdev->dev.platform_data;
1302 struct sdma_engine *sdma;
1305 sdma = kzalloc(sizeof(*sdma), GFP_KERNEL);
1309 mutex_init(&sdma->channel_0_lock);
1311 sdma->dev = &pdev->dev;
1313 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1314 irq = platform_get_irq(pdev, 0);
1315 if (!iores || irq < 0) {
1320 if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) {
1322 goto err_request_region;
1325 sdma->clk = clk_get(&pdev->dev, NULL);
1326 if (IS_ERR(sdma->clk)) {
1327 ret = PTR_ERR(sdma->clk);
1331 sdma->regs = ioremap(iores->start, resource_size(iores));
1337 ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma);
1339 goto err_request_irq;
1341 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1342 if (!sdma->script_addrs) {
1347 /* initially no scripts available */
1348 saddr_arr = (s32 *)sdma->script_addrs;
1349 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1350 saddr_arr[i] = -EINVAL;
1353 pdev->id_entry = of_id->data;
1354 sdma->devtype = pdev->id_entry->driver_data;
1356 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1357 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1359 INIT_LIST_HEAD(&sdma->dma_device.channels);
1360 /* Initialize channel parameters */
1361 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1362 struct sdma_channel *sdmac = &sdma->channel[i];
1365 spin_lock_init(&sdmac->lock);
1367 sdmac->chan.device = &sdma->dma_device;
1371 * Add the channel to the DMAC list. Do not add channel 0 though
1372 * because we need it internally in the SDMA driver. This also means
1373 * that channel 0 in dmaengine counting matches sdma channel 1.
1376 list_add_tail(&sdmac->chan.device_node,
1377 &sdma->dma_device.channels);
1380 ret = sdma_init(sdma);
1384 if (pdata && pdata->script_addrs)
1385 sdma_add_scripts(sdma, pdata->script_addrs);
1388 sdma_get_firmware(sdma, pdata->fw_name);
1391 * Because that device tree does not encode ROM script address,
1392 * the RAM script in firmware is mandatory for device tree
1393 * probe, otherwise it fails.
1395 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1398 dev_err(&pdev->dev, "failed to get firmware name\n");
1402 ret = sdma_get_firmware(sdma, fw_name);
1404 dev_err(&pdev->dev, "failed to get firmware\n");
1409 sdma->dma_device.dev = &pdev->dev;
1411 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1412 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1413 sdma->dma_device.device_tx_status = sdma_tx_status;
1414 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1415 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1416 sdma->dma_device.device_control = sdma_control;
1417 sdma->dma_device.device_issue_pending = sdma_issue_pending;
1418 sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1419 dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1421 ret = dma_async_device_register(&sdma->dma_device);
1423 dev_err(&pdev->dev, "unable to register\n");
1427 dev_info(sdma->dev, "initialized\n");
1432 kfree(sdma->script_addrs);
1434 free_irq(irq, sdma);
1436 iounmap(sdma->regs);
1440 release_mem_region(iores->start, resource_size(iores));
1447 static int __exit sdma_remove(struct platform_device *pdev)
1452 static struct platform_driver sdma_driver = {
1455 .of_match_table = sdma_dt_ids,
1457 .id_table = sdma_devtypes,
1458 .remove = __exit_p(sdma_remove),
1461 static int __init sdma_module_init(void)
1463 return platform_driver_probe(&sdma_driver, sdma_probe);
1465 module_init(sdma_module_init);
1467 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1468 MODULE_DESCRIPTION("i.MX SDMA driver");
1469 MODULE_LICENSE("GPL");