drivers/dma/imx-sdma.c

   1 /*
   2  * drivers/dma/imx-sdma.c
   3  *
   4  * This file contains a driver for the Freescale Smart DMA engine
   5  *
   6  * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   7  *
   8  * Based on code from Freescale:
   9  *
  10  * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  11  *
  12  * The code contained herein is licensed under the GNU General Public
  13  * License. You may obtain a copy of the GNU General Public License
  14  * Version 2 or later at the following locations:
  15  *
  16  * http://www.opensource.org/licenses/gpl-license.html
  17  * http://www.gnu.org/copyleft/gpl.html
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/module.h>
  22 #include <linux/types.h>
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/clk.h>
  26 #include <linux/wait.h>
  27 #include <linux/sched.h>
  28 #include <linux/semaphore.h>
  29 #include <linux/spinlock.h>
  30 #include <linux/device.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/firmware.h>
  33 #include <linux/slab.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/dmaengine.h>
  36 #include <linux/of.h>
  37 #include <linux/of_device.h>
  38 #include <linux/module.h>
  39
  40 #include <asm/irq.h>
  41 #include <mach/sdma.h>
  42 #include <mach/dma.h>
  43 #include <mach/hardware.h>
  44
  45 /* SDMA registers */
  46 #define SDMA_H_C0PTR            0x000
  47 #define SDMA_H_INTR             0x004
  48 #define SDMA_H_STATSTOP         0x008
  49 #define SDMA_H_START            0x00c
  50 #define SDMA_H_EVTOVR           0x010
  51 #define SDMA_H_DSPOVR           0x014
  52 #define SDMA_H_HOSTOVR          0x018
  53 #define SDMA_H_EVTPEND          0x01c
  54 #define SDMA_H_DSPENBL          0x020
  55 #define SDMA_H_RESET            0x024
  56 #define SDMA_H_EVTERR           0x028
  57 #define SDMA_H_INTRMSK          0x02c
  58 #define SDMA_H_PSW              0x030
  59 #define SDMA_H_EVTERRDBG        0x034
  60 #define SDMA_H_CONFIG           0x038
  61 #define SDMA_ONCE_ENB           0x040
  62 #define SDMA_ONCE_DATA          0x044
  63 #define SDMA_ONCE_INSTR         0x048
  64 #define SDMA_ONCE_STAT          0x04c
  65 #define SDMA_ONCE_CMD           0x050
  66 #define SDMA_EVT_MIRROR         0x054
  67 #define SDMA_ILLINSTADDR        0x058
  68 #define SDMA_CHN0ADDR           0x05c
  69 #define SDMA_ONCE_RTB           0x060
  70 #define SDMA_XTRIG_CONF1        0x070
  71 #define SDMA_XTRIG_CONF2        0x074
  72 #define SDMA_CHNENBL0_IMX35     0x200
  73 #define SDMA_CHNENBL0_IMX31     0x080
  74 #define SDMA_CHNPRI_0           0x100
  75
  76 /*
  77  * Buffer descriptor status values.
  78  */
  79 #define BD_DONE  0x01
  80 #define BD_WRAP  0x02
  81 #define BD_CONT  0x04
  82 #define BD_INTR  0x08
  83 #define BD_RROR  0x10
  84 #define BD_LAST  0x20
  85 #define BD_EXTD  0x80
  86
  87 /*
  88  * Data Node descriptor status values.
  89  */
  90 #define DND_END_OF_FRAME  0x80
  91 #define DND_END_OF_XFER   0x40
  92 #define DND_DONE          0x20
  93 #define DND_UNUSED        0x01
  94
  95 /*
  96  * IPCV2 descriptor status values.
  97  */
  98 #define BD_IPCV2_END_OF_FRAME  0x40
  99
 100 #define IPCV2_MAX_NODES        50
 101 /*
 102  * Error bit set in the CCB status field by the SDMA,
 103  * in setbd routine, in case of a transfer error
 104  */
 105 #define DATA_ERROR  0x10000000
 106
 107 /*
 108  * Buffer descriptor commands.
 109  */
 110 #define C0_ADDR             0x01
 111 #define C0_LOAD             0x02
 112 #define C0_DUMP             0x03
 113 #define C0_SETCTX           0x07
 114 #define C0_GETCTX           0x03
 115 #define C0_SETDM            0x01
 116 #define C0_SETPM            0x04
 117 #define C0_GETDM            0x02
 118 #define C0_GETPM            0x08
 119 /*
 120  * Change endianness indicator in the BD command field
 121  */
 122 #define CHANGE_ENDIANNESS   0x80
 123
 124 /*
 125  * Mode/Count of data node descriptors - IPCv2
 126  */
 127 struct sdma_mode_count {
 128         u32 count   : 16; /* size of the buffer pointed by this BD */
 129         u32 status  :  8; /* E,R,I,C,W,D status bits stored here */
 130         u32 command :  8; /* command mostlky used for channel 0 */
 131 };
 132
 133 /*
 134  * Buffer descriptor
 135  */
 136 struct sdma_buffer_descriptor {
 137         struct sdma_mode_count  mode;
 138         u32 buffer_addr;        /* address of the buffer described */
 139         u32 ext_buffer_addr;    /* extended buffer address */
 140 } __attribute__ ((packed));
 141
 142 /**
 143  * struct sdma_channel_control - Channel control Block
 144  *
 145  * @current_bd_ptr      current buffer descriptor processed
 146  * @base_bd_ptr         first element of buffer descriptor array
 147  * @unused              padding. The SDMA engine expects an array of 128 byte
 148  *                      control blocks
 149  */
 150 struct sdma_channel_control {
 151         u32 current_bd_ptr;
 152         u32 base_bd_ptr;
 153         u32 unused[2];
 154 } __attribute__ ((packed));
 155
 156 /**
 157  * struct sdma_state_registers - SDMA context for a channel
 158  *
 159  * @pc:         program counter
 160  * @t:          test bit: status of arithmetic & test instruction
 161  * @rpc:        return program counter
 162  * @sf:         source fault while loading data
 163  * @spc:        loop start program counter
 164  * @df:         destination fault while storing data
 165  * @epc:        loop end program counter
 166  * @lm:         loop mode
 167  */
 168 struct sdma_state_registers {
 169         u32 pc     :14;
 170         u32 unused1: 1;
 171         u32 t      : 1;
 172         u32 rpc    :14;
 173         u32 unused0: 1;
 174         u32 sf     : 1;
 175         u32 spc    :14;
 176         u32 unused2: 1;
 177         u32 df     : 1;
 178         u32 epc    :14;
 179         u32 lm     : 2;
 180 } __attribute__ ((packed));
 181
 182 /**
 183  * struct sdma_context_data - sdma context specific to a channel
 184  *
 185  * @channel_state:      channel state bits
 186  * @gReg:               general registers
 187  * @mda:                burst dma destination address register
 188  * @msa:                burst dma source address register
 189  * @ms:                 burst dma status register
 190  * @md:                 burst dma data register
 191  * @pda:                peripheral dma destination address register
 192  * @psa:                peripheral dma source address register
 193  * @ps:                 peripheral dma status register
 194  * @pd:                 peripheral dma data register
 195  * @ca:                 CRC polynomial register
 196  * @cs:                 CRC accumulator register
 197  * @dda:                dedicated core destination address register
 198  * @dsa:                dedicated core source address register
 199  * @ds:                 dedicated core status register
 200  * @dd:                 dedicated core data register
 201  */
 202 struct sdma_context_data {
 203         struct sdma_state_registers  channel_state;
 204         u32  gReg[8];
 205         u32  mda;
 206         u32  msa;
 207         u32  ms;
 208         u32  md;
 209         u32  pda;
 210         u32  psa;
 211         u32  ps;
 212         u32  pd;
 213         u32  ca;
 214         u32  cs;
 215         u32  dda;
 216         u32  dsa;
 217         u32  ds;
 218         u32  dd;
 219         u32  scratch0;
 220         u32  scratch1;
 221         u32  scratch2;
 222         u32  scratch3;
 223         u32  scratch4;
 224         u32  scratch5;
 225         u32  scratch6;
 226         u32  scratch7;
 227 } __attribute__ ((packed));
 228
 229 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
 230
 231 struct sdma_engine;
 232
 233 /**
 234  * struct sdma_channel - housekeeping for a SDMA channel
 235  *
 236  * @sdma                pointer to the SDMA engine for this channel
 237  * @channel             the channel number, matches dmaengine chan_id + 1
 238  * @direction           transfer type. Needed for setting SDMA script
 239  * @peripheral_type     Peripheral type. Needed for setting SDMA script
 240  * @event_id0           aka dma request line
 241  * @event_id1           for channels that use 2 events
 242  * @word_size           peripheral access size
 243  * @buf_tail            ID of the buffer that was processed
 244  * @done                channel completion
 245  * @num_bd              max NUM_BD. number of descriptors currently handling
 246  */
 247 struct sdma_channel {
 248         struct sdma_engine              *sdma;
 249         unsigned int                    channel;
 250         enum dma_transfer_direction             direction;
 251         enum sdma_peripheral_type       peripheral_type;
 252         unsigned int                    event_id0;
 253         unsigned int                    event_id1;
 254         enum dma_slave_buswidth         word_size;
 255         unsigned int                    buf_tail;
 256         struct completion               done;
 257         unsigned int                    num_bd;
 258         struct sdma_buffer_descriptor   *bd;
 259         dma_addr_t                      bd_phys;
 260         unsigned int                    pc_from_device, pc_to_device;
 261         unsigned long                   flags;
 262         dma_addr_t                      per_address;
 263         u32                             event_mask0, event_mask1;
 264         u32                             watermark_level;
 265         u32                             shp_addr, per_addr;
 266         struct dma_chan                 chan;
 267         spinlock_t                      lock;
 268         struct dma_async_tx_descriptor  desc;
 269         dma_cookie_t                    last_completed;
 270         enum dma_status                 status;
 271         unsigned int                    chn_count;
 272         unsigned int                    chn_real_count;
 273 };
 274
 275 #define IMX_DMA_SG_LOOP         (1 << 0)
 276
 277 #define MAX_DMA_CHANNELS 32
 278 #define MXC_SDMA_DEFAULT_PRIORITY 1
 279 #define MXC_SDMA_MIN_PRIORITY 1
 280 #define MXC_SDMA_MAX_PRIORITY 7
 281
 282 #define SDMA_FIRMWARE_MAGIC 0x414d4453
 283
 284 /**
 285  * struct sdma_firmware_header - Layout of the firmware image
 286  *
 287  * @magic               "SDMA"
 288  * @version_major       increased whenever layout of struct sdma_script_start_addrs
 289  *                      changes.
 290  * @version_minor       firmware minor version (for binary compatible changes)
 291  * @script_addrs_start  offset of struct sdma_script_start_addrs in this image
 292  * @num_script_addrs    Number of script addresses in this image
 293  * @ram_code_start      offset of SDMA ram image in this firmware image
 294  * @ram_code_size       size of SDMA ram image
 295  * @script_addrs        Stores the start address of the SDMA scripts
 296  *                      (in SDMA memory space)
 297  */
 298 struct sdma_firmware_header {
 299         u32     magic;
 300         u32     version_major;
 301         u32     version_minor;
 302         u32     script_addrs_start;
 303         u32     num_script_addrs;
 304         u32     ram_code_start;
 305         u32     ram_code_size;
 306 };
 307
 308 enum sdma_devtype {
 309         IMX31_SDMA,     /* runs on i.mx31 */
 310         IMX35_SDMA,     /* runs on i.mx35 and later */
 311 };
 312
 313 struct sdma_engine {
 314         struct device                   *dev;
 315         struct device_dma_parameters    dma_parms;
 316         struct sdma_channel             channel[MAX_DMA_CHANNELS];
 317         struct sdma_channel_control     *channel_control;
 318         void __iomem                    *regs;
 319         enum sdma_devtype               devtype;
 320         unsigned int                    num_events;
 321         struct sdma_context_data        *context;
 322         dma_addr_t                      context_phys;
 323         struct dma_device               dma_device;
 324         struct clk                      *clk;
 325         struct mutex                    channel_0_lock;
 326         struct sdma_script_start_addrs  *script_addrs;
 327 };
 328
 329 static struct platform_device_id sdma_devtypes[] = {
 330         {
 331                 .name = "imx31-sdma",
 332                 .driver_data = IMX31_SDMA,
 333         }, {
 334                 .name = "imx35-sdma",
 335                 .driver_data = IMX35_SDMA,
 336         }, {
 337                 /* sentinel */
 338         }
 339 };
 340 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
 341
 342 static const struct of_device_id sdma_dt_ids[] = {
 343         { .compatible = "fsl,imx31-sdma", .data = &sdma_devtypes[IMX31_SDMA], },
 344         { .compatible = "fsl,imx35-sdma", .data = &sdma_devtypes[IMX35_SDMA], },
 345         { /* sentinel */ }
 346 };
 347 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
 348
 349 #define SDMA_H_CONFIG_DSPDMA    (1 << 12) /* indicates if the DSPDMA is used */
 350 #define SDMA_H_CONFIG_RTD_PINS  (1 << 11) /* indicates if Real-Time Debug pins are enabled */
 351 #define SDMA_H_CONFIG_ACR       (1 << 4)  /* indicates if AHB freq /core freq = 2 or 1 */
 352 #define SDMA_H_CONFIG_CSM       (3)       /* indicates which context switch mode is selected*/
 353
 354 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
 355 {
 356         u32 chnenbl0 = (sdma->devtype == IMX31_SDMA ? SDMA_CHNENBL0_IMX31 :
 357                                                       SDMA_CHNENBL0_IMX35);
 358         return chnenbl0 + event * 4;
 359 }
 360
 361 static int sdma_config_ownership(struct sdma_channel *sdmac,
 362                 bool event_override, bool mcu_override, bool dsp_override)
 363 {
 364         struct sdma_engine *sdma = sdmac->sdma;
 365         int channel = sdmac->channel;
 366         u32 evt, mcu, dsp;
 367
 368         if (event_override && mcu_override && dsp_override)
 369                 return -EINVAL;
 370
 371         evt = __raw_readl(sdma->regs + SDMA_H_EVTOVR);
 372         mcu = __raw_readl(sdma->regs + SDMA_H_HOSTOVR);
 373         dsp = __raw_readl(sdma->regs + SDMA_H_DSPOVR);
 374
 375         if (dsp_override)
 376                 dsp &= ~(1 << channel);
 377         else
 378                 dsp |= (1 << channel);
 379
 380         if (event_override)
 381                 evt &= ~(1 << channel);
 382         else
 383                 evt |= (1 << channel);
 384
 385         if (mcu_override)
 386                 mcu &= ~(1 << channel);
 387         else
 388                 mcu |= (1 << channel);
 389
 390         __raw_writel(evt, sdma->regs + SDMA_H_EVTOVR);
 391         __raw_writel(mcu, sdma->regs + SDMA_H_HOSTOVR);
 392         __raw_writel(dsp, sdma->regs + SDMA_H_DSPOVR);
 393
 394         return 0;
 395 }
 396
 397 /*
 398  * sdma_run_channel - run a channel and wait till it's done
 399  */
 400 static int sdma_run_channel(struct sdma_channel *sdmac)
 401 {
 402         struct sdma_engine *sdma = sdmac->sdma;
 403         int channel = sdmac->channel;
 404         int ret;
 405
 406         init_completion(&sdmac->done);
 407
 408         __raw_writel(1 << channel, sdma->regs + SDMA_H_START);
 409
 410         ret = wait_for_completion_timeout(&sdmac->done, HZ);
 411
 412         return ret ? 0 : -ETIMEDOUT;
 413 }
 414
 415 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
 416                 u32 address)
 417 {
 418         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
 419         void *buf_virt;
 420         dma_addr_t buf_phys;
 421         int ret;
 422
 423         mutex_lock(&sdma->channel_0_lock);
 424
 425         buf_virt = dma_alloc_coherent(NULL,
 426                         size,
 427                         &buf_phys, GFP_KERNEL);
 428         if (!buf_virt) {
 429                 ret = -ENOMEM;
 430                 goto err_out;
 431         }
 432
 433         bd0->mode.command = C0_SETPM;
 434         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 435         bd0->mode.count = size / 2;
 436         bd0->buffer_addr = buf_phys;
 437         bd0->ext_buffer_addr = address;
 438
 439         memcpy(buf_virt, buf, size);
 440
 441         ret = sdma_run_channel(&sdma->channel[0]);
 442
 443         dma_free_coherent(NULL, size, buf_virt, buf_phys);
 444
 445 err_out:
 446         mutex_unlock(&sdma->channel_0_lock);
 447
 448         return ret;
 449 }
 450
 451 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
 452 {
 453         struct sdma_engine *sdma = sdmac->sdma;
 454         int channel = sdmac->channel;
 455         u32 val;
 456         u32 chnenbl = chnenbl_ofs(sdma, event);
 457
 458         val = __raw_readl(sdma->regs + chnenbl);
 459         val |= (1 << channel);
 460         __raw_writel(val, sdma->regs + chnenbl);
 461 }
 462
 463 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
 464 {
 465         struct sdma_engine *sdma = sdmac->sdma;
 466         int channel = sdmac->channel;
 467         u32 chnenbl = chnenbl_ofs(sdma, event);
 468         u32 val;
 469
 470         val = __raw_readl(sdma->regs + chnenbl);
 471         val &= ~(1 << channel);
 472         __raw_writel(val, sdma->regs + chnenbl);
 473 }
 474
 475 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
 476 {
 477         struct sdma_buffer_descriptor *bd;
 478
 479         /*
 480          * loop mode. Iterate over descriptors, re-setup them and
 481          * call callback function.
 482          */
 483         while (1) {
 484                 bd = &sdmac->bd[sdmac->buf_tail];
 485
 486                 if (bd->mode.status & BD_DONE)
 487                         break;
 488
 489                 if (bd->mode.status & BD_RROR)
 490                         sdmac->status = DMA_ERROR;
 491                 else
 492                         sdmac->status = DMA_IN_PROGRESS;
 493
 494                 bd->mode.status |= BD_DONE;
 495                 sdmac->buf_tail++;
 496                 sdmac->buf_tail %= sdmac->num_bd;
 497
 498                 if (sdmac->desc.callback)
 499                         sdmac->desc.callback(sdmac->desc.callback_param);
 500         }
 501 }
 502
 503 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
 504 {
 505         struct sdma_buffer_descriptor *bd;
 506         int i, error = 0;
 507
 508         sdmac->chn_real_count = 0;
 509         /*
 510          * non loop mode. Iterate over all descriptors, collect
 511          * errors and call callback function
 512          */
 513         for (i = 0; i < sdmac->num_bd; i++) {
 514                 bd = &sdmac->bd[i];
 515
 516                  if (bd->mode.status & (BD_DONE | BD_RROR))
 517                         error = -EIO;
 518                  sdmac->chn_real_count += bd->mode.count;
 519         }
 520
 521         if (error)
 522                 sdmac->status = DMA_ERROR;
 523         else
 524                 sdmac->status = DMA_SUCCESS;
 525
 526         sdmac->last_completed = sdmac->desc.cookie;
 527         if (sdmac->desc.callback)
 528                 sdmac->desc.callback(sdmac->desc.callback_param);
 529 }
 530
 531 static void mxc_sdma_handle_channel(struct sdma_channel *sdmac)
 532 {
 533         complete(&sdmac->done);
 534
 535         /* not interested in channel 0 interrupts */
 536         if (sdmac->channel == 0)
 537                 return;
 538
 539         if (sdmac->flags & IMX_DMA_SG_LOOP)
 540                 sdma_handle_channel_loop(sdmac);
 541         else
 542                 mxc_sdma_handle_channel_normal(sdmac);
 543 }
 544
 545 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
 546 {
 547         struct sdma_engine *sdma = dev_id;
 548         u32 stat;
 549
 550         stat = __raw_readl(sdma->regs + SDMA_H_INTR);
 551         __raw_writel(stat, sdma->regs + SDMA_H_INTR);
 552
 553         while (stat) {
 554                 int channel = fls(stat) - 1;
 555                 struct sdma_channel *sdmac = &sdma->channel[channel];
 556
 557                 mxc_sdma_handle_channel(sdmac);
 558
 559                 stat &= ~(1 << channel);
 560         }
 561
 562         return IRQ_HANDLED;
 563 }
 564
 565 /*
 566  * sets the pc of SDMA script according to the peripheral type
 567  */
 568 static void sdma_get_pc(struct sdma_channel *sdmac,
 569                 enum sdma_peripheral_type peripheral_type)
 570 {
 571         struct sdma_engine *sdma = sdmac->sdma;
 572         int per_2_emi = 0, emi_2_per = 0;
 573         /*
 574          * These are needed once we start to support transfers between
 575          * two peripherals or memory-to-memory transfers
 576          */
 577         int per_2_per = 0, emi_2_emi = 0;
 578
 579         sdmac->pc_from_device = 0;
 580         sdmac->pc_to_device = 0;
 581
 582         switch (peripheral_type) {
 583         case IMX_DMATYPE_MEMORY:
 584                 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
 585                 break;
 586         case IMX_DMATYPE_DSP:
 587                 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
 588                 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
 589                 break;
 590         case IMX_DMATYPE_FIRI:
 591                 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
 592                 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
 593                 break;
 594         case IMX_DMATYPE_UART:
 595                 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
 596                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 597                 break;
 598         case IMX_DMATYPE_UART_SP:
 599                 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
 600                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 601                 break;
 602         case IMX_DMATYPE_ATA:
 603                 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
 604                 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
 605                 break;
 606         case IMX_DMATYPE_CSPI:
 607         case IMX_DMATYPE_EXT:
 608         case IMX_DMATYPE_SSI:
 609                 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
 610                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 611                 break;
 612         case IMX_DMATYPE_SSI_SP:
 613         case IMX_DMATYPE_MMC:
 614         case IMX_DMATYPE_SDHC:
 615         case IMX_DMATYPE_CSPI_SP:
 616         case IMX_DMATYPE_ESAI:
 617         case IMX_DMATYPE_MSHC_SP:
 618                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 619                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 620                 break;
 621         case IMX_DMATYPE_ASRC:
 622                 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
 623                 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
 624                 per_2_per = sdma->script_addrs->per_2_per_addr;
 625                 break;
 626         case IMX_DMATYPE_MSHC:
 627                 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
 628                 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
 629                 break;
 630         case IMX_DMATYPE_CCM:
 631                 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
 632                 break;
 633         case IMX_DMATYPE_SPDIF:
 634                 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
 635                 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
 636                 break;
 637         case IMX_DMATYPE_IPU_MEMORY:
 638                 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
 639                 break;
 640         default:
 641                 break;
 642         }
 643
 644         sdmac->pc_from_device = per_2_emi;
 645         sdmac->pc_to_device = emi_2_per;
 646 }
 647
 648 static int sdma_load_context(struct sdma_channel *sdmac)
 649 {
 650         struct sdma_engine *sdma = sdmac->sdma;
 651         int channel = sdmac->channel;
 652         int load_address;
 653         struct sdma_context_data *context = sdma->context;
 654         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
 655         int ret;
 656
 657         if (sdmac->direction == DMA_DEV_TO_MEM) {
 658                 load_address = sdmac->pc_from_device;
 659         } else {
 660                 load_address = sdmac->pc_to_device;
 661         }
 662
 663         if (load_address < 0)
 664                 return load_address;
 665
 666         dev_dbg(sdma->dev, "load_address = %d\n", load_address);
 667         dev_dbg(sdma->dev, "wml = 0x%08x\n", sdmac->watermark_level);
 668         dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
 669         dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
 670         dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", sdmac->event_mask0);
 671         dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", sdmac->event_mask1);
 672
 673         mutex_lock(&sdma->channel_0_lock);
 674
 675         memset(context, 0, sizeof(*context));
 676         context->channel_state.pc = load_address;
 677
 678         /* Send by context the event mask,base address for peripheral
 679          * and watermark level
 680          */
 681         context->gReg[0] = sdmac->event_mask1;
 682         context->gReg[1] = sdmac->event_mask0;
 683         context->gReg[2] = sdmac->per_addr;
 684         context->gReg[6] = sdmac->shp_addr;
 685         context->gReg[7] = sdmac->watermark_level;
 686
 687         bd0->mode.command = C0_SETDM;
 688         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 689         bd0->mode.count = sizeof(*context) / 4;
 690         bd0->buffer_addr = sdma->context_phys;
 691         bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
 692
 693         ret = sdma_run_channel(&sdma->channel[0]);
 694
 695         mutex_unlock(&sdma->channel_0_lock);
 696
 697         return ret;
 698 }
 699
 700 static void sdma_disable_channel(struct sdma_channel *sdmac)
 701 {
 702         struct sdma_engine *sdma = sdmac->sdma;
 703         int channel = sdmac->channel;
 704
 705         __raw_writel(1 << channel, sdma->regs + SDMA_H_STATSTOP);
 706         sdmac->status = DMA_ERROR;
 707 }
 708
 709 static int sdma_config_channel(struct sdma_channel *sdmac)
 710 {
 711         int ret;
 712
 713         sdma_disable_channel(sdmac);
 714
 715         sdmac->event_mask0 = 0;
 716         sdmac->event_mask1 = 0;
 717         sdmac->shp_addr = 0;
 718         sdmac->per_addr = 0;
 719
 720         if (sdmac->event_id0) {
 721                 if (sdmac->event_id0 > 32)
 722                         return -EINVAL;
 723                 sdma_event_enable(sdmac, sdmac->event_id0);
 724         }
 725
 726         switch (sdmac->peripheral_type) {
 727         case IMX_DMATYPE_DSP:
 728                 sdma_config_ownership(sdmac, false, true, true);
 729                 break;
 730         case IMX_DMATYPE_MEMORY:
 731                 sdma_config_ownership(sdmac, false, true, false);
 732                 break;
 733         default:
 734                 sdma_config_ownership(sdmac, true, true, false);
 735                 break;
 736         }
 737
 738         sdma_get_pc(sdmac, sdmac->peripheral_type);
 739
 740         if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
 741                         (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
 742                 /* Handle multiple event channels differently */
 743                 if (sdmac->event_id1) {
 744                         sdmac->event_mask1 = 1 << (sdmac->event_id1 % 32);
 745                         if (sdmac->event_id1 > 31)
 746                                 sdmac->watermark_level |= 1 << 31;
 747                         sdmac->event_mask0 = 1 << (sdmac->event_id0 % 32);
 748                         if (sdmac->event_id0 > 31)
 749                                 sdmac->watermark_level |= 1 << 30;
 750                 } else {
 751                         sdmac->event_mask0 = 1 << sdmac->event_id0;
 752                         sdmac->event_mask1 = 1 << (sdmac->event_id0 - 32);
 753                 }
 754                 /* Watermark Level */
 755                 sdmac->watermark_level |= sdmac->watermark_level;
 756                 /* Address */
 757                 sdmac->shp_addr = sdmac->per_address;
 758         } else {
 759                 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
 760         }
 761
 762         ret = sdma_load_context(sdmac);
 763
 764         return ret;
 765 }
 766
 767 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
 768                 unsigned int priority)
 769 {
 770         struct sdma_engine *sdma = sdmac->sdma;
 771         int channel = sdmac->channel;
 772
 773         if (priority < MXC_SDMA_MIN_PRIORITY
 774             || priority > MXC_SDMA_MAX_PRIORITY) {
 775                 return -EINVAL;
 776         }
 777
 778         __raw_writel(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
 779
 780         return 0;
 781 }
 782
 783 static int sdma_request_channel(struct sdma_channel *sdmac)
 784 {
 785         struct sdma_engine *sdma = sdmac->sdma;
 786         int channel = sdmac->channel;
 787         int ret = -EBUSY;
 788
 789         sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL);
 790         if (!sdmac->bd) {
 791                 ret = -ENOMEM;
 792                 goto out;
 793         }
 794
 795         memset(sdmac->bd, 0, PAGE_SIZE);
 796
 797         sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
 798         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
 799
 800         clk_enable(sdma->clk);
 801
 802         sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
 803
 804         init_completion(&sdmac->done);
 805
 806         sdmac->buf_tail = 0;
 807
 808         return 0;
 809 out:
 810
 811         return ret;
 812 }
 813
 814 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
 815 {
 816         __raw_writel(1 << channel, sdma->regs + SDMA_H_START);
 817 }
 818
 819 static dma_cookie_t sdma_assign_cookie(struct sdma_channel *sdmac)
 820 {
 821         dma_cookie_t cookie = sdmac->chan.cookie;
 822
 823         if (++cookie < 0)
 824                 cookie = 1;
 825
 826         sdmac->chan.cookie = cookie;
 827         sdmac->desc.cookie = cookie;
 828
 829         return cookie;
 830 }
 831
 832 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
 833 {
 834         return container_of(chan, struct sdma_channel, chan);
 835 }
 836
 837 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
 838 {
 839         unsigned long flags;
 840         struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
 841         struct sdma_engine *sdma = sdmac->sdma;
 842         dma_cookie_t cookie;
 843
 844         spin_lock_irqsave(&sdmac->lock, flags);
 845
 846         cookie = sdma_assign_cookie(sdmac);
 847
 848         sdma_enable_channel(sdma, sdmac->channel);
 849
 850         spin_unlock_irqrestore(&sdmac->lock, flags);
 851
 852         return cookie;
 853 }
 854
 855 static int sdma_alloc_chan_resources(struct dma_chan *chan)
 856 {
 857         struct sdma_channel *sdmac = to_sdma_chan(chan);
 858         struct imx_dma_data *data = chan->private;
 859         int prio, ret;
 860
 861         if (!data)
 862                 return -EINVAL;
 863
 864         switch (data->priority) {
 865         case DMA_PRIO_HIGH:
 866                 prio = 3;
 867                 break;
 868         case DMA_PRIO_MEDIUM:
 869                 prio = 2;
 870                 break;
 871         case DMA_PRIO_LOW:
 872         default:
 873                 prio = 1;
 874                 break;
 875         }
 876
 877         sdmac->peripheral_type = data->peripheral_type;
 878         sdmac->event_id0 = data->dma_request;
 879         ret = sdma_set_channel_priority(sdmac, prio);
 880         if (ret)
 881                 return ret;
 882
 883         ret = sdma_request_channel(sdmac);
 884         if (ret)
 885                 return ret;
 886
 887         dma_async_tx_descriptor_init(&sdmac->desc, chan);
 888         sdmac->desc.tx_submit = sdma_tx_submit;
 889         /* txd.flags will be overwritten in prep funcs */
 890         sdmac->desc.flags = DMA_CTRL_ACK;
 891
 892         return 0;
 893 }
 894
 895 static void sdma_free_chan_resources(struct dma_chan *chan)
 896 {
 897         struct sdma_channel *sdmac = to_sdma_chan(chan);
 898         struct sdma_engine *sdma = sdmac->sdma;
 899
 900         sdma_disable_channel(sdmac);
 901
 902         if (sdmac->event_id0)
 903                 sdma_event_disable(sdmac, sdmac->event_id0);
 904         if (sdmac->event_id1)
 905                 sdma_event_disable(sdmac, sdmac->event_id1);
 906
 907         sdmac->event_id0 = 0;
 908         sdmac->event_id1 = 0;
 909
 910         sdma_set_channel_priority(sdmac, 0);
 911
 912         dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
 913
 914         clk_disable(sdma->clk);
 915 }
 916
 917 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
 918                 struct dma_chan *chan, struct scatterlist *sgl,
 919                 unsigned int sg_len, enum dma_transfer_direction direction,
 920                 unsigned long flags)
 921 {
 922         struct sdma_channel *sdmac = to_sdma_chan(chan);
 923         struct sdma_engine *sdma = sdmac->sdma;
 924         int ret, i, count;
 925         int channel = sdmac->channel;
 926         struct scatterlist *sg;
 927
 928         if (sdmac->status == DMA_IN_PROGRESS)
 929                 return NULL;
 930         sdmac->status = DMA_IN_PROGRESS;
 931
 932         sdmac->flags = 0;
 933
 934         dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
 935                         sg_len, channel);
 936
 937         sdmac->direction = direction;
 938         ret = sdma_load_context(sdmac);
 939         if (ret)
 940                 goto err_out;
 941
 942         if (sg_len > NUM_BD) {
 943                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
 944                                 channel, sg_len, NUM_BD);
 945                 ret = -EINVAL;
 946                 goto err_out;
 947         }
 948
 949         sdmac->chn_count = 0;
 950         for_each_sg(sgl, sg, sg_len, i) {
 951                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
 952                 int param;
 953
 954                 bd->buffer_addr = sg->dma_address;
 955
 956                 count = sg->length;
 957
 958                 if (count > 0xffff) {
 959                         dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
 960                                         channel, count, 0xffff);
 961                         ret = -EINVAL;
 962                         goto err_out;
 963                 }
 964
 965                 bd->mode.count = count;
 966                 sdmac->chn_count += count;
 967
 968                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
 969                         ret =  -EINVAL;
 970                         goto err_out;
 971                 }
 972
 973                 switch (sdmac->word_size) {
 974                 case DMA_SLAVE_BUSWIDTH_4_BYTES:
 975                         bd->mode.command = 0;
 976                         if (count & 3 || sg->dma_address & 3)
 977                                 return NULL;
 978                         break;
 979                 case DMA_SLAVE_BUSWIDTH_2_BYTES:
 980                         bd->mode.command = 2;
 981                         if (count & 1 || sg->dma_address & 1)
 982                                 return NULL;
 983                         break;
 984                 case DMA_SLAVE_BUSWIDTH_1_BYTE:
 985                         bd->mode.command = 1;
 986                         break;
 987                 default:
 988                         return NULL;
 989                 }
 990
 991                 param = BD_DONE | BD_EXTD | BD_CONT;
 992
 993                 if (i + 1 == sg_len) {
 994                         param |= BD_INTR;
 995                         param |= BD_LAST;
 996                         param &= ~BD_CONT;
 997                 }
 998
 999                 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
1000                                 i, count, sg->dma_address,
1001                                 param & BD_WRAP ? "wrap" : "",
1002                                 param & BD_INTR ? " intr" : "");
1003
1004                 bd->mode.status = param;
1005         }
1006
1007         sdmac->num_bd = sg_len;
1008         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1009
1010         return &sdmac->desc;
1011 err_out:
1012         sdmac->status = DMA_ERROR;
1013         return NULL;
1014 }
1015
1016 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1017                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1018                 size_t period_len, enum dma_transfer_direction direction)
1019 {
1020         struct sdma_channel *sdmac = to_sdma_chan(chan);
1021         struct sdma_engine *sdma = sdmac->sdma;
1022         int num_periods = buf_len / period_len;
1023         int channel = sdmac->channel;
1024         int ret, i = 0, buf = 0;
1025
1026         dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1027
1028         if (sdmac->status == DMA_IN_PROGRESS)
1029                 return NULL;
1030
1031         sdmac->status = DMA_IN_PROGRESS;
1032
1033         sdmac->flags |= IMX_DMA_SG_LOOP;
1034         sdmac->direction = direction;
1035         ret = sdma_load_context(sdmac);
1036         if (ret)
1037                 goto err_out;
1038
1039         if (num_periods > NUM_BD) {
1040                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1041                                 channel, num_periods, NUM_BD);
1042                 goto err_out;
1043         }
1044
1045         if (period_len > 0xffff) {
1046                 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1047                                 channel, period_len, 0xffff);
1048                 goto err_out;
1049         }
1050
1051         while (buf < buf_len) {
1052                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1053                 int param;
1054
1055                 bd->buffer_addr = dma_addr;
1056
1057                 bd->mode.count = period_len;
1058
1059                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1060                         goto err_out;
1061                 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1062                         bd->mode.command = 0;
1063                 else
1064                         bd->mode.command = sdmac->word_size;
1065
1066                 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1067                 if (i + 1 == num_periods)
1068                         param |= BD_WRAP;
1069
1070                 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
1071                                 i, period_len, dma_addr,
1072                                 param & BD_WRAP ? "wrap" : "",
1073                                 param & BD_INTR ? " intr" : "");
1074
1075                 bd->mode.status = param;
1076
1077                 dma_addr += period_len;
1078                 buf += period_len;
1079
1080                 i++;
1081         }
1082
1083         sdmac->num_bd = num_periods;
1084         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1085
1086         return &sdmac->desc;
1087 err_out:
1088         sdmac->status = DMA_ERROR;
1089         return NULL;
1090 }
1091
1092 static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1093                 unsigned long arg)
1094 {
1095         struct sdma_channel *sdmac = to_sdma_chan(chan);
1096         struct dma_slave_config *dmaengine_cfg = (void *)arg;
1097
1098         switch (cmd) {
1099         case DMA_TERMINATE_ALL:
1100                 sdma_disable_channel(sdmac);
1101                 return 0;
1102         case DMA_SLAVE_CONFIG:
1103                 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1104                         sdmac->per_address = dmaengine_cfg->src_addr;
1105                         sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1106                                                 dmaengine_cfg->src_addr_width;
1107                         sdmac->word_size = dmaengine_cfg->src_addr_width;
1108                 } else {
1109                         sdmac->per_address = dmaengine_cfg->dst_addr;
1110                         sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1111                                                 dmaengine_cfg->dst_addr_width;
1112                         sdmac->word_size = dmaengine_cfg->dst_addr_width;
1113                 }
1114                 sdmac->direction = dmaengine_cfg->direction;
1115                 return sdma_config_channel(sdmac);
1116         default:
1117                 return -ENOSYS;
1118         }
1119
1120         return -EINVAL;
1121 }
1122
1123 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1124                                             dma_cookie_t cookie,
1125                                             struct dma_tx_state *txstate)
1126 {
1127         struct sdma_channel *sdmac = to_sdma_chan(chan);
1128         dma_cookie_t last_used;
1129
1130         last_used = chan->cookie;
1131
1132         dma_set_tx_state(txstate, sdmac->last_completed, last_used,
1133                         sdmac->chn_count - sdmac->chn_real_count);
1134
1135         return sdmac->status;
1136 }
1137
1138 static void sdma_issue_pending(struct dma_chan *chan)
1139 {
1140         /*
1141          * Nothing to do. We only have a single descriptor
1142          */
1143 }
1144
1145 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1146
1147 static void sdma_add_scripts(struct sdma_engine *sdma,
1148                 const struct sdma_script_start_addrs *addr)
1149 {
1150         s32 *addr_arr = (u32 *)addr;
1151         s32 *saddr_arr = (u32 *)sdma->script_addrs;
1152         int i;
1153
1154         for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1155                 if (addr_arr[i] > 0)
1156                         saddr_arr[i] = addr_arr[i];
1157 }
1158
1159 static void sdma_load_firmware(const struct firmware *fw, void *context)
1160 {
1161         struct sdma_engine *sdma = context;
1162         const struct sdma_firmware_header *header;
1163         const struct sdma_script_start_addrs *addr;
1164         unsigned short *ram_code;
1165
1166         if (!fw) {
1167                 dev_err(sdma->dev, "firmware not found\n");
1168                 return;
1169         }
1170
1171         if (fw->size < sizeof(*header))
1172                 goto err_firmware;
1173
1174         header = (struct sdma_firmware_header *)fw->data;
1175
1176         if (header->magic != SDMA_FIRMWARE_MAGIC)
1177                 goto err_firmware;
1178         if (header->ram_code_start + header->ram_code_size > fw->size)
1179                 goto err_firmware;
1180
1181         addr = (void *)header + header->script_addrs_start;
1182         ram_code = (void *)header + header->ram_code_start;
1183
1184         clk_enable(sdma->clk);
1185         /* download the RAM image for SDMA */
1186         sdma_load_script(sdma, ram_code,
1187                         header->ram_code_size,
1188                         addr->ram_code_start_addr);
1189         clk_disable(sdma->clk);
1190
1191         sdma_add_scripts(sdma, addr);
1192
1193         dev_info(sdma->dev, "loaded firmware %d.%d\n",
1194                         header->version_major,
1195                         header->version_minor);
1196
1197 err_firmware:
1198         release_firmware(fw);
1199 }
1200
1201 static int __init sdma_get_firmware(struct sdma_engine *sdma,
1202                 const char *fw_name)
1203 {
1204         int ret;
1205
1206         ret = request_firmware_nowait(THIS_MODULE,
1207                         FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1208                         GFP_KERNEL, sdma, sdma_load_firmware);
1209
1210         return ret;
1211 }
1212
1213 static int __init sdma_init(struct sdma_engine *sdma)
1214 {
1215         int i, ret;
1216         dma_addr_t ccb_phys;
1217
1218         switch (sdma->devtype) {
1219         case IMX31_SDMA:
1220                 sdma->num_events = 32;
1221                 break;
1222         case IMX35_SDMA:
1223                 sdma->num_events = 48;
1224                 break;
1225         default:
1226                 dev_err(sdma->dev, "Unknown sdma type %d. aborting\n",
1227                         sdma->devtype);
1228                 return -ENODEV;
1229         }
1230
1231         clk_enable(sdma->clk);
1232
1233         /* Be sure SDMA has not started yet */
1234         __raw_writel(0, sdma->regs + SDMA_H_C0PTR);
1235
1236         sdma->channel_control = dma_alloc_coherent(NULL,
1237                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1238                         sizeof(struct sdma_context_data),
1239                         &ccb_phys, GFP_KERNEL);
1240
1241         if (!sdma->channel_control) {
1242                 ret = -ENOMEM;
1243                 goto err_dma_alloc;
1244         }
1245
1246         sdma->context = (void *)sdma->channel_control +
1247                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1248         sdma->context_phys = ccb_phys +
1249                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1250
1251         /* Zero-out the CCB structures array just allocated */
1252         memset(sdma->channel_control, 0,
1253                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1254
1255         /* disable all channels */
1256         for (i = 0; i < sdma->num_events; i++)
1257                 __raw_writel(0, sdma->regs + chnenbl_ofs(sdma, i));
1258
1259         /* All channels have priority 0 */
1260         for (i = 0; i < MAX_DMA_CHANNELS; i++)
1261                 __raw_writel(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1262
1263         ret = sdma_request_channel(&sdma->channel[0]);
1264         if (ret)
1265                 goto err_dma_alloc;
1266
1267         sdma_config_ownership(&sdma->channel[0], false, true, false);
1268
1269         /* Set Command Channel (Channel Zero) */
1270         __raw_writel(0x4050, sdma->regs + SDMA_CHN0ADDR);
1271
1272         /* Set bits of CONFIG register but with static context switching */
1273         /* FIXME: Check whether to set ACR bit depending on clock ratios */
1274         __raw_writel(0, sdma->regs + SDMA_H_CONFIG);
1275
1276         __raw_writel(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1277
1278         /* Set bits of CONFIG register with given context switching mode */
1279         __raw_writel(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
1280
1281         /* Initializes channel's priorities */
1282         sdma_set_channel_priority(&sdma->channel[0], 7);
1283
1284         clk_disable(sdma->clk);
1285
1286         return 0;
1287
1288 err_dma_alloc:
1289         clk_disable(sdma->clk);
1290         dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1291         return ret;
1292 }
1293
1294 static int __init sdma_probe(struct platform_device *pdev)
1295 {
1296         const struct of_device_id *of_id =
1297                         of_match_device(sdma_dt_ids, &pdev->dev);
1298         struct device_node *np = pdev->dev.of_node;
1299         const char *fw_name;
1300         int ret;
1301         int irq;
1302         struct resource *iores;
1303         struct sdma_platform_data *pdata = pdev->dev.platform_data;
1304         int i;
1305         struct sdma_engine *sdma;
1306         s32 *saddr_arr;
1307
1308         sdma = kzalloc(sizeof(*sdma), GFP_KERNEL);
1309         if (!sdma)
1310                 return -ENOMEM;
1311
1312         mutex_init(&sdma->channel_0_lock);
1313
1314         sdma->dev = &pdev->dev;
1315
1316         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1317         irq = platform_get_irq(pdev, 0);
1318         if (!iores || irq < 0) {
1319                 ret = -EINVAL;
1320                 goto err_irq;
1321         }
1322
1323         if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) {
1324                 ret = -EBUSY;
1325                 goto err_request_region;
1326         }
1327
1328         sdma->clk = clk_get(&pdev->dev, NULL);
1329         if (IS_ERR(sdma->clk)) {
1330                 ret = PTR_ERR(sdma->clk);
1331                 goto err_clk;
1332         }
1333
1334         sdma->regs = ioremap(iores->start, resource_size(iores));
1335         if (!sdma->regs) {
1336                 ret = -ENOMEM;
1337                 goto err_ioremap;
1338         }
1339
1340         ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma);
1341         if (ret)
1342                 goto err_request_irq;
1343
1344         sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1345         if (!sdma->script_addrs) {
1346                 ret = -ENOMEM;
1347                 goto err_alloc;
1348         }
1349
1350         /* initially no scripts available */
1351         saddr_arr = (s32 *)sdma->script_addrs;
1352         for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1353                 saddr_arr[i] = -EINVAL;
1354
1355         if (of_id)
1356                 pdev->id_entry = of_id->data;
1357         sdma->devtype = pdev->id_entry->driver_data;
1358
1359         dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1360         dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1361
1362         INIT_LIST_HEAD(&sdma->dma_device.channels);
1363         /* Initialize channel parameters */
1364         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1365                 struct sdma_channel *sdmac = &sdma->channel[i];
1366
1367                 sdmac->sdma = sdma;
1368                 spin_lock_init(&sdmac->lock);
1369
1370                 sdmac->chan.device = &sdma->dma_device;
1371                 sdmac->channel = i;
1372
1373                 /*
1374                  * Add the channel to the DMAC list. Do not add channel 0 though
1375                  * because we need it internally in the SDMA driver. This also means
1376                  * that channel 0 in dmaengine counting matches sdma channel 1.
1377                  */
1378                 if (i)
1379                         list_add_tail(&sdmac->chan.device_node,
1380                                         &sdma->dma_device.channels);
1381         }
1382
1383         ret = sdma_init(sdma);
1384         if (ret)
1385                 goto err_init;
1386
1387         if (pdata && pdata->script_addrs)
1388                 sdma_add_scripts(sdma, pdata->script_addrs);
1389
1390         if (pdata) {
1391                 sdma_get_firmware(sdma, pdata->fw_name);
1392         } else {
1393                 /*
1394                  * Because that device tree does not encode ROM script address,
1395                  * the RAM script in firmware is mandatory for device tree
1396                  * probe, otherwise it fails.
1397                  */
1398                 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1399                                               &fw_name);
1400                 if (ret) {
1401                         dev_err(&pdev->dev, "failed to get firmware name\n");
1402                         goto err_init;
1403                 }
1404
1405                 ret = sdma_get_firmware(sdma, fw_name);
1406                 if (ret) {
1407                         dev_err(&pdev->dev, "failed to get firmware\n");
1408                         goto err_init;
1409                 }
1410         }
1411
1412         sdma->dma_device.dev = &pdev->dev;
1413
1414         sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1415         sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1416         sdma->dma_device.device_tx_status = sdma_tx_status;
1417         sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1418         sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1419         sdma->dma_device.device_control = sdma_control;
1420         sdma->dma_device.device_issue_pending = sdma_issue_pending;
1421         sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1422         dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1423
1424         ret = dma_async_device_register(&sdma->dma_device);
1425         if (ret) {
1426                 dev_err(&pdev->dev, "unable to register\n");
1427                 goto err_init;
1428         }
1429
1430         dev_info(sdma->dev, "initialized\n");
1431
1432         return 0;
1433
1434 err_init:
1435         kfree(sdma->script_addrs);
1436 err_alloc:
1437         free_irq(irq, sdma);
1438 err_request_irq:
1439         iounmap(sdma->regs);
1440 err_ioremap:
1441         clk_put(sdma->clk);
1442 err_clk:
1443         release_mem_region(iores->start, resource_size(iores));
1444 err_request_region:
1445 err_irq:
1446         kfree(sdma);
1447         return ret;
1448 }
1449
1450 static int __exit sdma_remove(struct platform_device *pdev)
1451 {
1452         return -EBUSY;
1453 }
1454
1455 static struct platform_driver sdma_driver = {
1456         .driver         = {
1457                 .name   = "imx-sdma",
1458                 .of_match_table = sdma_dt_ids,
1459         },
1460         .id_table       = sdma_devtypes,
1461         .remove         = __exit_p(sdma_remove),
1462 };
1463
1464 static int __init sdma_module_init(void)
1465 {
1466         return platform_driver_probe(&sdma_driver, sdma_probe);
1467 }
1468 module_init(sdma_module_init);
1469
1470 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1471 MODULE_DESCRIPTION("i.MX SDMA driver");
1472 MODULE_LICENSE("GPL");