2 * Freescale MPC85xx, MPC83xx DMA Engine support
4 * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
7 * Zhang Wei <wei.zhang@freescale.com>, Jul 2007
8 * Ebony Zhu <ebony.zhu@freescale.com>, May 2007
11 * DMA engine driver for Freescale MPC8540 DMA controller, which is
12 * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
13 * The support for MPC8349 DMA controller is also added.
15 * This driver instructs the DMA controller to issue the PCI Read Multiple
16 * command for PCI read operations, instead of using the default PCI Read Line
17 * command. Please be aware that this setting may result in read pre-fetching
20 * This is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/dmaengine.h>
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/dmapool.h>
36 #include <linux/of_platform.h>
38 #include <asm/fsldma.h>
41 static void dma_init(struct fsldma_chan *chan)
43 /* Reset the channel */
44 DMA_OUT(chan, &chan->regs->mr, 0, 32);
46 switch (chan->feature & FSL_DMA_IP_MASK) {
48 /* Set the channel to below modes:
49 * EIE - Error interrupt enable
50 * EOSIE - End of segments interrupt enable (basic mode)
51 * EOLNIE - End of links interrupt enable
53 DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EIE
54 | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32);
57 /* Set the channel to below modes:
58 * EOTIE - End-of-transfer interrupt enable
59 * PRC_RM - PCI read multiple
61 DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE
62 | FSL_DMA_MR_PRC_RM, 32);
67 static void set_sr(struct fsldma_chan *chan, u32 val)
69 DMA_OUT(chan, &chan->regs->sr, val, 32);
72 static u32 get_sr(struct fsldma_chan *chan)
74 return DMA_IN(chan, &chan->regs->sr, 32);
77 static void set_desc_cnt(struct fsldma_chan *chan,
78 struct fsl_dma_ld_hw *hw, u32 count)
80 hw->count = CPU_TO_DMA(chan, count, 32);
83 static void set_desc_src(struct fsldma_chan *chan,
84 struct fsl_dma_ld_hw *hw, dma_addr_t src)
88 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
89 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
90 hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64);
93 static void set_desc_dst(struct fsldma_chan *chan,
94 struct fsl_dma_ld_hw *hw, dma_addr_t dst)
98 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
99 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
100 hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64);
103 static void set_desc_next(struct fsldma_chan *chan,
104 struct fsl_dma_ld_hw *hw, dma_addr_t next)
108 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
110 hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
113 static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
115 DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
118 static dma_addr_t get_cdar(struct fsldma_chan *chan)
120 return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
123 static dma_addr_t get_ndar(struct fsldma_chan *chan)
125 return DMA_IN(chan, &chan->regs->ndar, 64);
128 static u32 get_bcr(struct fsldma_chan *chan)
130 return DMA_IN(chan, &chan->regs->bcr, 32);
133 static int dma_is_idle(struct fsldma_chan *chan)
135 u32 sr = get_sr(chan);
136 return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
139 static void dma_start(struct fsldma_chan *chan)
143 mode = DMA_IN(chan, &chan->regs->mr, 32);
145 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
146 if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
147 DMA_OUT(chan, &chan->regs->bcr, 0, 32);
148 mode |= FSL_DMA_MR_EMP_EN;
150 mode &= ~FSL_DMA_MR_EMP_EN;
154 if (chan->feature & FSL_DMA_CHAN_START_EXT)
155 mode |= FSL_DMA_MR_EMS_EN;
157 mode |= FSL_DMA_MR_CS;
159 DMA_OUT(chan, &chan->regs->mr, mode, 32);
162 static void dma_halt(struct fsldma_chan *chan)
167 mode = DMA_IN(chan, &chan->regs->mr, 32);
168 mode |= FSL_DMA_MR_CA;
169 DMA_OUT(chan, &chan->regs->mr, mode, 32);
171 mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA);
172 DMA_OUT(chan, &chan->regs->mr, mode, 32);
174 for (i = 0; i < 100; i++) {
175 if (dma_is_idle(chan))
181 if (!dma_is_idle(chan))
182 dev_err(chan->dev, "DMA halt timeout!\n");
185 static void set_ld_eol(struct fsldma_chan *chan,
186 struct fsl_desc_sw *desc)
190 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
193 desc->hw.next_ln_addr = CPU_TO_DMA(chan,
194 DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
199 * fsl_chan_set_src_loop_size - Set source address hold transfer size
200 * @chan : Freescale DMA channel
201 * @size : Address loop size, 0 for disable loop
203 * The set source address hold transfer size. The source
204 * address hold or loop transfer size is when the DMA transfer
205 * data from source address (SA), if the loop size is 4, the DMA will
206 * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
207 * SA + 1 ... and so on.
209 static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size)
213 mode = DMA_IN(chan, &chan->regs->mr, 32);
217 mode &= ~FSL_DMA_MR_SAHE;
223 mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14);
227 DMA_OUT(chan, &chan->regs->mr, mode, 32);
231 * fsl_chan_set_dst_loop_size - Set destination address hold transfer size
232 * @chan : Freescale DMA channel
233 * @size : Address loop size, 0 for disable loop
235 * The set destination address hold transfer size. The destination
236 * address hold or loop transfer size is when the DMA transfer
237 * data to destination address (TA), if the loop size is 4, the DMA will
238 * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
239 * TA + 1 ... and so on.
241 static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size)
245 mode = DMA_IN(chan, &chan->regs->mr, 32);
249 mode &= ~FSL_DMA_MR_DAHE;
255 mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16);
259 DMA_OUT(chan, &chan->regs->mr, mode, 32);
263 * fsl_chan_set_request_count - Set DMA Request Count for external control
264 * @chan : Freescale DMA channel
265 * @size : Number of bytes to transfer in a single request
267 * The Freescale DMA channel can be controlled by the external signal DREQ#.
268 * The DMA request count is how many bytes are allowed to transfer before
269 * pausing the channel, after which a new assertion of DREQ# resumes channel
272 * A size of 0 disables external pause control. The maximum size is 1024.
274 static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size)
280 mode = DMA_IN(chan, &chan->regs->mr, 32);
281 mode |= (__ilog2(size) << 24) & 0x0f000000;
283 DMA_OUT(chan, &chan->regs->mr, mode, 32);
287 * fsl_chan_toggle_ext_pause - Toggle channel external pause status
288 * @chan : Freescale DMA channel
289 * @enable : 0 is disabled, 1 is enabled.
291 * The Freescale DMA channel can be controlled by the external signal DREQ#.
292 * The DMA Request Count feature should be used in addition to this feature
293 * to set the number of bytes to transfer before pausing the channel.
295 static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable)
298 chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
300 chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
304 * fsl_chan_toggle_ext_start - Toggle channel external start status
305 * @chan : Freescale DMA channel
306 * @enable : 0 is disabled, 1 is enabled.
308 * If enable the external start, the channel can be started by an
309 * external DMA start pin. So the dma_start() does not start the
310 * transfer immediately. The DMA channel will wait for the
311 * control pin asserted.
313 static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable)
316 chan->feature |= FSL_DMA_CHAN_START_EXT;
318 chan->feature &= ~FSL_DMA_CHAN_START_EXT;
321 static void append_ld_queue(struct fsldma_chan *chan,
322 struct fsl_desc_sw *desc)
324 struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev);
326 if (list_empty(&chan->ld_pending))
330 * Add the hardware descriptor to the chain of hardware descriptors
331 * that already exists in memory.
333 * This will un-set the EOL bit of the existing transaction, and the
334 * last link in this transaction will become the EOL descriptor.
336 set_desc_next(chan, &tail->hw, desc->async_tx.phys);
339 * Add the software descriptor and all children to the list
340 * of pending transactions
343 list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
346 static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
348 struct fsldma_chan *chan = to_fsl_chan(tx->chan);
349 struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
350 struct fsl_desc_sw *child;
354 spin_lock_irqsave(&chan->desc_lock, flags);
357 * assign cookies to all of the software descriptors
358 * that make up this transaction
360 cookie = chan->common.cookie;
361 list_for_each_entry(child, &desc->tx_list, node) {
366 child->async_tx.cookie = cookie;
369 chan->common.cookie = cookie;
371 /* put this transaction onto the tail of the pending queue */
372 append_ld_queue(chan, desc);
374 spin_unlock_irqrestore(&chan->desc_lock, flags);
380 * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
381 * @chan : Freescale DMA channel
383 * Return - The descriptor allocated. NULL for failed.
385 static struct fsl_desc_sw *fsl_dma_alloc_descriptor(
386 struct fsldma_chan *chan)
388 struct fsl_desc_sw *desc;
391 desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
393 dev_dbg(chan->dev, "out of memory for link desc\n");
397 memset(desc, 0, sizeof(*desc));
398 INIT_LIST_HEAD(&desc->tx_list);
399 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
400 desc->async_tx.tx_submit = fsl_dma_tx_submit;
401 desc->async_tx.phys = pdesc;
408 * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
409 * @chan : Freescale DMA channel
411 * This function will create a dma pool for descriptor allocation.
413 * Return - The number of descriptors allocated.
415 static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan)
417 struct fsldma_chan *chan = to_fsl_chan(dchan);
419 /* Has this channel already been allocated? */
424 * We need the descriptor to be aligned to 32bytes
425 * for meeting FSL DMA specification requirement.
427 chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool",
429 sizeof(struct fsl_desc_sw),
430 __alignof__(struct fsl_desc_sw), 0);
431 if (!chan->desc_pool) {
432 dev_err(chan->dev, "unable to allocate channel %d "
433 "descriptor pool\n", chan->id);
437 /* there is at least one descriptor free to be allocated */
442 * fsldma_free_desc_list - Free all descriptors in a queue
443 * @chan: Freescae DMA channel
444 * @list: the list to free
446 * LOCKING: must hold chan->desc_lock
448 static void fsldma_free_desc_list(struct fsldma_chan *chan,
449 struct list_head *list)
451 struct fsl_desc_sw *desc, *_desc;
453 list_for_each_entry_safe(desc, _desc, list, node) {
454 list_del(&desc->node);
455 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
459 static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
460 struct list_head *list)
462 struct fsl_desc_sw *desc, *_desc;
464 list_for_each_entry_safe_reverse(desc, _desc, list, node) {
465 list_del(&desc->node);
466 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
471 * fsl_dma_free_chan_resources - Free all resources of the channel.
472 * @chan : Freescale DMA channel
474 static void fsl_dma_free_chan_resources(struct dma_chan *dchan)
476 struct fsldma_chan *chan = to_fsl_chan(dchan);
479 dev_dbg(chan->dev, "Free all channel resources.\n");
480 spin_lock_irqsave(&chan->desc_lock, flags);
481 fsldma_free_desc_list(chan, &chan->ld_pending);
482 fsldma_free_desc_list(chan, &chan->ld_running);
483 spin_unlock_irqrestore(&chan->desc_lock, flags);
485 dma_pool_destroy(chan->desc_pool);
486 chan->desc_pool = NULL;
489 static struct dma_async_tx_descriptor *
490 fsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags)
492 struct fsldma_chan *chan;
493 struct fsl_desc_sw *new;
498 chan = to_fsl_chan(dchan);
500 new = fsl_dma_alloc_descriptor(chan);
502 dev_err(chan->dev, "No free memory for link descriptor\n");
506 new->async_tx.cookie = -EBUSY;
507 new->async_tx.flags = flags;
509 /* Insert the link descriptor to the LD ring */
510 list_add_tail(&new->node, &new->tx_list);
512 /* Set End-of-link to the last link descriptor of new list*/
513 set_ld_eol(chan, new);
515 return &new->async_tx;
518 static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
519 struct dma_chan *dchan, dma_addr_t dma_dst, dma_addr_t dma_src,
520 size_t len, unsigned long flags)
522 struct fsldma_chan *chan;
523 struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
532 chan = to_fsl_chan(dchan);
536 /* Allocate the link descriptor from DMA pool */
537 new = fsl_dma_alloc_descriptor(chan);
540 "No free memory for link descriptor\n");
543 #ifdef FSL_DMA_LD_DEBUG
544 dev_dbg(chan->dev, "new link desc alloc %p\n", new);
547 copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
549 set_desc_cnt(chan, &new->hw, copy);
550 set_desc_src(chan, &new->hw, dma_src);
551 set_desc_dst(chan, &new->hw, dma_dst);
556 set_desc_next(chan, &prev->hw, new->async_tx.phys);
558 new->async_tx.cookie = 0;
559 async_tx_ack(&new->async_tx);
566 /* Insert the link descriptor to the LD ring */
567 list_add_tail(&new->node, &first->tx_list);
570 new->async_tx.flags = flags; /* client is in control of this ack */
571 new->async_tx.cookie = -EBUSY;
573 /* Set End-of-link to the last link descriptor of new list*/
574 set_ld_eol(chan, new);
576 return &first->async_tx;
582 fsldma_free_desc_list_reverse(chan, &first->tx_list);
587 * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
589 * @sgl: scatterlist to transfer to/from
590 * @sg_len: number of entries in @scatterlist
591 * @direction: DMA direction
592 * @flags: DMAEngine flags
594 * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the
595 * DMA_SLAVE API, this gets the device-specific information from the
596 * chan->private variable.
598 static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg(
599 struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
600 enum dma_data_direction direction, unsigned long flags)
602 struct fsldma_chan *chan;
603 struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL;
604 struct fsl_dma_slave *slave;
608 struct scatterlist *sg;
611 struct fsl_dma_hw_addr *hw;
612 dma_addr_t dma_dst, dma_src;
620 chan = to_fsl_chan(dchan);
621 slave = dchan->private;
623 if (list_empty(&slave->addresses))
626 hw = list_first_entry(&slave->addresses, struct fsl_dma_hw_addr, entry);
630 * Build the hardware transaction to copy from the scatterlist to
631 * the hardware, or from the hardware to the scatterlist
633 * If you are copying from the hardware to the scatterlist and it
634 * takes two hardware entries to fill an entire page, then both
635 * hardware entries will be coalesced into the same page
637 * If you are copying from the scatterlist to the hardware and a
638 * single page can fill two hardware entries, then the data will
639 * be read out of the page into the first hardware entry, and so on
641 for_each_sg(sgl, sg, sg_len, i) {
644 /* Loop until the entire scatterlist entry is used */
645 while (sg_used < sg_dma_len(sg)) {
648 * If we've used up the current hardware address/length
649 * pair, we need to load a new one
651 * This is done in a while loop so that descriptors with
652 * length == 0 will be skipped
654 while (hw_used >= hw->length) {
657 * If the current hardware entry is the last
658 * entry in the list, we're finished
660 if (list_is_last(&hw->entry, &slave->addresses))
663 /* Get the next hardware address/length pair */
664 hw = list_entry(hw->entry.next,
665 struct fsl_dma_hw_addr, entry);
669 /* Allocate the link descriptor from DMA pool */
670 new = fsl_dma_alloc_descriptor(chan);
672 dev_err(chan->dev, "No free memory for "
673 "link descriptor\n");
676 #ifdef FSL_DMA_LD_DEBUG
677 dev_dbg(chan->dev, "new link desc alloc %p\n", new);
681 * Calculate the maximum number of bytes to transfer,
682 * making sure it is less than the DMA controller limit
684 copy = min_t(size_t, sg_dma_len(sg) - sg_used,
685 hw->length - hw_used);
686 copy = min_t(size_t, copy, FSL_DMA_BCR_MAX_CNT);
690 * from the hardware to the scatterlist
693 * from the scatterlist to the hardware
695 if (direction == DMA_FROM_DEVICE) {
696 dma_src = hw->address + hw_used;
697 dma_dst = sg_dma_address(sg) + sg_used;
699 dma_src = sg_dma_address(sg) + sg_used;
700 dma_dst = hw->address + hw_used;
703 /* Fill in the descriptor */
704 set_desc_cnt(chan, &new->hw, copy);
705 set_desc_src(chan, &new->hw, dma_src);
706 set_desc_dst(chan, &new->hw, dma_dst);
709 * If this is not the first descriptor, chain the
710 * current descriptor after the previous descriptor
715 set_desc_next(chan, &prev->hw,
719 new->async_tx.cookie = 0;
720 async_tx_ack(&new->async_tx);
726 /* Insert the link descriptor into the LD ring */
727 list_add_tail(&new->node, &first->tx_list);
733 /* All of the hardware address/length pairs had length == 0 */
737 new->async_tx.flags = flags;
738 new->async_tx.cookie = -EBUSY;
740 /* Set End-of-link to the last link descriptor of new list */
741 set_ld_eol(chan, new);
743 /* Enable extra controller features */
744 if (chan->set_src_loop_size)
745 chan->set_src_loop_size(chan, slave->src_loop_size);
747 if (chan->set_dst_loop_size)
748 chan->set_dst_loop_size(chan, slave->dst_loop_size);
750 if (chan->toggle_ext_start)
751 chan->toggle_ext_start(chan, slave->external_start);
753 if (chan->toggle_ext_pause)
754 chan->toggle_ext_pause(chan, slave->external_pause);
756 if (chan->set_request_count)
757 chan->set_request_count(chan, slave->request_count);
759 return &first->async_tx;
762 /* If first was not set, then we failed to allocate the very first
763 * descriptor, and we're done */
768 * First is set, so all of the descriptors we allocated have been added
769 * to first->tx_list, INCLUDING "first" itself. Therefore we
770 * must traverse the list backwards freeing each descriptor in turn
772 * We're re-using variables for the loop, oh well
774 fsldma_free_desc_list_reverse(chan, &first->tx_list);
778 static int fsl_dma_device_control(struct dma_chan *dchan,
779 enum dma_ctrl_cmd cmd, unsigned long arg)
781 struct fsldma_chan *chan;
784 /* Only supports DMA_TERMINATE_ALL */
785 if (cmd != DMA_TERMINATE_ALL)
791 chan = to_fsl_chan(dchan);
793 /* Halt the DMA engine */
796 spin_lock_irqsave(&chan->desc_lock, flags);
798 /* Remove and free all of the descriptors in the LD queue */
799 fsldma_free_desc_list(chan, &chan->ld_pending);
800 fsldma_free_desc_list(chan, &chan->ld_running);
802 spin_unlock_irqrestore(&chan->desc_lock, flags);
808 * fsl_dma_update_completed_cookie - Update the completed cookie.
809 * @chan : Freescale DMA channel
813 static void fsl_dma_update_completed_cookie(struct fsldma_chan *chan)
815 struct fsl_desc_sw *desc;
819 spin_lock_irqsave(&chan->desc_lock, flags);
821 if (list_empty(&chan->ld_running)) {
822 dev_dbg(chan->dev, "no running descriptors\n");
826 /* Get the last descriptor, update the cookie to that */
827 desc = to_fsl_desc(chan->ld_running.prev);
828 if (dma_is_idle(chan))
829 cookie = desc->async_tx.cookie;
831 cookie = desc->async_tx.cookie - 1;
832 if (unlikely(cookie < DMA_MIN_COOKIE))
833 cookie = DMA_MAX_COOKIE;
836 chan->completed_cookie = cookie;
839 spin_unlock_irqrestore(&chan->desc_lock, flags);
843 * fsldma_desc_status - Check the status of a descriptor
844 * @chan: Freescale DMA channel
845 * @desc: DMA SW descriptor
847 * This function will return the status of the given descriptor
849 static enum dma_status fsldma_desc_status(struct fsldma_chan *chan,
850 struct fsl_desc_sw *desc)
852 return dma_async_is_complete(desc->async_tx.cookie,
853 chan->completed_cookie,
854 chan->common.cookie);
858 * fsl_chan_ld_cleanup - Clean up link descriptors
859 * @chan : Freescale DMA channel
861 * This function clean up the ld_queue of DMA channel.
863 static void fsl_chan_ld_cleanup(struct fsldma_chan *chan)
865 struct fsl_desc_sw *desc, *_desc;
868 spin_lock_irqsave(&chan->desc_lock, flags);
870 dev_dbg(chan->dev, "chan completed_cookie = %d\n", chan->completed_cookie);
871 list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) {
872 dma_async_tx_callback callback;
873 void *callback_param;
875 if (fsldma_desc_status(chan, desc) == DMA_IN_PROGRESS)
878 /* Remove from the list of running transactions */
879 list_del(&desc->node);
881 /* Run the link descriptor callback function */
882 callback = desc->async_tx.callback;
883 callback_param = desc->async_tx.callback_param;
885 spin_unlock_irqrestore(&chan->desc_lock, flags);
886 dev_dbg(chan->dev, "LD %p callback\n", desc);
887 callback(callback_param);
888 spin_lock_irqsave(&chan->desc_lock, flags);
891 /* Run any dependencies, then free the descriptor */
892 dma_run_dependencies(&desc->async_tx);
893 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
896 spin_unlock_irqrestore(&chan->desc_lock, flags);
900 * fsl_chan_xfer_ld_queue - transfer any pending transactions
901 * @chan : Freescale DMA channel
903 * This will make sure that any pending transactions will be run.
904 * If the DMA controller is idle, it will be started. Otherwise,
905 * the DMA controller's interrupt handler will start any pending
906 * transactions when it becomes idle.
908 static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
910 struct fsl_desc_sw *desc;
913 spin_lock_irqsave(&chan->desc_lock, flags);
916 * If the list of pending descriptors is empty, then we
917 * don't need to do any work at all
919 if (list_empty(&chan->ld_pending)) {
920 dev_dbg(chan->dev, "no pending LDs\n");
925 * The DMA controller is not idle, which means the interrupt
926 * handler will start any queued transactions when it runs
927 * at the end of the current transaction
929 if (!dma_is_idle(chan)) {
930 dev_dbg(chan->dev, "DMA controller still busy\n");
936 * make sure the dma_halt() function really un-wedges the
937 * controller as much as possible
942 * If there are some link descriptors which have not been
943 * transferred, we need to start the controller
947 * Move all elements from the queue of pending transactions
948 * onto the list of running transactions
950 desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node);
951 list_splice_tail_init(&chan->ld_pending, &chan->ld_running);
954 * Program the descriptor's address into the DMA controller,
955 * then start the DMA transaction
957 set_cdar(chan, desc->async_tx.phys);
961 spin_unlock_irqrestore(&chan->desc_lock, flags);
965 * fsl_dma_memcpy_issue_pending - Issue the DMA start command
966 * @chan : Freescale DMA channel
968 static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan)
970 struct fsldma_chan *chan = to_fsl_chan(dchan);
971 fsl_chan_xfer_ld_queue(chan);
975 * fsl_tx_status - Determine the DMA status
976 * @chan : Freescale DMA channel
978 static enum dma_status fsl_tx_status(struct dma_chan *dchan,
980 struct dma_tx_state *txstate)
982 struct fsldma_chan *chan = to_fsl_chan(dchan);
983 dma_cookie_t last_used;
984 dma_cookie_t last_complete;
986 fsl_chan_ld_cleanup(chan);
988 last_used = dchan->cookie;
989 last_complete = chan->completed_cookie;
991 dma_set_tx_state(txstate, last_complete, last_used, 0);
993 return dma_async_is_complete(cookie, last_complete, last_used);
996 /*----------------------------------------------------------------------------*/
997 /* Interrupt Handling */
998 /*----------------------------------------------------------------------------*/
1000 static irqreturn_t fsldma_chan_irq(int irq, void *data)
1002 struct fsldma_chan *chan = data;
1003 int update_cookie = 0;
1007 /* save and clear the status register */
1008 stat = get_sr(chan);
1010 dev_dbg(chan->dev, "irq: channel %d, stat = 0x%x\n", chan->id, stat);
1012 stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
1016 if (stat & FSL_DMA_SR_TE)
1017 dev_err(chan->dev, "Transfer Error!\n");
1021 * The DMA_INTERRUPT async_tx is a NULL transfer, which will
1022 * triger a PE interrupt.
1024 if (stat & FSL_DMA_SR_PE) {
1025 dev_dbg(chan->dev, "irq: Programming Error INT\n");
1026 if (get_bcr(chan) == 0) {
1027 /* BCR register is 0, this is a DMA_INTERRUPT async_tx.
1028 * Now, update the completed cookie, and continue the
1029 * next uncompleted transfer.
1034 stat &= ~FSL_DMA_SR_PE;
1038 * If the link descriptor segment transfer finishes,
1039 * we will recycle the used descriptor.
1041 if (stat & FSL_DMA_SR_EOSI) {
1042 dev_dbg(chan->dev, "irq: End-of-segments INT\n");
1043 dev_dbg(chan->dev, "irq: clndar 0x%llx, nlndar 0x%llx\n",
1044 (unsigned long long)get_cdar(chan),
1045 (unsigned long long)get_ndar(chan));
1046 stat &= ~FSL_DMA_SR_EOSI;
1051 * For MPC8349, EOCDI event need to update cookie
1052 * and start the next transfer if it exist.
1054 if (stat & FSL_DMA_SR_EOCDI) {
1055 dev_dbg(chan->dev, "irq: End-of-Chain link INT\n");
1056 stat &= ~FSL_DMA_SR_EOCDI;
1062 * If it current transfer is the end-of-transfer,
1063 * we should clear the Channel Start bit for
1064 * prepare next transfer.
1066 if (stat & FSL_DMA_SR_EOLNI) {
1067 dev_dbg(chan->dev, "irq: End-of-link INT\n");
1068 stat &= ~FSL_DMA_SR_EOLNI;
1073 fsl_dma_update_completed_cookie(chan);
1075 fsl_chan_xfer_ld_queue(chan);
1077 dev_dbg(chan->dev, "irq: unhandled sr 0x%02x\n", stat);
1079 dev_dbg(chan->dev, "irq: Exit\n");
1080 tasklet_schedule(&chan->tasklet);
1084 static void dma_do_tasklet(unsigned long data)
1086 struct fsldma_chan *chan = (struct fsldma_chan *)data;
1087 fsl_chan_ld_cleanup(chan);
1090 static irqreturn_t fsldma_ctrl_irq(int irq, void *data)
1092 struct fsldma_device *fdev = data;
1093 struct fsldma_chan *chan;
1094 unsigned int handled = 0;
1098 gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs)
1099 : in_le32(fdev->regs);
1101 dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr);
1103 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1104 chan = fdev->chan[i];
1109 dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id);
1110 fsldma_chan_irq(irq, chan);
1118 return IRQ_RETVAL(handled);
1121 static void fsldma_free_irqs(struct fsldma_device *fdev)
1123 struct fsldma_chan *chan;
1126 if (fdev->irq != NO_IRQ) {
1127 dev_dbg(fdev->dev, "free per-controller IRQ\n");
1128 free_irq(fdev->irq, fdev);
1132 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1133 chan = fdev->chan[i];
1134 if (chan && chan->irq != NO_IRQ) {
1135 dev_dbg(fdev->dev, "free channel %d IRQ\n", chan->id);
1136 free_irq(chan->irq, chan);
1141 static int fsldma_request_irqs(struct fsldma_device *fdev)
1143 struct fsldma_chan *chan;
1147 /* if we have a per-controller IRQ, use that */
1148 if (fdev->irq != NO_IRQ) {
1149 dev_dbg(fdev->dev, "request per-controller IRQ\n");
1150 ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED,
1151 "fsldma-controller", fdev);
1155 /* no per-controller IRQ, use the per-channel IRQs */
1156 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1157 chan = fdev->chan[i];
1161 if (chan->irq == NO_IRQ) {
1162 dev_err(fdev->dev, "no interrupts property defined for "
1163 "DMA channel %d. Please fix your "
1164 "device tree\n", chan->id);
1169 dev_dbg(fdev->dev, "request channel %d IRQ\n", chan->id);
1170 ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED,
1171 "fsldma-chan", chan);
1173 dev_err(fdev->dev, "unable to request IRQ for DMA "
1174 "channel %d\n", chan->id);
1182 for (/* none */; i >= 0; i--) {
1183 chan = fdev->chan[i];
1187 if (chan->irq == NO_IRQ)
1190 free_irq(chan->irq, chan);
1196 /*----------------------------------------------------------------------------*/
1197 /* OpenFirmware Subsystem */
1198 /*----------------------------------------------------------------------------*/
1200 static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev,
1201 struct device_node *node, u32 feature, const char *compatible)
1203 struct fsldma_chan *chan;
1204 struct resource res;
1208 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
1210 dev_err(fdev->dev, "no free memory for DMA channels!\n");
1215 /* ioremap registers for use */
1216 chan->regs = of_iomap(node, 0);
1218 dev_err(fdev->dev, "unable to ioremap registers\n");
1223 err = of_address_to_resource(node, 0, &res);
1225 dev_err(fdev->dev, "unable to find 'reg' property\n");
1226 goto out_iounmap_regs;
1229 chan->feature = feature;
1231 fdev->feature = chan->feature;
1234 * If the DMA device's feature is different than the feature
1235 * of its channels, report the bug
1237 WARN_ON(fdev->feature != chan->feature);
1239 chan->dev = fdev->dev;
1240 chan->id = ((res.start - 0x100) & 0xfff) >> 7;
1241 if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
1242 dev_err(fdev->dev, "too many channels for device\n");
1244 goto out_iounmap_regs;
1247 fdev->chan[chan->id] = chan;
1248 tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
1250 /* Initialize the channel */
1253 /* Clear cdar registers */
1256 switch (chan->feature & FSL_DMA_IP_MASK) {
1257 case FSL_DMA_IP_85XX:
1258 chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
1259 case FSL_DMA_IP_83XX:
1260 chan->toggle_ext_start = fsl_chan_toggle_ext_start;
1261 chan->set_src_loop_size = fsl_chan_set_src_loop_size;
1262 chan->set_dst_loop_size = fsl_chan_set_dst_loop_size;
1263 chan->set_request_count = fsl_chan_set_request_count;
1266 spin_lock_init(&chan->desc_lock);
1267 INIT_LIST_HEAD(&chan->ld_pending);
1268 INIT_LIST_HEAD(&chan->ld_running);
1270 chan->common.device = &fdev->common;
1272 /* find the IRQ line, if it exists in the device tree */
1273 chan->irq = irq_of_parse_and_map(node, 0);
1275 /* Add the channel to DMA device channel list */
1276 list_add_tail(&chan->common.device_node, &fdev->common.channels);
1277 fdev->common.chancnt++;
1279 dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible,
1280 chan->irq != NO_IRQ ? chan->irq : fdev->irq);
1285 iounmap(chan->regs);
1292 static void fsl_dma_chan_remove(struct fsldma_chan *chan)
1294 irq_dispose_mapping(chan->irq);
1295 list_del(&chan->common.device_node);
1296 iounmap(chan->regs);
1300 static int __devinit fsldma_of_probe(struct platform_device *op,
1301 const struct of_device_id *match)
1303 struct fsldma_device *fdev;
1304 struct device_node *child;
1307 fdev = kzalloc(sizeof(*fdev), GFP_KERNEL);
1309 dev_err(&op->dev, "No enough memory for 'priv'\n");
1314 fdev->dev = &op->dev;
1315 INIT_LIST_HEAD(&fdev->common.channels);
1317 /* ioremap the registers for use */
1318 fdev->regs = of_iomap(op->dev.of_node, 0);
1320 dev_err(&op->dev, "unable to ioremap registers\n");
1325 /* map the channel IRQ if it exists, but don't hookup the handler yet */
1326 fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0);
1328 dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
1329 dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask);
1330 dma_cap_set(DMA_SLAVE, fdev->common.cap_mask);
1331 fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
1332 fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
1333 fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt;
1334 fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
1335 fdev->common.device_tx_status = fsl_tx_status;
1336 fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
1337 fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg;
1338 fdev->common.device_control = fsl_dma_device_control;
1339 fdev->common.dev = &op->dev;
1341 dev_set_drvdata(&op->dev, fdev);
1344 * We cannot use of_platform_bus_probe() because there is no
1345 * of_platform_bus_remove(). Instead, we manually instantiate every DMA
1348 for_each_child_of_node(op->dev.of_node, child) {
1349 if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) {
1350 fsl_dma_chan_probe(fdev, child,
1351 FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,
1352 "fsl,eloplus-dma-channel");
1355 if (of_device_is_compatible(child, "fsl,elo-dma-channel")) {
1356 fsl_dma_chan_probe(fdev, child,
1357 FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN,
1358 "fsl,elo-dma-channel");
1363 * Hookup the IRQ handler(s)
1365 * If we have a per-controller interrupt, we prefer that to the
1366 * per-channel interrupts to reduce the number of shared interrupt
1367 * handlers on the same IRQ line
1369 err = fsldma_request_irqs(fdev);
1371 dev_err(fdev->dev, "unable to request IRQs\n");
1375 dma_async_device_register(&fdev->common);
1379 irq_dispose_mapping(fdev->irq);
1385 static int fsldma_of_remove(struct platform_device *op)
1387 struct fsldma_device *fdev;
1390 fdev = dev_get_drvdata(&op->dev);
1391 dma_async_device_unregister(&fdev->common);
1393 fsldma_free_irqs(fdev);
1395 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1397 fsl_dma_chan_remove(fdev->chan[i]);
1400 iounmap(fdev->regs);
1401 dev_set_drvdata(&op->dev, NULL);
1407 static const struct of_device_id fsldma_of_ids[] = {
1408 { .compatible = "fsl,eloplus-dma", },
1409 { .compatible = "fsl,elo-dma", },
1413 static struct of_platform_driver fsldma_of_driver = {
1415 .name = "fsl-elo-dma",
1416 .owner = THIS_MODULE,
1417 .of_match_table = fsldma_of_ids,
1419 .probe = fsldma_of_probe,
1420 .remove = fsldma_of_remove,
1423 /*----------------------------------------------------------------------------*/
1424 /* Module Init / Exit */
1425 /*----------------------------------------------------------------------------*/
1427 static __init int fsldma_init(void)
1431 pr_info("Freescale Elo / Elo Plus DMA driver\n");
1433 ret = of_register_platform_driver(&fsldma_of_driver);
1435 pr_err("fsldma: failed to register platform driver\n");
1440 static void __exit fsldma_exit(void)
1442 of_unregister_platform_driver(&fsldma_of_driver);
1445 subsys_initcall(fsldma_init);
1446 module_exit(fsldma_exit);
1448 MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver");
1449 MODULE_LICENSE("GPL");