2 * Driver for the Cirrus Logic EP93xx DMA Controller
4 * Copyright (C) 2011 Mika Westerberg
6 * DMA M2P implementation is based on the original
7 * arch/arm/mach-ep93xx/dma-m2p.c which has following copyrights:
9 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
10 * Copyright (C) 2006 Applied Data Systems
11 * Copyright (C) 2009 Ryan Mallon <rmallon@gmail.com>
13 * This driver is based on dw_dmac and amba-pl08x drivers.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
21 #include <linux/clk.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/dmaengine.h>
25 #include <linux/module.h>
26 #include <linux/platform_device.h>
27 #include <linux/slab.h>
32 #define M2P_CONTROL 0x0000
33 #define M2P_CONTROL_STALLINT BIT(0)
34 #define M2P_CONTROL_NFBINT BIT(1)
35 #define M2P_CONTROL_CH_ERROR_INT BIT(3)
36 #define M2P_CONTROL_ENABLE BIT(4)
37 #define M2P_CONTROL_ICE BIT(6)
39 #define M2P_INTERRUPT 0x0004
40 #define M2P_INTERRUPT_STALL BIT(0)
41 #define M2P_INTERRUPT_NFB BIT(1)
42 #define M2P_INTERRUPT_ERROR BIT(3)
44 #define M2P_PPALLOC 0x0008
45 #define M2P_STATUS 0x000c
47 #define M2P_MAXCNT0 0x0020
48 #define M2P_BASE0 0x0024
49 #define M2P_MAXCNT1 0x0030
50 #define M2P_BASE1 0x0034
52 #define M2P_STATE_IDLE 0
53 #define M2P_STATE_STALL 1
54 #define M2P_STATE_ON 2
55 #define M2P_STATE_NEXT 3
58 #define M2M_CONTROL 0x0000
59 #define M2M_CONTROL_DONEINT BIT(2)
60 #define M2M_CONTROL_ENABLE BIT(3)
61 #define M2M_CONTROL_START BIT(4)
62 #define M2M_CONTROL_DAH BIT(11)
63 #define M2M_CONTROL_SAH BIT(12)
64 #define M2M_CONTROL_PW_SHIFT 9
65 #define M2M_CONTROL_PW_8 (0 << M2M_CONTROL_PW_SHIFT)
66 #define M2M_CONTROL_PW_16 (1 << M2M_CONTROL_PW_SHIFT)
67 #define M2M_CONTROL_PW_32 (2 << M2M_CONTROL_PW_SHIFT)
68 #define M2M_CONTROL_PW_MASK (3 << M2M_CONTROL_PW_SHIFT)
69 #define M2M_CONTROL_TM_SHIFT 13
70 #define M2M_CONTROL_TM_TX (1 << M2M_CONTROL_TM_SHIFT)
71 #define M2M_CONTROL_TM_RX (2 << M2M_CONTROL_TM_SHIFT)
72 #define M2M_CONTROL_RSS_SHIFT 22
73 #define M2M_CONTROL_RSS_SSPRX (1 << M2M_CONTROL_RSS_SHIFT)
74 #define M2M_CONTROL_RSS_SSPTX (2 << M2M_CONTROL_RSS_SHIFT)
75 #define M2M_CONTROL_RSS_IDE (3 << M2M_CONTROL_RSS_SHIFT)
76 #define M2M_CONTROL_NO_HDSK BIT(24)
77 #define M2M_CONTROL_PWSC_SHIFT 25
79 #define M2M_INTERRUPT 0x0004
80 #define M2M_INTERRUPT_DONEINT BIT(1)
82 #define M2M_BCR0 0x0010
83 #define M2M_BCR1 0x0014
84 #define M2M_SAR_BASE0 0x0018
85 #define M2M_SAR_BASE1 0x001c
86 #define M2M_DAR_BASE0 0x002c
87 #define M2M_DAR_BASE1 0x0030
89 #define DMA_MAX_CHAN_BYTES 0xffff
90 #define DMA_MAX_CHAN_DESCRIPTORS 32
92 struct ep93xx_dma_engine;
95 * struct ep93xx_dma_desc - EP93xx specific transaction descriptor
96 * @src_addr: source address of the transaction
97 * @dst_addr: destination address of the transaction
98 * @size: size of the transaction (in bytes)
99 * @complete: this descriptor is completed
100 * @txd: dmaengine API descriptor
101 * @tx_list: list of linked descriptors
102 * @node: link used for putting this into a channel queue
104 struct ep93xx_dma_desc {
109 struct dma_async_tx_descriptor txd;
110 struct list_head tx_list;
111 struct list_head node;
115 * struct ep93xx_dma_chan - an EP93xx DMA M2P/M2M channel
116 * @chan: dmaengine API channel
117 * @edma: pointer to to the engine device
118 * @regs: memory mapped registers
119 * @irq: interrupt number of the channel
120 * @clk: clock used by this channel
121 * @tasklet: channel specific tasklet used for callbacks
122 * @lock: lock protecting the fields following
123 * @flags: flags for the channel
124 * @buffer: which buffer to use next (0/1)
125 * @last_completed: last completed cookie value
126 * @active: flattened chain of descriptors currently being processed
127 * @queue: pending descriptors which are handled next
128 * @free_list: list of free descriptors which can be used
129 * @runtime_addr: physical address currently used as dest/src (M2M only). This
130 * is set via %DMA_SLAVE_CONFIG before slave operation is
132 * @runtime_ctrl: M2M runtime values for the control register.
134 * As EP93xx DMA controller doesn't support real chained DMA descriptors we
135 * will have slightly different scheme here: @active points to a head of
136 * flattened DMA descriptor chain.
138 * @queue holds pending transactions. These are linked through the first
139 * descriptor in the chain. When a descriptor is moved to the @active queue,
140 * the first and chained descriptors are flattened into a single list.
142 * @chan.private holds pointer to &struct ep93xx_dma_data which contains
143 * necessary channel configuration information. For memcpy channels this must
146 struct ep93xx_dma_chan {
147 struct dma_chan chan;
148 const struct ep93xx_dma_engine *edma;
152 struct tasklet_struct tasklet;
153 /* protects the fields following */
156 /* Channel is configured for cyclic transfers */
157 #define EP93XX_DMA_IS_CYCLIC 0
160 dma_cookie_t last_completed;
161 struct list_head active;
162 struct list_head queue;
163 struct list_head free_list;
169 * struct ep93xx_dma_engine - the EP93xx DMA engine instance
170 * @dma_dev: holds the dmaengine device
171 * @m2m: is this an M2M or M2P device
172 * @hw_setup: method which sets the channel up for operation
173 * @hw_shutdown: shuts the channel down and flushes whatever is left
174 * @hw_submit: pushes active descriptor(s) to the hardware
175 * @hw_interrupt: handle the interrupt
176 * @num_channels: number of channels for this instance
177 * @channels: array of channels
179 * There is one instance of this struct for the M2P channels and one for the
180 * M2M channels. hw_xxx() methods are used to perform operations which are
181 * different on M2M and M2P channels. These methods are called with channel
182 * lock held and interrupts disabled so they cannot sleep.
184 struct ep93xx_dma_engine {
185 struct dma_device dma_dev;
187 int (*hw_setup)(struct ep93xx_dma_chan *);
188 void (*hw_shutdown)(struct ep93xx_dma_chan *);
189 void (*hw_submit)(struct ep93xx_dma_chan *);
190 int (*hw_interrupt)(struct ep93xx_dma_chan *);
191 #define INTERRUPT_UNKNOWN 0
192 #define INTERRUPT_DONE 1
193 #define INTERRUPT_NEXT_BUFFER 2
196 struct ep93xx_dma_chan channels[];
199 static inline struct device *chan2dev(struct ep93xx_dma_chan *edmac)
201 return &edmac->chan.dev->device;
204 static struct ep93xx_dma_chan *to_ep93xx_dma_chan(struct dma_chan *chan)
206 return container_of(chan, struct ep93xx_dma_chan, chan);
210 * ep93xx_dma_set_active - set new active descriptor chain
212 * @desc: head of the new active descriptor chain
214 * Sets @desc to be the head of the new active descriptor chain. This is the
215 * chain which is processed next. The active list must be empty before calling
218 * Called with @edmac->lock held and interrupts disabled.
220 static void ep93xx_dma_set_active(struct ep93xx_dma_chan *edmac,
221 struct ep93xx_dma_desc *desc)
223 BUG_ON(!list_empty(&edmac->active));
225 list_add_tail(&desc->node, &edmac->active);
227 /* Flatten the @desc->tx_list chain into @edmac->active list */
228 while (!list_empty(&desc->tx_list)) {
229 struct ep93xx_dma_desc *d = list_first_entry(&desc->tx_list,
230 struct ep93xx_dma_desc, node);
233 * We copy the callback parameters from the first descriptor
234 * to all the chained descriptors. This way we can call the
235 * callback without having to find out the first descriptor in
236 * the chain. Useful for cyclic transfers.
238 d->txd.callback = desc->txd.callback;
239 d->txd.callback_param = desc->txd.callback_param;
241 list_move_tail(&d->node, &edmac->active);
245 /* Called with @edmac->lock held and interrupts disabled */
246 static struct ep93xx_dma_desc *
247 ep93xx_dma_get_active(struct ep93xx_dma_chan *edmac)
249 return list_first_entry(&edmac->active, struct ep93xx_dma_desc, node);
253 * ep93xx_dma_advance_active - advances to the next active descriptor
256 * Function advances active descriptor to the next in the @edmac->active and
257 * returns %true if we still have descriptors in the chain to process.
258 * Otherwise returns %false.
260 * When the channel is in cyclic mode always returns %true.
262 * Called with @edmac->lock held and interrupts disabled.
264 static bool ep93xx_dma_advance_active(struct ep93xx_dma_chan *edmac)
266 list_rotate_left(&edmac->active);
268 if (test_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags))
272 * If txd.cookie is set it means that we are back in the first
273 * descriptor in the chain and hence done with it.
275 return !ep93xx_dma_get_active(edmac)->txd.cookie;
279 * M2P DMA implementation
282 static void m2p_set_control(struct ep93xx_dma_chan *edmac, u32 control)
284 writel(control, edmac->regs + M2P_CONTROL);
286 * EP93xx User's Guide states that we must perform a dummy read after
287 * write to the control register.
289 readl(edmac->regs + M2P_CONTROL);
292 static int m2p_hw_setup(struct ep93xx_dma_chan *edmac)
294 struct ep93xx_dma_data *data = edmac->chan.private;
297 writel(data->port & 0xf, edmac->regs + M2P_PPALLOC);
299 control = M2P_CONTROL_CH_ERROR_INT | M2P_CONTROL_ICE
300 | M2P_CONTROL_ENABLE;
301 m2p_set_control(edmac, control);
308 static inline u32 m2p_channel_state(struct ep93xx_dma_chan *edmac)
310 return (readl(edmac->regs + M2P_STATUS) >> 4) & 0x3;
313 static void m2p_hw_shutdown(struct ep93xx_dma_chan *edmac)
317 control = readl(edmac->regs + M2P_CONTROL);
318 control &= ~(M2P_CONTROL_STALLINT | M2P_CONTROL_NFBINT);
319 m2p_set_control(edmac, control);
321 while (m2p_channel_state(edmac) >= M2P_STATE_ON)
324 m2p_set_control(edmac, 0);
326 while (m2p_channel_state(edmac) == M2P_STATE_STALL)
330 static void m2p_fill_desc(struct ep93xx_dma_chan *edmac)
332 struct ep93xx_dma_desc *desc = ep93xx_dma_get_active(edmac);
335 if (ep93xx_dma_chan_direction(&edmac->chan) == DMA_TO_DEVICE)
336 bus_addr = desc->src_addr;
338 bus_addr = desc->dst_addr;
340 if (edmac->buffer == 0) {
341 writel(desc->size, edmac->regs + M2P_MAXCNT0);
342 writel(bus_addr, edmac->regs + M2P_BASE0);
344 writel(desc->size, edmac->regs + M2P_MAXCNT1);
345 writel(bus_addr, edmac->regs + M2P_BASE1);
351 static void m2p_hw_submit(struct ep93xx_dma_chan *edmac)
353 u32 control = readl(edmac->regs + M2P_CONTROL);
355 m2p_fill_desc(edmac);
356 control |= M2P_CONTROL_STALLINT;
358 if (ep93xx_dma_advance_active(edmac)) {
359 m2p_fill_desc(edmac);
360 control |= M2P_CONTROL_NFBINT;
363 m2p_set_control(edmac, control);
366 static int m2p_hw_interrupt(struct ep93xx_dma_chan *edmac)
368 u32 irq_status = readl(edmac->regs + M2P_INTERRUPT);
371 if (irq_status & M2P_INTERRUPT_ERROR) {
372 struct ep93xx_dma_desc *desc = ep93xx_dma_get_active(edmac);
374 /* Clear the error interrupt */
375 writel(1, edmac->regs + M2P_INTERRUPT);
378 * It seems that there is no easy way of reporting errors back
379 * to client so we just report the error here and continue as
382 * Revisit this when there is a mechanism to report back the
385 dev_err(chan2dev(edmac),
386 "DMA transfer failed! Details:\n"
388 "\tsrc_addr : 0x%08x\n"
389 "\tdst_addr : 0x%08x\n"
391 desc->txd.cookie, desc->src_addr, desc->dst_addr,
395 switch (irq_status & (M2P_INTERRUPT_STALL | M2P_INTERRUPT_NFB)) {
396 case M2P_INTERRUPT_STALL:
397 /* Disable interrupts */
398 control = readl(edmac->regs + M2P_CONTROL);
399 control &= ~(M2P_CONTROL_STALLINT | M2P_CONTROL_NFBINT);
400 m2p_set_control(edmac, control);
402 return INTERRUPT_DONE;
404 case M2P_INTERRUPT_NFB:
405 if (ep93xx_dma_advance_active(edmac))
406 m2p_fill_desc(edmac);
408 return INTERRUPT_NEXT_BUFFER;
411 return INTERRUPT_UNKNOWN;
415 * M2M DMA implementation
417 * For the M2M transfers we don't use NFB at all. This is because it simply
418 * doesn't work well with memcpy transfers. When you submit both buffers it is
419 * extremely unlikely that you get an NFB interrupt, but it instead reports
420 * DONE interrupt and both buffers are already transferred which means that we
421 * weren't able to update the next buffer.
423 * So for now we "simulate" NFB by just submitting buffer after buffer
424 * without double buffering.
427 static int m2m_hw_setup(struct ep93xx_dma_chan *edmac)
429 const struct ep93xx_dma_data *data = edmac->chan.private;
433 /* This is memcpy channel, nothing to configure */
434 writel(control, edmac->regs + M2M_CONTROL);
438 switch (data->port) {
441 * This was found via experimenting - anything less than 5
442 * causes the channel to perform only a partial transfer which
443 * leads to problems since we don't get DONE interrupt then.
445 control = (5 << M2M_CONTROL_PWSC_SHIFT);
446 control |= M2M_CONTROL_NO_HDSK;
448 if (data->direction == DMA_TO_DEVICE) {
449 control |= M2M_CONTROL_DAH;
450 control |= M2M_CONTROL_TM_TX;
451 control |= M2M_CONTROL_RSS_SSPTX;
453 control |= M2M_CONTROL_SAH;
454 control |= M2M_CONTROL_TM_RX;
455 control |= M2M_CONTROL_RSS_SSPRX;
461 * This IDE part is totally untested. Values below are taken
462 * from the EP93xx Users's Guide and might not be correct.
464 control |= M2M_CONTROL_NO_HDSK;
465 control |= M2M_CONTROL_RSS_IDE;
466 control |= M2M_CONTROL_PW_16;
468 if (data->direction == DMA_TO_DEVICE) {
469 /* Worst case from the UG */
470 control = (3 << M2M_CONTROL_PWSC_SHIFT);
471 control |= M2M_CONTROL_DAH;
472 control |= M2M_CONTROL_TM_TX;
474 control = (2 << M2M_CONTROL_PWSC_SHIFT);
475 control |= M2M_CONTROL_SAH;
476 control |= M2M_CONTROL_TM_RX;
484 writel(control, edmac->regs + M2M_CONTROL);
488 static void m2m_hw_shutdown(struct ep93xx_dma_chan *edmac)
490 /* Just disable the channel */
491 writel(0, edmac->regs + M2M_CONTROL);
494 static void m2m_fill_desc(struct ep93xx_dma_chan *edmac)
496 struct ep93xx_dma_desc *desc = ep93xx_dma_get_active(edmac);
498 if (edmac->buffer == 0) {
499 writel(desc->src_addr, edmac->regs + M2M_SAR_BASE0);
500 writel(desc->dst_addr, edmac->regs + M2M_DAR_BASE0);
501 writel(desc->size, edmac->regs + M2M_BCR0);
503 writel(desc->src_addr, edmac->regs + M2M_SAR_BASE1);
504 writel(desc->dst_addr, edmac->regs + M2M_DAR_BASE1);
505 writel(desc->size, edmac->regs + M2M_BCR1);
511 static void m2m_hw_submit(struct ep93xx_dma_chan *edmac)
513 struct ep93xx_dma_data *data = edmac->chan.private;
514 u32 control = readl(edmac->regs + M2M_CONTROL);
517 * Since we allow clients to configure PW (peripheral width) we always
518 * clear PW bits here and then set them according what is given in
519 * the runtime configuration.
521 control &= ~M2M_CONTROL_PW_MASK;
522 control |= edmac->runtime_ctrl;
524 m2m_fill_desc(edmac);
525 control |= M2M_CONTROL_DONEINT;
528 * Now we can finally enable the channel. For M2M channel this must be
529 * done _after_ the BCRx registers are programmed.
531 control |= M2M_CONTROL_ENABLE;
532 writel(control, edmac->regs + M2M_CONTROL);
536 * For memcpy channels the software trigger must be asserted
537 * in order to start the memcpy operation.
539 control |= M2M_CONTROL_START;
540 writel(control, edmac->regs + M2M_CONTROL);
544 static int m2m_hw_interrupt(struct ep93xx_dma_chan *edmac)
548 if (!(readl(edmac->regs + M2M_INTERRUPT) & M2M_INTERRUPT_DONEINT))
549 return INTERRUPT_UNKNOWN;
551 /* Clear the DONE bit */
552 writel(0, edmac->regs + M2M_INTERRUPT);
554 /* Disable interrupts and the channel */
555 control = readl(edmac->regs + M2M_CONTROL);
556 control &= ~(M2M_CONTROL_DONEINT | M2M_CONTROL_ENABLE);
557 writel(control, edmac->regs + M2M_CONTROL);
560 * Since we only get DONE interrupt we have to find out ourselves
561 * whether there still is something to process. So we try to advance
562 * the chain an see whether it succeeds.
564 if (ep93xx_dma_advance_active(edmac)) {
565 edmac->edma->hw_submit(edmac);
566 return INTERRUPT_NEXT_BUFFER;
569 return INTERRUPT_DONE;
573 * DMA engine API implementation
576 static struct ep93xx_dma_desc *
577 ep93xx_dma_desc_get(struct ep93xx_dma_chan *edmac)
579 struct ep93xx_dma_desc *desc, *_desc;
580 struct ep93xx_dma_desc *ret = NULL;
583 spin_lock_irqsave(&edmac->lock, flags);
584 list_for_each_entry_safe(desc, _desc, &edmac->free_list, node) {
585 if (async_tx_test_ack(&desc->txd)) {
586 list_del_init(&desc->node);
588 /* Re-initialize the descriptor */
592 desc->complete = false;
593 desc->txd.cookie = 0;
594 desc->txd.callback = NULL;
595 desc->txd.callback_param = NULL;
601 spin_unlock_irqrestore(&edmac->lock, flags);
605 static void ep93xx_dma_desc_put(struct ep93xx_dma_chan *edmac,
606 struct ep93xx_dma_desc *desc)
611 spin_lock_irqsave(&edmac->lock, flags);
612 list_splice_init(&desc->tx_list, &edmac->free_list);
613 list_add(&desc->node, &edmac->free_list);
614 spin_unlock_irqrestore(&edmac->lock, flags);
619 * ep93xx_dma_advance_work - start processing the next pending transaction
622 * If we have pending transactions queued and we are currently idling, this
623 * function takes the next queued transaction from the @edmac->queue and
624 * pushes it to the hardware for execution.
626 static void ep93xx_dma_advance_work(struct ep93xx_dma_chan *edmac)
628 struct ep93xx_dma_desc *new;
631 spin_lock_irqsave(&edmac->lock, flags);
632 if (!list_empty(&edmac->active) || list_empty(&edmac->queue)) {
633 spin_unlock_irqrestore(&edmac->lock, flags);
637 /* Take the next descriptor from the pending queue */
638 new = list_first_entry(&edmac->queue, struct ep93xx_dma_desc, node);
639 list_del_init(&new->node);
641 ep93xx_dma_set_active(edmac, new);
643 /* Push it to the hardware */
644 edmac->edma->hw_submit(edmac);
645 spin_unlock_irqrestore(&edmac->lock, flags);
648 static void ep93xx_dma_unmap_buffers(struct ep93xx_dma_desc *desc)
650 struct device *dev = desc->txd.chan->device->dev;
652 if (!(desc->txd.flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
653 if (desc->txd.flags & DMA_COMPL_SRC_UNMAP_SINGLE)
654 dma_unmap_single(dev, desc->src_addr, desc->size,
657 dma_unmap_page(dev, desc->src_addr, desc->size,
660 if (!(desc->txd.flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
661 if (desc->txd.flags & DMA_COMPL_DEST_UNMAP_SINGLE)
662 dma_unmap_single(dev, desc->dst_addr, desc->size,
665 dma_unmap_page(dev, desc->dst_addr, desc->size,
670 static void ep93xx_dma_tasklet(unsigned long data)
672 struct ep93xx_dma_chan *edmac = (struct ep93xx_dma_chan *)data;
673 struct ep93xx_dma_desc *desc, *d;
674 dma_async_tx_callback callback;
675 void *callback_param;
678 spin_lock_irq(&edmac->lock);
679 desc = ep93xx_dma_get_active(edmac);
680 if (desc->complete) {
681 edmac->last_completed = desc->txd.cookie;
682 list_splice_init(&edmac->active, &list);
684 spin_unlock_irq(&edmac->lock);
686 /* Pick up the next descriptor from the queue */
687 ep93xx_dma_advance_work(edmac);
689 callback = desc->txd.callback;
690 callback_param = desc->txd.callback_param;
692 /* Now we can release all the chained descriptors */
693 list_for_each_entry_safe(desc, d, &list, node) {
695 * For the memcpy channels the API requires us to unmap the
696 * buffers unless requested otherwise.
698 if (!edmac->chan.private)
699 ep93xx_dma_unmap_buffers(desc);
701 ep93xx_dma_desc_put(edmac, desc);
705 callback(callback_param);
708 static irqreturn_t ep93xx_dma_interrupt(int irq, void *dev_id)
710 struct ep93xx_dma_chan *edmac = dev_id;
711 irqreturn_t ret = IRQ_HANDLED;
713 spin_lock(&edmac->lock);
715 switch (edmac->edma->hw_interrupt(edmac)) {
717 ep93xx_dma_get_active(edmac)->complete = true;
718 tasklet_schedule(&edmac->tasklet);
721 case INTERRUPT_NEXT_BUFFER:
722 if (test_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags))
723 tasklet_schedule(&edmac->tasklet);
727 dev_warn(chan2dev(edmac), "unknown interrupt!\n");
732 spin_unlock(&edmac->lock);
737 * ep93xx_dma_tx_submit - set the prepared descriptor(s) to be executed
738 * @tx: descriptor to be executed
740 * Function will execute given descriptor on the hardware or if the hardware
741 * is busy, queue the descriptor to be executed later on. Returns cookie which
742 * can be used to poll the status of the descriptor.
744 static dma_cookie_t ep93xx_dma_tx_submit(struct dma_async_tx_descriptor *tx)
746 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(tx->chan);
747 struct ep93xx_dma_desc *desc;
751 spin_lock_irqsave(&edmac->lock, flags);
753 cookie = edmac->chan.cookie;
758 desc = container_of(tx, struct ep93xx_dma_desc, txd);
760 edmac->chan.cookie = cookie;
761 desc->txd.cookie = cookie;
764 * If nothing is currently prosessed, we push this descriptor
765 * directly to the hardware. Otherwise we put the descriptor
766 * to the pending queue.
768 if (list_empty(&edmac->active)) {
769 ep93xx_dma_set_active(edmac, desc);
770 edmac->edma->hw_submit(edmac);
772 list_add_tail(&desc->node, &edmac->queue);
775 spin_unlock_irqrestore(&edmac->lock, flags);
780 * ep93xx_dma_alloc_chan_resources - allocate resources for the channel
781 * @chan: channel to allocate resources
783 * Function allocates necessary resources for the given DMA channel and
784 * returns number of allocated descriptors for the channel. Negative errno
785 * is returned in case of failure.
787 static int ep93xx_dma_alloc_chan_resources(struct dma_chan *chan)
789 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
790 struct ep93xx_dma_data *data = chan->private;
791 const char *name = dma_chan_name(chan);
794 /* Sanity check the channel parameters */
795 if (!edmac->edma->m2m) {
798 if (data->port < EP93XX_DMA_I2S1 ||
799 data->port > EP93XX_DMA_IRDA)
801 if (data->direction != ep93xx_dma_chan_direction(chan))
805 switch (data->port) {
808 if (data->direction != DMA_TO_DEVICE &&
809 data->direction != DMA_FROM_DEVICE)
818 if (data && data->name)
821 ret = clk_enable(edmac->clk);
825 ret = request_irq(edmac->irq, ep93xx_dma_interrupt, 0, name, edmac);
827 goto fail_clk_disable;
829 spin_lock_irq(&edmac->lock);
830 edmac->last_completed = 1;
831 edmac->chan.cookie = 1;
832 ret = edmac->edma->hw_setup(edmac);
833 spin_unlock_irq(&edmac->lock);
838 for (i = 0; i < DMA_MAX_CHAN_DESCRIPTORS; i++) {
839 struct ep93xx_dma_desc *desc;
841 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
843 dev_warn(chan2dev(edmac), "not enough descriptors\n");
847 INIT_LIST_HEAD(&desc->tx_list);
849 dma_async_tx_descriptor_init(&desc->txd, chan);
850 desc->txd.flags = DMA_CTRL_ACK;
851 desc->txd.tx_submit = ep93xx_dma_tx_submit;
853 ep93xx_dma_desc_put(edmac, desc);
859 free_irq(edmac->irq, edmac);
861 clk_disable(edmac->clk);
867 * ep93xx_dma_free_chan_resources - release resources for the channel
870 * Function releases all the resources allocated for the given channel.
871 * The channel must be idle when this is called.
873 static void ep93xx_dma_free_chan_resources(struct dma_chan *chan)
875 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
876 struct ep93xx_dma_desc *desc, *d;
880 BUG_ON(!list_empty(&edmac->active));
881 BUG_ON(!list_empty(&edmac->queue));
883 spin_lock_irqsave(&edmac->lock, flags);
884 edmac->edma->hw_shutdown(edmac);
885 edmac->runtime_addr = 0;
886 edmac->runtime_ctrl = 0;
888 list_splice_init(&edmac->free_list, &list);
889 spin_unlock_irqrestore(&edmac->lock, flags);
891 list_for_each_entry_safe(desc, d, &list, node)
894 clk_disable(edmac->clk);
895 free_irq(edmac->irq, edmac);
899 * ep93xx_dma_prep_dma_memcpy - prepare a memcpy DMA operation
901 * @dest: destination bus address
902 * @src: source bus address
903 * @len: size of the transaction
904 * @flags: flags for the descriptor
906 * Returns a valid DMA descriptor or %NULL in case of failure.
908 static struct dma_async_tx_descriptor *
909 ep93xx_dma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest,
910 dma_addr_t src, size_t len, unsigned long flags)
912 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
913 struct ep93xx_dma_desc *desc, *first;
914 size_t bytes, offset;
917 for (offset = 0; offset < len; offset += bytes) {
918 desc = ep93xx_dma_desc_get(edmac);
920 dev_warn(chan2dev(edmac), "couln't get descriptor\n");
924 bytes = min_t(size_t, len - offset, DMA_MAX_CHAN_BYTES);
926 desc->src_addr = src + offset;
927 desc->dst_addr = dest + offset;
933 list_add_tail(&desc->node, &first->tx_list);
936 first->txd.cookie = -EBUSY;
937 first->txd.flags = flags;
941 ep93xx_dma_desc_put(edmac, first);
946 * ep93xx_dma_prep_slave_sg - prepare a slave DMA operation
948 * @sgl: list of buffers to transfer
949 * @sg_len: number of entries in @sgl
950 * @dir: direction of tha DMA transfer
951 * @flags: flags for the descriptor
953 * Returns a valid DMA descriptor or %NULL in case of failure.
955 static struct dma_async_tx_descriptor *
956 ep93xx_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
957 unsigned int sg_len, enum dma_data_direction dir,
960 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
961 struct ep93xx_dma_desc *desc, *first;
962 struct scatterlist *sg;
965 if (!edmac->edma->m2m && dir != ep93xx_dma_chan_direction(chan)) {
966 dev_warn(chan2dev(edmac),
967 "channel was configured with different direction\n");
971 if (test_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags)) {
972 dev_warn(chan2dev(edmac),
973 "channel is already used for cyclic transfers\n");
978 for_each_sg(sgl, sg, sg_len, i) {
979 size_t sg_len = sg_dma_len(sg);
981 if (sg_len > DMA_MAX_CHAN_BYTES) {
982 dev_warn(chan2dev(edmac), "too big transfer size %d\n",
987 desc = ep93xx_dma_desc_get(edmac);
989 dev_warn(chan2dev(edmac), "couln't get descriptor\n");
993 if (dir == DMA_TO_DEVICE) {
994 desc->src_addr = sg_dma_address(sg);
995 desc->dst_addr = edmac->runtime_addr;
997 desc->src_addr = edmac->runtime_addr;
998 desc->dst_addr = sg_dma_address(sg);
1000 desc->size = sg_len;
1005 list_add_tail(&desc->node, &first->tx_list);
1008 first->txd.cookie = -EBUSY;
1009 first->txd.flags = flags;
1014 ep93xx_dma_desc_put(edmac, first);
1019 * ep93xx_dma_prep_dma_cyclic - prepare a cyclic DMA operation
1021 * @dma_addr: DMA mapped address of the buffer
1022 * @buf_len: length of the buffer (in bytes)
1023 * @period_len: lenght of a single period
1024 * @dir: direction of the operation
1026 * Prepares a descriptor for cyclic DMA operation. This means that once the
1027 * descriptor is submitted, we will be submitting in a @period_len sized
1028 * buffers and calling callback once the period has been elapsed. Transfer
1029 * terminates only when client calls dmaengine_terminate_all() for this
1032 * Returns a valid DMA descriptor or %NULL in case of failure.
1034 static struct dma_async_tx_descriptor *
1035 ep93xx_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
1036 size_t buf_len, size_t period_len,
1037 enum dma_data_direction dir)
1039 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
1040 struct ep93xx_dma_desc *desc, *first;
1043 if (!edmac->edma->m2m && dir != ep93xx_dma_chan_direction(chan)) {
1044 dev_warn(chan2dev(edmac),
1045 "channel was configured with different direction\n");
1049 if (test_and_set_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags)) {
1050 dev_warn(chan2dev(edmac),
1051 "channel is already used for cyclic transfers\n");
1055 if (period_len > DMA_MAX_CHAN_BYTES) {
1056 dev_warn(chan2dev(edmac), "too big period length %d\n",
1061 /* Split the buffer into period size chunks */
1063 for (offset = 0; offset < buf_len; offset += period_len) {
1064 desc = ep93xx_dma_desc_get(edmac);
1066 dev_warn(chan2dev(edmac), "couln't get descriptor\n");
1070 if (dir == DMA_TO_DEVICE) {
1071 desc->src_addr = dma_addr + offset;
1072 desc->dst_addr = edmac->runtime_addr;
1074 desc->src_addr = edmac->runtime_addr;
1075 desc->dst_addr = dma_addr + offset;
1078 desc->size = period_len;
1083 list_add_tail(&desc->node, &first->tx_list);
1086 first->txd.cookie = -EBUSY;
1091 ep93xx_dma_desc_put(edmac, first);
1096 * ep93xx_dma_terminate_all - terminate all transactions
1099 * Stops all DMA transactions. All descriptors are put back to the
1100 * @edmac->free_list and callbacks are _not_ called.
1102 static int ep93xx_dma_terminate_all(struct ep93xx_dma_chan *edmac)
1104 struct ep93xx_dma_desc *desc, *_d;
1105 unsigned long flags;
1108 spin_lock_irqsave(&edmac->lock, flags);
1109 /* First we disable and flush the DMA channel */
1110 edmac->edma->hw_shutdown(edmac);
1111 clear_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags);
1112 list_splice_init(&edmac->active, &list);
1113 list_splice_init(&edmac->queue, &list);
1115 * We then re-enable the channel. This way we can continue submitting
1116 * the descriptors by just calling ->hw_submit() again.
1118 edmac->edma->hw_setup(edmac);
1119 spin_unlock_irqrestore(&edmac->lock, flags);
1121 list_for_each_entry_safe(desc, _d, &list, node)
1122 ep93xx_dma_desc_put(edmac, desc);
1127 static int ep93xx_dma_slave_config(struct ep93xx_dma_chan *edmac,
1128 struct dma_slave_config *config)
1130 enum dma_slave_buswidth width;
1131 unsigned long flags;
1134 if (!edmac->edma->m2m)
1137 switch (config->direction) {
1138 case DMA_FROM_DEVICE:
1139 width = config->src_addr_width;
1140 addr = config->src_addr;
1144 width = config->dst_addr_width;
1145 addr = config->dst_addr;
1153 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1156 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1157 ctrl = M2M_CONTROL_PW_16;
1159 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1160 ctrl = M2M_CONTROL_PW_32;
1166 spin_lock_irqsave(&edmac->lock, flags);
1167 edmac->runtime_addr = addr;
1168 edmac->runtime_ctrl = ctrl;
1169 spin_unlock_irqrestore(&edmac->lock, flags);
1175 * ep93xx_dma_control - manipulate all pending operations on a channel
1177 * @cmd: control command to perform
1178 * @arg: optional argument
1180 * Controls the channel. Function returns %0 in case of success or negative
1181 * error in case of failure.
1183 static int ep93xx_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1186 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
1187 struct dma_slave_config *config;
1190 case DMA_TERMINATE_ALL:
1191 return ep93xx_dma_terminate_all(edmac);
1193 case DMA_SLAVE_CONFIG:
1194 config = (struct dma_slave_config *)arg;
1195 return ep93xx_dma_slave_config(edmac, config);
1205 * ep93xx_dma_tx_status - check if a transaction is completed
1207 * @cookie: transaction specific cookie
1208 * @state: state of the transaction is stored here if given
1210 * This function can be used to query state of a given transaction.
1212 static enum dma_status ep93xx_dma_tx_status(struct dma_chan *chan,
1213 dma_cookie_t cookie,
1214 struct dma_tx_state *state)
1216 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
1217 dma_cookie_t last_used, last_completed;
1218 enum dma_status ret;
1219 unsigned long flags;
1221 spin_lock_irqsave(&edmac->lock, flags);
1222 last_used = chan->cookie;
1223 last_completed = edmac->last_completed;
1224 spin_unlock_irqrestore(&edmac->lock, flags);
1226 ret = dma_async_is_complete(cookie, last_completed, last_used);
1227 dma_set_tx_state(state, last_completed, last_used, 0);
1233 * ep93xx_dma_issue_pending - push pending transactions to the hardware
1236 * When this function is called, all pending transactions are pushed to the
1237 * hardware and executed.
1239 static void ep93xx_dma_issue_pending(struct dma_chan *chan)
1241 ep93xx_dma_advance_work(to_ep93xx_dma_chan(chan));
1244 static int __init ep93xx_dma_probe(struct platform_device *pdev)
1246 struct ep93xx_dma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1247 struct ep93xx_dma_engine *edma;
1248 struct dma_device *dma_dev;
1252 edma_size = pdata->num_channels * sizeof(struct ep93xx_dma_chan);
1253 edma = kzalloc(sizeof(*edma) + edma_size, GFP_KERNEL);
1257 dma_dev = &edma->dma_dev;
1258 edma->m2m = platform_get_device_id(pdev)->driver_data;
1259 edma->num_channels = pdata->num_channels;
1261 INIT_LIST_HEAD(&dma_dev->channels);
1262 for (i = 0; i < pdata->num_channels; i++) {
1263 const struct ep93xx_dma_chan_data *cdata = &pdata->channels[i];
1264 struct ep93xx_dma_chan *edmac = &edma->channels[i];
1266 edmac->chan.device = dma_dev;
1267 edmac->regs = cdata->base;
1268 edmac->irq = cdata->irq;
1271 edmac->clk = clk_get(NULL, cdata->name);
1272 if (IS_ERR(edmac->clk)) {
1273 dev_warn(&pdev->dev, "failed to get clock for %s\n",
1278 spin_lock_init(&edmac->lock);
1279 INIT_LIST_HEAD(&edmac->active);
1280 INIT_LIST_HEAD(&edmac->queue);
1281 INIT_LIST_HEAD(&edmac->free_list);
1282 tasklet_init(&edmac->tasklet, ep93xx_dma_tasklet,
1283 (unsigned long)edmac);
1285 list_add_tail(&edmac->chan.device_node,
1286 &dma_dev->channels);
1289 dma_cap_zero(dma_dev->cap_mask);
1290 dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
1291 dma_cap_set(DMA_CYCLIC, dma_dev->cap_mask);
1293 dma_dev->dev = &pdev->dev;
1294 dma_dev->device_alloc_chan_resources = ep93xx_dma_alloc_chan_resources;
1295 dma_dev->device_free_chan_resources = ep93xx_dma_free_chan_resources;
1296 dma_dev->device_prep_slave_sg = ep93xx_dma_prep_slave_sg;
1297 dma_dev->device_prep_dma_cyclic = ep93xx_dma_prep_dma_cyclic;
1298 dma_dev->device_control = ep93xx_dma_control;
1299 dma_dev->device_issue_pending = ep93xx_dma_issue_pending;
1300 dma_dev->device_tx_status = ep93xx_dma_tx_status;
1302 dma_set_max_seg_size(dma_dev->dev, DMA_MAX_CHAN_BYTES);
1305 dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
1306 dma_dev->device_prep_dma_memcpy = ep93xx_dma_prep_dma_memcpy;
1308 edma->hw_setup = m2m_hw_setup;
1309 edma->hw_shutdown = m2m_hw_shutdown;
1310 edma->hw_submit = m2m_hw_submit;
1311 edma->hw_interrupt = m2m_hw_interrupt;
1313 dma_cap_set(DMA_PRIVATE, dma_dev->cap_mask);
1315 edma->hw_setup = m2p_hw_setup;
1316 edma->hw_shutdown = m2p_hw_shutdown;
1317 edma->hw_submit = m2p_hw_submit;
1318 edma->hw_interrupt = m2p_hw_interrupt;
1321 ret = dma_async_device_register(dma_dev);
1322 if (unlikely(ret)) {
1323 for (i = 0; i < edma->num_channels; i++) {
1324 struct ep93xx_dma_chan *edmac = &edma->channels[i];
1325 if (!IS_ERR_OR_NULL(edmac->clk))
1326 clk_put(edmac->clk);
1330 dev_info(dma_dev->dev, "EP93xx M2%s DMA ready\n",
1331 edma->m2m ? "M" : "P");
1337 static struct platform_device_id ep93xx_dma_driver_ids[] = {
1338 { "ep93xx-dma-m2p", 0 },
1339 { "ep93xx-dma-m2m", 1 },
1343 static struct platform_driver ep93xx_dma_driver = {
1345 .name = "ep93xx-dma",
1347 .id_table = ep93xx_dma_driver_ids,
1350 static int __init ep93xx_dma_module_init(void)
1352 return platform_driver_probe(&ep93xx_dma_driver, ep93xx_dma_probe);
1354 subsys_initcall(ep93xx_dma_module_init);
1356 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
1357 MODULE_DESCRIPTION("EP93xx DMA driver");
1358 MODULE_LICENSE("GPL");