2 * Copyright (c) 2006 ARM Ltd.
3 * Copyright (c) 2010 ST-Ericsson SA
5 * Author: Peter Pearse <peter.pearse@arm.com>
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 * The full GNU General Public License is in this distribution in the file
25 * Documentation: ARM DDI 0196G == PL080
26 * Documentation: ARM DDI 0218E == PL081
28 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any
31 * The PL080 has 8 channels available for simultaneous use, and the PL081
32 * has only two channels. So on these DMA controllers the number of channels
33 * and the number of incoming DMA signals are two totally different things.
34 * It is usually not possible to theoretically handle all physical signals,
35 * so a multiplexing scheme with possible denial of use is necessary.
37 * The PL080 has a dual bus master, PL081 has a single master.
39 * Memory to peripheral transfer may be visualized as
40 * Get data from memory to DMAC
42 * On burst request from peripheral
43 * Destination burst from DMAC to peripheral
45 * Raise terminal count interrupt
47 * For peripherals with a FIFO:
48 * Source burst size == half the depth of the peripheral FIFO
49 * Destination burst size == the depth of the peripheral FIFO
51 * (Bursts are irrelevant for mem to mem transfers - there are no burst
52 * signals, the DMA controller will simply facilitate its AHB master.)
54 * ASSUMES default (little) endianness for DMA transfers
56 * The PL08x has two flow control settings:
57 * - DMAC flow control: the transfer size defines the number of transfers
58 * which occur for the current LLI entry, and the DMAC raises TC at the
59 * end of every LLI entry. Observed behaviour shows the DMAC listening
60 * to both the BREQ and SREQ signals (contrary to documented),
61 * transferring data if either is active. The LBREQ and LSREQ signals
64 * - Peripheral flow control: the transfer size is ignored (and should be
65 * zero). The data is transferred from the current LLI entry, until
66 * after the final transfer signalled by LBREQ or LSREQ. The DMAC
67 * will then move to the next LLI entry.
70 * - Break out common code from arch/arm/mach-s3c64xx and share
72 #include <linux/amba/bus.h>
73 #include <linux/amba/pl08x.h>
74 #include <linux/debugfs.h>
75 #include <linux/delay.h>
76 #include <linux/device.h>
77 #include <linux/dmaengine.h>
78 #include <linux/dmapool.h>
79 #include <linux/dma-mapping.h>
80 #include <linux/init.h>
81 #include <linux/interrupt.h>
82 #include <linux/module.h>
83 #include <linux/pm_runtime.h>
84 #include <linux/seq_file.h>
85 #include <linux/slab.h>
86 #include <asm/hardware/pl080.h>
88 #include "dmaengine.h"
90 #define DRIVER_NAME "pl08xdmac"
92 static struct amba_driver pl08x_amba_driver;
93 struct pl08x_driver_data;
96 * struct vendor_data - vendor-specific config parameters for PL08x derivatives
97 * @channels: the number of channels available in this variant
98 * @dualmaster: whether this version supports dual AHB masters or not.
99 * @nomadik: whether the channels have Nomadik security extension bits
100 * that need to be checked for permission before use and some registers are
110 * PL08X private data structures
111 * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit,
112 * start & end do not - their bus bit info is in cctl. Also note that these
113 * are fixed 32-bit quantities.
123 * struct pl08x_bus_data - information of source or destination
124 * busses for a transfer
125 * @addr: current address
126 * @maxwidth: the maximum width of a transfer on this bus
127 * @buswidth: the width of this bus in bytes: 1, 2 or 4
129 struct pl08x_bus_data {
136 * struct pl08x_phy_chan - holder for the physical channels
137 * @id: physical index to this channel
138 * @lock: a lock to use when altering an instance of this struct
139 * @signal: the physical signal (aka channel) serving this physical channel
141 * @serving: the virtual channel currently being served by this physical
144 struct pl08x_phy_chan {
149 struct pl08x_dma_chan *serving;
153 * struct pl08x_sg - structure containing data per sg
154 * @src_addr: src address of sg
155 * @dst_addr: dst address of sg
156 * @len: transfer len in bytes
157 * @node: node for txd's dsg_list
163 struct list_head node;
167 * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
168 * @tx: async tx descriptor
169 * @node: node for txd list for channels
170 * @dsg_list: list of children sg's
171 * @direction: direction of transfer
172 * @llis_bus: DMA memory address (physical) start for the LLIs
173 * @llis_va: virtual memory address start for the LLIs
174 * @cctl: control reg values for current txd
175 * @ccfg: config reg values for current txd
178 struct dma_async_tx_descriptor tx;
179 struct list_head node;
180 struct list_head dsg_list;
181 enum dma_transfer_direction direction;
183 struct pl08x_lli *llis_va;
184 /* Default cctl value for LLIs */
187 * Settings to be put into the physical channel when we
188 * trigger this txd. Other registers are in llis_va[0].
194 * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel
196 * @PL08X_CHAN_IDLE: the channel is idle
197 * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
198 * channel and is running a transfer on it
199 * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport
200 * channel, but the transfer is currently paused
201 * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport
202 * channel to become available (only pertains to memcpy channels)
204 enum pl08x_dma_chan_state {
212 * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
213 * @chan: wrappped abstract channel
214 * @phychan: the physical channel utilized by this channel, if there is one
215 * @phychan_hold: if non-zero, hold on to the physical channel even if we
216 * have no pending entries
217 * @tasklet: tasklet scheduled by the IRQ to handle actual work etc
218 * @name: name of channel
219 * @cd: channel platform data
220 * @runtime_addr: address for RX/TX according to the runtime config
221 * @pend_list: queued transactions pending on this channel
222 * @at: active transaction on this channel
223 * @lock: a lock for this channel data
224 * @host: a pointer to the host (internal use)
225 * @state: whether the channel is idle, paused, running etc
226 * @slave: whether this channel is a device (slave) or for memcpy
227 * @waiting: a TX descriptor on this channel which is waiting for a physical
228 * channel to become available
230 struct pl08x_dma_chan {
231 struct dma_chan chan;
232 struct pl08x_phy_chan *phychan;
234 struct tasklet_struct tasklet;
236 const struct pl08x_channel_data *cd;
237 struct dma_slave_config cfg;
238 struct list_head pend_list;
239 struct pl08x_txd *at;
241 struct pl08x_driver_data *host;
242 enum pl08x_dma_chan_state state;
244 struct pl08x_txd *waiting;
248 * struct pl08x_driver_data - the local state holder for the PL08x
249 * @slave: slave engine for this instance
250 * @memcpy: memcpy engine for this instance
251 * @base: virtual memory base (remapped) for the PL08x
252 * @adev: the corresponding AMBA (PrimeCell) bus entry
253 * @vd: vendor data for this PL08x variant
254 * @pd: platform data passed in from the platform/machine
255 * @phy_chans: array of data for the physical channels
256 * @pool: a pool for the LLI descriptors
257 * @pool_ctr: counter of LLIs in the pool
258 * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI
260 * @mem_buses: set to indicate memory transfers on AHB2.
261 * @lock: a spinlock for this struct
263 struct pl08x_driver_data {
264 struct dma_device slave;
265 struct dma_device memcpy;
267 struct amba_device *adev;
268 const struct vendor_data *vd;
269 struct pl08x_platform_data *pd;
270 struct pl08x_phy_chan *phy_chans;
271 struct dma_pool *pool;
278 * PL08X specific defines
281 /* Size (bytes) of each LLI buffer allocated for one transfer */
282 # define PL08X_LLI_TSFR_SIZE 0x2000
284 /* Maximum times we call dma_pool_alloc on this pool without freeing */
285 #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
286 #define PL08X_ALIGN 8
288 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
290 return container_of(chan, struct pl08x_dma_chan, chan);
293 static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx)
295 return container_of(tx, struct pl08x_txd, tx);
299 * Physical channel handling
302 /* Whether a certain channel is busy or not */
303 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
307 val = readl(ch->base + PL080_CH_CONFIG);
308 return val & PL080_CONFIG_ACTIVE;
312 * Set the initial DMA register values i.e. those for the first LLI
313 * The next LLI pointer and the configuration interrupt bit have
314 * been set when the LLIs were constructed. Poke them into the hardware
315 * and start the transfer.
317 static void pl08x_start_txd(struct pl08x_dma_chan *plchan,
318 struct pl08x_txd *txd)
320 struct pl08x_driver_data *pl08x = plchan->host;
321 struct pl08x_phy_chan *phychan = plchan->phychan;
322 struct pl08x_lli *lli = &txd->llis_va[0];
327 /* Wait for channel inactive */
328 while (pl08x_phy_channel_busy(phychan))
331 dev_vdbg(&pl08x->adev->dev,
332 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
333 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
334 phychan->id, lli->src, lli->dst, lli->lli, lli->cctl,
337 writel(lli->src, phychan->base + PL080_CH_SRC_ADDR);
338 writel(lli->dst, phychan->base + PL080_CH_DST_ADDR);
339 writel(lli->lli, phychan->base + PL080_CH_LLI);
340 writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
341 writel(txd->ccfg, phychan->base + PL080_CH_CONFIG);
343 /* Enable the DMA channel */
344 /* Do not access config register until channel shows as disabled */
345 while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id))
348 /* Do not access config register until channel shows as inactive */
349 val = readl(phychan->base + PL080_CH_CONFIG);
350 while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
351 val = readl(phychan->base + PL080_CH_CONFIG);
353 writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG);
357 * Pause the channel by setting the HALT bit.
359 * For M->P transfers, pause the DMAC first and then stop the peripheral -
360 * the FIFO can only drain if the peripheral is still requesting data.
361 * (note: this can still timeout if the DMAC FIFO never drains of data.)
363 * For P->M transfers, disable the peripheral first to stop it filling
364 * the DMAC FIFO, and then pause the DMAC.
366 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
371 /* Set the HALT bit and wait for the FIFO to drain */
372 val = readl(ch->base + PL080_CH_CONFIG);
373 val |= PL080_CONFIG_HALT;
374 writel(val, ch->base + PL080_CH_CONFIG);
376 /* Wait for channel inactive */
377 for (timeout = 1000; timeout; timeout--) {
378 if (!pl08x_phy_channel_busy(ch))
382 if (pl08x_phy_channel_busy(ch))
383 pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id);
386 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
390 /* Clear the HALT bit */
391 val = readl(ch->base + PL080_CH_CONFIG);
392 val &= ~PL080_CONFIG_HALT;
393 writel(val, ch->base + PL080_CH_CONFIG);
397 * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and
398 * clears any pending interrupt status. This should not be used for
399 * an on-going transfer, but as a method of shutting down a channel
400 * (eg, when it's no longer used) or terminating a transfer.
402 static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x,
403 struct pl08x_phy_chan *ch)
405 u32 val = readl(ch->base + PL080_CH_CONFIG);
407 val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK |
408 PL080_CONFIG_TC_IRQ_MASK);
410 writel(val, ch->base + PL080_CH_CONFIG);
412 writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR);
413 writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR);
416 static inline u32 get_bytes_in_cctl(u32 cctl)
418 /* The source width defines the number of bytes */
419 u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
421 switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
422 case PL080_WIDTH_8BIT:
424 case PL080_WIDTH_16BIT:
427 case PL080_WIDTH_32BIT:
434 /* The channel should be paused when calling this */
435 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
437 struct pl08x_phy_chan *ch;
438 struct pl08x_txd *txd;
442 spin_lock_irqsave(&plchan->lock, flags);
443 ch = plchan->phychan;
447 * Follow the LLIs to get the number of remaining
448 * bytes in the currently active transaction.
451 u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
453 /* First get the remaining bytes in the active transfer */
454 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
457 struct pl08x_lli *llis_va = txd->llis_va;
458 dma_addr_t llis_bus = txd->llis_bus;
461 BUG_ON(clli < llis_bus || clli >= llis_bus +
462 sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS);
465 * Locate the next LLI - as this is an array,
466 * it's simple maths to find.
468 index = (clli - llis_bus) / sizeof(struct pl08x_lli);
470 for (; index < MAX_NUM_TSFR_LLIS; index++) {
471 bytes += get_bytes_in_cctl(llis_va[index].cctl);
474 * A LLI pointer of 0 terminates the LLI list
476 if (!llis_va[index].lli)
482 /* Sum up all queued transactions */
483 if (!list_empty(&plchan->pend_list)) {
484 struct pl08x_txd *txdi;
485 list_for_each_entry(txdi, &plchan->pend_list, node) {
486 struct pl08x_sg *dsg;
487 list_for_each_entry(dsg, &txd->dsg_list, node)
492 spin_unlock_irqrestore(&plchan->lock, flags);
498 * Allocate a physical channel for a virtual channel
500 * Try to locate a physical channel to be used for this transfer. If all
501 * are taken return NULL and the requester will have to cope by using
502 * some fallback PIO mode or retrying later.
504 static struct pl08x_phy_chan *
505 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
506 struct pl08x_dma_chan *virt_chan)
508 struct pl08x_phy_chan *ch = NULL;
512 for (i = 0; i < pl08x->vd->channels; i++) {
513 ch = &pl08x->phy_chans[i];
515 spin_lock_irqsave(&ch->lock, flags);
517 if (!ch->locked && !ch->serving) {
518 ch->serving = virt_chan;
520 spin_unlock_irqrestore(&ch->lock, flags);
524 spin_unlock_irqrestore(&ch->lock, flags);
527 if (i == pl08x->vd->channels) {
528 /* No physical channel available, cope with it */
535 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
536 struct pl08x_phy_chan *ch)
540 spin_lock_irqsave(&ch->lock, flags);
542 /* Stop the channel and clear its interrupts */
543 pl08x_terminate_phy_chan(pl08x, ch);
545 /* Mark it as free */
547 spin_unlock_irqrestore(&ch->lock, flags);
554 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
557 case PL080_WIDTH_8BIT:
559 case PL080_WIDTH_16BIT:
561 case PL080_WIDTH_32BIT:
570 static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
575 /* Remove all src, dst and transfer size bits */
576 retbits &= ~PL080_CONTROL_DWIDTH_MASK;
577 retbits &= ~PL080_CONTROL_SWIDTH_MASK;
578 retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
580 /* Then set the bits according to the parameters */
583 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
586 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
589 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
598 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
601 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
604 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
611 retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
615 struct pl08x_lli_build_data {
616 struct pl08x_txd *txd;
617 struct pl08x_bus_data srcbus;
618 struct pl08x_bus_data dstbus;
624 * Autoselect a master bus to use for the transfer. Slave will be the chosen as
625 * victim in case src & dest are not similarly aligned. i.e. If after aligning
626 * masters address with width requirements of transfer (by sending few byte by
627 * byte data), slave is still not aligned, then its width will be reduced to
629 * - prefers the destination bus if both available
630 * - prefers bus with fixed address (i.e. peripheral)
632 static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd,
633 struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl)
635 if (!(cctl & PL080_CONTROL_DST_INCR)) {
638 } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
642 if (bd->dstbus.buswidth >= bd->srcbus.buswidth) {
653 * Fills in one LLI for a certain transfer descriptor and advance the counter
655 static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd,
656 int num_llis, int len, u32 cctl)
658 struct pl08x_lli *llis_va = bd->txd->llis_va;
659 dma_addr_t llis_bus = bd->txd->llis_bus;
661 BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
663 llis_va[num_llis].cctl = cctl;
664 llis_va[num_llis].src = bd->srcbus.addr;
665 llis_va[num_llis].dst = bd->dstbus.addr;
666 llis_va[num_llis].lli = llis_bus + (num_llis + 1) *
667 sizeof(struct pl08x_lli);
668 llis_va[num_llis].lli |= bd->lli_bus;
670 if (cctl & PL080_CONTROL_SRC_INCR)
671 bd->srcbus.addr += len;
672 if (cctl & PL080_CONTROL_DST_INCR)
673 bd->dstbus.addr += len;
675 BUG_ON(bd->remainder < len);
677 bd->remainder -= len;
680 static inline void prep_byte_width_lli(struct pl08x_lli_build_data *bd,
681 u32 *cctl, u32 len, int num_llis, size_t *total_bytes)
683 *cctl = pl08x_cctl_bits(*cctl, 1, 1, len);
684 pl08x_fill_lli_for_desc(bd, num_llis, len, *cctl);
685 (*total_bytes) += len;
689 * This fills in the table of LLIs for the transfer descriptor
690 * Note that we assume we never have to change the burst sizes
693 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
694 struct pl08x_txd *txd)
696 struct pl08x_bus_data *mbus, *sbus;
697 struct pl08x_lli_build_data bd;
699 u32 cctl, early_bytes = 0;
700 size_t max_bytes_per_lli, total_bytes;
701 struct pl08x_lli *llis_va;
702 struct pl08x_sg *dsg;
704 txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, &txd->llis_bus);
706 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
713 bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0;
716 /* Find maximum width of the source bus */
718 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
719 PL080_CONTROL_SWIDTH_SHIFT);
721 /* Find maximum width of the destination bus */
723 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
724 PL080_CONTROL_DWIDTH_SHIFT);
726 list_for_each_entry(dsg, &txd->dsg_list, node) {
730 bd.srcbus.addr = dsg->src_addr;
731 bd.dstbus.addr = dsg->dst_addr;
732 bd.remainder = dsg->len;
733 bd.srcbus.buswidth = bd.srcbus.maxwidth;
734 bd.dstbus.buswidth = bd.dstbus.maxwidth;
736 pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl);
738 dev_vdbg(&pl08x->adev->dev, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu\n",
739 bd.srcbus.addr, cctl & PL080_CONTROL_SRC_INCR ? "+" : "",
741 bd.dstbus.addr, cctl & PL080_CONTROL_DST_INCR ? "+" : "",
744 dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n",
745 mbus == &bd.srcbus ? "src" : "dst",
746 sbus == &bd.srcbus ? "src" : "dst");
749 * Zero length is only allowed if all these requirements are
751 * - flow controller is peripheral.
752 * - src.addr is aligned to src.width
753 * - dst.addr is aligned to dst.width
755 * sg_len == 1 should be true, as there can be two cases here:
757 * - Memory addresses are contiguous and are not scattered.
758 * Here, Only one sg will be passed by user driver, with
759 * memory address and zero length. We pass this to controller
760 * and after the transfer it will receive the last burst
761 * request from peripheral and so transfer finishes.
763 * - Memory addresses are scattered and are not contiguous.
764 * Here, Obviously as DMA controller doesn't know when a lli's
765 * transfer gets over, it can't load next lli. So in this
766 * case, there has to be an assumption that only one lli is
767 * supported. Thus, we can't have scattered addresses.
770 u32 fc = (txd->ccfg & PL080_CONFIG_FLOW_CONTROL_MASK) >>
771 PL080_CONFIG_FLOW_CONTROL_SHIFT;
772 if (!((fc >= PL080_FLOW_SRC2DST_DST) &&
773 (fc <= PL080_FLOW_SRC2DST_SRC))) {
774 dev_err(&pl08x->adev->dev, "%s sg len can't be zero",
779 if ((bd.srcbus.addr % bd.srcbus.buswidth) ||
780 (bd.dstbus.addr % bd.dstbus.buswidth)) {
781 dev_err(&pl08x->adev->dev,
782 "%s src & dst address must be aligned to src"
783 " & dst width if peripheral is flow controller",
788 cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth,
789 bd.dstbus.buswidth, 0);
790 pl08x_fill_lli_for_desc(&bd, num_llis++, 0, cctl);
795 * Send byte by byte for following cases
796 * - Less than a bus width available
797 * - until master bus is aligned
799 if (bd.remainder < mbus->buswidth)
800 early_bytes = bd.remainder;
801 else if ((mbus->addr) % (mbus->buswidth)) {
802 early_bytes = mbus->buswidth - (mbus->addr) %
804 if ((bd.remainder - early_bytes) < mbus->buswidth)
805 early_bytes = bd.remainder;
809 dev_vdbg(&pl08x->adev->dev,
810 "%s byte width LLIs (remain 0x%08x)\n",
811 __func__, bd.remainder);
812 prep_byte_width_lli(&bd, &cctl, early_bytes, num_llis++,
819 * - if slave is not then we must set its width down
821 if (sbus->addr % sbus->buswidth) {
822 dev_dbg(&pl08x->adev->dev,
823 "%s set down bus width to one byte\n",
830 * Bytes transferred = tsize * src width, not
833 max_bytes_per_lli = bd.srcbus.buswidth *
834 PL080_CONTROL_TRANSFER_SIZE_MASK;
835 dev_vdbg(&pl08x->adev->dev,
836 "%s max bytes per lli = %zu\n",
837 __func__, max_bytes_per_lli);
840 * Make largest possible LLIs until less than one bus
843 while (bd.remainder > (mbus->buswidth - 1)) {
844 size_t lli_len, tsize, width;
847 * If enough left try to send max possible,
848 * otherwise try to send the remainder
850 lli_len = min(bd.remainder, max_bytes_per_lli);
853 * Check against maximum bus alignment:
854 * Calculate actual transfer size in relation to
855 * bus width an get a maximum remainder of the
856 * highest bus width - 1
858 width = max(mbus->buswidth, sbus->buswidth);
859 lli_len = (lli_len / width) * width;
860 tsize = lli_len / bd.srcbus.buswidth;
862 dev_vdbg(&pl08x->adev->dev,
863 "%s fill lli with single lli chunk of "
864 "size 0x%08zx (remainder 0x%08zx)\n",
865 __func__, lli_len, bd.remainder);
867 cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth,
868 bd.dstbus.buswidth, tsize);
869 pl08x_fill_lli_for_desc(&bd, num_llis++,
871 total_bytes += lli_len;
878 dev_vdbg(&pl08x->adev->dev,
879 "%s align with boundary, send odd bytes (remain %zu)\n",
880 __func__, bd.remainder);
881 prep_byte_width_lli(&bd, &cctl, bd.remainder,
882 num_llis++, &total_bytes);
886 if (total_bytes != dsg->len) {
887 dev_err(&pl08x->adev->dev,
888 "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
889 __func__, total_bytes, dsg->len);
893 if (num_llis >= MAX_NUM_TSFR_LLIS) {
894 dev_err(&pl08x->adev->dev,
895 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
896 __func__, (u32) MAX_NUM_TSFR_LLIS);
901 llis_va = txd->llis_va;
902 /* The final LLI terminates the LLI. */
903 llis_va[num_llis - 1].lli = 0;
904 /* The final LLI element shall also fire an interrupt. */
905 llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
911 dev_vdbg(&pl08x->adev->dev,
912 "%-3s %-9s %-10s %-10s %-10s %s\n",
913 "lli", "", "csrc", "cdst", "clli", "cctl");
914 for (i = 0; i < num_llis; i++) {
915 dev_vdbg(&pl08x->adev->dev,
916 "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n",
917 i, &llis_va[i], llis_va[i].src,
918 llis_va[i].dst, llis_va[i].lli, llis_va[i].cctl
927 /* You should call this with the struct pl08x lock held */
928 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
929 struct pl08x_txd *txd)
931 struct pl08x_sg *dsg, *_dsg;
935 dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
939 list_for_each_entry_safe(dsg, _dsg, &txd->dsg_list, node) {
940 list_del(&dsg->node);
947 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
948 struct pl08x_dma_chan *plchan)
950 struct pl08x_txd *txdi = NULL;
951 struct pl08x_txd *next;
953 if (!list_empty(&plchan->pend_list)) {
954 list_for_each_entry_safe(txdi,
955 next, &plchan->pend_list, node) {
956 list_del(&txdi->node);
957 pl08x_free_txd(pl08x, txdi);
965 static int pl08x_alloc_chan_resources(struct dma_chan *chan)
970 static void pl08x_free_chan_resources(struct dma_chan *chan)
975 * This should be called with the channel plchan->lock held
977 static int prep_phy_channel(struct pl08x_dma_chan *plchan,
978 struct pl08x_txd *txd)
980 struct pl08x_driver_data *pl08x = plchan->host;
981 struct pl08x_phy_chan *ch;
984 /* Check if we already have a channel */
985 if (plchan->phychan) {
986 ch = plchan->phychan;
990 ch = pl08x_get_phy_channel(pl08x, plchan);
992 /* No physical channel available, cope with it */
993 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
998 * OK we have a physical channel: for memcpy() this is all we
999 * need, but for slaves the physical signals may be muxed!
1000 * Can the platform allow us to use this channel?
1002 if (plchan->slave && pl08x->pd->get_signal) {
1003 ret = pl08x->pd->get_signal(plchan->cd);
1005 dev_dbg(&pl08x->adev->dev,
1006 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
1007 ch->id, plchan->name);
1008 /* Release physical channel & return */
1009 pl08x_put_phy_channel(pl08x, ch);
1015 plchan->phychan = ch;
1016 dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
1022 /* Assign the flow control signal to this channel */
1023 if (txd->direction == DMA_MEM_TO_DEV)
1024 txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT;
1025 else if (txd->direction == DMA_DEV_TO_MEM)
1026 txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT;
1028 plchan->phychan_hold++;
1033 static void release_phy_channel(struct pl08x_dma_chan *plchan)
1035 struct pl08x_driver_data *pl08x = plchan->host;
1037 if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) {
1038 pl08x->pd->put_signal(plchan->cd, plchan->phychan->signal);
1039 plchan->phychan->signal = -1;
1041 pl08x_put_phy_channel(pl08x, plchan->phychan);
1042 plchan->phychan = NULL;
1045 static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
1047 struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
1048 struct pl08x_txd *txd = to_pl08x_txd(tx);
1049 unsigned long flags;
1050 dma_cookie_t cookie;
1052 spin_lock_irqsave(&plchan->lock, flags);
1053 cookie = dma_cookie_assign(tx);
1055 /* Put this onto the pending list */
1056 list_add_tail(&txd->node, &plchan->pend_list);
1059 * If there was no physical channel available for this memcpy,
1060 * stack the request up and indicate that the channel is waiting
1061 * for a free physical channel.
1063 if (!plchan->slave && !plchan->phychan) {
1064 /* Do this memcpy whenever there is a channel ready */
1065 plchan->state = PL08X_CHAN_WAITING;
1066 plchan->waiting = txd;
1068 plchan->phychan_hold--;
1071 spin_unlock_irqrestore(&plchan->lock, flags);
1076 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
1077 struct dma_chan *chan, unsigned long flags)
1079 struct dma_async_tx_descriptor *retval = NULL;
1085 * Code accessing dma_async_is_complete() in a tight loop may give problems.
1086 * If slaves are relying on interrupts to signal completion this function
1087 * must not be called with interrupts disabled.
1089 static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan,
1090 dma_cookie_t cookie, struct dma_tx_state *txstate)
1092 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1093 enum dma_status ret;
1095 ret = dma_cookie_status(chan, cookie, txstate);
1096 if (ret == DMA_SUCCESS)
1100 * This cookie not complete yet
1101 * Get number of bytes left in the active transactions and queue
1103 dma_set_residue(txstate, pl08x_getbytes_chan(plchan));
1105 if (plchan->state == PL08X_CHAN_PAUSED)
1108 /* Whether waiting or running, we're in progress */
1109 return DMA_IN_PROGRESS;
1112 /* PrimeCell DMA extension */
1113 struct burst_table {
1118 static const struct burst_table burst_sizes[] = {
1121 .reg = PL080_BSIZE_256,
1125 .reg = PL080_BSIZE_128,
1129 .reg = PL080_BSIZE_64,
1133 .reg = PL080_BSIZE_32,
1137 .reg = PL080_BSIZE_16,
1141 .reg = PL080_BSIZE_8,
1145 .reg = PL080_BSIZE_4,
1149 .reg = PL080_BSIZE_1,
1154 * Given the source and destination available bus masks, select which
1155 * will be routed to each port. We try to have source and destination
1156 * on separate ports, but always respect the allowable settings.
1158 static u32 pl08x_select_bus(u8 src, u8 dst)
1162 if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1)))
1163 cctl |= PL080_CONTROL_DST_AHB2;
1164 if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2)))
1165 cctl |= PL080_CONTROL_SRC_AHB2;
1170 static u32 pl08x_cctl(u32 cctl)
1172 cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 |
1173 PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR |
1174 PL080_CONTROL_PROT_MASK);
1176 /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1177 return cctl | PL080_CONTROL_PROT_SYS;
1180 static u32 pl08x_width(enum dma_slave_buswidth width)
1183 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1184 return PL080_WIDTH_8BIT;
1185 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1186 return PL080_WIDTH_16BIT;
1187 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1188 return PL080_WIDTH_32BIT;
1194 static u32 pl08x_burst(u32 maxburst)
1198 for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
1199 if (burst_sizes[i].burstwords <= maxburst)
1202 return burst_sizes[i].reg;
1205 static u32 pl08x_get_cctl(struct pl08x_dma_chan *plchan,
1206 enum dma_slave_buswidth addr_width, u32 maxburst)
1208 u32 width, burst, cctl = 0;
1210 width = pl08x_width(addr_width);
1214 cctl |= width << PL080_CONTROL_SWIDTH_SHIFT;
1215 cctl |= width << PL080_CONTROL_DWIDTH_SHIFT;
1218 * If this channel will only request single transfers, set this
1219 * down to ONE element. Also select one element if no maxburst
1222 if (plchan->cd->single)
1225 burst = pl08x_burst(maxburst);
1226 cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT;
1227 cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT;
1229 return pl08x_cctl(cctl);
1232 static int dma_set_runtime_config(struct dma_chan *chan,
1233 struct dma_slave_config *config)
1235 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1240 /* Reject definitely invalid configurations */
1241 if (config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
1242 config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
1245 plchan->cfg = *config;
1251 * Slave transactions callback to the slave device to allow
1252 * synchronization of slave DMA signals with the DMAC enable
1254 static void pl08x_issue_pending(struct dma_chan *chan)
1256 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1257 unsigned long flags;
1259 spin_lock_irqsave(&plchan->lock, flags);
1260 /* Something is already active, or we're waiting for a channel... */
1261 if (plchan->at || plchan->state == PL08X_CHAN_WAITING) {
1262 spin_unlock_irqrestore(&plchan->lock, flags);
1266 /* Take the first element in the queue and execute it */
1267 if (!list_empty(&plchan->pend_list)) {
1268 struct pl08x_txd *next;
1270 next = list_first_entry(&plchan->pend_list,
1273 list_del(&next->node);
1274 plchan->state = PL08X_CHAN_RUNNING;
1276 pl08x_start_txd(plchan, next);
1279 spin_unlock_irqrestore(&plchan->lock, flags);
1282 static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
1283 struct pl08x_txd *txd)
1285 struct pl08x_driver_data *pl08x = plchan->host;
1286 unsigned long flags;
1289 num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
1291 spin_lock_irqsave(&plchan->lock, flags);
1292 pl08x_free_txd(pl08x, txd);
1293 spin_unlock_irqrestore(&plchan->lock, flags);
1297 spin_lock_irqsave(&plchan->lock, flags);
1300 * See if we already have a physical channel allocated,
1301 * else this is the time to try to get one.
1303 ret = prep_phy_channel(plchan, txd);
1306 * No physical channel was available.
1308 * memcpy transfers can be sorted out at submission time.
1310 * Slave transfers may have been denied due to platform
1311 * channel muxing restrictions. Since there is no guarantee
1312 * that this will ever be resolved, and the signal must be
1313 * acquired AFTER acquiring the physical channel, we will let
1314 * them be NACK:ed with -EBUSY here. The drivers can retry
1315 * the prep() call if they are eager on doing this using DMA.
1317 if (plchan->slave) {
1318 pl08x_free_txd_list(pl08x, plchan);
1319 pl08x_free_txd(pl08x, txd);
1320 spin_unlock_irqrestore(&plchan->lock, flags);
1325 * Else we're all set, paused and ready to roll, status
1326 * will switch to PL08X_CHAN_RUNNING when we call
1327 * issue_pending(). If there is something running on the
1328 * channel already we don't change its state.
1330 if (plchan->state == PL08X_CHAN_IDLE)
1331 plchan->state = PL08X_CHAN_PAUSED;
1333 spin_unlock_irqrestore(&plchan->lock, flags);
1338 static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan,
1339 unsigned long flags)
1341 struct pl08x_txd *txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
1344 dma_async_tx_descriptor_init(&txd->tx, &plchan->chan);
1345 txd->tx.flags = flags;
1346 txd->tx.tx_submit = pl08x_tx_submit;
1347 INIT_LIST_HEAD(&txd->node);
1348 INIT_LIST_HEAD(&txd->dsg_list);
1350 /* Always enable error and terminal interrupts */
1351 txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK |
1352 PL080_CONFIG_TC_IRQ_MASK;
1358 * Initialize a descriptor to be used by memcpy submit
1360 static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1361 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1362 size_t len, unsigned long flags)
1364 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1365 struct pl08x_driver_data *pl08x = plchan->host;
1366 struct pl08x_txd *txd;
1367 struct pl08x_sg *dsg;
1370 txd = pl08x_get_txd(plchan, flags);
1372 dev_err(&pl08x->adev->dev,
1373 "%s no memory for descriptor\n", __func__);
1377 dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT);
1379 pl08x_free_txd(pl08x, txd);
1380 dev_err(&pl08x->adev->dev, "%s no memory for pl080 sg\n",
1384 list_add_tail(&dsg->node, &txd->dsg_list);
1386 txd->direction = DMA_MEM_TO_MEM;
1387 dsg->src_addr = src;
1388 dsg->dst_addr = dest;
1391 /* Set platform data for m2m */
1392 txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1393 txd->cctl = pl08x->pd->memcpy_channel.cctl_memcpy &
1394 ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
1396 /* Both to be incremented or the code will break */
1397 txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
1399 if (pl08x->vd->dualmaster)
1400 txd->cctl |= pl08x_select_bus(pl08x->mem_buses,
1403 ret = pl08x_prep_channel_resources(plchan, txd);
1410 static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1411 struct dma_chan *chan, struct scatterlist *sgl,
1412 unsigned int sg_len, enum dma_transfer_direction direction,
1413 unsigned long flags, void *context)
1415 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1416 struct pl08x_driver_data *pl08x = plchan->host;
1417 struct pl08x_txd *txd;
1418 struct pl08x_sg *dsg;
1419 struct scatterlist *sg;
1420 enum dma_slave_buswidth addr_width;
1421 dma_addr_t slave_addr;
1423 u8 src_buses, dst_buses;
1426 dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1427 __func__, sg_dma_len(sgl), plchan->name);
1429 txd = pl08x_get_txd(plchan, flags);
1431 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1436 * Set up addresses, the PrimeCell configured address
1437 * will take precedence since this may configure the
1438 * channel target address dynamically at runtime.
1440 txd->direction = direction;
1442 if (direction == DMA_MEM_TO_DEV) {
1443 cctl = PL080_CONTROL_SRC_INCR;
1444 slave_addr = plchan->cfg.dst_addr;
1445 addr_width = plchan->cfg.dst_addr_width;
1446 maxburst = plchan->cfg.dst_maxburst;
1447 src_buses = pl08x->mem_buses;
1448 dst_buses = plchan->cd->periph_buses;
1449 } else if (direction == DMA_DEV_TO_MEM) {
1450 cctl = PL080_CONTROL_DST_INCR;
1451 slave_addr = plchan->cfg.src_addr;
1452 addr_width = plchan->cfg.src_addr_width;
1453 maxburst = plchan->cfg.src_maxburst;
1454 src_buses = plchan->cd->periph_buses;
1455 dst_buses = pl08x->mem_buses;
1457 pl08x_free_txd(pl08x, txd);
1458 dev_err(&pl08x->adev->dev,
1459 "%s direction unsupported\n", __func__);
1463 cctl |= pl08x_get_cctl(plchan, addr_width, maxburst);
1465 pl08x_free_txd(pl08x, txd);
1466 dev_err(&pl08x->adev->dev,
1467 "DMA slave configuration botched?\n");
1471 txd->cctl = cctl | pl08x_select_bus(src_buses, dst_buses);
1473 if (plchan->cfg.device_fc)
1474 tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER_PER :
1475 PL080_FLOW_PER2MEM_PER;
1477 tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER :
1480 txd->ccfg |= tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1482 for_each_sg(sgl, sg, sg_len, tmp) {
1483 dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT);
1485 pl08x_free_txd(pl08x, txd);
1486 dev_err(&pl08x->adev->dev, "%s no mem for pl080 sg\n",
1490 list_add_tail(&dsg->node, &txd->dsg_list);
1492 dsg->len = sg_dma_len(sg);
1493 if (direction == DMA_MEM_TO_DEV) {
1494 dsg->src_addr = sg_dma_address(sg);
1495 dsg->dst_addr = slave_addr;
1497 dsg->src_addr = slave_addr;
1498 dsg->dst_addr = sg_dma_address(sg);
1502 ret = pl08x_prep_channel_resources(plchan, txd);
1509 static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1512 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1513 struct pl08x_driver_data *pl08x = plchan->host;
1514 unsigned long flags;
1517 /* Controls applicable to inactive channels */
1518 if (cmd == DMA_SLAVE_CONFIG) {
1519 return dma_set_runtime_config(chan,
1520 (struct dma_slave_config *)arg);
1524 * Anything succeeds on channels with no physical allocation and
1525 * no queued transfers.
1527 spin_lock_irqsave(&plchan->lock, flags);
1528 if (!plchan->phychan && !plchan->at) {
1529 spin_unlock_irqrestore(&plchan->lock, flags);
1534 case DMA_TERMINATE_ALL:
1535 plchan->state = PL08X_CHAN_IDLE;
1537 if (plchan->phychan) {
1538 pl08x_terminate_phy_chan(pl08x, plchan->phychan);
1541 * Mark physical channel as free and free any slave
1544 release_phy_channel(plchan);
1545 plchan->phychan_hold = 0;
1547 /* Dequeue jobs and free LLIs */
1549 pl08x_free_txd(pl08x, plchan->at);
1552 /* Dequeue jobs not yet fired as well */
1553 pl08x_free_txd_list(pl08x, plchan);
1556 pl08x_pause_phy_chan(plchan->phychan);
1557 plchan->state = PL08X_CHAN_PAUSED;
1560 pl08x_resume_phy_chan(plchan->phychan);
1561 plchan->state = PL08X_CHAN_RUNNING;
1564 /* Unknown command */
1569 spin_unlock_irqrestore(&plchan->lock, flags);
1574 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1576 struct pl08x_dma_chan *plchan;
1577 char *name = chan_id;
1579 /* Reject channels for devices not bound to this driver */
1580 if (chan->device->dev->driver != &pl08x_amba_driver.drv)
1583 plchan = to_pl08x_chan(chan);
1585 /* Check that the channel is not taken! */
1586 if (!strcmp(plchan->name, name))
1593 * Just check that the device is there and active
1594 * TODO: turn this bit on/off depending on the number of physical channels
1595 * actually used, if it is zero... well shut it off. That will save some
1596 * power. Cut the clock at the same time.
1598 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1600 /* The Nomadik variant does not have the config register */
1601 if (pl08x->vd->nomadik)
1603 writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG);
1606 static void pl08x_unmap_buffers(struct pl08x_txd *txd)
1608 struct device *dev = txd->tx.chan->device->dev;
1609 struct pl08x_sg *dsg;
1611 if (!(txd->tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
1612 if (txd->tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE)
1613 list_for_each_entry(dsg, &txd->dsg_list, node)
1614 dma_unmap_single(dev, dsg->src_addr, dsg->len,
1617 list_for_each_entry(dsg, &txd->dsg_list, node)
1618 dma_unmap_page(dev, dsg->src_addr, dsg->len,
1622 if (!(txd->tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
1623 if (txd->tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE)
1624 list_for_each_entry(dsg, &txd->dsg_list, node)
1625 dma_unmap_single(dev, dsg->dst_addr, dsg->len,
1628 list_for_each_entry(dsg, &txd->dsg_list, node)
1629 dma_unmap_page(dev, dsg->dst_addr, dsg->len,
1634 static void pl08x_tasklet(unsigned long data)
1636 struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
1637 struct pl08x_driver_data *pl08x = plchan->host;
1638 struct pl08x_txd *txd;
1639 unsigned long flags;
1641 spin_lock_irqsave(&plchan->lock, flags);
1647 /* Update last completed */
1648 dma_cookie_complete(&txd->tx);
1651 /* If a new descriptor is queued, set it up plchan->at is NULL here */
1652 if (!list_empty(&plchan->pend_list)) {
1653 struct pl08x_txd *next;
1655 next = list_first_entry(&plchan->pend_list,
1658 list_del(&next->node);
1660 pl08x_start_txd(plchan, next);
1661 } else if (plchan->phychan_hold) {
1663 * This channel is still in use - we have a new txd being
1664 * prepared and will soon be queued. Don't give up the
1668 struct pl08x_dma_chan *waiting = NULL;
1671 * No more jobs, so free up the physical channel
1672 * Free any allocated signal on slave transfers too
1674 release_phy_channel(plchan);
1675 plchan->state = PL08X_CHAN_IDLE;
1678 * And NOW before anyone else can grab that free:d up
1679 * physical channel, see if there is some memcpy pending
1680 * that seriously needs to start because of being stacked
1681 * up while we were choking the physical channels with data.
1683 list_for_each_entry(waiting, &pl08x->memcpy.channels,
1685 if (waiting->state == PL08X_CHAN_WAITING &&
1686 waiting->waiting != NULL) {
1689 /* This should REALLY not fail now */
1690 ret = prep_phy_channel(waiting,
1693 waiting->phychan_hold--;
1694 waiting->state = PL08X_CHAN_RUNNING;
1695 waiting->waiting = NULL;
1696 pl08x_issue_pending(&waiting->chan);
1702 spin_unlock_irqrestore(&plchan->lock, flags);
1705 dma_async_tx_callback callback = txd->tx.callback;
1706 void *callback_param = txd->tx.callback_param;
1708 /* Don't try to unmap buffers on slave channels */
1710 pl08x_unmap_buffers(txd);
1712 /* Free the descriptor */
1713 spin_lock_irqsave(&plchan->lock, flags);
1714 pl08x_free_txd(pl08x, txd);
1715 spin_unlock_irqrestore(&plchan->lock, flags);
1717 /* Callback to signal completion */
1719 callback(callback_param);
1723 static irqreturn_t pl08x_irq(int irq, void *dev)
1725 struct pl08x_driver_data *pl08x = dev;
1726 u32 mask = 0, err, tc, i;
1728 /* check & clear - ERR & TC interrupts */
1729 err = readl(pl08x->base + PL080_ERR_STATUS);
1731 dev_err(&pl08x->adev->dev, "%s error interrupt, register value 0x%08x\n",
1733 writel(err, pl08x->base + PL080_ERR_CLEAR);
1735 tc = readl(pl08x->base + PL080_TC_STATUS);
1737 writel(tc, pl08x->base + PL080_TC_CLEAR);
1742 for (i = 0; i < pl08x->vd->channels; i++) {
1743 if (((1 << i) & err) || ((1 << i) & tc)) {
1744 /* Locate physical channel */
1745 struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
1746 struct pl08x_dma_chan *plchan = phychan->serving;
1749 dev_err(&pl08x->adev->dev,
1750 "%s Error TC interrupt on unused channel: 0x%08x\n",
1755 /* Schedule tasklet on this channel */
1756 tasklet_schedule(&plchan->tasklet);
1761 return mask ? IRQ_HANDLED : IRQ_NONE;
1764 static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan)
1767 chan->name = chan->cd->bus_id;
1768 chan->cfg.src_addr = chan->cd->addr;
1769 chan->cfg.dst_addr = chan->cd->addr;
1773 * Initialise the DMAC memcpy/slave channels.
1774 * Make a local wrapper to hold required data
1776 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
1777 struct dma_device *dmadev, unsigned int channels, bool slave)
1779 struct pl08x_dma_chan *chan;
1782 INIT_LIST_HEAD(&dmadev->channels);
1785 * Register as many many memcpy as we have physical channels,
1786 * we won't always be able to use all but the code will have
1787 * to cope with that situation.
1789 for (i = 0; i < channels; i++) {
1790 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
1792 dev_err(&pl08x->adev->dev,
1793 "%s no memory for channel\n", __func__);
1798 chan->state = PL08X_CHAN_IDLE;
1801 chan->cd = &pl08x->pd->slave_channels[i];
1802 pl08x_dma_slave_init(chan);
1804 chan->cd = &pl08x->pd->memcpy_channel;
1805 chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1811 dev_dbg(&pl08x->adev->dev,
1812 "initialize virtual channel \"%s\"\n",
1815 chan->chan.device = dmadev;
1816 dma_cookie_init(&chan->chan);
1818 spin_lock_init(&chan->lock);
1819 INIT_LIST_HEAD(&chan->pend_list);
1820 tasklet_init(&chan->tasklet, pl08x_tasklet,
1821 (unsigned long) chan);
1823 list_add_tail(&chan->chan.device_node, &dmadev->channels);
1825 dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
1826 i, slave ? "slave" : "memcpy");
1830 static void pl08x_free_virtual_channels(struct dma_device *dmadev)
1832 struct pl08x_dma_chan *chan = NULL;
1833 struct pl08x_dma_chan *next;
1835 list_for_each_entry_safe(chan,
1836 next, &dmadev->channels, chan.device_node) {
1837 list_del(&chan->chan.device_node);
1842 #ifdef CONFIG_DEBUG_FS
1843 static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
1846 case PL08X_CHAN_IDLE:
1848 case PL08X_CHAN_RUNNING:
1850 case PL08X_CHAN_PAUSED:
1852 case PL08X_CHAN_WAITING:
1857 return "UNKNOWN STATE";
1860 static int pl08x_debugfs_show(struct seq_file *s, void *data)
1862 struct pl08x_driver_data *pl08x = s->private;
1863 struct pl08x_dma_chan *chan;
1864 struct pl08x_phy_chan *ch;
1865 unsigned long flags;
1868 seq_printf(s, "PL08x physical channels:\n");
1869 seq_printf(s, "CHANNEL:\tUSER:\n");
1870 seq_printf(s, "--------\t-----\n");
1871 for (i = 0; i < pl08x->vd->channels; i++) {
1872 struct pl08x_dma_chan *virt_chan;
1874 ch = &pl08x->phy_chans[i];
1876 spin_lock_irqsave(&ch->lock, flags);
1877 virt_chan = ch->serving;
1879 seq_printf(s, "%d\t\t%s%s\n",
1881 virt_chan ? virt_chan->name : "(none)",
1882 ch->locked ? " LOCKED" : "");
1884 spin_unlock_irqrestore(&ch->lock, flags);
1887 seq_printf(s, "\nPL08x virtual memcpy channels:\n");
1888 seq_printf(s, "CHANNEL:\tSTATE:\n");
1889 seq_printf(s, "--------\t------\n");
1890 list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) {
1891 seq_printf(s, "%s\t\t%s\n", chan->name,
1892 pl08x_state_str(chan->state));
1895 seq_printf(s, "\nPL08x virtual slave channels:\n");
1896 seq_printf(s, "CHANNEL:\tSTATE:\n");
1897 seq_printf(s, "--------\t------\n");
1898 list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) {
1899 seq_printf(s, "%s\t\t%s\n", chan->name,
1900 pl08x_state_str(chan->state));
1906 static int pl08x_debugfs_open(struct inode *inode, struct file *file)
1908 return single_open(file, pl08x_debugfs_show, inode->i_private);
1911 static const struct file_operations pl08x_debugfs_operations = {
1912 .open = pl08x_debugfs_open,
1914 .llseek = seq_lseek,
1915 .release = single_release,
1918 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1920 /* Expose a simple debugfs interface to view all clocks */
1921 (void) debugfs_create_file(dev_name(&pl08x->adev->dev),
1922 S_IFREG | S_IRUGO, NULL, pl08x,
1923 &pl08x_debugfs_operations);
1927 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1932 static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
1934 struct pl08x_driver_data *pl08x;
1935 const struct vendor_data *vd = id->data;
1939 ret = amba_request_regions(adev, NULL);
1943 /* Create the driver state holder */
1944 pl08x = kzalloc(sizeof(*pl08x), GFP_KERNEL);
1950 /* Initialize memcpy engine */
1951 dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
1952 pl08x->memcpy.dev = &adev->dev;
1953 pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1954 pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
1955 pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
1956 pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1957 pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
1958 pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
1959 pl08x->memcpy.device_control = pl08x_control;
1961 /* Initialize slave engine */
1962 dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
1963 pl08x->slave.dev = &adev->dev;
1964 pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1965 pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
1966 pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1967 pl08x->slave.device_tx_status = pl08x_dma_tx_status;
1968 pl08x->slave.device_issue_pending = pl08x_issue_pending;
1969 pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
1970 pl08x->slave.device_control = pl08x_control;
1972 /* Get the platform data */
1973 pl08x->pd = dev_get_platdata(&adev->dev);
1975 dev_err(&adev->dev, "no platform data supplied\n");
1976 goto out_no_platdata;
1979 /* Assign useful pointers to the driver state */
1983 /* By default, AHB1 only. If dualmaster, from platform */
1984 pl08x->lli_buses = PL08X_AHB1;
1985 pl08x->mem_buses = PL08X_AHB1;
1986 if (pl08x->vd->dualmaster) {
1987 pl08x->lli_buses = pl08x->pd->lli_buses;
1988 pl08x->mem_buses = pl08x->pd->mem_buses;
1991 /* A DMA memory pool for LLIs, align on 1-byte boundary */
1992 pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
1993 PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
1996 goto out_no_lli_pool;
1999 pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
2002 goto out_no_ioremap;
2005 /* Turn on the PL08x */
2006 pl08x_ensure_on(pl08x);
2008 /* Attach the interrupt handler */
2009 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
2010 writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
2012 ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
2013 DRIVER_NAME, pl08x);
2015 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
2016 __func__, adev->irq[0]);
2020 /* Initialize physical channels */
2021 pl08x->phy_chans = kzalloc((vd->channels * sizeof(*pl08x->phy_chans)),
2023 if (!pl08x->phy_chans) {
2024 dev_err(&adev->dev, "%s failed to allocate "
2025 "physical channel holders\n",
2027 goto out_no_phychans;
2030 for (i = 0; i < vd->channels; i++) {
2031 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
2034 ch->base = pl08x->base + PL080_Cx_BASE(i);
2035 spin_lock_init(&ch->lock);
2039 * Nomadik variants can have channels that are locked
2040 * down for the secure world only. Lock up these channels
2041 * by perpetually serving a dummy virtual channel.
2046 val = readl(ch->base + PL080_CH_CONFIG);
2047 if (val & (PL080N_CONFIG_ITPROT | PL080N_CONFIG_SECPROT)) {
2048 dev_info(&adev->dev, "physical channel %d reserved for secure access only\n", i);
2053 dev_dbg(&adev->dev, "physical channel %d is %s\n",
2054 i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
2057 /* Register as many memcpy channels as there are physical channels */
2058 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
2059 pl08x->vd->channels, false);
2061 dev_warn(&pl08x->adev->dev,
2062 "%s failed to enumerate memcpy channels - %d\n",
2066 pl08x->memcpy.chancnt = ret;
2068 /* Register slave channels */
2069 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
2070 pl08x->pd->num_slave_channels, true);
2072 dev_warn(&pl08x->adev->dev,
2073 "%s failed to enumerate slave channels - %d\n",
2077 pl08x->slave.chancnt = ret;
2079 ret = dma_async_device_register(&pl08x->memcpy);
2081 dev_warn(&pl08x->adev->dev,
2082 "%s failed to register memcpy as an async device - %d\n",
2084 goto out_no_memcpy_reg;
2087 ret = dma_async_device_register(&pl08x->slave);
2089 dev_warn(&pl08x->adev->dev,
2090 "%s failed to register slave as an async device - %d\n",
2092 goto out_no_slave_reg;
2095 amba_set_drvdata(adev, pl08x);
2096 init_pl08x_debugfs(pl08x);
2097 dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
2098 amba_part(adev), amba_rev(adev),
2099 (unsigned long long)adev->res.start, adev->irq[0]);
2104 dma_async_device_unregister(&pl08x->memcpy);
2106 pl08x_free_virtual_channels(&pl08x->slave);
2108 pl08x_free_virtual_channels(&pl08x->memcpy);
2110 kfree(pl08x->phy_chans);
2112 free_irq(adev->irq[0], pl08x);
2114 iounmap(pl08x->base);
2116 dma_pool_destroy(pl08x->pool);
2121 amba_release_regions(adev);
2125 /* PL080 has 8 channels and the PL080 have just 2 */
2126 static struct vendor_data vendor_pl080 = {
2131 static struct vendor_data vendor_nomadik = {
2137 static struct vendor_data vendor_pl081 = {
2139 .dualmaster = false,
2142 static struct amba_id pl08x_ids[] = {
2147 .data = &vendor_pl080,
2153 .data = &vendor_pl081,
2155 /* Nomadik 8815 PL080 variant */
2159 .data = &vendor_nomadik,
2164 MODULE_DEVICE_TABLE(amba, pl08x_ids);
2166 static struct amba_driver pl08x_amba_driver = {
2167 .drv.name = DRIVER_NAME,
2168 .id_table = pl08x_ids,
2169 .probe = pl08x_probe,
2172 static int __init pl08x_init(void)
2175 retval = amba_driver_register(&pl08x_amba_driver);
2177 printk(KERN_WARNING DRIVER_NAME
2178 "failed to register as an AMBA device (%d)\n",
2182 subsys_initcall(pl08x_init);