2 * Copyright (c) 2006 ARM Ltd.
3 * Copyright (c) 2010 ST-Ericsson SA
5 * Author: Peter Pearse <peter.pearse@arm.com>
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 * The full GNU General Public License is in this distribution in the file
25 * Documentation: ARM DDI 0196G == PL080
26 * Documentation: ARM DDI 0218E == PL081
28 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any
31 * The PL080 has 8 channels available for simultaneous use, and the PL081
32 * has only two channels. So on these DMA controllers the number of channels
33 * and the number of incoming DMA signals are two totally different things.
34 * It is usually not possible to theoretically handle all physical signals,
35 * so a multiplexing scheme with possible denial of use is necessary.
37 * The PL080 has a dual bus master, PL081 has a single master.
39 * Memory to peripheral transfer may be visualized as
40 * Get data from memory to DMAC
42 * On burst request from peripheral
43 * Destination burst from DMAC to peripheral
45 * Raise terminal count interrupt
47 * For peripherals with a FIFO:
48 * Source burst size == half the depth of the peripheral FIFO
49 * Destination burst size == the depth of the peripheral FIFO
51 * (Bursts are irrelevant for mem to mem transfers - there are no burst
52 * signals, the DMA controller will simply facilitate its AHB master.)
54 * ASSUMES default (little) endianness for DMA transfers
56 * The PL08x has two flow control settings:
57 * - DMAC flow control: the transfer size defines the number of transfers
58 * which occur for the current LLI entry, and the DMAC raises TC at the
59 * end of every LLI entry. Observed behaviour shows the DMAC listening
60 * to both the BREQ and SREQ signals (contrary to documented),
61 * transferring data if either is active. The LBREQ and LSREQ signals
64 * - Peripheral flow control: the transfer size is ignored (and should be
65 * zero). The data is transferred from the current LLI entry, until
66 * after the final transfer signalled by LBREQ or LSREQ. The DMAC
67 * will then move to the next LLI entry.
70 * - Break out common code from arch/arm/mach-s3c64xx and share
72 #include <linux/amba/bus.h>
73 #include <linux/amba/pl08x.h>
74 #include <linux/debugfs.h>
75 #include <linux/delay.h>
76 #include <linux/device.h>
77 #include <linux/dmaengine.h>
78 #include <linux/dmapool.h>
79 #include <linux/dma-mapping.h>
80 #include <linux/init.h>
81 #include <linux/interrupt.h>
82 #include <linux/module.h>
83 #include <linux/pm_runtime.h>
84 #include <linux/seq_file.h>
85 #include <linux/slab.h>
86 #include <asm/hardware/pl080.h>
88 #include "dmaengine.h"
90 #define DRIVER_NAME "pl08xdmac"
92 static struct amba_driver pl08x_amba_driver;
93 struct pl08x_driver_data;
96 * struct vendor_data - vendor-specific config parameters for PL08x derivatives
97 * @channels: the number of channels available in this variant
98 * @dualmaster: whether this version supports dual AHB masters or not.
99 * @nomadik: whether the channels have Nomadik security extension bits
100 * that need to be checked for permission before use and some registers are
110 * PL08X private data structures
111 * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit,
112 * start & end do not - their bus bit info is in cctl. Also note that these
113 * are fixed 32-bit quantities.
123 * struct pl08x_bus_data - information of source or destination
124 * busses for a transfer
125 * @addr: current address
126 * @maxwidth: the maximum width of a transfer on this bus
127 * @buswidth: the width of this bus in bytes: 1, 2 or 4
129 struct pl08x_bus_data {
136 * struct pl08x_phy_chan - holder for the physical channels
137 * @id: physical index to this channel
138 * @lock: a lock to use when altering an instance of this struct
139 * @signal: the physical signal (aka channel) serving this physical channel
141 * @serving: the virtual channel currently being served by this physical
144 struct pl08x_phy_chan {
149 struct pl08x_dma_chan *serving;
153 * struct pl08x_sg - structure containing data per sg
154 * @src_addr: src address of sg
155 * @dst_addr: dst address of sg
156 * @len: transfer len in bytes
157 * @node: node for txd's dsg_list
163 struct list_head node;
167 * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
168 * @tx: async tx descriptor
169 * @node: node for txd list for channels
170 * @dsg_list: list of children sg's
171 * @direction: direction of transfer
172 * @llis_bus: DMA memory address (physical) start for the LLIs
173 * @llis_va: virtual memory address start for the LLIs
174 * @cctl: control reg values for current txd
175 * @ccfg: config reg values for current txd
178 struct dma_async_tx_descriptor tx;
179 struct list_head node;
180 struct list_head dsg_list;
181 enum dma_transfer_direction direction;
183 struct pl08x_lli *llis_va;
184 /* Default cctl value for LLIs */
187 * Settings to be put into the physical channel when we
188 * trigger this txd. Other registers are in llis_va[0].
194 * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel
196 * @PL08X_CHAN_IDLE: the channel is idle
197 * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
198 * channel and is running a transfer on it
199 * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport
200 * channel, but the transfer is currently paused
201 * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport
202 * channel to become available (only pertains to memcpy channels)
204 enum pl08x_dma_chan_state {
212 * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
213 * @chan: wrappped abstract channel
214 * @phychan: the physical channel utilized by this channel, if there is one
215 * @phychan_hold: if non-zero, hold on to the physical channel even if we
216 * have no pending entries
217 * @tasklet: tasklet scheduled by the IRQ to handle actual work etc
218 * @name: name of channel
219 * @cd: channel platform data
220 * @runtime_addr: address for RX/TX according to the runtime config
221 * @runtime_direction: current direction of this channel according to
223 * @pend_list: queued transactions pending on this channel
224 * @at: active transaction on this channel
225 * @lock: a lock for this channel data
226 * @host: a pointer to the host (internal use)
227 * @state: whether the channel is idle, paused, running etc
228 * @slave: whether this channel is a device (slave) or for memcpy
229 * @device_fc: Flow Controller Settings for ccfg register. Only valid for slave
230 * channels. Fill with 'true' if peripheral should be flow controller. Direction
231 * will be selected at Runtime.
232 * @waiting: a TX descriptor on this channel which is waiting for a physical
233 * channel to become available
235 struct pl08x_dma_chan {
236 struct dma_chan chan;
237 struct pl08x_phy_chan *phychan;
239 struct tasklet_struct tasklet;
241 const struct pl08x_channel_data *cd;
246 enum dma_transfer_direction runtime_direction;
247 struct list_head pend_list;
248 struct pl08x_txd *at;
250 struct pl08x_driver_data *host;
251 enum pl08x_dma_chan_state state;
254 struct pl08x_txd *waiting;
258 * struct pl08x_driver_data - the local state holder for the PL08x
259 * @slave: slave engine for this instance
260 * @memcpy: memcpy engine for this instance
261 * @base: virtual memory base (remapped) for the PL08x
262 * @adev: the corresponding AMBA (PrimeCell) bus entry
263 * @vd: vendor data for this PL08x variant
264 * @pd: platform data passed in from the platform/machine
265 * @phy_chans: array of data for the physical channels
266 * @pool: a pool for the LLI descriptors
267 * @pool_ctr: counter of LLIs in the pool
268 * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI
270 * @mem_buses: set to indicate memory transfers on AHB2.
271 * @lock: a spinlock for this struct
273 struct pl08x_driver_data {
274 struct dma_device slave;
275 struct dma_device memcpy;
277 struct amba_device *adev;
278 const struct vendor_data *vd;
279 struct pl08x_platform_data *pd;
280 struct pl08x_phy_chan *phy_chans;
281 struct dma_pool *pool;
288 * PL08X specific defines
291 /* Size (bytes) of each LLI buffer allocated for one transfer */
292 # define PL08X_LLI_TSFR_SIZE 0x2000
294 /* Maximum times we call dma_pool_alloc on this pool without freeing */
295 #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
296 #define PL08X_ALIGN 8
298 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
300 return container_of(chan, struct pl08x_dma_chan, chan);
303 static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx)
305 return container_of(tx, struct pl08x_txd, tx);
309 * Physical channel handling
312 /* Whether a certain channel is busy or not */
313 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
317 val = readl(ch->base + PL080_CH_CONFIG);
318 return val & PL080_CONFIG_ACTIVE;
322 * Set the initial DMA register values i.e. those for the first LLI
323 * The next LLI pointer and the configuration interrupt bit have
324 * been set when the LLIs were constructed. Poke them into the hardware
325 * and start the transfer.
327 static void pl08x_start_txd(struct pl08x_dma_chan *plchan,
328 struct pl08x_txd *txd)
330 struct pl08x_driver_data *pl08x = plchan->host;
331 struct pl08x_phy_chan *phychan = plchan->phychan;
332 struct pl08x_lli *lli = &txd->llis_va[0];
337 /* Wait for channel inactive */
338 while (pl08x_phy_channel_busy(phychan))
341 dev_vdbg(&pl08x->adev->dev,
342 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
343 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
344 phychan->id, lli->src, lli->dst, lli->lli, lli->cctl,
347 writel(lli->src, phychan->base + PL080_CH_SRC_ADDR);
348 writel(lli->dst, phychan->base + PL080_CH_DST_ADDR);
349 writel(lli->lli, phychan->base + PL080_CH_LLI);
350 writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
351 writel(txd->ccfg, phychan->base + PL080_CH_CONFIG);
353 /* Enable the DMA channel */
354 /* Do not access config register until channel shows as disabled */
355 while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id))
358 /* Do not access config register until channel shows as inactive */
359 val = readl(phychan->base + PL080_CH_CONFIG);
360 while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
361 val = readl(phychan->base + PL080_CH_CONFIG);
363 writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG);
367 * Pause the channel by setting the HALT bit.
369 * For M->P transfers, pause the DMAC first and then stop the peripheral -
370 * the FIFO can only drain if the peripheral is still requesting data.
371 * (note: this can still timeout if the DMAC FIFO never drains of data.)
373 * For P->M transfers, disable the peripheral first to stop it filling
374 * the DMAC FIFO, and then pause the DMAC.
376 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
381 /* Set the HALT bit and wait for the FIFO to drain */
382 val = readl(ch->base + PL080_CH_CONFIG);
383 val |= PL080_CONFIG_HALT;
384 writel(val, ch->base + PL080_CH_CONFIG);
386 /* Wait for channel inactive */
387 for (timeout = 1000; timeout; timeout--) {
388 if (!pl08x_phy_channel_busy(ch))
392 if (pl08x_phy_channel_busy(ch))
393 pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id);
396 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
400 /* Clear the HALT bit */
401 val = readl(ch->base + PL080_CH_CONFIG);
402 val &= ~PL080_CONFIG_HALT;
403 writel(val, ch->base + PL080_CH_CONFIG);
407 * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and
408 * clears any pending interrupt status. This should not be used for
409 * an on-going transfer, but as a method of shutting down a channel
410 * (eg, when it's no longer used) or terminating a transfer.
412 static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x,
413 struct pl08x_phy_chan *ch)
415 u32 val = readl(ch->base + PL080_CH_CONFIG);
417 val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK |
418 PL080_CONFIG_TC_IRQ_MASK);
420 writel(val, ch->base + PL080_CH_CONFIG);
422 writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR);
423 writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR);
426 static inline u32 get_bytes_in_cctl(u32 cctl)
428 /* The source width defines the number of bytes */
429 u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
431 switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
432 case PL080_WIDTH_8BIT:
434 case PL080_WIDTH_16BIT:
437 case PL080_WIDTH_32BIT:
444 /* The channel should be paused when calling this */
445 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
447 struct pl08x_phy_chan *ch;
448 struct pl08x_txd *txd;
452 spin_lock_irqsave(&plchan->lock, flags);
453 ch = plchan->phychan;
457 * Follow the LLIs to get the number of remaining
458 * bytes in the currently active transaction.
461 u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
463 /* First get the remaining bytes in the active transfer */
464 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
467 struct pl08x_lli *llis_va = txd->llis_va;
468 dma_addr_t llis_bus = txd->llis_bus;
471 BUG_ON(clli < llis_bus || clli >= llis_bus +
472 sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS);
475 * Locate the next LLI - as this is an array,
476 * it's simple maths to find.
478 index = (clli - llis_bus) / sizeof(struct pl08x_lli);
480 for (; index < MAX_NUM_TSFR_LLIS; index++) {
481 bytes += get_bytes_in_cctl(llis_va[index].cctl);
484 * A LLI pointer of 0 terminates the LLI list
486 if (!llis_va[index].lli)
492 /* Sum up all queued transactions */
493 if (!list_empty(&plchan->pend_list)) {
494 struct pl08x_txd *txdi;
495 list_for_each_entry(txdi, &plchan->pend_list, node) {
496 struct pl08x_sg *dsg;
497 list_for_each_entry(dsg, &txd->dsg_list, node)
502 spin_unlock_irqrestore(&plchan->lock, flags);
508 * Allocate a physical channel for a virtual channel
510 * Try to locate a physical channel to be used for this transfer. If all
511 * are taken return NULL and the requester will have to cope by using
512 * some fallback PIO mode or retrying later.
514 static struct pl08x_phy_chan *
515 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
516 struct pl08x_dma_chan *virt_chan)
518 struct pl08x_phy_chan *ch = NULL;
522 for (i = 0; i < pl08x->vd->channels; i++) {
523 ch = &pl08x->phy_chans[i];
525 spin_lock_irqsave(&ch->lock, flags);
527 if (!ch->locked && !ch->serving) {
528 ch->serving = virt_chan;
530 spin_unlock_irqrestore(&ch->lock, flags);
534 spin_unlock_irqrestore(&ch->lock, flags);
537 if (i == pl08x->vd->channels) {
538 /* No physical channel available, cope with it */
545 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
546 struct pl08x_phy_chan *ch)
550 spin_lock_irqsave(&ch->lock, flags);
552 /* Stop the channel and clear its interrupts */
553 pl08x_terminate_phy_chan(pl08x, ch);
555 /* Mark it as free */
557 spin_unlock_irqrestore(&ch->lock, flags);
564 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
567 case PL080_WIDTH_8BIT:
569 case PL080_WIDTH_16BIT:
571 case PL080_WIDTH_32BIT:
580 static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
585 /* Remove all src, dst and transfer size bits */
586 retbits &= ~PL080_CONTROL_DWIDTH_MASK;
587 retbits &= ~PL080_CONTROL_SWIDTH_MASK;
588 retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
590 /* Then set the bits according to the parameters */
593 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
596 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
599 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
608 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
611 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
614 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
621 retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
625 struct pl08x_lli_build_data {
626 struct pl08x_txd *txd;
627 struct pl08x_bus_data srcbus;
628 struct pl08x_bus_data dstbus;
634 * Autoselect a master bus to use for the transfer. Slave will be the chosen as
635 * victim in case src & dest are not similarly aligned. i.e. If after aligning
636 * masters address with width requirements of transfer (by sending few byte by
637 * byte data), slave is still not aligned, then its width will be reduced to
639 * - prefers the destination bus if both available
640 * - prefers bus with fixed address (i.e. peripheral)
642 static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd,
643 struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl)
645 if (!(cctl & PL080_CONTROL_DST_INCR)) {
648 } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
652 if (bd->dstbus.buswidth >= bd->srcbus.buswidth) {
663 * Fills in one LLI for a certain transfer descriptor and advance the counter
665 static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd,
666 int num_llis, int len, u32 cctl)
668 struct pl08x_lli *llis_va = bd->txd->llis_va;
669 dma_addr_t llis_bus = bd->txd->llis_bus;
671 BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
673 llis_va[num_llis].cctl = cctl;
674 llis_va[num_llis].src = bd->srcbus.addr;
675 llis_va[num_llis].dst = bd->dstbus.addr;
676 llis_va[num_llis].lli = llis_bus + (num_llis + 1) *
677 sizeof(struct pl08x_lli);
678 llis_va[num_llis].lli |= bd->lli_bus;
680 if (cctl & PL080_CONTROL_SRC_INCR)
681 bd->srcbus.addr += len;
682 if (cctl & PL080_CONTROL_DST_INCR)
683 bd->dstbus.addr += len;
685 BUG_ON(bd->remainder < len);
687 bd->remainder -= len;
690 static inline void prep_byte_width_lli(struct pl08x_lli_build_data *bd,
691 u32 *cctl, u32 len, int num_llis, size_t *total_bytes)
693 *cctl = pl08x_cctl_bits(*cctl, 1, 1, len);
694 pl08x_fill_lli_for_desc(bd, num_llis, len, *cctl);
695 (*total_bytes) += len;
699 * This fills in the table of LLIs for the transfer descriptor
700 * Note that we assume we never have to change the burst sizes
703 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
704 struct pl08x_txd *txd)
706 struct pl08x_bus_data *mbus, *sbus;
707 struct pl08x_lli_build_data bd;
709 u32 cctl, early_bytes = 0;
710 size_t max_bytes_per_lli, total_bytes;
711 struct pl08x_lli *llis_va;
712 struct pl08x_sg *dsg;
714 txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, &txd->llis_bus);
716 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
723 bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0;
726 /* Find maximum width of the source bus */
728 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
729 PL080_CONTROL_SWIDTH_SHIFT);
731 /* Find maximum width of the destination bus */
733 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
734 PL080_CONTROL_DWIDTH_SHIFT);
736 list_for_each_entry(dsg, &txd->dsg_list, node) {
740 bd.srcbus.addr = dsg->src_addr;
741 bd.dstbus.addr = dsg->dst_addr;
742 bd.remainder = dsg->len;
743 bd.srcbus.buswidth = bd.srcbus.maxwidth;
744 bd.dstbus.buswidth = bd.dstbus.maxwidth;
746 pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl);
748 dev_vdbg(&pl08x->adev->dev, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu\n",
749 bd.srcbus.addr, cctl & PL080_CONTROL_SRC_INCR ? "+" : "",
751 bd.dstbus.addr, cctl & PL080_CONTROL_DST_INCR ? "+" : "",
754 dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n",
755 mbus == &bd.srcbus ? "src" : "dst",
756 sbus == &bd.srcbus ? "src" : "dst");
759 * Zero length is only allowed if all these requirements are
761 * - flow controller is peripheral.
762 * - src.addr is aligned to src.width
763 * - dst.addr is aligned to dst.width
765 * sg_len == 1 should be true, as there can be two cases here:
767 * - Memory addresses are contiguous and are not scattered.
768 * Here, Only one sg will be passed by user driver, with
769 * memory address and zero length. We pass this to controller
770 * and after the transfer it will receive the last burst
771 * request from peripheral and so transfer finishes.
773 * - Memory addresses are scattered and are not contiguous.
774 * Here, Obviously as DMA controller doesn't know when a lli's
775 * transfer gets over, it can't load next lli. So in this
776 * case, there has to be an assumption that only one lli is
777 * supported. Thus, we can't have scattered addresses.
780 u32 fc = (txd->ccfg & PL080_CONFIG_FLOW_CONTROL_MASK) >>
781 PL080_CONFIG_FLOW_CONTROL_SHIFT;
782 if (!((fc >= PL080_FLOW_SRC2DST_DST) &&
783 (fc <= PL080_FLOW_SRC2DST_SRC))) {
784 dev_err(&pl08x->adev->dev, "%s sg len can't be zero",
789 if ((bd.srcbus.addr % bd.srcbus.buswidth) ||
790 (bd.dstbus.addr % bd.dstbus.buswidth)) {
791 dev_err(&pl08x->adev->dev,
792 "%s src & dst address must be aligned to src"
793 " & dst width if peripheral is flow controller",
798 cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth,
799 bd.dstbus.buswidth, 0);
800 pl08x_fill_lli_for_desc(&bd, num_llis++, 0, cctl);
805 * Send byte by byte for following cases
806 * - Less than a bus width available
807 * - until master bus is aligned
809 if (bd.remainder < mbus->buswidth)
810 early_bytes = bd.remainder;
811 else if ((mbus->addr) % (mbus->buswidth)) {
812 early_bytes = mbus->buswidth - (mbus->addr) %
814 if ((bd.remainder - early_bytes) < mbus->buswidth)
815 early_bytes = bd.remainder;
819 dev_vdbg(&pl08x->adev->dev,
820 "%s byte width LLIs (remain 0x%08x)\n",
821 __func__, bd.remainder);
822 prep_byte_width_lli(&bd, &cctl, early_bytes, num_llis++,
829 * - if slave is not then we must set its width down
831 if (sbus->addr % sbus->buswidth) {
832 dev_dbg(&pl08x->adev->dev,
833 "%s set down bus width to one byte\n",
840 * Bytes transferred = tsize * src width, not
843 max_bytes_per_lli = bd.srcbus.buswidth *
844 PL080_CONTROL_TRANSFER_SIZE_MASK;
845 dev_vdbg(&pl08x->adev->dev,
846 "%s max bytes per lli = %zu\n",
847 __func__, max_bytes_per_lli);
850 * Make largest possible LLIs until less than one bus
853 while (bd.remainder > (mbus->buswidth - 1)) {
854 size_t lli_len, tsize, width;
857 * If enough left try to send max possible,
858 * otherwise try to send the remainder
860 lli_len = min(bd.remainder, max_bytes_per_lli);
863 * Check against maximum bus alignment:
864 * Calculate actual transfer size in relation to
865 * bus width an get a maximum remainder of the
866 * highest bus width - 1
868 width = max(mbus->buswidth, sbus->buswidth);
869 lli_len = (lli_len / width) * width;
870 tsize = lli_len / bd.srcbus.buswidth;
872 dev_vdbg(&pl08x->adev->dev,
873 "%s fill lli with single lli chunk of "
874 "size 0x%08zx (remainder 0x%08zx)\n",
875 __func__, lli_len, bd.remainder);
877 cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth,
878 bd.dstbus.buswidth, tsize);
879 pl08x_fill_lli_for_desc(&bd, num_llis++,
881 total_bytes += lli_len;
888 dev_vdbg(&pl08x->adev->dev,
889 "%s align with boundary, send odd bytes (remain %zu)\n",
890 __func__, bd.remainder);
891 prep_byte_width_lli(&bd, &cctl, bd.remainder,
892 num_llis++, &total_bytes);
896 if (total_bytes != dsg->len) {
897 dev_err(&pl08x->adev->dev,
898 "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
899 __func__, total_bytes, dsg->len);
903 if (num_llis >= MAX_NUM_TSFR_LLIS) {
904 dev_err(&pl08x->adev->dev,
905 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
906 __func__, (u32) MAX_NUM_TSFR_LLIS);
911 llis_va = txd->llis_va;
912 /* The final LLI terminates the LLI. */
913 llis_va[num_llis - 1].lli = 0;
914 /* The final LLI element shall also fire an interrupt. */
915 llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
921 dev_vdbg(&pl08x->adev->dev,
922 "%-3s %-9s %-10s %-10s %-10s %s\n",
923 "lli", "", "csrc", "cdst", "clli", "cctl");
924 for (i = 0; i < num_llis; i++) {
925 dev_vdbg(&pl08x->adev->dev,
926 "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n",
927 i, &llis_va[i], llis_va[i].src,
928 llis_va[i].dst, llis_va[i].lli, llis_va[i].cctl
937 /* You should call this with the struct pl08x lock held */
938 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
939 struct pl08x_txd *txd)
941 struct pl08x_sg *dsg, *_dsg;
945 dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
949 list_for_each_entry_safe(dsg, _dsg, &txd->dsg_list, node) {
950 list_del(&dsg->node);
957 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
958 struct pl08x_dma_chan *plchan)
960 struct pl08x_txd *txdi = NULL;
961 struct pl08x_txd *next;
963 if (!list_empty(&plchan->pend_list)) {
964 list_for_each_entry_safe(txdi,
965 next, &plchan->pend_list, node) {
966 list_del(&txdi->node);
967 pl08x_free_txd(pl08x, txdi);
975 static int pl08x_alloc_chan_resources(struct dma_chan *chan)
980 static void pl08x_free_chan_resources(struct dma_chan *chan)
985 * This should be called with the channel plchan->lock held
987 static int prep_phy_channel(struct pl08x_dma_chan *plchan,
988 struct pl08x_txd *txd)
990 struct pl08x_driver_data *pl08x = plchan->host;
991 struct pl08x_phy_chan *ch;
994 /* Check if we already have a channel */
995 if (plchan->phychan) {
996 ch = plchan->phychan;
1000 ch = pl08x_get_phy_channel(pl08x, plchan);
1002 /* No physical channel available, cope with it */
1003 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
1008 * OK we have a physical channel: for memcpy() this is all we
1009 * need, but for slaves the physical signals may be muxed!
1010 * Can the platform allow us to use this channel?
1012 if (plchan->slave && pl08x->pd->get_signal) {
1013 ret = pl08x->pd->get_signal(plchan->cd);
1015 dev_dbg(&pl08x->adev->dev,
1016 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
1017 ch->id, plchan->name);
1018 /* Release physical channel & return */
1019 pl08x_put_phy_channel(pl08x, ch);
1025 plchan->phychan = ch;
1026 dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
1032 /* Assign the flow control signal to this channel */
1033 if (txd->direction == DMA_MEM_TO_DEV)
1034 txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT;
1035 else if (txd->direction == DMA_DEV_TO_MEM)
1036 txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT;
1038 plchan->phychan_hold++;
1043 static void release_phy_channel(struct pl08x_dma_chan *plchan)
1045 struct pl08x_driver_data *pl08x = plchan->host;
1047 if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) {
1048 pl08x->pd->put_signal(plchan->cd, plchan->phychan->signal);
1049 plchan->phychan->signal = -1;
1051 pl08x_put_phy_channel(pl08x, plchan->phychan);
1052 plchan->phychan = NULL;
1055 static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
1057 struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
1058 struct pl08x_txd *txd = to_pl08x_txd(tx);
1059 unsigned long flags;
1060 dma_cookie_t cookie;
1062 spin_lock_irqsave(&plchan->lock, flags);
1063 cookie = dma_cookie_assign(tx);
1065 /* Put this onto the pending list */
1066 list_add_tail(&txd->node, &plchan->pend_list);
1069 * If there was no physical channel available for this memcpy,
1070 * stack the request up and indicate that the channel is waiting
1071 * for a free physical channel.
1073 if (!plchan->slave && !plchan->phychan) {
1074 /* Do this memcpy whenever there is a channel ready */
1075 plchan->state = PL08X_CHAN_WAITING;
1076 plchan->waiting = txd;
1078 plchan->phychan_hold--;
1081 spin_unlock_irqrestore(&plchan->lock, flags);
1086 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
1087 struct dma_chan *chan, unsigned long flags)
1089 struct dma_async_tx_descriptor *retval = NULL;
1095 * Code accessing dma_async_is_complete() in a tight loop may give problems.
1096 * If slaves are relying on interrupts to signal completion this function
1097 * must not be called with interrupts disabled.
1099 static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan,
1100 dma_cookie_t cookie, struct dma_tx_state *txstate)
1102 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1103 enum dma_status ret;
1105 ret = dma_cookie_status(chan, cookie, txstate);
1106 if (ret == DMA_SUCCESS)
1110 * This cookie not complete yet
1111 * Get number of bytes left in the active transactions and queue
1113 dma_set_residue(txstate, pl08x_getbytes_chan(plchan));
1115 if (plchan->state == PL08X_CHAN_PAUSED)
1118 /* Whether waiting or running, we're in progress */
1119 return DMA_IN_PROGRESS;
1122 /* PrimeCell DMA extension */
1123 struct burst_table {
1128 static const struct burst_table burst_sizes[] = {
1131 .reg = PL080_BSIZE_256,
1135 .reg = PL080_BSIZE_128,
1139 .reg = PL080_BSIZE_64,
1143 .reg = PL080_BSIZE_32,
1147 .reg = PL080_BSIZE_16,
1151 .reg = PL080_BSIZE_8,
1155 .reg = PL080_BSIZE_4,
1159 .reg = PL080_BSIZE_1,
1164 * Given the source and destination available bus masks, select which
1165 * will be routed to each port. We try to have source and destination
1166 * on separate ports, but always respect the allowable settings.
1168 static u32 pl08x_select_bus(u8 src, u8 dst)
1172 if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1)))
1173 cctl |= PL080_CONTROL_DST_AHB2;
1174 if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2)))
1175 cctl |= PL080_CONTROL_SRC_AHB2;
1180 static u32 pl08x_cctl(u32 cctl)
1182 cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 |
1183 PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR |
1184 PL080_CONTROL_PROT_MASK);
1186 /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1187 return cctl | PL080_CONTROL_PROT_SYS;
1190 static u32 pl08x_width(enum dma_slave_buswidth width)
1193 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1194 return PL080_WIDTH_8BIT;
1195 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1196 return PL080_WIDTH_16BIT;
1197 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1198 return PL080_WIDTH_32BIT;
1204 static u32 pl08x_burst(u32 maxburst)
1208 for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
1209 if (burst_sizes[i].burstwords <= maxburst)
1212 return burst_sizes[i].reg;
1215 static int dma_set_runtime_config(struct dma_chan *chan,
1216 struct dma_slave_config *config)
1218 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1219 struct pl08x_driver_data *pl08x = plchan->host;
1220 enum dma_slave_buswidth addr_width;
1221 u32 width, burst, maxburst;
1227 /* Transfer direction */
1228 plchan->runtime_direction = config->direction;
1229 if (config->direction == DMA_MEM_TO_DEV) {
1230 addr_width = config->dst_addr_width;
1231 maxburst = config->dst_maxburst;
1232 } else if (config->direction == DMA_DEV_TO_MEM) {
1233 addr_width = config->src_addr_width;
1234 maxburst = config->src_maxburst;
1236 dev_err(&pl08x->adev->dev,
1237 "bad runtime_config: alien transfer direction\n");
1241 width = pl08x_width(addr_width);
1243 dev_err(&pl08x->adev->dev,
1244 "bad runtime_config: alien address width\n");
1248 cctl |= width << PL080_CONTROL_SWIDTH_SHIFT;
1249 cctl |= width << PL080_CONTROL_DWIDTH_SHIFT;
1252 * If this channel will only request single transfers, set this
1253 * down to ONE element. Also select one element if no maxburst
1256 if (plchan->cd->single)
1259 burst = pl08x_burst(maxburst);
1260 cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT;
1261 cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT;
1263 plchan->device_fc = config->device_fc;
1265 if (plchan->runtime_direction == DMA_DEV_TO_MEM) {
1266 plchan->src_addr = config->src_addr;
1267 plchan->src_cctl = pl08x_cctl(cctl) | PL080_CONTROL_DST_INCR |
1268 pl08x_select_bus(plchan->cd->periph_buses,
1271 plchan->dst_addr = config->dst_addr;
1272 plchan->dst_cctl = pl08x_cctl(cctl) | PL080_CONTROL_SRC_INCR |
1273 pl08x_select_bus(pl08x->mem_buses,
1274 plchan->cd->periph_buses);
1277 dev_dbg(&pl08x->adev->dev,
1278 "configured channel %s (%s) for %s, data width %d, "
1279 "maxburst %d words, LE, CCTL=0x%08x\n",
1280 dma_chan_name(chan), plchan->name,
1281 (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
1290 * Slave transactions callback to the slave device to allow
1291 * synchronization of slave DMA signals with the DMAC enable
1293 static void pl08x_issue_pending(struct dma_chan *chan)
1295 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1296 unsigned long flags;
1298 spin_lock_irqsave(&plchan->lock, flags);
1299 /* Something is already active, or we're waiting for a channel... */
1300 if (plchan->at || plchan->state == PL08X_CHAN_WAITING) {
1301 spin_unlock_irqrestore(&plchan->lock, flags);
1305 /* Take the first element in the queue and execute it */
1306 if (!list_empty(&plchan->pend_list)) {
1307 struct pl08x_txd *next;
1309 next = list_first_entry(&plchan->pend_list,
1312 list_del(&next->node);
1313 plchan->state = PL08X_CHAN_RUNNING;
1315 pl08x_start_txd(plchan, next);
1318 spin_unlock_irqrestore(&plchan->lock, flags);
1321 static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
1322 struct pl08x_txd *txd)
1324 struct pl08x_driver_data *pl08x = plchan->host;
1325 unsigned long flags;
1328 num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
1330 spin_lock_irqsave(&plchan->lock, flags);
1331 pl08x_free_txd(pl08x, txd);
1332 spin_unlock_irqrestore(&plchan->lock, flags);
1336 spin_lock_irqsave(&plchan->lock, flags);
1339 * See if we already have a physical channel allocated,
1340 * else this is the time to try to get one.
1342 ret = prep_phy_channel(plchan, txd);
1345 * No physical channel was available.
1347 * memcpy transfers can be sorted out at submission time.
1349 * Slave transfers may have been denied due to platform
1350 * channel muxing restrictions. Since there is no guarantee
1351 * that this will ever be resolved, and the signal must be
1352 * acquired AFTER acquiring the physical channel, we will let
1353 * them be NACK:ed with -EBUSY here. The drivers can retry
1354 * the prep() call if they are eager on doing this using DMA.
1356 if (plchan->slave) {
1357 pl08x_free_txd_list(pl08x, plchan);
1358 pl08x_free_txd(pl08x, txd);
1359 spin_unlock_irqrestore(&plchan->lock, flags);
1364 * Else we're all set, paused and ready to roll, status
1365 * will switch to PL08X_CHAN_RUNNING when we call
1366 * issue_pending(). If there is something running on the
1367 * channel already we don't change its state.
1369 if (plchan->state == PL08X_CHAN_IDLE)
1370 plchan->state = PL08X_CHAN_PAUSED;
1372 spin_unlock_irqrestore(&plchan->lock, flags);
1377 static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan,
1378 unsigned long flags)
1380 struct pl08x_txd *txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
1383 dma_async_tx_descriptor_init(&txd->tx, &plchan->chan);
1384 txd->tx.flags = flags;
1385 txd->tx.tx_submit = pl08x_tx_submit;
1386 INIT_LIST_HEAD(&txd->node);
1387 INIT_LIST_HEAD(&txd->dsg_list);
1389 /* Always enable error and terminal interrupts */
1390 txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK |
1391 PL080_CONFIG_TC_IRQ_MASK;
1397 * Initialize a descriptor to be used by memcpy submit
1399 static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1400 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1401 size_t len, unsigned long flags)
1403 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1404 struct pl08x_driver_data *pl08x = plchan->host;
1405 struct pl08x_txd *txd;
1406 struct pl08x_sg *dsg;
1409 txd = pl08x_get_txd(plchan, flags);
1411 dev_err(&pl08x->adev->dev,
1412 "%s no memory for descriptor\n", __func__);
1416 dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT);
1418 pl08x_free_txd(pl08x, txd);
1419 dev_err(&pl08x->adev->dev, "%s no memory for pl080 sg\n",
1423 list_add_tail(&dsg->node, &txd->dsg_list);
1425 txd->direction = DMA_MEM_TO_MEM;
1426 dsg->src_addr = src;
1427 dsg->dst_addr = dest;
1430 /* Set platform data for m2m */
1431 txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1432 txd->cctl = pl08x->pd->memcpy_channel.cctl &
1433 ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
1435 /* Both to be incremented or the code will break */
1436 txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
1438 if (pl08x->vd->dualmaster)
1439 txd->cctl |= pl08x_select_bus(pl08x->mem_buses,
1442 ret = pl08x_prep_channel_resources(plchan, txd);
1449 static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1450 struct dma_chan *chan, struct scatterlist *sgl,
1451 unsigned int sg_len, enum dma_transfer_direction direction,
1452 unsigned long flags, void *context)
1454 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1455 struct pl08x_driver_data *pl08x = plchan->host;
1456 struct pl08x_txd *txd;
1457 struct pl08x_sg *dsg;
1458 struct scatterlist *sg;
1459 dma_addr_t slave_addr;
1462 dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1463 __func__, sg_dma_len(sgl), plchan->name);
1465 txd = pl08x_get_txd(plchan, flags);
1467 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1471 if (direction != plchan->runtime_direction)
1472 dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
1473 "the direction configured for the PrimeCell\n",
1477 * Set up addresses, the PrimeCell configured address
1478 * will take precedence since this may configure the
1479 * channel target address dynamically at runtime.
1481 txd->direction = direction;
1483 if (direction == DMA_MEM_TO_DEV) {
1484 txd->cctl = plchan->dst_cctl;
1485 slave_addr = plchan->dst_addr;
1486 } else if (direction == DMA_DEV_TO_MEM) {
1487 txd->cctl = plchan->src_cctl;
1488 slave_addr = plchan->src_addr;
1490 pl08x_free_txd(pl08x, txd);
1491 dev_err(&pl08x->adev->dev,
1492 "%s direction unsupported\n", __func__);
1496 if (plchan->device_fc)
1497 tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER_PER :
1498 PL080_FLOW_PER2MEM_PER;
1500 tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER :
1503 txd->ccfg |= tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1505 for_each_sg(sgl, sg, sg_len, tmp) {
1506 dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT);
1508 pl08x_free_txd(pl08x, txd);
1509 dev_err(&pl08x->adev->dev, "%s no mem for pl080 sg\n",
1513 list_add_tail(&dsg->node, &txd->dsg_list);
1515 dsg->len = sg_dma_len(sg);
1516 if (direction == DMA_MEM_TO_DEV) {
1517 dsg->src_addr = sg_dma_address(sg);
1518 dsg->dst_addr = slave_addr;
1520 dsg->src_addr = slave_addr;
1521 dsg->dst_addr = sg_dma_address(sg);
1525 ret = pl08x_prep_channel_resources(plchan, txd);
1532 static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1535 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1536 struct pl08x_driver_data *pl08x = plchan->host;
1537 unsigned long flags;
1540 /* Controls applicable to inactive channels */
1541 if (cmd == DMA_SLAVE_CONFIG) {
1542 return dma_set_runtime_config(chan,
1543 (struct dma_slave_config *)arg);
1547 * Anything succeeds on channels with no physical allocation and
1548 * no queued transfers.
1550 spin_lock_irqsave(&plchan->lock, flags);
1551 if (!plchan->phychan && !plchan->at) {
1552 spin_unlock_irqrestore(&plchan->lock, flags);
1557 case DMA_TERMINATE_ALL:
1558 plchan->state = PL08X_CHAN_IDLE;
1560 if (plchan->phychan) {
1561 pl08x_terminate_phy_chan(pl08x, plchan->phychan);
1564 * Mark physical channel as free and free any slave
1567 release_phy_channel(plchan);
1568 plchan->phychan_hold = 0;
1570 /* Dequeue jobs and free LLIs */
1572 pl08x_free_txd(pl08x, plchan->at);
1575 /* Dequeue jobs not yet fired as well */
1576 pl08x_free_txd_list(pl08x, plchan);
1579 pl08x_pause_phy_chan(plchan->phychan);
1580 plchan->state = PL08X_CHAN_PAUSED;
1583 pl08x_resume_phy_chan(plchan->phychan);
1584 plchan->state = PL08X_CHAN_RUNNING;
1587 /* Unknown command */
1592 spin_unlock_irqrestore(&plchan->lock, flags);
1597 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1599 struct pl08x_dma_chan *plchan;
1600 char *name = chan_id;
1602 /* Reject channels for devices not bound to this driver */
1603 if (chan->device->dev->driver != &pl08x_amba_driver.drv)
1606 plchan = to_pl08x_chan(chan);
1608 /* Check that the channel is not taken! */
1609 if (!strcmp(plchan->name, name))
1616 * Just check that the device is there and active
1617 * TODO: turn this bit on/off depending on the number of physical channels
1618 * actually used, if it is zero... well shut it off. That will save some
1619 * power. Cut the clock at the same time.
1621 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1623 /* The Nomadik variant does not have the config register */
1624 if (pl08x->vd->nomadik)
1626 writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG);
1629 static void pl08x_unmap_buffers(struct pl08x_txd *txd)
1631 struct device *dev = txd->tx.chan->device->dev;
1632 struct pl08x_sg *dsg;
1634 if (!(txd->tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
1635 if (txd->tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE)
1636 list_for_each_entry(dsg, &txd->dsg_list, node)
1637 dma_unmap_single(dev, dsg->src_addr, dsg->len,
1640 list_for_each_entry(dsg, &txd->dsg_list, node)
1641 dma_unmap_page(dev, dsg->src_addr, dsg->len,
1645 if (!(txd->tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
1646 if (txd->tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE)
1647 list_for_each_entry(dsg, &txd->dsg_list, node)
1648 dma_unmap_single(dev, dsg->dst_addr, dsg->len,
1651 list_for_each_entry(dsg, &txd->dsg_list, node)
1652 dma_unmap_page(dev, dsg->dst_addr, dsg->len,
1657 static void pl08x_tasklet(unsigned long data)
1659 struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
1660 struct pl08x_driver_data *pl08x = plchan->host;
1661 struct pl08x_txd *txd;
1662 unsigned long flags;
1664 spin_lock_irqsave(&plchan->lock, flags);
1670 /* Update last completed */
1671 dma_cookie_complete(&txd->tx);
1674 /* If a new descriptor is queued, set it up plchan->at is NULL here */
1675 if (!list_empty(&plchan->pend_list)) {
1676 struct pl08x_txd *next;
1678 next = list_first_entry(&plchan->pend_list,
1681 list_del(&next->node);
1683 pl08x_start_txd(plchan, next);
1684 } else if (plchan->phychan_hold) {
1686 * This channel is still in use - we have a new txd being
1687 * prepared and will soon be queued. Don't give up the
1691 struct pl08x_dma_chan *waiting = NULL;
1694 * No more jobs, so free up the physical channel
1695 * Free any allocated signal on slave transfers too
1697 release_phy_channel(plchan);
1698 plchan->state = PL08X_CHAN_IDLE;
1701 * And NOW before anyone else can grab that free:d up
1702 * physical channel, see if there is some memcpy pending
1703 * that seriously needs to start because of being stacked
1704 * up while we were choking the physical channels with data.
1706 list_for_each_entry(waiting, &pl08x->memcpy.channels,
1708 if (waiting->state == PL08X_CHAN_WAITING &&
1709 waiting->waiting != NULL) {
1712 /* This should REALLY not fail now */
1713 ret = prep_phy_channel(waiting,
1716 waiting->phychan_hold--;
1717 waiting->state = PL08X_CHAN_RUNNING;
1718 waiting->waiting = NULL;
1719 pl08x_issue_pending(&waiting->chan);
1725 spin_unlock_irqrestore(&plchan->lock, flags);
1728 dma_async_tx_callback callback = txd->tx.callback;
1729 void *callback_param = txd->tx.callback_param;
1731 /* Don't try to unmap buffers on slave channels */
1733 pl08x_unmap_buffers(txd);
1735 /* Free the descriptor */
1736 spin_lock_irqsave(&plchan->lock, flags);
1737 pl08x_free_txd(pl08x, txd);
1738 spin_unlock_irqrestore(&plchan->lock, flags);
1740 /* Callback to signal completion */
1742 callback(callback_param);
1746 static irqreturn_t pl08x_irq(int irq, void *dev)
1748 struct pl08x_driver_data *pl08x = dev;
1749 u32 mask = 0, err, tc, i;
1751 /* check & clear - ERR & TC interrupts */
1752 err = readl(pl08x->base + PL080_ERR_STATUS);
1754 dev_err(&pl08x->adev->dev, "%s error interrupt, register value 0x%08x\n",
1756 writel(err, pl08x->base + PL080_ERR_CLEAR);
1758 tc = readl(pl08x->base + PL080_TC_STATUS);
1760 writel(tc, pl08x->base + PL080_TC_CLEAR);
1765 for (i = 0; i < pl08x->vd->channels; i++) {
1766 if (((1 << i) & err) || ((1 << i) & tc)) {
1767 /* Locate physical channel */
1768 struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
1769 struct pl08x_dma_chan *plchan = phychan->serving;
1772 dev_err(&pl08x->adev->dev,
1773 "%s Error TC interrupt on unused channel: 0x%08x\n",
1778 /* Schedule tasklet on this channel */
1779 tasklet_schedule(&plchan->tasklet);
1784 return mask ? IRQ_HANDLED : IRQ_NONE;
1787 static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan)
1789 u32 cctl = pl08x_cctl(chan->cd->cctl);
1792 chan->name = chan->cd->bus_id;
1793 chan->src_addr = chan->cd->addr;
1794 chan->dst_addr = chan->cd->addr;
1795 chan->src_cctl = cctl | PL080_CONTROL_DST_INCR |
1796 pl08x_select_bus(chan->cd->periph_buses, chan->host->mem_buses);
1797 chan->dst_cctl = cctl | PL080_CONTROL_SRC_INCR |
1798 pl08x_select_bus(chan->host->mem_buses, chan->cd->periph_buses);
1802 * Initialise the DMAC memcpy/slave channels.
1803 * Make a local wrapper to hold required data
1805 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
1806 struct dma_device *dmadev, unsigned int channels, bool slave)
1808 struct pl08x_dma_chan *chan;
1811 INIT_LIST_HEAD(&dmadev->channels);
1814 * Register as many many memcpy as we have physical channels,
1815 * we won't always be able to use all but the code will have
1816 * to cope with that situation.
1818 for (i = 0; i < channels; i++) {
1819 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
1821 dev_err(&pl08x->adev->dev,
1822 "%s no memory for channel\n", __func__);
1827 chan->state = PL08X_CHAN_IDLE;
1830 chan->cd = &pl08x->pd->slave_channels[i];
1831 pl08x_dma_slave_init(chan);
1833 chan->cd = &pl08x->pd->memcpy_channel;
1834 chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1840 dev_dbg(&pl08x->adev->dev,
1841 "initialize virtual channel \"%s\"\n",
1844 chan->chan.device = dmadev;
1845 dma_cookie_init(&chan->chan);
1847 spin_lock_init(&chan->lock);
1848 INIT_LIST_HEAD(&chan->pend_list);
1849 tasklet_init(&chan->tasklet, pl08x_tasklet,
1850 (unsigned long) chan);
1852 list_add_tail(&chan->chan.device_node, &dmadev->channels);
1854 dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
1855 i, slave ? "slave" : "memcpy");
1859 static void pl08x_free_virtual_channels(struct dma_device *dmadev)
1861 struct pl08x_dma_chan *chan = NULL;
1862 struct pl08x_dma_chan *next;
1864 list_for_each_entry_safe(chan,
1865 next, &dmadev->channels, chan.device_node) {
1866 list_del(&chan->chan.device_node);
1871 #ifdef CONFIG_DEBUG_FS
1872 static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
1875 case PL08X_CHAN_IDLE:
1877 case PL08X_CHAN_RUNNING:
1879 case PL08X_CHAN_PAUSED:
1881 case PL08X_CHAN_WAITING:
1886 return "UNKNOWN STATE";
1889 static int pl08x_debugfs_show(struct seq_file *s, void *data)
1891 struct pl08x_driver_data *pl08x = s->private;
1892 struct pl08x_dma_chan *chan;
1893 struct pl08x_phy_chan *ch;
1894 unsigned long flags;
1897 seq_printf(s, "PL08x physical channels:\n");
1898 seq_printf(s, "CHANNEL:\tUSER:\n");
1899 seq_printf(s, "--------\t-----\n");
1900 for (i = 0; i < pl08x->vd->channels; i++) {
1901 struct pl08x_dma_chan *virt_chan;
1903 ch = &pl08x->phy_chans[i];
1905 spin_lock_irqsave(&ch->lock, flags);
1906 virt_chan = ch->serving;
1908 seq_printf(s, "%d\t\t%s%s\n",
1910 virt_chan ? virt_chan->name : "(none)",
1911 ch->locked ? " LOCKED" : "");
1913 spin_unlock_irqrestore(&ch->lock, flags);
1916 seq_printf(s, "\nPL08x virtual memcpy channels:\n");
1917 seq_printf(s, "CHANNEL:\tSTATE:\n");
1918 seq_printf(s, "--------\t------\n");
1919 list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) {
1920 seq_printf(s, "%s\t\t%s\n", chan->name,
1921 pl08x_state_str(chan->state));
1924 seq_printf(s, "\nPL08x virtual slave channels:\n");
1925 seq_printf(s, "CHANNEL:\tSTATE:\n");
1926 seq_printf(s, "--------\t------\n");
1927 list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) {
1928 seq_printf(s, "%s\t\t%s\n", chan->name,
1929 pl08x_state_str(chan->state));
1935 static int pl08x_debugfs_open(struct inode *inode, struct file *file)
1937 return single_open(file, pl08x_debugfs_show, inode->i_private);
1940 static const struct file_operations pl08x_debugfs_operations = {
1941 .open = pl08x_debugfs_open,
1943 .llseek = seq_lseek,
1944 .release = single_release,
1947 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1949 /* Expose a simple debugfs interface to view all clocks */
1950 (void) debugfs_create_file(dev_name(&pl08x->adev->dev),
1951 S_IFREG | S_IRUGO, NULL, pl08x,
1952 &pl08x_debugfs_operations);
1956 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1961 static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
1963 struct pl08x_driver_data *pl08x;
1964 const struct vendor_data *vd = id->data;
1968 ret = amba_request_regions(adev, NULL);
1972 /* Create the driver state holder */
1973 pl08x = kzalloc(sizeof(*pl08x), GFP_KERNEL);
1979 /* Initialize memcpy engine */
1980 dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
1981 pl08x->memcpy.dev = &adev->dev;
1982 pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1983 pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
1984 pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
1985 pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1986 pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
1987 pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
1988 pl08x->memcpy.device_control = pl08x_control;
1990 /* Initialize slave engine */
1991 dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
1992 pl08x->slave.dev = &adev->dev;
1993 pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1994 pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
1995 pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1996 pl08x->slave.device_tx_status = pl08x_dma_tx_status;
1997 pl08x->slave.device_issue_pending = pl08x_issue_pending;
1998 pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
1999 pl08x->slave.device_control = pl08x_control;
2001 /* Get the platform data */
2002 pl08x->pd = dev_get_platdata(&adev->dev);
2004 dev_err(&adev->dev, "no platform data supplied\n");
2005 goto out_no_platdata;
2008 /* Assign useful pointers to the driver state */
2012 /* By default, AHB1 only. If dualmaster, from platform */
2013 pl08x->lli_buses = PL08X_AHB1;
2014 pl08x->mem_buses = PL08X_AHB1;
2015 if (pl08x->vd->dualmaster) {
2016 pl08x->lli_buses = pl08x->pd->lli_buses;
2017 pl08x->mem_buses = pl08x->pd->mem_buses;
2020 /* A DMA memory pool for LLIs, align on 1-byte boundary */
2021 pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
2022 PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
2025 goto out_no_lli_pool;
2028 pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
2031 goto out_no_ioremap;
2034 /* Turn on the PL08x */
2035 pl08x_ensure_on(pl08x);
2037 /* Attach the interrupt handler */
2038 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
2039 writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
2041 ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
2042 DRIVER_NAME, pl08x);
2044 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
2045 __func__, adev->irq[0]);
2049 /* Initialize physical channels */
2050 pl08x->phy_chans = kzalloc((vd->channels * sizeof(*pl08x->phy_chans)),
2052 if (!pl08x->phy_chans) {
2053 dev_err(&adev->dev, "%s failed to allocate "
2054 "physical channel holders\n",
2056 goto out_no_phychans;
2059 for (i = 0; i < vd->channels; i++) {
2060 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
2063 ch->base = pl08x->base + PL080_Cx_BASE(i);
2064 spin_lock_init(&ch->lock);
2068 * Nomadik variants can have channels that are locked
2069 * down for the secure world only. Lock up these channels
2070 * by perpetually serving a dummy virtual channel.
2075 val = readl(ch->base + PL080_CH_CONFIG);
2076 if (val & (PL080N_CONFIG_ITPROT | PL080N_CONFIG_SECPROT)) {
2077 dev_info(&adev->dev, "physical channel %d reserved for secure access only\n", i);
2082 dev_dbg(&adev->dev, "physical channel %d is %s\n",
2083 i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
2086 /* Register as many memcpy channels as there are physical channels */
2087 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
2088 pl08x->vd->channels, false);
2090 dev_warn(&pl08x->adev->dev,
2091 "%s failed to enumerate memcpy channels - %d\n",
2095 pl08x->memcpy.chancnt = ret;
2097 /* Register slave channels */
2098 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
2099 pl08x->pd->num_slave_channels, true);
2101 dev_warn(&pl08x->adev->dev,
2102 "%s failed to enumerate slave channels - %d\n",
2106 pl08x->slave.chancnt = ret;
2108 ret = dma_async_device_register(&pl08x->memcpy);
2110 dev_warn(&pl08x->adev->dev,
2111 "%s failed to register memcpy as an async device - %d\n",
2113 goto out_no_memcpy_reg;
2116 ret = dma_async_device_register(&pl08x->slave);
2118 dev_warn(&pl08x->adev->dev,
2119 "%s failed to register slave as an async device - %d\n",
2121 goto out_no_slave_reg;
2124 amba_set_drvdata(adev, pl08x);
2125 init_pl08x_debugfs(pl08x);
2126 dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
2127 amba_part(adev), amba_rev(adev),
2128 (unsigned long long)adev->res.start, adev->irq[0]);
2133 dma_async_device_unregister(&pl08x->memcpy);
2135 pl08x_free_virtual_channels(&pl08x->slave);
2137 pl08x_free_virtual_channels(&pl08x->memcpy);
2139 kfree(pl08x->phy_chans);
2141 free_irq(adev->irq[0], pl08x);
2143 iounmap(pl08x->base);
2145 dma_pool_destroy(pl08x->pool);
2150 amba_release_regions(adev);
2154 /* PL080 has 8 channels and the PL080 have just 2 */
2155 static struct vendor_data vendor_pl080 = {
2160 static struct vendor_data vendor_nomadik = {
2166 static struct vendor_data vendor_pl081 = {
2168 .dualmaster = false,
2171 static struct amba_id pl08x_ids[] = {
2176 .data = &vendor_pl080,
2182 .data = &vendor_pl081,
2184 /* Nomadik 8815 PL080 variant */
2188 .data = &vendor_nomadik,
2193 MODULE_DEVICE_TABLE(amba, pl08x_ids);
2195 static struct amba_driver pl08x_amba_driver = {
2196 .drv.name = DRIVER_NAME,
2197 .id_table = pl08x_ids,
2198 .probe = pl08x_probe,
2201 static int __init pl08x_init(void)
2204 retval = amba_driver_register(&pl08x_amba_driver);
2206 printk(KERN_WARNING DRIVER_NAME
2207 "failed to register as an AMBA device (%d)\n",
2211 subsys_initcall(pl08x_init);