2 * Copyright (c) 2006 ARM Ltd.
3 * Copyright (c) 2010 ST-Ericsson SA
5 * Author: Peter Pearse <peter.pearse@arm.com>
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 * The full GNU General Public License is iin this distribution in the
23 * file called COPYING.
25 * Documentation: ARM DDI 0196G == PL080
26 * Documentation: ARM DDI 0218E == PL081
28 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to
31 * The PL080 has 8 channels available for simultaneous use, and the PL081
32 * has only two channels. So on these DMA controllers the number of channels
33 * and the number of incoming DMA signals are two totally different things.
34 * It is usually not possible to theoretically handle all physical signals,
35 * so a multiplexing scheme with possible denial of use is necessary.
37 * The PL080 has a dual bus master, PL081 has a single master.
39 * Memory to peripheral transfer may be visualized as
40 * Get data from memory to DMAC
42 * On burst request from peripheral
43 * Destination burst from DMAC to peripheral
45 * Raise terminal count interrupt
47 * For peripherals with a FIFO:
48 * Source burst size == half the depth of the peripheral FIFO
49 * Destination burst size == the depth of the peripheral FIFO
51 * (Bursts are irrelevant for mem to mem transfers - there are no burst
52 * signals, the DMA controller will simply facilitate its AHB master.)
54 * ASSUMES default (little) endianness for DMA transfers
56 * Only DMAC flow control is implemented
59 * - Break out common code from arch/arm/mach-s3c64xx and share
61 #include <linux/device.h>
62 #include <linux/init.h>
63 #include <linux/module.h>
64 #include <linux/pci.h>
65 #include <linux/interrupt.h>
66 #include <linux/slab.h>
67 #include <linux/dmapool.h>
68 #include <linux/amba/bus.h>
69 #include <linux/dmaengine.h>
70 #include <linux/amba/pl08x.h>
71 #include <linux/debugfs.h>
72 #include <linux/seq_file.h>
74 #include <asm/hardware/pl080.h>
76 #include <asm/mach/dma.h>
77 #include <asm/atomic.h>
78 #include <asm/processor.h>
79 #include <asm/cacheflush.h>
81 #define DRIVER_NAME "pl08xdmac"
84 * struct vendor_data - vendor-specific config parameters
86 * @name: the name of this specific variant
87 * @channels: the number of channels available in this variant
88 * @dualmaster: whether this version supports dual AHB masters
98 * PL08X private data structures
99 * An LLI struct - see pl08x TRM
100 * Note that next uses bit[0] as a bus bit,
101 * start & end do not - their bus bit info
112 * struct pl08x_driver_data - the local state holder for the PL08x
113 * @slave: slave engine for this instance
114 * @memcpy: memcpy engine for this instance
115 * @base: virtual memory base (remapped) for the PL08x
116 * @adev: the corresponding AMBA (PrimeCell) bus entry
117 * @vd: vendor data for this PL08x variant
118 * @pd: platform data passed in from the platform/machine
119 * @phy_chans: array of data for the physical channels
120 * @pool: a pool for the LLI descriptors
121 * @pool_ctr: counter of LLIs in the pool
122 * @lock: a spinlock for this struct
124 struct pl08x_driver_data {
125 struct dma_device slave;
126 struct dma_device memcpy;
128 struct amba_device *adev;
129 struct vendor_data *vd;
130 struct pl08x_platform_data *pd;
131 struct pl08x_phy_chan *phy_chans;
132 struct dma_pool *pool;
138 * PL08X specific defines
142 * Memory boundaries: the manual for PL08x says that the controller
143 * cannot read past a 1KiB boundary, so these defines are used to
144 * create transfer LLIs that do not cross such boundaries.
146 #define PL08X_BOUNDARY_SHIFT (10) /* 1KB 0x400 */
147 #define PL08X_BOUNDARY_SIZE (1 << PL08X_BOUNDARY_SHIFT)
149 /* Minimum period between work queue runs */
150 #define PL08X_WQ_PERIODMIN 20
152 /* Size (bytes) of each LLI buffer allocated for one transfer */
153 # define PL08X_LLI_TSFR_SIZE 0x2000
155 /* Maximimum times we call dma_pool_alloc on this pool without freeing */
156 #define PL08X_MAX_ALLOCS 0x40
157 #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct lli))
158 #define PL08X_ALIGN 8
160 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
162 return container_of(chan, struct pl08x_dma_chan, chan);
166 * Physical channel handling
169 /* Whether a certain channel is busy or not */
170 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
174 val = readl(ch->base + PL080_CH_CONFIG);
175 return val & PL080_CONFIG_ACTIVE;
179 * Set the initial DMA register values i.e. those for the first LLI
180 * The next lli pointer and the configuration interrupt bit have
181 * been set when the LLIs were constructed
183 static void pl08x_set_cregs(struct pl08x_driver_data *pl08x,
184 struct pl08x_phy_chan *ch)
186 /* Wait for channel inactive */
187 while (pl08x_phy_channel_busy(ch))
190 dev_vdbg(&pl08x->adev->dev,
191 "WRITE channel %d: csrc=%08x, cdst=%08x, "
192 "cctl=%08x, clli=%08x, ccfg=%08x\n",
200 writel(ch->csrc, ch->base + PL080_CH_SRC_ADDR);
201 writel(ch->cdst, ch->base + PL080_CH_DST_ADDR);
202 writel(ch->clli, ch->base + PL080_CH_LLI);
203 writel(ch->cctl, ch->base + PL080_CH_CONTROL);
204 writel(ch->ccfg, ch->base + PL080_CH_CONFIG);
207 static inline void pl08x_config_phychan_for_txd(struct pl08x_dma_chan *plchan)
209 struct pl08x_channel_data *cd = plchan->cd;
210 struct pl08x_phy_chan *phychan = plchan->phychan;
211 struct pl08x_txd *txd = plchan->at;
213 /* Copy the basic control register calculated at transfer config */
214 phychan->csrc = txd->csrc;
215 phychan->cdst = txd->cdst;
216 phychan->clli = txd->clli;
217 phychan->cctl = txd->cctl;
219 /* Assign the signal to the proper control registers */
220 phychan->ccfg = cd->ccfg;
221 phychan->ccfg &= ~PL080_CONFIG_SRC_SEL_MASK;
222 phychan->ccfg &= ~PL080_CONFIG_DST_SEL_MASK;
223 /* If it wasn't set from AMBA, ignore it */
224 if (txd->direction == DMA_TO_DEVICE)
225 /* Select signal as destination */
227 (phychan->signal << PL080_CONFIG_DST_SEL_SHIFT);
228 else if (txd->direction == DMA_FROM_DEVICE)
229 /* Select signal as source */
231 (phychan->signal << PL080_CONFIG_SRC_SEL_SHIFT);
232 /* Always enable error interrupts */
233 phychan->ccfg |= PL080_CONFIG_ERR_IRQ_MASK;
234 /* Always enable terminal interrupts */
235 phychan->ccfg |= PL080_CONFIG_TC_IRQ_MASK;
239 * Enable the DMA channel
240 * Assumes all other configuration bits have been set
241 * as desired before this code is called
243 static void pl08x_enable_phy_chan(struct pl08x_driver_data *pl08x,
244 struct pl08x_phy_chan *ch)
249 * Do not access config register until channel shows as disabled
251 while (readl(pl08x->base + PL080_EN_CHAN) & (1 << ch->id))
255 * Do not access config register until channel shows as inactive
257 val = readl(ch->base + PL080_CH_CONFIG);
258 while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
259 val = readl(ch->base + PL080_CH_CONFIG);
261 writel(val | PL080_CONFIG_ENABLE, ch->base + PL080_CH_CONFIG);
265 * Overall DMAC remains enabled always.
267 * Disabling individual channels could lose data.
269 * Disable the peripheral DMA after disabling the DMAC
270 * in order to allow the DMAC FIFO to drain, and
271 * hence allow the channel to show inactive
274 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
278 /* Set the HALT bit and wait for the FIFO to drain */
279 val = readl(ch->base + PL080_CH_CONFIG);
280 val |= PL080_CONFIG_HALT;
281 writel(val, ch->base + PL080_CH_CONFIG);
283 /* Wait for channel inactive */
284 while (pl08x_phy_channel_busy(ch))
288 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
292 /* Clear the HALT bit */
293 val = readl(ch->base + PL080_CH_CONFIG);
294 val &= ~PL080_CONFIG_HALT;
295 writel(val, ch->base + PL080_CH_CONFIG);
299 /* Stops the channel */
300 static void pl08x_stop_phy_chan(struct pl08x_phy_chan *ch)
304 pl08x_pause_phy_chan(ch);
306 /* Disable channel */
307 val = readl(ch->base + PL080_CH_CONFIG);
308 val &= ~PL080_CONFIG_ENABLE;
309 val &= ~PL080_CONFIG_ERR_IRQ_MASK;
310 val &= ~PL080_CONFIG_TC_IRQ_MASK;
311 writel(val, ch->base + PL080_CH_CONFIG);
314 static inline u32 get_bytes_in_cctl(u32 cctl)
316 /* The source width defines the number of bytes */
317 u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
319 switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
320 case PL080_WIDTH_8BIT:
322 case PL080_WIDTH_16BIT:
325 case PL080_WIDTH_32BIT:
332 /* The channel should be paused when calling this */
333 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
335 struct pl08x_phy_chan *ch;
336 struct pl08x_txd *txdi = NULL;
337 struct pl08x_txd *txd;
341 spin_lock_irqsave(&plchan->lock, flags);
343 ch = plchan->phychan;
347 * Next follow the LLIs to get the number of pending bytes in the
348 * currently active transaction.
351 struct lli *llis_va = txd->llis_va;
352 struct lli *llis_bus = (struct lli *) txd->llis_bus;
353 u32 clli = readl(ch->base + PL080_CH_LLI);
355 /* First get the bytes in the current active LLI */
356 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
361 /* Forward to the LLI pointed to by clli */
362 while ((clli != (u32) &(llis_bus[i])) &&
363 (i < MAX_NUM_TSFR_LLIS))
367 bytes += get_bytes_in_cctl(llis_va[i].cctl);
369 * A clli of 0x00000000 will terminate the
372 clli = llis_va[i].next;
378 /* Sum up all queued transactions */
379 if (!list_empty(&plchan->desc_list)) {
380 list_for_each_entry(txdi, &plchan->desc_list, node) {
386 spin_unlock_irqrestore(&plchan->lock, flags);
392 * Allocate a physical channel for a virtual channel
394 static struct pl08x_phy_chan *
395 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
396 struct pl08x_dma_chan *virt_chan)
398 struct pl08x_phy_chan *ch = NULL;
403 * Try to locate a physical channel to be used for
404 * this transfer. If all are taken return NULL and
405 * the requester will have to cope by using some fallback
406 * PIO mode or retrying later.
408 for (i = 0; i < pl08x->vd->channels; i++) {
409 ch = &pl08x->phy_chans[i];
411 spin_lock_irqsave(&ch->lock, flags);
414 ch->serving = virt_chan;
416 spin_unlock_irqrestore(&ch->lock, flags);
420 spin_unlock_irqrestore(&ch->lock, flags);
423 if (i == pl08x->vd->channels) {
424 /* No physical channel available, cope with it */
431 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
432 struct pl08x_phy_chan *ch)
436 /* Stop the channel and clear its interrupts */
437 pl08x_stop_phy_chan(ch);
438 writel((1 << ch->id), pl08x->base + PL080_ERR_CLEAR);
439 writel((1 << ch->id), pl08x->base + PL080_TC_CLEAR);
441 /* Mark it as free */
442 spin_lock_irqsave(&ch->lock, flags);
444 spin_unlock_irqrestore(&ch->lock, flags);
451 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
454 case PL080_WIDTH_8BIT:
456 case PL080_WIDTH_16BIT:
458 case PL080_WIDTH_32BIT:
467 static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
472 /* Remove all src, dst and transfersize bits */
473 retbits &= ~PL080_CONTROL_DWIDTH_MASK;
474 retbits &= ~PL080_CONTROL_SWIDTH_MASK;
475 retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
477 /* Then set the bits according to the parameters */
480 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
483 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
486 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
495 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
498 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
501 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
508 retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
513 * Autoselect a master bus to use for the transfer
514 * this prefers the destination bus if both available
515 * if fixed address on one bus the other will be chosen
517 void pl08x_choose_master_bus(struct pl08x_bus_data *src_bus,
518 struct pl08x_bus_data *dst_bus, struct pl08x_bus_data **mbus,
519 struct pl08x_bus_data **sbus, u32 cctl)
521 if (!(cctl & PL080_CONTROL_DST_INCR)) {
524 } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
528 if (dst_bus->buswidth == 4) {
531 } else if (src_bus->buswidth == 4) {
534 } else if (dst_bus->buswidth == 2) {
537 } else if (src_bus->buswidth == 2) {
541 /* src_bus->buswidth == 1 */
549 * Fills in one LLI for a certain transfer descriptor
550 * and advance the counter
552 int pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x,
553 struct pl08x_txd *txd, int num_llis, int len,
554 u32 cctl, u32 *remainder)
556 struct lli *llis_va = txd->llis_va;
557 struct lli *llis_bus = (struct lli *) txd->llis_bus;
559 BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
561 llis_va[num_llis].cctl = cctl;
562 llis_va[num_llis].src = txd->srcbus.addr;
563 llis_va[num_llis].dst = txd->dstbus.addr;
566 * On versions with dual masters, you can optionally AND on
567 * PL080_LLI_LM_AHB2 to the LLI to tell the hardware to read
568 * in new LLIs with that controller, but we always try to
569 * choose AHB1 to point into memory. The idea is to have AHB2
570 * fixed on the peripheral and AHB1 messing around in the
571 * memory. So we don't manipulate this bit currently.
574 llis_va[num_llis].next =
575 (dma_addr_t)((u32) &(llis_bus[num_llis + 1]));
577 if (cctl & PL080_CONTROL_SRC_INCR)
578 txd->srcbus.addr += len;
579 if (cctl & PL080_CONTROL_DST_INCR)
580 txd->dstbus.addr += len;
588 * Return number of bytes to fill to boundary, or len
590 static inline u32 pl08x_pre_boundary(u32 addr, u32 len)
594 boundary = ((addr >> PL08X_BOUNDARY_SHIFT) + 1)
595 << PL08X_BOUNDARY_SHIFT;
597 if (boundary < addr + len)
598 return boundary - addr;
604 * This fills in the table of LLIs for the transfer descriptor
605 * Note that we assume we never have to change the burst sizes
608 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
609 struct pl08x_txd *txd)
611 struct pl08x_channel_data *cd = txd->cd;
612 struct pl08x_bus_data *mbus, *sbus;
616 int max_bytes_per_lli;
619 struct lli *llis_bus;
622 dev_err(&pl08x->adev->dev, "%s no descriptor\n", __func__);
626 txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT,
629 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
636 * Initialize bus values for this transfer
637 * from the passed optimal values
640 dev_err(&pl08x->adev->dev, "%s no channel data\n", __func__);
644 /* Get the default CCTL from the platform data */
648 * On the PL080 we have two bus masters and we
649 * should select one for source and one for
650 * destination. We try to use AHB2 for the
651 * bus which does not increment (typically the
652 * peripheral) else we just choose something.
654 cctl &= ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
655 if (pl08x->vd->dualmaster) {
656 if (cctl & PL080_CONTROL_SRC_INCR)
657 /* Source increments, use AHB2 for destination */
658 cctl |= PL080_CONTROL_DST_AHB2;
659 else if (cctl & PL080_CONTROL_DST_INCR)
660 /* Destination increments, use AHB2 for source */
661 cctl |= PL080_CONTROL_SRC_AHB2;
663 /* Just pick something, source AHB1 dest AHB2 */
664 cctl |= PL080_CONTROL_DST_AHB2;
667 /* Find maximum width of the source bus */
668 txd->srcbus.maxwidth =
669 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
670 PL080_CONTROL_SWIDTH_SHIFT);
672 /* Find maximum width of the destination bus */
673 txd->dstbus.maxwidth =
674 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
675 PL080_CONTROL_DWIDTH_SHIFT);
677 /* Set up the bus widths to the maximum */
678 txd->srcbus.buswidth = txd->srcbus.maxwidth;
679 txd->dstbus.buswidth = txd->dstbus.maxwidth;
680 dev_vdbg(&pl08x->adev->dev,
681 "%s source bus is %d bytes wide, dest bus is %d bytes wide\n",
682 __func__, txd->srcbus.buswidth, txd->dstbus.buswidth);
686 * Bytes transferred == tsize * MIN(buswidths), not max(buswidths)
688 max_bytes_per_lli = min(txd->srcbus.buswidth, txd->dstbus.buswidth) *
689 PL080_CONTROL_TRANSFER_SIZE_MASK;
690 dev_vdbg(&pl08x->adev->dev,
691 "%s max bytes per lli = %d\n",
692 __func__, max_bytes_per_lli);
694 /* We need to count this down to zero */
695 remainder = txd->len;
696 dev_vdbg(&pl08x->adev->dev,
697 "%s remainder = %d\n",
698 __func__, remainder);
701 * Choose bus to align to
702 * - prefers destination bus if both available
703 * - if fixed address on one bus chooses other
704 * - modifies cctl to choose an apropriate master
706 pl08x_choose_master_bus(&txd->srcbus, &txd->dstbus,
711 * The lowest bit of the LLI register
712 * is also used to indicate which master to
713 * use for reading the LLIs.
716 if (txd->len < mbus->buswidth) {
718 * Less than a bus width available
719 * - send as single bytes
722 dev_vdbg(&pl08x->adev->dev,
723 "%s single byte LLIs for a transfer of "
724 "less than a bus width (remain %08x)\n",
725 __func__, remainder);
726 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
728 pl08x_fill_lli_for_desc(pl08x, txd, num_llis, 1,
734 * Make one byte LLIs until master bus is aligned
735 * - slave will then be aligned also
737 while ((mbus->addr) % (mbus->buswidth)) {
738 dev_vdbg(&pl08x->adev->dev,
739 "%s adjustment lli for less than bus width "
741 __func__, remainder);
742 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
743 num_llis = pl08x_fill_lli_for_desc
744 (pl08x, txd, num_llis, 1, cctl, &remainder);
750 * - if slave is not then we must set its width down
752 if (sbus->addr % sbus->buswidth) {
753 dev_dbg(&pl08x->adev->dev,
754 "%s set down bus width to one byte\n",
761 * Make largest possible LLIs until less than one bus
764 while (remainder > (mbus->buswidth - 1)) {
765 int lli_len, target_len;
770 * If enough left try to send max possible,
771 * otherwise try to send the remainder
773 target_len = remainder;
774 if (remainder > max_bytes_per_lli)
775 target_len = max_bytes_per_lli;
778 * Set bus lengths for incrementing busses
779 * to number of bytes which fill to next memory
782 if (cctl & PL080_CONTROL_SRC_INCR)
783 txd->srcbus.fill_bytes =
788 txd->srcbus.fill_bytes =
791 if (cctl & PL080_CONTROL_DST_INCR)
792 txd->dstbus.fill_bytes =
797 txd->dstbus.fill_bytes =
803 lli_len = min(txd->srcbus.fill_bytes,
804 txd->dstbus.fill_bytes);
806 BUG_ON(lli_len > remainder);
809 dev_err(&pl08x->adev->dev,
810 "%s lli_len is %d, <= 0\n",
815 if (lli_len == target_len) {
817 * Can send what we wanted
822 lli_len = (lli_len/mbus->buswidth) *
827 * So now we know how many bytes to transfer
828 * to get to the nearest boundary
829 * The next lli will past the boundary
830 * - however we may be working to a boundary
832 * We need to ensure the master stays aligned
834 odd_bytes = lli_len % mbus->buswidth;
836 * - and that we are working in multiples
839 lli_len -= odd_bytes;
845 * Check against minimum bus alignment:
846 * Calculate actual transfer size in relation
847 * to bus width an get a maximum remainder of
848 * the smallest bus width - 1
850 /* FIXME: use round_down()? */
851 tsize = lli_len / min(mbus->buswidth,
853 lli_len = tsize * min(mbus->buswidth,
856 if (target_len != lli_len) {
857 dev_vdbg(&pl08x->adev->dev,
858 "%s can't send what we want. Desired %08x, lli of %08x bytes in txd of %08x\n",
859 __func__, target_len, lli_len, txd->len);
862 cctl = pl08x_cctl_bits(cctl,
863 txd->srcbus.buswidth,
864 txd->dstbus.buswidth,
867 dev_vdbg(&pl08x->adev->dev,
868 "%s fill lli with single lli chunk of size %08x (remainder %08x)\n",
869 __func__, lli_len, remainder);
870 num_llis = pl08x_fill_lli_for_desc(pl08x, txd,
871 num_llis, lli_len, cctl,
873 total_bytes += lli_len;
879 * Creep past the boundary,
880 * maintaining master alignment
883 for (j = 0; (j < mbus->buswidth)
884 && (remainder); j++) {
885 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
886 dev_vdbg(&pl08x->adev->dev,
887 "%s align with boundardy, single byte (remain %08x)\n",
888 __func__, remainder);
890 pl08x_fill_lli_for_desc(pl08x,
902 dev_err(&pl08x->adev->dev, "%s remainder not fitted 0x%08x bytes\n",
903 __func__, remainder);
908 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
909 dev_vdbg(&pl08x->adev->dev,
910 "%s align with boundardy, single odd byte (remain %d)\n",
911 __func__, remainder);
912 num_llis = pl08x_fill_lli_for_desc(pl08x, txd, num_llis,
913 1, cctl, &remainder);
917 if (total_bytes != txd->len) {
918 dev_err(&pl08x->adev->dev,
919 "%s size of encoded lli:s don't match total txd, transferred 0x%08x from size 0x%08x\n",
920 __func__, total_bytes, txd->len);
924 if (num_llis >= MAX_NUM_TSFR_LLIS) {
925 dev_err(&pl08x->adev->dev,
926 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
927 __func__, (u32) MAX_NUM_TSFR_LLIS);
931 * Decide whether this is a loop or a terminated transfer
933 llis_va = txd->llis_va;
934 llis_bus = (struct lli *) txd->llis_bus;
936 if (cd->circular_buffer) {
938 * Loop the circular buffer so that the next element
939 * points back to the beginning of the LLI.
941 llis_va[num_llis - 1].next =
942 (dma_addr_t)((unsigned int)&(llis_bus[0]));
945 * On non-circular buffers, the final LLI terminates
948 llis_va[num_llis - 1].next = 0;
950 * The final LLI element shall also fire an interrupt
952 llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
955 /* Now store the channel register values */
956 txd->csrc = llis_va[0].src;
957 txd->cdst = llis_va[0].dst;
959 txd->clli = llis_va[0].next;
963 txd->cctl = llis_va[0].cctl;
964 /* ccfg will be set at physical channel allocation time */
970 for (i = 0; i < num_llis; i++) {
971 dev_vdbg(&pl08x->adev->dev,
972 "lli %d @%p: csrc=%08x, cdst=%08x, cctl=%08x, clli=%08x\n",
987 /* You should call this with the struct pl08x lock held */
988 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
989 struct pl08x_txd *txd)
992 dev_err(&pl08x->adev->dev,
993 "%s no descriptor to free\n",
997 dma_pool_free(pl08x->pool, txd->llis_va,
1005 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
1006 struct pl08x_dma_chan *plchan)
1008 struct pl08x_txd *txdi = NULL;
1009 struct pl08x_txd *next;
1011 if (!list_empty(&plchan->desc_list)) {
1012 list_for_each_entry_safe(txdi,
1013 next, &plchan->desc_list, node) {
1014 list_del(&txdi->node);
1015 pl08x_free_txd(pl08x, txdi);
1022 * The DMA ENGINE API
1024 static int pl08x_alloc_chan_resources(struct dma_chan *chan)
1029 static void pl08x_free_chan_resources(struct dma_chan *chan)
1034 * This should be called with the channel plchan->lock held
1036 static int prep_phy_channel(struct pl08x_dma_chan *plchan,
1037 struct pl08x_txd *txd)
1039 struct pl08x_driver_data *pl08x = plchan->host;
1040 struct pl08x_phy_chan *ch;
1043 /* Check if we already have a channel */
1044 if (plchan->phychan)
1047 ch = pl08x_get_phy_channel(pl08x, plchan);
1049 /* No physical channel available, cope with it */
1050 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
1055 * OK we have a physical channel: for memcpy() this is all we
1056 * need, but for slaves the physical signals may be muxed!
1057 * Can the platform allow us to use this channel?
1059 if (plchan->slave &&
1061 pl08x->pd->get_signal) {
1062 ret = pl08x->pd->get_signal(plchan);
1064 dev_dbg(&pl08x->adev->dev,
1065 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
1066 ch->id, plchan->name);
1067 /* Release physical channel & return */
1068 pl08x_put_phy_channel(pl08x, ch);
1074 dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
1079 plchan->phychan = ch;
1084 static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
1086 struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
1088 atomic_inc(&plchan->last_issued);
1089 tx->cookie = atomic_read(&plchan->last_issued);
1090 /* This unlock follows the lock in the prep() function */
1091 spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
1096 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
1097 struct dma_chan *chan, unsigned long flags)
1099 struct dma_async_tx_descriptor *retval = NULL;
1105 * Code accessing dma_async_is_complete() in a tight loop
1106 * may give problems - could schedule where indicated.
1107 * If slaves are relying on interrupts to signal completion this
1108 * function must not be called with interrupts disabled
1110 static enum dma_status
1111 pl08x_dma_tx_status(struct dma_chan *chan,
1112 dma_cookie_t cookie,
1113 struct dma_tx_state *txstate)
1115 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1116 dma_cookie_t last_used;
1117 dma_cookie_t last_complete;
1118 enum dma_status ret;
1121 last_used = atomic_read(&plchan->last_issued);
1122 last_complete = plchan->lc;
1124 ret = dma_async_is_complete(cookie, last_complete, last_used);
1125 if (ret == DMA_SUCCESS) {
1126 dma_set_tx_state(txstate, last_complete, last_used, 0);
1131 * schedule(); could be inserted here
1135 * This cookie not complete yet
1137 last_used = atomic_read(&plchan->last_issued);
1138 last_complete = plchan->lc;
1140 /* Get number of bytes left in the active transactions and queue */
1141 bytesleft = pl08x_getbytes_chan(plchan);
1143 dma_set_tx_state(txstate, last_complete, last_used,
1146 if (plchan->state == PL08X_CHAN_PAUSED)
1149 /* Whether waiting or running, we're in progress */
1150 return DMA_IN_PROGRESS;
1153 /* PrimeCell DMA extension */
1154 struct burst_table {
1159 static const struct burst_table burst_sizes[] = {
1162 .reg = (PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT) |
1163 (PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT),
1167 .reg = (PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT) |
1168 (PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT),
1172 .reg = (PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT) |
1173 (PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT),
1177 .reg = (PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT) |
1178 (PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT),
1182 .reg = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT) |
1183 (PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT),
1187 .reg = (PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT) |
1188 (PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT),
1192 .reg = (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT) |
1193 (PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT),
1197 .reg = (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1198 (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT),
1202 static void dma_set_runtime_config(struct dma_chan *chan,
1203 struct dma_slave_config *config)
1205 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1206 struct pl08x_driver_data *pl08x = plchan->host;
1207 struct pl08x_channel_data *cd = plchan->cd;
1208 enum dma_slave_buswidth addr_width;
1211 /* Mask out all except src and dst channel */
1212 u32 ccfg = cd->ccfg & 0x000003DEU;
1215 /* Transfer direction */
1216 plchan->runtime_direction = config->direction;
1217 if (config->direction == DMA_TO_DEVICE) {
1218 plchan->runtime_addr = config->dst_addr;
1219 cctl |= PL080_CONTROL_SRC_INCR;
1220 ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1221 addr_width = config->dst_addr_width;
1222 maxburst = config->dst_maxburst;
1223 } else if (config->direction == DMA_FROM_DEVICE) {
1224 plchan->runtime_addr = config->src_addr;
1225 cctl |= PL080_CONTROL_DST_INCR;
1226 ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1227 addr_width = config->src_addr_width;
1228 maxburst = config->src_maxburst;
1230 dev_err(&pl08x->adev->dev,
1231 "bad runtime_config: alien transfer direction\n");
1235 switch (addr_width) {
1236 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1237 cctl |= (PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1238 (PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT);
1240 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1241 cctl |= (PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1242 (PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT);
1244 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1245 cctl |= (PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1246 (PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT);
1249 dev_err(&pl08x->adev->dev,
1250 "bad runtime_config: alien address width\n");
1255 * Now decide on a maxburst:
1256 * If this channel will only request single transfers, set
1257 * this down to ONE element.
1259 if (plchan->cd->single) {
1260 cctl |= (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1261 (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT);
1263 while (i < ARRAY_SIZE(burst_sizes)) {
1264 if (burst_sizes[i].burstwords <= maxburst)
1268 cctl |= burst_sizes[i].reg;
1271 /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1272 cctl &= ~PL080_CONTROL_PROT_MASK;
1273 cctl |= PL080_CONTROL_PROT_SYS;
1275 /* Modify the default channel data to fit PrimeCell request */
1279 dev_dbg(&pl08x->adev->dev,
1280 "configured channel %s (%s) for %s, data width %d, "
1281 "maxburst %d words, LE, CCTL=%08x, CCFG=%08x\n",
1282 dma_chan_name(chan), plchan->name,
1283 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
1290 * Slave transactions callback to the slave device to allow
1291 * synchronization of slave DMA signals with the DMAC enable
1293 static void pl08x_issue_pending(struct dma_chan *chan)
1295 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1296 struct pl08x_driver_data *pl08x = plchan->host;
1297 unsigned long flags;
1299 spin_lock_irqsave(&plchan->lock, flags);
1300 /* Something is already active */
1302 spin_unlock_irqrestore(&plchan->lock, flags);
1306 /* Didn't get a physical channel so waiting for it ... */
1307 if (plchan->state == PL08X_CHAN_WAITING)
1310 /* Take the first element in the queue and execute it */
1311 if (!list_empty(&plchan->desc_list)) {
1312 struct pl08x_txd *next;
1314 next = list_first_entry(&plchan->desc_list,
1317 list_del(&next->node);
1319 plchan->state = PL08X_CHAN_RUNNING;
1321 /* Configure the physical channel for the active txd */
1322 pl08x_config_phychan_for_txd(plchan);
1323 pl08x_set_cregs(pl08x, plchan->phychan);
1324 pl08x_enable_phy_chan(pl08x, plchan->phychan);
1327 spin_unlock_irqrestore(&plchan->lock, flags);
1330 static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
1331 struct pl08x_txd *txd)
1334 struct pl08x_driver_data *pl08x = plchan->host;
1337 num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
1342 spin_lock_irqsave(&plchan->lock, plchan->lockflags);
1345 * If this device is not using a circular buffer then
1346 * queue this new descriptor for transfer.
1347 * The descriptor for a circular buffer continues
1348 * to be used until the channel is freed.
1350 if (txd->cd->circular_buffer)
1351 dev_err(&pl08x->adev->dev,
1352 "%s attempting to queue a circular buffer\n",
1355 list_add_tail(&txd->node,
1356 &plchan->desc_list);
1359 * See if we already have a physical channel allocated,
1360 * else this is the time to try to get one.
1362 ret = prep_phy_channel(plchan, txd);
1365 * No physical channel available, we will
1366 * stack up the memcpy channels until there is a channel
1367 * available to handle it whereas slave transfers may
1368 * have been denied due to platform channel muxing restrictions
1369 * and since there is no guarantee that this will ever be
1370 * resolved, and since the signal must be aquired AFTER
1371 * aquiring the physical channel, we will let them be NACK:ed
1372 * with -EBUSY here. The drivers can alway retry the prep()
1373 * call if they are eager on doing this using DMA.
1375 if (plchan->slave) {
1376 pl08x_free_txd_list(pl08x, plchan);
1377 spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
1380 /* Do this memcpy whenever there is a channel ready */
1381 plchan->state = PL08X_CHAN_WAITING;
1382 plchan->waiting = txd;
1385 * Else we're all set, paused and ready to roll,
1386 * status will switch to PL08X_CHAN_RUNNING when
1387 * we call issue_pending(). If there is something
1388 * running on the channel already we don't change
1391 if (plchan->state == PL08X_CHAN_IDLE)
1392 plchan->state = PL08X_CHAN_PAUSED;
1395 * Notice that we leave plchan->lock locked on purpose:
1396 * it will be unlocked in the subsequent tx_submit()
1397 * call. This is a consequence of the current API.
1404 * Initialize a descriptor to be used by memcpy submit
1406 static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1407 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1408 size_t len, unsigned long flags)
1410 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1411 struct pl08x_driver_data *pl08x = plchan->host;
1412 struct pl08x_txd *txd;
1415 txd = kzalloc(sizeof(struct pl08x_txd), GFP_NOWAIT);
1417 dev_err(&pl08x->adev->dev,
1418 "%s no memory for descriptor\n", __func__);
1422 dma_async_tx_descriptor_init(&txd->tx, chan);
1423 txd->direction = DMA_NONE;
1424 txd->srcbus.addr = src;
1425 txd->dstbus.addr = dest;
1427 /* Set platform data for m2m */
1428 txd->cd = &pl08x->pd->memcpy_channel;
1429 /* Both to be incremented or the code will break */
1430 txd->cd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
1431 txd->tx.tx_submit = pl08x_tx_submit;
1432 txd->tx.callback = NULL;
1433 txd->tx.callback_param = NULL;
1436 INIT_LIST_HEAD(&txd->node);
1437 ret = pl08x_prep_channel_resources(plchan, txd);
1441 * NB: the channel lock is held at this point so tx_submit()
1442 * must be called in direct succession.
1448 struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1449 struct dma_chan *chan, struct scatterlist *sgl,
1450 unsigned int sg_len, enum dma_data_direction direction,
1451 unsigned long flags)
1453 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1454 struct pl08x_driver_data *pl08x = plchan->host;
1455 struct pl08x_txd *txd;
1459 * Current implementation ASSUMES only one sg
1462 dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n",
1467 dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1468 __func__, sgl->length, plchan->name);
1470 txd = kzalloc(sizeof(struct pl08x_txd), GFP_NOWAIT);
1472 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1476 dma_async_tx_descriptor_init(&txd->tx, chan);
1478 if (direction != plchan->runtime_direction)
1479 dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
1480 "the direction configured for the PrimeCell\n",
1484 * Set up addresses, the PrimeCell configured address
1485 * will take precedence since this may configure the
1486 * channel target address dynamically at runtime.
1488 txd->direction = direction;
1489 if (direction == DMA_TO_DEVICE) {
1490 txd->srcbus.addr = sgl->dma_address;
1491 if (plchan->runtime_addr)
1492 txd->dstbus.addr = plchan->runtime_addr;
1494 txd->dstbus.addr = plchan->cd->addr;
1495 } else if (direction == DMA_FROM_DEVICE) {
1496 if (plchan->runtime_addr)
1497 txd->srcbus.addr = plchan->runtime_addr;
1499 txd->srcbus.addr = plchan->cd->addr;
1500 txd->dstbus.addr = sgl->dma_address;
1502 dev_err(&pl08x->adev->dev,
1503 "%s direction unsupported\n", __func__);
1506 txd->cd = plchan->cd;
1507 txd->tx.tx_submit = pl08x_tx_submit;
1508 txd->tx.callback = NULL;
1509 txd->tx.callback_param = NULL;
1510 txd->len = sgl->length;
1511 INIT_LIST_HEAD(&txd->node);
1513 ret = pl08x_prep_channel_resources(plchan, txd);
1517 * NB: the channel lock is held at this point so tx_submit()
1518 * must be called in direct succession.
1524 static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1527 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1528 struct pl08x_driver_data *pl08x = plchan->host;
1529 unsigned long flags;
1532 /* Controls applicable to inactive channels */
1533 if (cmd == DMA_SLAVE_CONFIG) {
1534 dma_set_runtime_config(chan,
1535 (struct dma_slave_config *)
1541 * Anything succeeds on channels with no physical allocation and
1542 * no queued transfers.
1544 spin_lock_irqsave(&plchan->lock, flags);
1545 if (!plchan->phychan && !plchan->at) {
1546 spin_unlock_irqrestore(&plchan->lock, flags);
1551 case DMA_TERMINATE_ALL:
1552 plchan->state = PL08X_CHAN_IDLE;
1554 if (plchan->phychan) {
1555 pl08x_stop_phy_chan(plchan->phychan);
1558 * Mark physical channel as free and free any slave
1561 if ((plchan->phychan->signal >= 0) &&
1562 pl08x->pd->put_signal) {
1563 pl08x->pd->put_signal(plchan);
1564 plchan->phychan->signal = -1;
1566 pl08x_put_phy_channel(pl08x, plchan->phychan);
1567 plchan->phychan = NULL;
1569 /* Stop any pending tasklet */
1570 tasklet_disable(&plchan->tasklet);
1571 /* Dequeue jobs and free LLIs */
1573 pl08x_free_txd(pl08x, plchan->at);
1576 /* Dequeue jobs not yet fired as well */
1577 pl08x_free_txd_list(pl08x, plchan);
1580 pl08x_pause_phy_chan(plchan->phychan);
1581 plchan->state = PL08X_CHAN_PAUSED;
1584 pl08x_resume_phy_chan(plchan->phychan);
1585 plchan->state = PL08X_CHAN_RUNNING;
1588 /* Unknown command */
1593 spin_unlock_irqrestore(&plchan->lock, flags);
1598 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1600 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1601 char *name = chan_id;
1603 /* Check that the channel is not taken! */
1604 if (!strcmp(plchan->name, name))
1611 * Just check that the device is there and active
1612 * TODO: turn this bit on/off depending on the number of
1613 * physical channels actually used, if it is zero... well
1614 * shut it off. That will save some power. Cut the clock
1617 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1621 val = readl(pl08x->base + PL080_CONFIG);
1622 val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE);
1623 /* We implictly clear bit 1 and that means little-endian mode */
1624 val |= PL080_CONFIG_ENABLE;
1625 writel(val, pl08x->base + PL080_CONFIG);
1628 static void pl08x_tasklet(unsigned long data)
1630 struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
1631 struct pl08x_phy_chan *phychan = plchan->phychan;
1632 struct pl08x_driver_data *pl08x = plchan->host;
1637 spin_lock(&plchan->lock);
1640 dma_async_tx_callback callback =
1641 plchan->at->tx.callback;
1642 void *callback_param =
1643 plchan->at->tx.callback_param;
1646 * Update last completed
1649 (plchan->at->tx.cookie);
1652 * Callback to signal completion
1655 callback(callback_param);
1658 * Device callbacks should NOT clear
1659 * the current transaction on the channel
1660 * Linus: sometimes they should?
1666 * Free the descriptor if it's not for a device
1667 * using a circular buffer
1669 if (!plchan->at->cd->circular_buffer) {
1670 pl08x_free_txd(pl08x, plchan->at);
1674 * else descriptor for circular
1675 * buffers only freed when
1676 * client has disabled dma
1680 * If a new descriptor is queued, set it up
1681 * plchan->at is NULL here
1683 if (!list_empty(&plchan->desc_list)) {
1684 struct pl08x_txd *next;
1686 next = list_first_entry(&plchan->desc_list,
1689 list_del(&next->node);
1691 /* Configure the physical channel for the next txd */
1692 pl08x_config_phychan_for_txd(plchan);
1693 pl08x_set_cregs(pl08x, plchan->phychan);
1694 pl08x_enable_phy_chan(pl08x, plchan->phychan);
1696 struct pl08x_dma_chan *waiting = NULL;
1699 * No more jobs, so free up the physical channel
1700 * Free any allocated signal on slave transfers too
1702 if ((phychan->signal >= 0) && pl08x->pd->put_signal) {
1703 pl08x->pd->put_signal(plchan);
1704 phychan->signal = -1;
1706 pl08x_put_phy_channel(pl08x, phychan);
1707 plchan->phychan = NULL;
1708 plchan->state = PL08X_CHAN_IDLE;
1711 * And NOW before anyone else can grab that free:d
1712 * up physical channel, see if there is some memcpy
1713 * pending that seriously needs to start because of
1714 * being stacked up while we were choking the
1715 * physical channels with data.
1717 list_for_each_entry(waiting, &pl08x->memcpy.channels,
1719 if (waiting->state == PL08X_CHAN_WAITING &&
1720 waiting->waiting != NULL) {
1723 /* This should REALLY not fail now */
1724 ret = prep_phy_channel(waiting,
1727 waiting->state = PL08X_CHAN_RUNNING;
1728 waiting->waiting = NULL;
1729 pl08x_issue_pending(&waiting->chan);
1735 spin_unlock(&plchan->lock);
1738 static irqreturn_t pl08x_irq(int irq, void *dev)
1740 struct pl08x_driver_data *pl08x = dev;
1745 val = readl(pl08x->base + PL080_ERR_STATUS);
1748 * An error interrupt (on one or more channels)
1750 dev_err(&pl08x->adev->dev,
1751 "%s error interrupt, register value 0x%08x\n",
1754 * Simply clear ALL PL08X error interrupts,
1755 * regardless of channel and cause
1756 * FIXME: should be 0x00000003 on PL081 really.
1758 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1760 val = readl(pl08x->base + PL080_INT_STATUS);
1761 for (i = 0; i < pl08x->vd->channels; i++) {
1762 if ((1 << i) & val) {
1763 /* Locate physical channel */
1764 struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
1765 struct pl08x_dma_chan *plchan = phychan->serving;
1767 /* Schedule tasklet on this channel */
1768 tasklet_schedule(&plchan->tasklet);
1774 * Clear only the terminal interrupts on channels we processed
1776 writel(mask, pl08x->base + PL080_TC_CLEAR);
1778 return mask ? IRQ_HANDLED : IRQ_NONE;
1782 * Initialise the DMAC memcpy/slave channels.
1783 * Make a local wrapper to hold required data
1785 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
1786 struct dma_device *dmadev,
1787 unsigned int channels,
1790 struct pl08x_dma_chan *chan;
1793 INIT_LIST_HEAD(&dmadev->channels);
1795 * Register as many many memcpy as we have physical channels,
1796 * we won't always be able to use all but the code will have
1797 * to cope with that situation.
1799 for (i = 0; i < channels; i++) {
1800 chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL);
1802 dev_err(&pl08x->adev->dev,
1803 "%s no memory for channel\n", __func__);
1808 chan->state = PL08X_CHAN_IDLE;
1812 chan->name = pl08x->pd->slave_channels[i].bus_id;
1813 chan->cd = &pl08x->pd->slave_channels[i];
1815 chan->cd = &pl08x->pd->memcpy_channel;
1816 chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1822 dev_info(&pl08x->adev->dev,
1823 "initialize virtual channel \"%s\"\n",
1826 chan->chan.device = dmadev;
1827 atomic_set(&chan->last_issued, 0);
1828 chan->lc = atomic_read(&chan->last_issued);
1830 spin_lock_init(&chan->lock);
1831 INIT_LIST_HEAD(&chan->desc_list);
1832 tasklet_init(&chan->tasklet, pl08x_tasklet,
1833 (unsigned long) chan);
1835 list_add_tail(&chan->chan.device_node, &dmadev->channels);
1837 dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
1838 i, slave ? "slave" : "memcpy");
1842 static void pl08x_free_virtual_channels(struct dma_device *dmadev)
1844 struct pl08x_dma_chan *chan = NULL;
1845 struct pl08x_dma_chan *next;
1847 list_for_each_entry_safe(chan,
1848 next, &dmadev->channels, chan.device_node) {
1849 list_del(&chan->chan.device_node);
1854 #ifdef CONFIG_DEBUG_FS
1855 static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
1858 case PL08X_CHAN_IDLE:
1860 case PL08X_CHAN_RUNNING:
1862 case PL08X_CHAN_PAUSED:
1864 case PL08X_CHAN_WAITING:
1869 return "UNKNOWN STATE";
1872 static int pl08x_debugfs_show(struct seq_file *s, void *data)
1874 struct pl08x_driver_data *pl08x = s->private;
1875 struct pl08x_dma_chan *chan;
1876 struct pl08x_phy_chan *ch;
1877 unsigned long flags;
1880 seq_printf(s, "PL08x physical channels:\n");
1881 seq_printf(s, "CHANNEL:\tUSER:\n");
1882 seq_printf(s, "--------\t-----\n");
1883 for (i = 0; i < pl08x->vd->channels; i++) {
1884 struct pl08x_dma_chan *virt_chan;
1886 ch = &pl08x->phy_chans[i];
1888 spin_lock_irqsave(&ch->lock, flags);
1889 virt_chan = ch->serving;
1891 seq_printf(s, "%d\t\t%s\n",
1892 ch->id, virt_chan ? virt_chan->name : "(none)");
1894 spin_unlock_irqrestore(&ch->lock, flags);
1897 seq_printf(s, "\nPL08x virtual memcpy channels:\n");
1898 seq_printf(s, "CHANNEL:\tSTATE:\n");
1899 seq_printf(s, "--------\t------\n");
1900 list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) {
1901 seq_printf(s, "%s\t\t\%s\n", chan->name,
1902 pl08x_state_str(chan->state));
1905 seq_printf(s, "\nPL08x virtual slave channels:\n");
1906 seq_printf(s, "CHANNEL:\tSTATE:\n");
1907 seq_printf(s, "--------\t------\n");
1908 list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) {
1909 seq_printf(s, "%s\t\t\%s\n", chan->name,
1910 pl08x_state_str(chan->state));
1916 static int pl08x_debugfs_open(struct inode *inode, struct file *file)
1918 return single_open(file, pl08x_debugfs_show, inode->i_private);
1921 static const struct file_operations pl08x_debugfs_operations = {
1922 .open = pl08x_debugfs_open,
1924 .llseek = seq_lseek,
1925 .release = single_release,
1928 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1930 /* Expose a simple debugfs interface to view all clocks */
1931 (void) debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO,
1933 &pl08x_debugfs_operations);
1937 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1942 static int pl08x_probe(struct amba_device *adev, struct amba_id *id)
1944 struct pl08x_driver_data *pl08x;
1945 struct vendor_data *vd = id->data;
1949 ret = amba_request_regions(adev, NULL);
1953 /* Create the driver state holder */
1954 pl08x = kzalloc(sizeof(struct pl08x_driver_data), GFP_KERNEL);
1960 /* Initialize memcpy engine */
1961 dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
1962 pl08x->memcpy.dev = &adev->dev;
1963 pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1964 pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
1965 pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
1966 pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1967 pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
1968 pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
1969 pl08x->memcpy.device_control = pl08x_control;
1971 /* Initialize slave engine */
1972 dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
1973 pl08x->slave.dev = &adev->dev;
1974 pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1975 pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
1976 pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1977 pl08x->slave.device_tx_status = pl08x_dma_tx_status;
1978 pl08x->slave.device_issue_pending = pl08x_issue_pending;
1979 pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
1980 pl08x->slave.device_control = pl08x_control;
1982 /* Get the platform data */
1983 pl08x->pd = dev_get_platdata(&adev->dev);
1985 dev_err(&adev->dev, "no platform data supplied\n");
1986 goto out_no_platdata;
1989 /* Assign useful pointers to the driver state */
1993 /* A DMA memory pool for LLIs, align on 1-byte boundary */
1994 pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
1995 PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
1998 goto out_no_lli_pool;
2001 spin_lock_init(&pl08x->lock);
2003 pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
2006 goto out_no_ioremap;
2009 /* Turn on the PL08x */
2010 pl08x_ensure_on(pl08x);
2013 * Attach the interrupt handler
2015 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
2016 writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
2018 ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
2021 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
2022 __func__, adev->irq[0]);
2026 /* Initialize physical channels */
2027 pl08x->phy_chans = kmalloc((vd->channels * sizeof(struct pl08x_phy_chan)),
2029 if (!pl08x->phy_chans) {
2030 dev_err(&adev->dev, "%s failed to allocate "
2031 "physical channel holders\n",
2033 goto out_no_phychans;
2036 for (i = 0; i < vd->channels; i++) {
2037 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
2040 ch->base = pl08x->base + PL080_Cx_BASE(i);
2041 spin_lock_init(&ch->lock);
2044 dev_info(&adev->dev,
2045 "physical channel %d is %s\n", i,
2046 pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
2049 /* Register as many memcpy channels as there are physical channels */
2050 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
2051 pl08x->vd->channels, false);
2053 dev_warn(&pl08x->adev->dev,
2054 "%s failed to enumerate memcpy channels - %d\n",
2058 pl08x->memcpy.chancnt = ret;
2060 /* Register slave channels */
2061 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
2062 pl08x->pd->num_slave_channels,
2065 dev_warn(&pl08x->adev->dev,
2066 "%s failed to enumerate slave channels - %d\n",
2070 pl08x->slave.chancnt = ret;
2072 ret = dma_async_device_register(&pl08x->memcpy);
2074 dev_warn(&pl08x->adev->dev,
2075 "%s failed to register memcpy as an async device - %d\n",
2077 goto out_no_memcpy_reg;
2080 ret = dma_async_device_register(&pl08x->slave);
2082 dev_warn(&pl08x->adev->dev,
2083 "%s failed to register slave as an async device - %d\n",
2085 goto out_no_slave_reg;
2088 amba_set_drvdata(adev, pl08x);
2089 init_pl08x_debugfs(pl08x);
2090 dev_info(&pl08x->adev->dev, "ARM(R) %s DMA block initialized @%08x\n",
2091 vd->name, adev->res.start);
2095 dma_async_device_unregister(&pl08x->memcpy);
2097 pl08x_free_virtual_channels(&pl08x->slave);
2099 pl08x_free_virtual_channels(&pl08x->memcpy);
2101 kfree(pl08x->phy_chans);
2103 free_irq(adev->irq[0], pl08x);
2105 iounmap(pl08x->base);
2107 dma_pool_destroy(pl08x->pool);
2112 amba_release_regions(adev);
2116 /* PL080 has 8 channels and the PL080 have just 2 */
2117 static struct vendor_data vendor_pl080 = {
2123 static struct vendor_data vendor_pl081 = {
2126 .dualmaster = false,
2129 static struct amba_id pl08x_ids[] = {
2134 .data = &vendor_pl080,
2140 .data = &vendor_pl081,
2142 /* Nomadik 8815 PL080 variant */
2146 .data = &vendor_pl080,
2151 static struct amba_driver pl08x_amba_driver = {
2152 .drv.name = DRIVER_NAME,
2153 .id_table = pl08x_ids,
2154 .probe = pl08x_probe,
2157 static int __init pl08x_init(void)
2160 retval = amba_driver_register(&pl08x_amba_driver);
2162 printk(KERN_WARNING DRIVER_NAME
2163 "failed to register as an amba device (%d)\n",
2167 subsys_initcall(pl08x_init);