3 * Support for Nomadik hardware crypto engine.
5 * Copyright (C) ST-Ericsson SA 2010
6 * Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson
7 * Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson
8 * Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson.
9 * Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson.
10 * Author: Andreas Westin <andreas.westin@stericsson.com> for ST-Ericsson.
11 * License terms: GNU General Public License (GPL) version 2
14 #include <linux/clk.h>
15 #include <linux/device.h>
16 #include <linux/err.h>
17 #include <linux/init.h>
19 #include <linux/klist.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/crypto.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/dmaengine.h>
27 #include <linux/bitops.h>
29 #include <crypto/internal/hash.h>
30 #include <crypto/sha.h>
31 #include <crypto/scatterwalk.h>
32 #include <crypto/algapi.h>
34 #include <linux/platform_data/crypto-ux500.h>
38 #define DEV_DBG_NAME "hashX hashX:"
41 module_param(hash_mode, int, 0);
42 MODULE_PARM_DESC(hash_mode, "CPU or DMA mode. CPU = 0 (default), DMA = 1");
45 * Pre-calculated empty message digests.
47 static u8 zero_message_hash_sha1[SHA1_DIGEST_SIZE] = {
48 0xda, 0x39, 0xa3, 0xee, 0x5e, 0x6b, 0x4b, 0x0d,
49 0x32, 0x55, 0xbf, 0xef, 0x95, 0x60, 0x18, 0x90,
50 0xaf, 0xd8, 0x07, 0x09
53 static u8 zero_message_hash_sha256[SHA256_DIGEST_SIZE] = {
54 0xe3, 0xb0, 0xc4, 0x42, 0x98, 0xfc, 0x1c, 0x14,
55 0x9a, 0xfb, 0xf4, 0xc8, 0x99, 0x6f, 0xb9, 0x24,
56 0x27, 0xae, 0x41, 0xe4, 0x64, 0x9b, 0x93, 0x4c,
57 0xa4, 0x95, 0x99, 0x1b, 0x78, 0x52, 0xb8, 0x55
60 /* HMAC-SHA1, no key */
61 static u8 zero_message_hmac_sha1[SHA1_DIGEST_SIZE] = {
62 0xfb, 0xdb, 0x1d, 0x1b, 0x18, 0xaa, 0x6c, 0x08,
63 0x32, 0x4b, 0x7d, 0x64, 0xb7, 0x1f, 0xb7, 0x63,
64 0x70, 0x69, 0x0e, 0x1d
67 /* HMAC-SHA256, no key */
68 static u8 zero_message_hmac_sha256[SHA256_DIGEST_SIZE] = {
69 0xb6, 0x13, 0x67, 0x9a, 0x08, 0x14, 0xd9, 0xec,
70 0x77, 0x2f, 0x95, 0xd7, 0x78, 0xc3, 0x5f, 0xc5,
71 0xff, 0x16, 0x97, 0xc4, 0x93, 0x71, 0x56, 0x53,
72 0xc6, 0xc7, 0x12, 0x14, 0x42, 0x92, 0xc5, 0xad
76 * struct hash_driver_data - data specific to the driver.
78 * @device_list: A list of registered devices to choose from.
79 * @device_allocation: A semaphore initialized with number of devices.
81 struct hash_driver_data {
82 struct klist device_list;
83 struct semaphore device_allocation;
86 static struct hash_driver_data driver_data;
88 /* Declaration of functions */
90 * hash_messagepad - Pads a message and write the nblw bits.
91 * @device_data: Structure for the hash device.
92 * @message: Last word of a message
93 * @index_bytes: The number of bytes in the last message
95 * This function manages the final part of the digest calculation, when less
96 * than 512 bits (64 bytes) remain in message. This means index_bytes < 64.
99 static void hash_messagepad(struct hash_device_data *device_data,
100 const u32 *message, u8 index_bytes);
103 * release_hash_device - Releases a previously allocated hash device.
104 * @device_data: Structure for the hash device.
107 static void release_hash_device(struct hash_device_data *device_data)
109 spin_lock(&device_data->ctx_lock);
110 device_data->current_ctx->device = NULL;
111 device_data->current_ctx = NULL;
112 spin_unlock(&device_data->ctx_lock);
115 * The down_interruptible part for this semaphore is called in
116 * cryp_get_device_data.
118 up(&driver_data.device_allocation);
121 static void hash_dma_setup_channel(struct hash_device_data *device_data,
124 struct hash_platform_data *platform_data = dev->platform_data;
125 struct dma_slave_config conf = {
126 .direction = DMA_MEM_TO_DEV,
127 .dst_addr = device_data->phybase + HASH_DMA_FIFO,
128 .dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
132 dma_cap_zero(device_data->dma.mask);
133 dma_cap_set(DMA_SLAVE, device_data->dma.mask);
135 device_data->dma.cfg_mem2hash = platform_data->mem_to_engine;
136 device_data->dma.chan_mem2hash =
137 dma_request_channel(device_data->dma.mask,
138 platform_data->dma_filter,
139 device_data->dma.cfg_mem2hash);
141 dmaengine_slave_config(device_data->dma.chan_mem2hash, &conf);
143 init_completion(&device_data->dma.complete);
146 static void hash_dma_callback(void *data)
148 struct hash_ctx *ctx = (struct hash_ctx *) data;
150 complete(&ctx->device->dma.complete);
153 static int hash_set_dma_transfer(struct hash_ctx *ctx, struct scatterlist *sg,
154 int len, enum dma_data_direction direction)
156 struct dma_async_tx_descriptor *desc = NULL;
157 struct dma_chan *channel = NULL;
160 if (direction != DMA_TO_DEVICE) {
161 dev_err(ctx->device->dev, "[%s] Invalid DMA direction",
166 sg->length = ALIGN(sg->length, HASH_DMA_ALIGN_SIZE);
168 channel = ctx->device->dma.chan_mem2hash;
169 ctx->device->dma.sg = sg;
170 ctx->device->dma.sg_len = dma_map_sg(channel->device->dev,
171 ctx->device->dma.sg, ctx->device->dma.nents,
174 if (!ctx->device->dma.sg_len) {
175 dev_err(ctx->device->dev,
176 "[%s]: Could not map the sg list (TO_DEVICE)",
181 dev_dbg(ctx->device->dev, "[%s]: Setting up DMA for buffer "
182 "(TO_DEVICE)", __func__);
183 desc = dmaengine_prep_slave_sg(channel,
184 ctx->device->dma.sg, ctx->device->dma.sg_len,
185 direction, DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
187 dev_err(ctx->device->dev,
188 "[%s]: device_prep_slave_sg() failed!", __func__);
192 desc->callback = hash_dma_callback;
193 desc->callback_param = ctx;
195 cookie = dmaengine_submit(desc);
196 dma_async_issue_pending(channel);
201 static void hash_dma_done(struct hash_ctx *ctx)
203 struct dma_chan *chan;
205 chan = ctx->device->dma.chan_mem2hash;
206 dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
207 dma_unmap_sg(chan->device->dev, ctx->device->dma.sg,
208 ctx->device->dma.sg_len, DMA_TO_DEVICE);
212 static int hash_dma_write(struct hash_ctx *ctx,
213 struct scatterlist *sg, int len)
215 int error = hash_set_dma_transfer(ctx, sg, len, DMA_TO_DEVICE);
217 dev_dbg(ctx->device->dev, "[%s]: hash_set_dma_transfer() "
226 * get_empty_message_digest - Returns a pre-calculated digest for
228 * @device_data: Structure for the hash device.
229 * @zero_hash: Buffer to return the empty message digest.
230 * @zero_hash_size: Hash size of the empty message digest.
231 * @zero_digest: True if zero_digest returned.
233 static int get_empty_message_digest(
234 struct hash_device_data *device_data,
235 u8 *zero_hash, u32 *zero_hash_size, bool *zero_digest)
238 struct hash_ctx *ctx = device_data->current_ctx;
239 *zero_digest = false;
242 * Caller responsible for ctx != NULL.
245 if (HASH_OPER_MODE_HASH == ctx->config.oper_mode) {
246 if (HASH_ALGO_SHA1 == ctx->config.algorithm) {
247 memcpy(zero_hash, &zero_message_hash_sha1[0],
249 *zero_hash_size = SHA1_DIGEST_SIZE;
251 } else if (HASH_ALGO_SHA256 ==
252 ctx->config.algorithm) {
253 memcpy(zero_hash, &zero_message_hash_sha256[0],
255 *zero_hash_size = SHA256_DIGEST_SIZE;
258 dev_err(device_data->dev, "[%s] "
259 "Incorrect algorithm!"
264 } else if (HASH_OPER_MODE_HMAC == ctx->config.oper_mode) {
266 if (HASH_ALGO_SHA1 == ctx->config.algorithm) {
267 memcpy(zero_hash, &zero_message_hmac_sha1[0],
269 *zero_hash_size = SHA1_DIGEST_SIZE;
271 } else if (HASH_ALGO_SHA256 == ctx->config.algorithm) {
272 memcpy(zero_hash, &zero_message_hmac_sha256[0],
274 *zero_hash_size = SHA256_DIGEST_SIZE;
277 dev_err(device_data->dev, "[%s] "
278 "Incorrect algorithm!"
284 dev_dbg(device_data->dev, "[%s] Continue hash "
285 "calculation, since hmac key avalable",
295 * hash_disable_power - Request to disable power and clock.
296 * @device_data: Structure for the hash device.
297 * @save_device_state: If true, saves the current hw state.
299 * This function request for disabling power (regulator) and clock,
300 * and could also save current hw state.
302 static int hash_disable_power(
303 struct hash_device_data *device_data,
304 bool save_device_state)
307 struct device *dev = device_data->dev;
309 spin_lock(&device_data->power_state_lock);
310 if (!device_data->power_state)
313 if (save_device_state) {
314 hash_save_state(device_data,
315 &device_data->state);
316 device_data->restore_dev_state = true;
319 clk_disable(device_data->clk);
320 ret = regulator_disable(device_data->regulator);
322 dev_err(dev, "[%s] regulator_disable() failed!", __func__);
324 device_data->power_state = false;
327 spin_unlock(&device_data->power_state_lock);
333 * hash_enable_power - Request to enable power and clock.
334 * @device_data: Structure for the hash device.
335 * @restore_device_state: If true, restores a previous saved hw state.
337 * This function request for enabling power (regulator) and clock,
338 * and could also restore a previously saved hw state.
340 static int hash_enable_power(
341 struct hash_device_data *device_data,
342 bool restore_device_state)
345 struct device *dev = device_data->dev;
347 spin_lock(&device_data->power_state_lock);
348 if (!device_data->power_state) {
349 ret = regulator_enable(device_data->regulator);
351 dev_err(dev, "[%s]: regulator_enable() failed!",
355 ret = clk_enable(device_data->clk);
357 dev_err(dev, "[%s]: clk_enable() failed!",
359 ret = regulator_disable(
360 device_data->regulator);
363 device_data->power_state = true;
366 if (device_data->restore_dev_state) {
367 if (restore_device_state) {
368 device_data->restore_dev_state = false;
369 hash_resume_state(device_data,
370 &device_data->state);
374 spin_unlock(&device_data->power_state_lock);
380 * hash_get_device_data - Checks for an available hash device and return it.
381 * @hash_ctx: Structure for the hash context.
382 * @device_data: Structure for the hash device.
384 * This function check for an available hash device and return it to
386 * Note! Caller need to release the device, calling up().
388 static int hash_get_device_data(struct hash_ctx *ctx,
389 struct hash_device_data **device_data)
392 struct klist_iter device_iterator;
393 struct klist_node *device_node;
394 struct hash_device_data *local_device_data = NULL;
396 /* Wait until a device is available */
397 ret = down_interruptible(&driver_data.device_allocation);
399 return ret; /* Interrupted */
401 /* Select a device */
402 klist_iter_init(&driver_data.device_list, &device_iterator);
403 device_node = klist_next(&device_iterator);
404 while (device_node) {
405 local_device_data = container_of(device_node,
406 struct hash_device_data, list_node);
407 spin_lock(&local_device_data->ctx_lock);
408 /* current_ctx allocates a device, NULL = unallocated */
409 if (local_device_data->current_ctx) {
410 device_node = klist_next(&device_iterator);
412 local_device_data->current_ctx = ctx;
413 ctx->device = local_device_data;
414 spin_unlock(&local_device_data->ctx_lock);
417 spin_unlock(&local_device_data->ctx_lock);
419 klist_iter_exit(&device_iterator);
423 * No free device found.
424 * Since we allocated a device with down_interruptible, this
425 * should not be able to happen.
426 * Number of available devices, which are contained in
427 * device_allocation, is therefore decremented by not doing
428 * an up(device_allocation).
433 *device_data = local_device_data;
439 * hash_hw_write_key - Writes the key to the hardware registries.
441 * @device_data: Structure for the hash device.
442 * @key: Key to be written.
443 * @keylen: The lengt of the key.
445 * Note! This function DOES NOT write to the NBLW registry, even though
446 * specified in the the hw design spec. Either due to incorrect info in the
447 * spec or due to a bug in the hw.
449 static void hash_hw_write_key(struct hash_device_data *device_data,
450 const u8 *key, unsigned int keylen)
455 HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK);
457 while (keylen >= 4) {
458 u32 *key_word = (u32 *)key;
460 HASH_SET_DIN(key_word, nwords);
465 /* Take care of the remaining bytes in the last word */
469 word |= (key[keylen - 1] << (8 * (keylen - 1)));
473 HASH_SET_DIN(&word, nwords);
476 while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
481 while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
486 * init_hash_hw - Initialise the hash hardware for a new calculation.
487 * @device_data: Structure for the hash device.
488 * @ctx: The hash context.
490 * This function will enable the bits needed to clear and start a new
493 static int init_hash_hw(struct hash_device_data *device_data,
494 struct hash_ctx *ctx)
498 ret = hash_setconfiguration(device_data, &ctx->config);
500 dev_err(device_data->dev, "[%s] hash_setconfiguration() "
501 "failed!", __func__);
505 hash_begin(device_data, ctx);
507 if (ctx->config.oper_mode == HASH_OPER_MODE_HMAC)
508 hash_hw_write_key(device_data, ctx->key, ctx->keylen);
514 * hash_get_nents - Return number of entries (nents) in scatterlist (sg).
517 * @size: Size in bytes.
518 * @aligned: True if sg data aligned to work in DMA mode.
521 static int hash_get_nents(struct scatterlist *sg, int size, bool *aligned)
524 bool aligned_data = true;
526 while (size > 0 && sg) {
530 /* hash_set_dma_transfer will align last nent */
531 if ((aligned && !IS_ALIGNED(sg->offset, HASH_DMA_ALIGN_SIZE))
532 || (!IS_ALIGNED(sg->length, HASH_DMA_ALIGN_SIZE) &&
534 aligned_data = false;
540 *aligned = aligned_data;
549 * hash_dma_valid_data - checks for dma valid sg data.
551 * @datasize: Datasize in bytes.
553 * NOTE! This function checks for dma valid sg data, since dma
554 * only accept datasizes of even wordsize.
556 static bool hash_dma_valid_data(struct scatterlist *sg, int datasize)
560 /* Need to include at least one nent, else error */
561 if (hash_get_nents(sg, datasize, &aligned) < 1)
568 * hash_init - Common hash init function for SHA1/SHA2 (SHA256).
569 * @req: The hash request for the job.
571 * Initialize structures.
573 static int hash_init(struct ahash_request *req)
575 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
576 struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
577 struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
582 memset(&req_ctx->state, 0, sizeof(struct hash_state));
583 req_ctx->updated = 0;
584 if (hash_mode == HASH_MODE_DMA) {
585 if (req->nbytes < HASH_DMA_ALIGN_SIZE) {
586 req_ctx->dma_mode = false; /* Don't use DMA */
588 pr_debug(DEV_DBG_NAME " [%s] DMA mode, but direct "
589 "to CPU mode for data size < %d",
590 __func__, HASH_DMA_ALIGN_SIZE);
592 if (req->nbytes >= HASH_DMA_PERFORMANCE_MIN_SIZE &&
593 hash_dma_valid_data(req->src,
595 req_ctx->dma_mode = true;
597 req_ctx->dma_mode = false;
598 pr_debug(DEV_DBG_NAME " [%s] DMA mode, but use"
599 " CPU mode for datalength < %d"
600 " or non-aligned data, except "
601 "in last nent", __func__,
602 HASH_DMA_PERFORMANCE_MIN_SIZE);
610 * hash_processblock - This function processes a single block of 512 bits (64
611 * bytes), word aligned, starting at message.
612 * @device_data: Structure for the hash device.
613 * @message: Block (512 bits) of message to be written to
617 static void hash_processblock(
618 struct hash_device_data *device_data,
619 const u32 *message, int length)
621 int len = length / HASH_BYTES_PER_WORD;
623 * NBLW bits. Reset the number of bits in last word (NBLW).
625 HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK);
628 * Write message data to the HASH_DIN register.
630 HASH_SET_DIN(message, len);
634 * hash_messagepad - Pads a message and write the nblw bits.
635 * @device_data: Structure for the hash device.
636 * @message: Last word of a message.
637 * @index_bytes: The number of bytes in the last message.
639 * This function manages the final part of the digest calculation, when less
640 * than 512 bits (64 bytes) remain in message. This means index_bytes < 64.
643 static void hash_messagepad(struct hash_device_data *device_data,
644 const u32 *message, u8 index_bytes)
649 * Clear hash str register, only clear NBLW
650 * since DCAL will be reset by hardware.
652 HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK);
655 while (index_bytes >= 4) {
656 HASH_SET_DIN(message, nwords);
662 HASH_SET_DIN(message, nwords);
664 while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
667 /* num_of_bytes == 0 => NBLW <- 0 (32 bits valid in DATAIN) */
668 HASH_SET_NBLW(index_bytes * 8);
669 dev_dbg(device_data->dev, "[%s] DIN=0x%08x NBLW=%d", __func__,
670 readl_relaxed(&device_data->base->din),
671 (int)(readl_relaxed(&device_data->base->str) &
672 HASH_STR_NBLW_MASK));
674 dev_dbg(device_data->dev, "[%s] after dcal -> DIN=0x%08x NBLW=%d",
675 __func__, readl_relaxed(&device_data->base->din),
676 (int)(readl_relaxed(&device_data->base->str) &
677 HASH_STR_NBLW_MASK));
679 while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
684 * hash_incrementlength - Increments the length of the current message.
686 * @incr: Length of message processed already
688 * Overflow cannot occur, because conditions for overflow are checked in
691 static void hash_incrementlength(struct hash_req_ctx *ctx, u32 incr)
693 ctx->state.length.low_word += incr;
695 /* Check for wrap-around */
696 if (ctx->state.length.low_word < incr)
697 ctx->state.length.high_word++;
701 * hash_setconfiguration - Sets the required configuration for the hash
703 * @device_data: Structure for the hash device.
704 * @config: Pointer to a configuration structure.
706 int hash_setconfiguration(struct hash_device_data *device_data,
707 struct hash_config *config)
711 if (config->algorithm != HASH_ALGO_SHA1 &&
712 config->algorithm != HASH_ALGO_SHA256)
716 * DATAFORM bits. Set the DATAFORM bits to 0b11, which means the data
717 * to be written to HASH_DIN is considered as 32 bits.
719 HASH_SET_DATA_FORMAT(config->data_format);
722 * ALGO bit. Set to 0b1 for SHA-1 and 0b0 for SHA-256
724 switch (config->algorithm) {
726 HASH_SET_BITS(&device_data->base->cr, HASH_CR_ALGO_MASK);
729 case HASH_ALGO_SHA256:
730 HASH_CLEAR_BITS(&device_data->base->cr, HASH_CR_ALGO_MASK);
734 dev_err(device_data->dev, "[%s] Incorrect algorithm.",
740 * MODE bit. This bit selects between HASH or HMAC mode for the
741 * selected algorithm. 0b0 = HASH and 0b1 = HMAC.
743 if (HASH_OPER_MODE_HASH == config->oper_mode)
744 HASH_CLEAR_BITS(&device_data->base->cr,
746 else if (HASH_OPER_MODE_HMAC == config->oper_mode) {
747 HASH_SET_BITS(&device_data->base->cr,
749 if (device_data->current_ctx->keylen > HASH_BLOCK_SIZE) {
750 /* Truncate key to blocksize */
751 dev_dbg(device_data->dev, "[%s] LKEY set", __func__);
752 HASH_SET_BITS(&device_data->base->cr,
755 dev_dbg(device_data->dev, "[%s] LKEY cleared",
757 HASH_CLEAR_BITS(&device_data->base->cr,
760 } else { /* Wrong hash mode */
762 dev_err(device_data->dev, "[%s] HASH_INVALID_PARAMETER!",
769 * hash_begin - This routine resets some globals and initializes the hash
771 * @device_data: Structure for the hash device.
772 * @ctx: Hash context.
774 void hash_begin(struct hash_device_data *device_data, struct hash_ctx *ctx)
776 /* HW and SW initializations */
777 /* Note: there is no need to initialize buffer and digest members */
779 while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
783 * INIT bit. Set this bit to 0b1 to reset the HASH processor core and
784 * prepare the initialize the HASH accelerator to compute the message
785 * digest of a new message.
790 * NBLW bits. Reset the number of bits in last word (NBLW).
792 HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK);
795 static int hash_process_data(struct hash_device_data *device_data,
796 struct hash_ctx *ctx, struct hash_req_ctx *req_ctx,
797 int msg_length, u8 *data_buffer, u8 *buffer, u8 *index)
803 if ((*index + msg_length) < HASH_BLOCK_SIZE) {
804 for (count = 0; count < msg_length; count++) {
805 buffer[*index + count] =
806 *(data_buffer + count);
808 *index += msg_length;
811 if (req_ctx->updated) {
813 ret = hash_resume_state(device_data,
814 &device_data->state);
815 memmove(req_ctx->state.buffer,
816 device_data->state.buffer,
817 HASH_BLOCK_SIZE / sizeof(u32));
819 dev_err(device_data->dev, "[%s] "
820 "hash_resume_state()"
821 " failed!", __func__);
825 ret = init_hash_hw(device_data, ctx);
827 dev_err(device_data->dev, "[%s] "
829 " failed!", __func__);
832 req_ctx->updated = 1;
835 * If 'data_buffer' is four byte aligned and
836 * local buffer does not have any data, we can
837 * write data directly from 'data_buffer' to
838 * HW peripheral, otherwise we first copy data
841 if ((0 == (((u32)data_buffer) % 4))
843 hash_processblock(device_data,
845 data_buffer, HASH_BLOCK_SIZE);
847 for (count = 0; count <
848 (u32)(HASH_BLOCK_SIZE -
851 buffer[*index + count] =
852 *(data_buffer + count);
854 hash_processblock(device_data,
858 hash_incrementlength(req_ctx, HASH_BLOCK_SIZE);
859 data_buffer += (HASH_BLOCK_SIZE - *index);
861 msg_length -= (HASH_BLOCK_SIZE - *index);
864 ret = hash_save_state(device_data,
865 &device_data->state);
867 memmove(device_data->state.buffer,
868 req_ctx->state.buffer,
869 HASH_BLOCK_SIZE / sizeof(u32));
871 dev_err(device_data->dev, "[%s] "
873 " failed!", __func__);
877 } while (msg_length != 0);
884 * hash_dma_final - The hash dma final function for SHA1/SHA256.
885 * @req: The hash request for the job.
887 static int hash_dma_final(struct ahash_request *req)
890 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
891 struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
892 struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
893 struct hash_device_data *device_data;
894 u8 digest[SHA256_DIGEST_SIZE];
895 int bytes_written = 0;
897 ret = hash_get_device_data(ctx, &device_data);
901 dev_dbg(device_data->dev, "[%s] (ctx=0x%x)!", __func__, (u32) ctx);
903 if (req_ctx->updated) {
904 ret = hash_resume_state(device_data, &device_data->state);
907 dev_err(device_data->dev, "[%s] hash_resume_state() "
908 "failed!", __func__);
914 if (!req_ctx->updated) {
915 ret = hash_setconfiguration(device_data, &ctx->config);
917 dev_err(device_data->dev, "[%s] "
918 "hash_setconfiguration() failed!",
923 /* Enable DMA input */
924 if (hash_mode != HASH_MODE_DMA || !req_ctx->dma_mode) {
925 HASH_CLEAR_BITS(&device_data->base->cr,
928 HASH_SET_BITS(&device_data->base->cr,
930 HASH_SET_BITS(&device_data->base->cr,
936 if (ctx->config.oper_mode == HASH_OPER_MODE_HMAC)
937 hash_hw_write_key(device_data, ctx->key, ctx->keylen);
939 /* Number of bits in last word = (nbytes * 8) % 32 */
940 HASH_SET_NBLW((req->nbytes * 8) % 32);
941 req_ctx->updated = 1;
944 /* Store the nents in the dma struct. */
945 ctx->device->dma.nents = hash_get_nents(req->src, req->nbytes, NULL);
946 if (!ctx->device->dma.nents) {
947 dev_err(device_data->dev, "[%s] "
948 "ctx->device->dma.nents = 0", __func__);
949 ret = ctx->device->dma.nents;
953 bytes_written = hash_dma_write(ctx, req->src, req->nbytes);
954 if (bytes_written != req->nbytes) {
955 dev_err(device_data->dev, "[%s] "
956 "hash_dma_write() failed!", __func__);
961 wait_for_completion(&ctx->device->dma.complete);
964 while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
967 if (ctx->config.oper_mode == HASH_OPER_MODE_HMAC && ctx->key) {
968 unsigned int keylen = ctx->keylen;
971 dev_dbg(device_data->dev, "[%s] keylen: %d", __func__,
973 hash_hw_write_key(device_data, key, keylen);
976 hash_get_digest(device_data, digest, ctx->config.algorithm);
977 memcpy(req->result, digest, ctx->digestsize);
980 release_hash_device(device_data);
983 * Allocated in setkey, and only used in HMAC.
991 * hash_hw_final - The final hash calculation function
992 * @req: The hash request for the job.
994 static int hash_hw_final(struct ahash_request *req)
997 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
998 struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
999 struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
1000 struct hash_device_data *device_data;
1001 u8 digest[SHA256_DIGEST_SIZE];
1003 ret = hash_get_device_data(ctx, &device_data);
1007 dev_dbg(device_data->dev, "[%s] (ctx=0x%x)!", __func__, (u32) ctx);
1009 if (req_ctx->updated) {
1010 ret = hash_resume_state(device_data, &device_data->state);
1013 dev_err(device_data->dev, "[%s] hash_resume_state() "
1014 "failed!", __func__);
1017 } else if (req->nbytes == 0 && ctx->keylen == 0) {
1018 u8 zero_hash[SHA256_DIGEST_SIZE];
1019 u32 zero_hash_size = 0;
1020 bool zero_digest = false;
1022 * Use a pre-calculated empty message digest
1023 * (workaround since hw return zeroes, hw bug!?)
1025 ret = get_empty_message_digest(device_data, &zero_hash[0],
1026 &zero_hash_size, &zero_digest);
1027 if (!ret && likely(zero_hash_size == ctx->digestsize) &&
1029 memcpy(req->result, &zero_hash[0], ctx->digestsize);
1031 } else if (!ret && !zero_digest) {
1032 dev_dbg(device_data->dev, "[%s] HMAC zero msg with "
1033 "key, continue...", __func__);
1035 dev_err(device_data->dev, "[%s] ret=%d, or wrong "
1036 "digest size? %s", __func__, ret,
1037 (zero_hash_size == ctx->digestsize) ?
1042 } else if (req->nbytes == 0 && ctx->keylen > 0) {
1043 dev_err(device_data->dev, "[%s] Empty message with "
1044 "keylength > 0, NOT supported.", __func__);
1048 if (!req_ctx->updated) {
1049 ret = init_hash_hw(device_data, ctx);
1051 dev_err(device_data->dev, "[%s] init_hash_hw() "
1052 "failed!", __func__);
1057 if (req_ctx->state.index) {
1058 hash_messagepad(device_data, req_ctx->state.buffer,
1059 req_ctx->state.index);
1062 while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
1066 if (ctx->config.oper_mode == HASH_OPER_MODE_HMAC && ctx->key) {
1067 unsigned int keylen = ctx->keylen;
1070 dev_dbg(device_data->dev, "[%s] keylen: %d", __func__,
1072 hash_hw_write_key(device_data, key, keylen);
1075 hash_get_digest(device_data, digest, ctx->config.algorithm);
1076 memcpy(req->result, digest, ctx->digestsize);
1079 release_hash_device(device_data);
1082 * Allocated in setkey, and only used in HMAC.
1090 * hash_hw_update - Updates current HASH computation hashing another part of
1092 * @req: Byte array containing the message to be hashed (caller
1095 int hash_hw_update(struct ahash_request *req)
1100 struct hash_device_data *device_data;
1102 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1103 struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1104 struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
1105 struct crypto_hash_walk walk;
1106 int msg_length = crypto_hash_walk_first(req, &walk);
1108 /* Empty message ("") is correct indata */
1109 if (msg_length == 0)
1112 index = req_ctx->state.index;
1113 buffer = (u8 *)req_ctx->state.buffer;
1115 /* Check if ctx->state.length + msg_length
1117 if (msg_length > (req_ctx->state.length.low_word + msg_length) &&
1118 HASH_HIGH_WORD_MAX_VAL ==
1119 req_ctx->state.length.high_word) {
1120 pr_err(DEV_DBG_NAME " [%s] HASH_MSG_LENGTH_OVERFLOW!",
1125 ret = hash_get_device_data(ctx, &device_data);
1130 while (0 != msg_length) {
1131 data_buffer = walk.data;
1132 ret = hash_process_data(device_data, ctx, req_ctx, msg_length,
1133 data_buffer, buffer, &index);
1136 dev_err(device_data->dev, "[%s] hash_internal_hw_"
1137 "update() failed!", __func__);
1141 msg_length = crypto_hash_walk_done(&walk, 0);
1144 req_ctx->state.index = index;
1145 dev_dbg(device_data->dev, "[%s] indata length=%d, bin=%d))",
1146 __func__, req_ctx->state.index,
1147 req_ctx->state.bit_index);
1150 release_hash_device(device_data);
1156 * hash_resume_state - Function that resumes the state of an calculation.
1157 * @device_data: Pointer to the device structure.
1158 * @device_state: The state to be restored in the hash hardware
1160 int hash_resume_state(struct hash_device_data *device_data,
1161 const struct hash_state *device_state)
1165 int hash_mode = HASH_OPER_MODE_HASH;
1167 if (NULL == device_state) {
1168 dev_err(device_data->dev, "[%s] HASH_INVALID_PARAMETER!",
1173 /* Check correctness of index and length members */
1174 if (device_state->index > HASH_BLOCK_SIZE
1175 || (device_state->length.low_word % HASH_BLOCK_SIZE) != 0) {
1176 dev_err(device_data->dev, "[%s] HASH_INVALID_PARAMETER!",
1182 * INIT bit. Set this bit to 0b1 to reset the HASH processor core and
1183 * prepare the initialize the HASH accelerator to compute the message
1184 * digest of a new message.
1188 temp_cr = device_state->temp_cr;
1189 writel_relaxed(temp_cr & HASH_CR_RESUME_MASK, &device_data->base->cr);
1191 if (readl(&device_data->base->cr) & HASH_CR_MODE_MASK)
1192 hash_mode = HASH_OPER_MODE_HMAC;
1194 hash_mode = HASH_OPER_MODE_HASH;
1196 for (count = 0; count < HASH_CSR_COUNT; count++) {
1197 if ((count >= 36) && (hash_mode == HASH_OPER_MODE_HASH))
1200 writel_relaxed(device_state->csr[count],
1201 &device_data->base->csrx[count]);
1204 writel_relaxed(device_state->csfull, &device_data->base->csfull);
1205 writel_relaxed(device_state->csdatain, &device_data->base->csdatain);
1207 writel_relaxed(device_state->str_reg, &device_data->base->str);
1208 writel_relaxed(temp_cr, &device_data->base->cr);
1214 * hash_save_state - Function that saves the state of hardware.
1215 * @device_data: Pointer to the device structure.
1216 * @device_state: The strucure where the hardware state should be saved.
1218 int hash_save_state(struct hash_device_data *device_data,
1219 struct hash_state *device_state)
1223 int hash_mode = HASH_OPER_MODE_HASH;
1225 if (NULL == device_state) {
1226 dev_err(device_data->dev, "[%s] HASH_INVALID_PARAMETER!",
1231 /* Write dummy value to force digest intermediate calculation. This
1232 * actually makes sure that there isn't any ongoing calculation in the
1235 while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
1238 temp_cr = readl_relaxed(&device_data->base->cr);
1240 device_state->str_reg = readl_relaxed(&device_data->base->str);
1242 device_state->din_reg = readl_relaxed(&device_data->base->din);
1244 if (readl(&device_data->base->cr) & HASH_CR_MODE_MASK)
1245 hash_mode = HASH_OPER_MODE_HMAC;
1247 hash_mode = HASH_OPER_MODE_HASH;
1249 for (count = 0; count < HASH_CSR_COUNT; count++) {
1250 if ((count >= 36) && (hash_mode == HASH_OPER_MODE_HASH))
1253 device_state->csr[count] =
1254 readl_relaxed(&device_data->base->csrx[count]);
1257 device_state->csfull = readl_relaxed(&device_data->base->csfull);
1258 device_state->csdatain = readl_relaxed(&device_data->base->csdatain);
1260 device_state->temp_cr = temp_cr;
1266 * hash_check_hw - This routine checks for peripheral Ids and PCell Ids.
1270 int hash_check_hw(struct hash_device_data *device_data)
1272 /* Checking Peripheral Ids */
1273 if (HASH_P_ID0 == readl_relaxed(&device_data->base->periphid0)
1274 && HASH_P_ID1 == readl_relaxed(&device_data->base->periphid1)
1275 && HASH_P_ID2 == readl_relaxed(&device_data->base->periphid2)
1276 && HASH_P_ID3 == readl_relaxed(&device_data->base->periphid3)
1277 && HASH_CELL_ID0 == readl_relaxed(&device_data->base->cellid0)
1278 && HASH_CELL_ID1 == readl_relaxed(&device_data->base->cellid1)
1279 && HASH_CELL_ID2 == readl_relaxed(&device_data->base->cellid2)
1280 && HASH_CELL_ID3 == readl_relaxed(&device_data->base->cellid3)
1285 dev_err(device_data->dev, "[%s] HASH_UNSUPPORTED_HW!",
1291 * hash_get_digest - Gets the digest.
1292 * @device_data: Pointer to the device structure.
1293 * @digest: User allocated byte array for the calculated digest.
1294 * @algorithm: The algorithm in use.
1296 void hash_get_digest(struct hash_device_data *device_data,
1297 u8 *digest, int algorithm)
1299 u32 temp_hx_val, count;
1302 if (algorithm != HASH_ALGO_SHA1 && algorithm != HASH_ALGO_SHA256) {
1303 dev_err(device_data->dev, "[%s] Incorrect algorithm %d",
1304 __func__, algorithm);
1308 if (algorithm == HASH_ALGO_SHA1)
1309 loop_ctr = SHA1_DIGEST_SIZE / sizeof(u32);
1311 loop_ctr = SHA256_DIGEST_SIZE / sizeof(u32);
1313 dev_dbg(device_data->dev, "[%s] digest array:(0x%x)",
1314 __func__, (u32) digest);
1316 /* Copy result into digest array */
1317 for (count = 0; count < loop_ctr; count++) {
1318 temp_hx_val = readl_relaxed(&device_data->base->hx[count]);
1319 digest[count * 4] = (u8) ((temp_hx_val >> 24) & 0xFF);
1320 digest[count * 4 + 1] = (u8) ((temp_hx_val >> 16) & 0xFF);
1321 digest[count * 4 + 2] = (u8) ((temp_hx_val >> 8) & 0xFF);
1322 digest[count * 4 + 3] = (u8) ((temp_hx_val >> 0) & 0xFF);
1327 * hash_update - The hash update function for SHA1/SHA2 (SHA256).
1328 * @req: The hash request for the job.
1330 static int ahash_update(struct ahash_request *req)
1333 struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
1335 if (hash_mode != HASH_MODE_DMA || !req_ctx->dma_mode)
1336 ret = hash_hw_update(req);
1337 /* Skip update for DMA, all data will be passed to DMA in final */
1340 pr_err(DEV_DBG_NAME " [%s] hash_hw_update() failed!",
1348 * hash_final - The hash final function for SHA1/SHA2 (SHA256).
1349 * @req: The hash request for the job.
1351 static int ahash_final(struct ahash_request *req)
1354 struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
1356 pr_debug(DEV_DBG_NAME " [%s] data size: %d", __func__, req->nbytes);
1358 if ((hash_mode == HASH_MODE_DMA) && req_ctx->dma_mode)
1359 ret = hash_dma_final(req);
1361 ret = hash_hw_final(req);
1364 pr_err(DEV_DBG_NAME " [%s] hash_hw/dma_final() failed",
1371 static int hash_setkey(struct crypto_ahash *tfm,
1372 const u8 *key, unsigned int keylen, int alg)
1375 struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1380 ctx->key = kmemdup(key, keylen, GFP_KERNEL);
1382 pr_err(DEV_DBG_NAME " [%s] Failed to allocate ctx->key "
1383 "for %d\n", __func__, alg);
1386 ctx->keylen = keylen;
1391 static int ahash_sha1_init(struct ahash_request *req)
1393 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1394 struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1396 ctx->config.data_format = HASH_DATA_8_BITS;
1397 ctx->config.algorithm = HASH_ALGO_SHA1;
1398 ctx->config.oper_mode = HASH_OPER_MODE_HASH;
1399 ctx->digestsize = SHA1_DIGEST_SIZE;
1401 return hash_init(req);
1404 static int ahash_sha256_init(struct ahash_request *req)
1406 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1407 struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1409 ctx->config.data_format = HASH_DATA_8_BITS;
1410 ctx->config.algorithm = HASH_ALGO_SHA256;
1411 ctx->config.oper_mode = HASH_OPER_MODE_HASH;
1412 ctx->digestsize = SHA256_DIGEST_SIZE;
1414 return hash_init(req);
1417 static int ahash_sha1_digest(struct ahash_request *req)
1421 ret1 = ahash_sha1_init(req);
1425 ret1 = ahash_update(req);
1426 ret2 = ahash_final(req);
1429 return ret1 ? ret1 : ret2;
1432 static int ahash_sha256_digest(struct ahash_request *req)
1436 ret1 = ahash_sha256_init(req);
1440 ret1 = ahash_update(req);
1441 ret2 = ahash_final(req);
1444 return ret1 ? ret1 : ret2;
1447 static int hmac_sha1_init(struct ahash_request *req)
1449 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1450 struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1452 ctx->config.data_format = HASH_DATA_8_BITS;
1453 ctx->config.algorithm = HASH_ALGO_SHA1;
1454 ctx->config.oper_mode = HASH_OPER_MODE_HMAC;
1455 ctx->digestsize = SHA1_DIGEST_SIZE;
1457 return hash_init(req);
1460 static int hmac_sha256_init(struct ahash_request *req)
1462 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1463 struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1465 ctx->config.data_format = HASH_DATA_8_BITS;
1466 ctx->config.algorithm = HASH_ALGO_SHA256;
1467 ctx->config.oper_mode = HASH_OPER_MODE_HMAC;
1468 ctx->digestsize = SHA256_DIGEST_SIZE;
1470 return hash_init(req);
1473 static int hmac_sha1_digest(struct ahash_request *req)
1477 ret1 = hmac_sha1_init(req);
1481 ret1 = ahash_update(req);
1482 ret2 = ahash_final(req);
1485 return ret1 ? ret1 : ret2;
1488 static int hmac_sha256_digest(struct ahash_request *req)
1492 ret1 = hmac_sha256_init(req);
1496 ret1 = ahash_update(req);
1497 ret2 = ahash_final(req);
1500 return ret1 ? ret1 : ret2;
1503 static int hmac_sha1_setkey(struct crypto_ahash *tfm,
1504 const u8 *key, unsigned int keylen)
1506 return hash_setkey(tfm, key, keylen, HASH_ALGO_SHA1);
1509 static int hmac_sha256_setkey(struct crypto_ahash *tfm,
1510 const u8 *key, unsigned int keylen)
1512 return hash_setkey(tfm, key, keylen, HASH_ALGO_SHA256);
1515 struct hash_algo_template {
1516 struct hash_config conf;
1517 struct ahash_alg hash;
1520 static int hash_cra_init(struct crypto_tfm *tfm)
1522 struct hash_ctx *ctx = crypto_tfm_ctx(tfm);
1523 struct crypto_alg *alg = tfm->__crt_alg;
1524 struct hash_algo_template *hash_alg;
1526 hash_alg = container_of(__crypto_ahash_alg(alg),
1527 struct hash_algo_template,
1530 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1531 sizeof(struct hash_req_ctx));
1533 ctx->config.data_format = HASH_DATA_8_BITS;
1534 ctx->config.algorithm = hash_alg->conf.algorithm;
1535 ctx->config.oper_mode = hash_alg->conf.oper_mode;
1537 ctx->digestsize = hash_alg->hash.halg.digestsize;
1542 static struct hash_algo_template hash_algs[] = {
1544 .conf.algorithm = HASH_ALGO_SHA1,
1545 .conf.oper_mode = HASH_OPER_MODE_HASH,
1548 .update = ahash_update,
1549 .final = ahash_final,
1550 .digest = ahash_sha1_digest,
1551 .halg.digestsize = SHA1_DIGEST_SIZE,
1552 .halg.statesize = sizeof(struct hash_ctx),
1555 .cra_driver_name = "sha1-ux500",
1556 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1558 .cra_blocksize = SHA1_BLOCK_SIZE,
1559 .cra_ctxsize = sizeof(struct hash_ctx),
1560 .cra_init = hash_cra_init,
1561 .cra_module = THIS_MODULE,
1566 .conf.algorithm = HASH_ALGO_SHA256,
1567 .conf.oper_mode = HASH_OPER_MODE_HASH,
1570 .update = ahash_update,
1571 .final = ahash_final,
1572 .digest = ahash_sha256_digest,
1573 .halg.digestsize = SHA256_DIGEST_SIZE,
1574 .halg.statesize = sizeof(struct hash_ctx),
1576 .cra_name = "sha256",
1577 .cra_driver_name = "sha256-ux500",
1578 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1580 .cra_blocksize = SHA256_BLOCK_SIZE,
1581 .cra_ctxsize = sizeof(struct hash_ctx),
1582 .cra_type = &crypto_ahash_type,
1583 .cra_init = hash_cra_init,
1584 .cra_module = THIS_MODULE,
1590 .conf.algorithm = HASH_ALGO_SHA1,
1591 .conf.oper_mode = HASH_OPER_MODE_HMAC,
1594 .update = ahash_update,
1595 .final = ahash_final,
1596 .digest = hmac_sha1_digest,
1597 .setkey = hmac_sha1_setkey,
1598 .halg.digestsize = SHA1_DIGEST_SIZE,
1599 .halg.statesize = sizeof(struct hash_ctx),
1601 .cra_name = "hmac(sha1)",
1602 .cra_driver_name = "hmac-sha1-ux500",
1603 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1605 .cra_blocksize = SHA1_BLOCK_SIZE,
1606 .cra_ctxsize = sizeof(struct hash_ctx),
1607 .cra_type = &crypto_ahash_type,
1608 .cra_init = hash_cra_init,
1609 .cra_module = THIS_MODULE,
1614 .conf.algorithm = HASH_ALGO_SHA256,
1615 .conf.oper_mode = HASH_OPER_MODE_HMAC,
1618 .update = ahash_update,
1619 .final = ahash_final,
1620 .digest = hmac_sha256_digest,
1621 .setkey = hmac_sha256_setkey,
1622 .halg.digestsize = SHA256_DIGEST_SIZE,
1623 .halg.statesize = sizeof(struct hash_ctx),
1625 .cra_name = "hmac(sha256)",
1626 .cra_driver_name = "hmac-sha256-ux500",
1627 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1629 .cra_blocksize = SHA256_BLOCK_SIZE,
1630 .cra_ctxsize = sizeof(struct hash_ctx),
1631 .cra_type = &crypto_ahash_type,
1632 .cra_init = hash_cra_init,
1633 .cra_module = THIS_MODULE,
1640 * hash_algs_register_all -
1642 static int ahash_algs_register_all(struct hash_device_data *device_data)
1648 for (i = 0; i < ARRAY_SIZE(hash_algs); i++) {
1649 ret = crypto_register_ahash(&hash_algs[i].hash);
1652 dev_err(device_data->dev, "[%s] alg registration failed",
1653 hash_algs[i].hash.halg.base.cra_driver_name);
1659 for (i = 0; i < count; i++)
1660 crypto_unregister_ahash(&hash_algs[i].hash);
1665 * hash_algs_unregister_all -
1667 static void ahash_algs_unregister_all(struct hash_device_data *device_data)
1671 for (i = 0; i < ARRAY_SIZE(hash_algs); i++)
1672 crypto_unregister_ahash(&hash_algs[i].hash);
1676 * ux500_hash_probe - Function that probes the hash hardware.
1677 * @pdev: The platform device.
1679 static int ux500_hash_probe(struct platform_device *pdev)
1682 struct resource *res = NULL;
1683 struct hash_device_data *device_data;
1684 struct device *dev = &pdev->dev;
1686 device_data = kzalloc(sizeof(struct hash_device_data), GFP_ATOMIC);
1688 dev_dbg(dev, "[%s] kzalloc() failed!", __func__);
1693 device_data->dev = dev;
1694 device_data->current_ctx = NULL;
1696 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1698 dev_dbg(dev, "[%s] platform_get_resource() failed!", __func__);
1703 res = request_mem_region(res->start, resource_size(res), pdev->name);
1705 dev_dbg(dev, "[%s] request_mem_region() failed!", __func__);
1710 device_data->phybase = res->start;
1711 device_data->base = ioremap(res->start, resource_size(res));
1712 if (!device_data->base) {
1713 dev_err(dev, "[%s] ioremap() failed!",
1718 spin_lock_init(&device_data->ctx_lock);
1719 spin_lock_init(&device_data->power_state_lock);
1721 /* Enable power for HASH1 hardware block */
1722 device_data->regulator = regulator_get(dev, "v-ape");
1723 if (IS_ERR(device_data->regulator)) {
1724 dev_err(dev, "[%s] regulator_get() failed!", __func__);
1725 ret = PTR_ERR(device_data->regulator);
1726 device_data->regulator = NULL;
1730 /* Enable the clock for HASH1 hardware block */
1731 device_data->clk = clk_get(dev, NULL);
1732 if (IS_ERR(device_data->clk)) {
1733 dev_err(dev, "[%s] clk_get() failed!", __func__);
1734 ret = PTR_ERR(device_data->clk);
1738 ret = clk_prepare(device_data->clk);
1740 dev_err(dev, "[%s] clk_prepare() failed!", __func__);
1744 /* Enable device power (and clock) */
1745 ret = hash_enable_power(device_data, false);
1747 dev_err(dev, "[%s]: hash_enable_power() failed!", __func__);
1748 goto out_clk_unprepare;
1751 ret = hash_check_hw(device_data);
1753 dev_err(dev, "[%s] hash_check_hw() failed!", __func__);
1757 if (hash_mode == HASH_MODE_DMA)
1758 hash_dma_setup_channel(device_data, dev);
1760 platform_set_drvdata(pdev, device_data);
1762 /* Put the new device into the device list... */
1763 klist_add_tail(&device_data->list_node, &driver_data.device_list);
1764 /* ... and signal that a new device is available. */
1765 up(&driver_data.device_allocation);
1767 ret = ahash_algs_register_all(device_data);
1769 dev_err(dev, "[%s] ahash_algs_register_all() "
1770 "failed!", __func__);
1774 dev_info(dev, "successfully registered\n");
1778 hash_disable_power(device_data, false);
1781 clk_unprepare(device_data->clk);
1784 clk_put(device_data->clk);
1787 regulator_put(device_data->regulator);
1790 iounmap(device_data->base);
1793 release_mem_region(res->start, resource_size(res));
1802 * ux500_hash_remove - Function that removes the hash device from the platform.
1803 * @pdev: The platform device.
1805 static int ux500_hash_remove(struct platform_device *pdev)
1807 struct resource *res;
1808 struct hash_device_data *device_data;
1809 struct device *dev = &pdev->dev;
1811 device_data = platform_get_drvdata(pdev);
1813 dev_err(dev, "[%s]: platform_get_drvdata() failed!",
1818 /* Try to decrease the number of available devices. */
1819 if (down_trylock(&driver_data.device_allocation))
1822 /* Check that the device is free */
1823 spin_lock(&device_data->ctx_lock);
1824 /* current_ctx allocates a device, NULL = unallocated */
1825 if (device_data->current_ctx) {
1826 /* The device is busy */
1827 spin_unlock(&device_data->ctx_lock);
1828 /* Return the device to the pool. */
1829 up(&driver_data.device_allocation);
1833 spin_unlock(&device_data->ctx_lock);
1835 /* Remove the device from the list */
1836 if (klist_node_attached(&device_data->list_node))
1837 klist_remove(&device_data->list_node);
1839 /* If this was the last device, remove the services */
1840 if (list_empty(&driver_data.device_list.k_list))
1841 ahash_algs_unregister_all(device_data);
1843 if (hash_disable_power(device_data, false))
1844 dev_err(dev, "[%s]: hash_disable_power() failed",
1847 clk_unprepare(device_data->clk);
1848 clk_put(device_data->clk);
1849 regulator_put(device_data->regulator);
1851 iounmap(device_data->base);
1853 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1855 release_mem_region(res->start, resource_size(res));
1863 * ux500_hash_shutdown - Function that shutdown the hash device.
1864 * @pdev: The platform device
1866 static void ux500_hash_shutdown(struct platform_device *pdev)
1868 struct resource *res = NULL;
1869 struct hash_device_data *device_data;
1871 device_data = platform_get_drvdata(pdev);
1873 dev_err(&pdev->dev, "[%s] platform_get_drvdata() failed!",
1878 /* Check that the device is free */
1879 spin_lock(&device_data->ctx_lock);
1880 /* current_ctx allocates a device, NULL = unallocated */
1881 if (!device_data->current_ctx) {
1882 if (down_trylock(&driver_data.device_allocation))
1883 dev_dbg(&pdev->dev, "[%s]: Cryp still in use!"
1884 "Shutting down anyway...", __func__);
1886 * (Allocate the device)
1887 * Need to set this to non-null (dummy) value,
1888 * to avoid usage if context switching.
1890 device_data->current_ctx++;
1892 spin_unlock(&device_data->ctx_lock);
1894 /* Remove the device from the list */
1895 if (klist_node_attached(&device_data->list_node))
1896 klist_remove(&device_data->list_node);
1898 /* If this was the last device, remove the services */
1899 if (list_empty(&driver_data.device_list.k_list))
1900 ahash_algs_unregister_all(device_data);
1902 iounmap(device_data->base);
1904 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1906 release_mem_region(res->start, resource_size(res));
1908 if (hash_disable_power(device_data, false))
1909 dev_err(&pdev->dev, "[%s] hash_disable_power() failed",
1914 * ux500_hash_suspend - Function that suspends the hash device.
1915 * @dev: Device to suspend.
1917 static int ux500_hash_suspend(struct device *dev)
1920 struct hash_device_data *device_data;
1921 struct hash_ctx *temp_ctx = NULL;
1923 device_data = dev_get_drvdata(dev);
1925 dev_err(dev, "[%s] platform_get_drvdata() failed!", __func__);
1929 spin_lock(&device_data->ctx_lock);
1930 if (!device_data->current_ctx)
1931 device_data->current_ctx++;
1932 spin_unlock(&device_data->ctx_lock);
1934 if (device_data->current_ctx == ++temp_ctx) {
1935 if (down_interruptible(&driver_data.device_allocation))
1936 dev_dbg(dev, "[%s]: down_interruptible() failed",
1938 ret = hash_disable_power(device_data, false);
1941 ret = hash_disable_power(device_data, true);
1944 dev_err(dev, "[%s]: hash_disable_power()", __func__);
1950 * ux500_hash_resume - Function that resume the hash device.
1951 * @dev: Device to resume.
1953 static int ux500_hash_resume(struct device *dev)
1956 struct hash_device_data *device_data;
1957 struct hash_ctx *temp_ctx = NULL;
1959 device_data = dev_get_drvdata(dev);
1961 dev_err(dev, "[%s] platform_get_drvdata() failed!", __func__);
1965 spin_lock(&device_data->ctx_lock);
1966 if (device_data->current_ctx == ++temp_ctx)
1967 device_data->current_ctx = NULL;
1968 spin_unlock(&device_data->ctx_lock);
1970 if (!device_data->current_ctx)
1971 up(&driver_data.device_allocation);
1973 ret = hash_enable_power(device_data, true);
1976 dev_err(dev, "[%s]: hash_enable_power() failed!", __func__);
1981 static SIMPLE_DEV_PM_OPS(ux500_hash_pm, ux500_hash_suspend, ux500_hash_resume);
1983 static const struct of_device_id ux500_hash_match[] = {
1984 { .compatible = "stericsson,ux500-hash" },
1988 static struct platform_driver hash_driver = {
1989 .probe = ux500_hash_probe,
1990 .remove = ux500_hash_remove,
1991 .shutdown = ux500_hash_shutdown,
1993 .owner = THIS_MODULE,
1995 .of_match_table = ux500_hash_match,
1996 .pm = &ux500_hash_pm,
2001 * ux500_hash_mod_init - The kernel module init function.
2003 static int __init ux500_hash_mod_init(void)
2005 klist_init(&driver_data.device_list, NULL, NULL);
2006 /* Initialize the semaphore to 0 devices (locked state) */
2007 sema_init(&driver_data.device_allocation, 0);
2009 return platform_driver_register(&hash_driver);
2013 * ux500_hash_mod_fini - The kernel module exit function.
2015 static void __exit ux500_hash_mod_fini(void)
2017 platform_driver_unregister(&hash_driver);
2020 module_init(ux500_hash_mod_init);
2021 module_exit(ux500_hash_mod_fini);
2023 MODULE_DESCRIPTION("Driver for ST-Ericsson UX500 HASH engine.");
2024 MODULE_LICENSE("GPL");
2026 MODULE_ALIAS("sha1-all");
2027 MODULE_ALIAS("sha256-all");
2028 MODULE_ALIAS("hmac-sha1-all");
2029 MODULE_ALIAS("hmac-sha256-all");