drivers/crypto/omap-aes.c

   1 /*
   2  * Cryptographic API.
   3  *
   4  * Support for OMAP AES HW acceleration.
   5  *
   6  * Copyright (c) 2010 Nokia Corporation
   7  * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
   8  * Copyright (c) 2011 Texas Instruments Incorporated
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as published
  12  * by the Free Software Foundation.
  13  *
  14  */
  15
  16 #define pr_fmt(fmt) "%20s: " fmt, __func__
  17 #define prn(num) pr_debug(#num "=%d\n", num)
  18 #define prx(num) pr_debug(#num "=%x\n", num)
  19
  20 #include <linux/err.h>
  21 #include <linux/module.h>
  22 #include <linux/init.h>
  23 #include <linux/errno.h>
  24 #include <linux/kernel.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/scatterlist.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/dmaengine.h>
  29 #include <linux/omap-dma.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/of.h>
  32 #include <linux/of_device.h>
  33 #include <linux/of_address.h>
  34 #include <linux/io.h>
  35 #include <linux/crypto.h>
  36 #include <linux/interrupt.h>
  37 #include <crypto/scatterwalk.h>
  38 #include <crypto/aes.h>
  39
  40 #define DST_MAXBURST                    4
  41 #define DMA_MIN                         (DST_MAXBURST * sizeof(u32))
  42
  43 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
  44    number. For example 7:0 */
  45 #define FLD_MASK(start, end)    (((1 << ((start) - (end) + 1)) - 1) << (end))
  46 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
  47
  48 #define AES_REG_KEY(dd, x)              ((dd)->pdata->key_ofs - \
  49                                                 ((x ^ 0x01) * 0x04))
  50 #define AES_REG_IV(dd, x)               ((dd)->pdata->iv_ofs + ((x) * 0x04))
  51
  52 #define AES_REG_CTRL(dd)                ((dd)->pdata->ctrl_ofs)
  53 #define AES_REG_CTRL_CTR_WIDTH_MASK     (3 << 7)
  54 #define AES_REG_CTRL_CTR_WIDTH_32               (0 << 7)
  55 #define AES_REG_CTRL_CTR_WIDTH_64               (1 << 7)
  56 #define AES_REG_CTRL_CTR_WIDTH_96               (2 << 7)
  57 #define AES_REG_CTRL_CTR_WIDTH_128              (3 << 7)
  58 #define AES_REG_CTRL_CTR                (1 << 6)
  59 #define AES_REG_CTRL_CBC                (1 << 5)
  60 #define AES_REG_CTRL_KEY_SIZE           (3 << 3)
  61 #define AES_REG_CTRL_DIRECTION          (1 << 2)
  62 #define AES_REG_CTRL_INPUT_READY        (1 << 1)
  63 #define AES_REG_CTRL_OUTPUT_READY       (1 << 0)
  64
  65 #define AES_REG_DATA_N(dd, x)           ((dd)->pdata->data_ofs + ((x) * 0x04))
  66
  67 #define AES_REG_REV(dd)                 ((dd)->pdata->rev_ofs)
  68
  69 #define AES_REG_MASK(dd)                ((dd)->pdata->mask_ofs)
  70 #define AES_REG_MASK_SIDLE              (1 << 6)
  71 #define AES_REG_MASK_START              (1 << 5)
  72 #define AES_REG_MASK_DMA_OUT_EN         (1 << 3)
  73 #define AES_REG_MASK_DMA_IN_EN          (1 << 2)
  74 #define AES_REG_MASK_SOFTRESET          (1 << 1)
  75 #define AES_REG_AUTOIDLE                (1 << 0)
  76
  77 #define AES_REG_LENGTH_N(x)             (0x54 + ((x) * 0x04))
  78
  79 #define DEFAULT_TIMEOUT         (5*HZ)
  80
  81 #define FLAGS_MODE_MASK         0x000f
  82 #define FLAGS_ENCRYPT           BIT(0)
  83 #define FLAGS_CBC               BIT(1)
  84 #define FLAGS_GIV               BIT(2)
  85 #define FLAGS_CTR               BIT(3)
  86
  87 #define FLAGS_INIT              BIT(4)
  88 #define FLAGS_FAST              BIT(5)
  89 #define FLAGS_BUSY              BIT(6)
  90
  91 struct omap_aes_ctx {
  92         struct omap_aes_dev *dd;
  93
  94         int             keylen;
  95         u32             key[AES_KEYSIZE_256 / sizeof(u32)];
  96         unsigned long   flags;
  97 };
  98
  99 struct omap_aes_reqctx {
 100         unsigned long mode;
 101 };
 102
 103 #define OMAP_AES_QUEUE_LENGTH   1
 104 #define OMAP_AES_CACHE_SIZE     0
 105
 106 struct omap_aes_algs_info {
 107         struct crypto_alg       *algs_list;
 108         unsigned int            size;
 109         unsigned int            registered;
 110 };
 111
 112 struct omap_aes_pdata {
 113         struct omap_aes_algs_info       *algs_info;
 114         unsigned int    algs_info_size;
 115
 116         void            (*trigger)(struct omap_aes_dev *dd, int length);
 117
 118         u32             key_ofs;
 119         u32             iv_ofs;
 120         u32             ctrl_ofs;
 121         u32             data_ofs;
 122         u32             rev_ofs;
 123         u32             mask_ofs;
 124
 125         u32             dma_enable_in;
 126         u32             dma_enable_out;
 127         u32             dma_start;
 128
 129         u32             major_mask;
 130         u32             major_shift;
 131         u32             minor_mask;
 132         u32             minor_shift;
 133 };
 134
 135 struct omap_aes_dev {
 136         struct list_head        list;
 137         unsigned long           phys_base;
 138         void __iomem            *io_base;
 139         struct omap_aes_ctx     *ctx;
 140         struct device           *dev;
 141         unsigned long           flags;
 142         int                     err;
 143
 144         spinlock_t              lock;
 145         struct crypto_queue     queue;
 146
 147         struct tasklet_struct   done_task;
 148         struct tasklet_struct   queue_task;
 149
 150         struct ablkcipher_request       *req;
 151         size_t                          total;
 152         struct scatterlist              *in_sg;
 153         struct scatterlist              in_sgl;
 154         size_t                          in_offset;
 155         struct scatterlist              *out_sg;
 156         struct scatterlist              out_sgl;
 157         size_t                          out_offset;
 158
 159         size_t                  buflen;
 160         void                    *buf_in;
 161         size_t                  dma_size;
 162         int                     dma_in;
 163         struct dma_chan         *dma_lch_in;
 164         dma_addr_t              dma_addr_in;
 165         void                    *buf_out;
 166         int                     dma_out;
 167         struct dma_chan         *dma_lch_out;
 168         dma_addr_t              dma_addr_out;
 169
 170         const struct omap_aes_pdata     *pdata;
 171 };
 172
 173 /* keep registered devices data here */
 174 static LIST_HEAD(dev_list);
 175 static DEFINE_SPINLOCK(list_lock);
 176
 177 #ifdef DEBUG
 178 #define omap_aes_read(dd, offset)                               \
 179 ({                                                              \
 180         int _read_ret;                                          \
 181         _read_ret = __raw_readl(dd->io_base + offset);          \
 182         pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n",       \
 183                  offset, _read_ret);                            \
 184         _read_ret;                                              \
 185 })
 186 #else
 187 static inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset)
 188 {
 189         return __raw_readl(dd->io_base + offset);
 190 }
 191 #endif
 192
 193 #ifdef DEBUG
 194 #define omap_aes_write(dd, offset, value)                               \
 195         do {                                                            \
 196                 pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \
 197                          offset, value);                                \
 198                 __raw_writel(value, dd->io_base + offset);              \
 199         } while (0)
 200 #else
 201 static inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset,
 202                                   u32 value)
 203 {
 204         __raw_writel(value, dd->io_base + offset);
 205 }
 206 #endif
 207
 208 static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset,
 209                                         u32 value, u32 mask)
 210 {
 211         u32 val;
 212
 213         val = omap_aes_read(dd, offset);
 214         val &= ~mask;
 215         val |= value;
 216         omap_aes_write(dd, offset, val);
 217 }
 218
 219 static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset,
 220                                         u32 *value, int count)
 221 {
 222         for (; count--; value++, offset += 4)
 223                 omap_aes_write(dd, offset, *value);
 224 }
 225
 226 static int omap_aes_hw_init(struct omap_aes_dev *dd)
 227 {
 228         if (!(dd->flags & FLAGS_INIT)) {
 229                 dd->flags |= FLAGS_INIT;
 230                 dd->err = 0;
 231         }
 232
 233         return 0;
 234 }
 235
 236 static int omap_aes_write_ctrl(struct omap_aes_dev *dd)
 237 {
 238         unsigned int key32;
 239         int i, err;
 240         u32 val, mask = 0;
 241
 242         err = omap_aes_hw_init(dd);
 243         if (err)
 244                 return err;
 245
 246         key32 = dd->ctx->keylen / sizeof(u32);
 247
 248         /* it seems a key should always be set even if it has not changed */
 249         for (i = 0; i < key32; i++) {
 250                 omap_aes_write(dd, AES_REG_KEY(dd, i),
 251                         __le32_to_cpu(dd->ctx->key[i]));
 252         }
 253
 254         if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->info)
 255                 omap_aes_write_n(dd, AES_REG_IV(dd, 0), dd->req->info, 4);
 256
 257         val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3);
 258         if (dd->flags & FLAGS_CBC)
 259                 val |= AES_REG_CTRL_CBC;
 260         if (dd->flags & FLAGS_CTR) {
 261                 val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_32;
 262                 mask = AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_MASK;
 263         }
 264         if (dd->flags & FLAGS_ENCRYPT)
 265                 val |= AES_REG_CTRL_DIRECTION;
 266
 267         mask |= AES_REG_CTRL_CBC | AES_REG_CTRL_DIRECTION |
 268                         AES_REG_CTRL_KEY_SIZE;
 269
 270         omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, mask);
 271
 272         return 0;
 273 }
 274
 275 static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length)
 276 {
 277         u32 mask, val;
 278
 279         val = dd->pdata->dma_start;
 280
 281         if (dd->dma_lch_out != NULL)
 282                 val |= dd->pdata->dma_enable_out;
 283         if (dd->dma_lch_in != NULL)
 284                 val |= dd->pdata->dma_enable_in;
 285
 286         mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
 287                dd->pdata->dma_start;
 288
 289         omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask);
 290
 291 }
 292
 293 static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length)
 294 {
 295         omap_aes_write(dd, AES_REG_LENGTH_N(0), length);
 296         omap_aes_write(dd, AES_REG_LENGTH_N(1), 0);
 297
 298         omap_aes_dma_trigger_omap2(dd, length);
 299 }
 300
 301 static void omap_aes_dma_stop(struct omap_aes_dev *dd)
 302 {
 303         u32 mask;
 304
 305         mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
 306                dd->pdata->dma_start;
 307
 308         omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask);
 309 }
 310
 311 static struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_ctx *ctx)
 312 {
 313         struct omap_aes_dev *dd = NULL, *tmp;
 314
 315         spin_lock_bh(&list_lock);
 316         if (!ctx->dd) {
 317                 list_for_each_entry(tmp, &dev_list, list) {
 318                         /* FIXME: take fist available aes core */
 319                         dd = tmp;
 320                         break;
 321                 }
 322                 ctx->dd = dd;
 323         } else {
 324                 /* already found before */
 325                 dd = ctx->dd;
 326         }
 327         spin_unlock_bh(&list_lock);
 328
 329         return dd;
 330 }
 331
 332 static void omap_aes_dma_out_callback(void *data)
 333 {
 334         struct omap_aes_dev *dd = data;
 335
 336         /* dma_lch_out - completed */
 337         tasklet_schedule(&dd->done_task);
 338 }
 339
 340 static int omap_aes_dma_init(struct omap_aes_dev *dd)
 341 {
 342         int err = -ENOMEM;
 343         dma_cap_mask_t mask;
 344
 345         dd->dma_lch_out = NULL;
 346         dd->dma_lch_in = NULL;
 347
 348         dd->buf_in = (void *)__get_free_pages(GFP_KERNEL, OMAP_AES_CACHE_SIZE);
 349         dd->buf_out = (void *)__get_free_pages(GFP_KERNEL, OMAP_AES_CACHE_SIZE);
 350         dd->buflen = PAGE_SIZE << OMAP_AES_CACHE_SIZE;
 351         dd->buflen &= ~(AES_BLOCK_SIZE - 1);
 352
 353         if (!dd->buf_in || !dd->buf_out) {
 354                 dev_err(dd->dev, "unable to alloc pages.\n");
 355                 goto err_alloc;
 356         }
 357
 358         /* MAP here */
 359         dd->dma_addr_in = dma_map_single(dd->dev, dd->buf_in, dd->buflen,
 360                                          DMA_TO_DEVICE);
 361         if (dma_mapping_error(dd->dev, dd->dma_addr_in)) {
 362                 dev_err(dd->dev, "dma %d bytes error\n", dd->buflen);
 363                 err = -EINVAL;
 364                 goto err_map_in;
 365         }
 366
 367         dd->dma_addr_out = dma_map_single(dd->dev, dd->buf_out, dd->buflen,
 368                                           DMA_FROM_DEVICE);
 369         if (dma_mapping_error(dd->dev, dd->dma_addr_out)) {
 370                 dev_err(dd->dev, "dma %d bytes error\n", dd->buflen);
 371                 err = -EINVAL;
 372                 goto err_map_out;
 373         }
 374
 375         dma_cap_zero(mask);
 376         dma_cap_set(DMA_SLAVE, mask);
 377
 378         dd->dma_lch_in = dma_request_slave_channel_compat(mask,
 379                                                           omap_dma_filter_fn,
 380                                                           &dd->dma_in,
 381                                                           dd->dev, "rx");
 382         if (!dd->dma_lch_in) {
 383                 dev_err(dd->dev, "Unable to request in DMA channel\n");
 384                 goto err_dma_in;
 385         }
 386
 387         dd->dma_lch_out = dma_request_slave_channel_compat(mask,
 388                                                            omap_dma_filter_fn,
 389                                                            &dd->dma_out,
 390                                                            dd->dev, "tx");
 391         if (!dd->dma_lch_out) {
 392                 dev_err(dd->dev, "Unable to request out DMA channel\n");
 393                 goto err_dma_out;
 394         }
 395
 396         return 0;
 397
 398 err_dma_out:
 399         dma_release_channel(dd->dma_lch_in);
 400 err_dma_in:
 401         dma_unmap_single(dd->dev, dd->dma_addr_out, dd->buflen,
 402                          DMA_FROM_DEVICE);
 403 err_map_out:
 404         dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen, DMA_TO_DEVICE);
 405 err_map_in:
 406         free_pages((unsigned long)dd->buf_out, OMAP_AES_CACHE_SIZE);
 407         free_pages((unsigned long)dd->buf_in, OMAP_AES_CACHE_SIZE);
 408 err_alloc:
 409         if (err)
 410                 pr_err("error: %d\n", err);
 411         return err;
 412 }
 413
 414 static void omap_aes_dma_cleanup(struct omap_aes_dev *dd)
 415 {
 416         dma_release_channel(dd->dma_lch_out);
 417         dma_release_channel(dd->dma_lch_in);
 418         dma_unmap_single(dd->dev, dd->dma_addr_out, dd->buflen,
 419                          DMA_FROM_DEVICE);
 420         dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen, DMA_TO_DEVICE);
 421         free_pages((unsigned long)dd->buf_out, OMAP_AES_CACHE_SIZE);
 422         free_pages((unsigned long)dd->buf_in, OMAP_AES_CACHE_SIZE);
 423 }
 424
 425 static void sg_copy_buf(void *buf, struct scatterlist *sg,
 426                               unsigned int start, unsigned int nbytes, int out)
 427 {
 428         struct scatter_walk walk;
 429
 430         if (!nbytes)
 431                 return;
 432
 433         scatterwalk_start(&walk, sg);
 434         scatterwalk_advance(&walk, start);
 435         scatterwalk_copychunks(buf, &walk, nbytes, out);
 436         scatterwalk_done(&walk, out, 0);
 437 }
 438
 439 static int sg_copy(struct scatterlist **sg, size_t *offset, void *buf,
 440                    size_t buflen, size_t total, int out)
 441 {
 442         unsigned int count, off = 0;
 443
 444         while (buflen && total) {
 445                 count = min((*sg)->length - *offset, total);
 446                 count = min(count, buflen);
 447
 448                 if (!count)
 449                         return off;
 450
 451                 /*
 452                  * buflen and total are AES_BLOCK_SIZE size aligned,
 453                  * so count should be also aligned
 454                  */
 455
 456                 sg_copy_buf(buf + off, *sg, *offset, count, out);
 457
 458                 off += count;
 459                 buflen -= count;
 460                 *offset += count;
 461                 total -= count;
 462
 463                 if (*offset == (*sg)->length) {
 464                         *sg = sg_next(*sg);
 465                         if (*sg)
 466                                 *offset = 0;
 467                         else
 468                                 total = 0;
 469                 }
 470         }
 471
 472         return off;
 473 }
 474
 475 static int omap_aes_crypt_dma(struct crypto_tfm *tfm,
 476                 struct scatterlist *in_sg, struct scatterlist *out_sg)
 477 {
 478         struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm);
 479         struct omap_aes_dev *dd = ctx->dd;
 480         struct dma_async_tx_descriptor *tx_in, *tx_out;
 481         struct dma_slave_config cfg;
 482         dma_addr_t dma_addr_in = sg_dma_address(in_sg);
 483         int ret, length = sg_dma_len(in_sg);
 484
 485         pr_debug("len: %d\n", length);
 486
 487         dd->dma_size = length;
 488
 489         if (!(dd->flags & FLAGS_FAST))
 490                 dma_sync_single_for_device(dd->dev, dma_addr_in, length,
 491                                            DMA_TO_DEVICE);
 492
 493         memset(&cfg, 0, sizeof(cfg));
 494
 495         cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
 496         cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
 497         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 498         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 499         cfg.src_maxburst = DST_MAXBURST;
 500         cfg.dst_maxburst = DST_MAXBURST;
 501
 502         /* IN */
 503         ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
 504         if (ret) {
 505                 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
 506                         ret);
 507                 return ret;
 508         }
 509
 510         tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, 1,
 511                                         DMA_MEM_TO_DEV,
 512                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 513         if (!tx_in) {
 514                 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
 515                 return -EINVAL;
 516         }
 517
 518         /* No callback necessary */
 519         tx_in->callback_param = dd;
 520
 521         /* OUT */
 522         ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
 523         if (ret) {
 524                 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
 525                         ret);
 526                 return ret;
 527         }
 528
 529         tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, 1,
 530                                         DMA_DEV_TO_MEM,
 531                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 532         if (!tx_out) {
 533                 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
 534                 return -EINVAL;
 535         }
 536
 537         tx_out->callback = omap_aes_dma_out_callback;
 538         tx_out->callback_param = dd;
 539
 540         dmaengine_submit(tx_in);
 541         dmaengine_submit(tx_out);
 542
 543         dma_async_issue_pending(dd->dma_lch_in);
 544         dma_async_issue_pending(dd->dma_lch_out);
 545
 546         /* start DMA */
 547         dd->pdata->trigger(dd, length);
 548
 549         return 0;
 550 }
 551
 552 static int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
 553 {
 554         struct crypto_tfm *tfm = crypto_ablkcipher_tfm(
 555                                         crypto_ablkcipher_reqtfm(dd->req));
 556         int err, fast = 0, in, out;
 557         size_t count;
 558         dma_addr_t addr_in, addr_out;
 559         struct scatterlist *in_sg, *out_sg;
 560         int len32;
 561
 562         pr_debug("total: %d\n", dd->total);
 563
 564         if (sg_is_last(dd->in_sg) && sg_is_last(dd->out_sg)) {
 565                 /* check for alignment */
 566                 in = IS_ALIGNED((u32)dd->in_sg->offset, sizeof(u32));
 567                 out = IS_ALIGNED((u32)dd->out_sg->offset, sizeof(u32));
 568
 569                 fast = in && out;
 570         }
 571
 572         if (fast)  {
 573                 count = min(dd->total, sg_dma_len(dd->in_sg));
 574                 count = min(count, sg_dma_len(dd->out_sg));
 575
 576                 if (count != dd->total) {
 577                         pr_err("request length != buffer length\n");
 578                         return -EINVAL;
 579                 }
 580
 581                 pr_debug("fast\n");
 582
 583                 err = dma_map_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
 584                 if (!err) {
 585                         dev_err(dd->dev, "dma_map_sg() error\n");
 586                         return -EINVAL;
 587                 }
 588
 589                 err = dma_map_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE);
 590                 if (!err) {
 591                         dev_err(dd->dev, "dma_map_sg() error\n");
 592                         dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
 593                         return -EINVAL;
 594                 }
 595
 596                 addr_in = sg_dma_address(dd->in_sg);
 597                 addr_out = sg_dma_address(dd->out_sg);
 598
 599                 in_sg = dd->in_sg;
 600                 out_sg = dd->out_sg;
 601
 602                 dd->flags |= FLAGS_FAST;
 603
 604         } else {
 605                 /* use cache buffers */
 606                 count = sg_copy(&dd->in_sg, &dd->in_offset, dd->buf_in,
 607                                  dd->buflen, dd->total, 0);
 608
 609                 len32 = DIV_ROUND_UP(count, DMA_MIN) * DMA_MIN;
 610
 611                 /*
 612                  * The data going into the AES module has been copied
 613                  * to a local buffer and the data coming out will go
 614                  * into a local buffer so set up local SG entries for
 615                  * both.
 616                  */
 617                 sg_init_table(&dd->in_sgl, 1);
 618                 dd->in_sgl.offset = dd->in_offset;
 619                 sg_dma_len(&dd->in_sgl) = len32;
 620                 sg_dma_address(&dd->in_sgl) = dd->dma_addr_in;
 621
 622                 sg_init_table(&dd->out_sgl, 1);
 623                 dd->out_sgl.offset = dd->out_offset;
 624                 sg_dma_len(&dd->out_sgl) = len32;
 625                 sg_dma_address(&dd->out_sgl) = dd->dma_addr_out;
 626
 627                 in_sg = &dd->in_sgl;
 628                 out_sg = &dd->out_sgl;
 629
 630                 addr_in = dd->dma_addr_in;
 631                 addr_out = dd->dma_addr_out;
 632
 633                 dd->flags &= ~FLAGS_FAST;
 634
 635         }
 636
 637         dd->total -= count;
 638
 639         err = omap_aes_crypt_dma(tfm, in_sg, out_sg);
 640         if (err) {
 641                 dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
 642                 dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_TO_DEVICE);
 643         }
 644
 645         return err;
 646 }
 647
 648 static void omap_aes_finish_req(struct omap_aes_dev *dd, int err)
 649 {
 650         struct ablkcipher_request *req = dd->req;
 651
 652         pr_debug("err: %d\n", err);
 653
 654         dd->flags &= ~FLAGS_BUSY;
 655
 656         req->base.complete(&req->base, err);
 657 }
 658
 659 static int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd)
 660 {
 661         int err = 0;
 662         size_t count;
 663
 664         pr_debug("total: %d\n", dd->total);
 665
 666         omap_aes_dma_stop(dd);
 667
 668         dmaengine_terminate_all(dd->dma_lch_in);
 669         dmaengine_terminate_all(dd->dma_lch_out);
 670
 671         if (dd->flags & FLAGS_FAST) {
 672                 dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE);
 673                 dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
 674         } else {
 675                 dma_sync_single_for_device(dd->dev, dd->dma_addr_out,
 676                                            dd->dma_size, DMA_FROM_DEVICE);
 677
 678                 /* copy data */
 679                 count = sg_copy(&dd->out_sg, &dd->out_offset, dd->buf_out,
 680                                  dd->buflen, dd->dma_size, 1);
 681                 if (count != dd->dma_size) {
 682                         err = -EINVAL;
 683                         pr_err("not all data converted: %u\n", count);
 684                 }
 685         }
 686
 687         return err;
 688 }
 689
 690 static int omap_aes_handle_queue(struct omap_aes_dev *dd,
 691                                struct ablkcipher_request *req)
 692 {
 693         struct crypto_async_request *async_req, *backlog;
 694         struct omap_aes_ctx *ctx;
 695         struct omap_aes_reqctx *rctx;
 696         unsigned long flags;
 697         int err, ret = 0;
 698
 699         spin_lock_irqsave(&dd->lock, flags);
 700         if (req)
 701                 ret = ablkcipher_enqueue_request(&dd->queue, req);
 702         if (dd->flags & FLAGS_BUSY) {
 703                 spin_unlock_irqrestore(&dd->lock, flags);
 704                 return ret;
 705         }
 706         backlog = crypto_get_backlog(&dd->queue);
 707         async_req = crypto_dequeue_request(&dd->queue);
 708         if (async_req)
 709                 dd->flags |= FLAGS_BUSY;
 710         spin_unlock_irqrestore(&dd->lock, flags);
 711
 712         if (!async_req)
 713                 return ret;
 714
 715         if (backlog)
 716                 backlog->complete(backlog, -EINPROGRESS);
 717
 718         req = ablkcipher_request_cast(async_req);
 719
 720         /* assign new request to device */
 721         dd->req = req;
 722         dd->total = req->nbytes;
 723         dd->in_offset = 0;
 724         dd->in_sg = req->src;
 725         dd->out_offset = 0;
 726         dd->out_sg = req->dst;
 727
 728         rctx = ablkcipher_request_ctx(req);
 729         ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
 730         rctx->mode &= FLAGS_MODE_MASK;
 731         dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
 732
 733         dd->ctx = ctx;
 734         ctx->dd = dd;
 735
 736         err = omap_aes_write_ctrl(dd);
 737         if (!err)
 738                 err = omap_aes_crypt_dma_start(dd);
 739         if (err) {
 740                 /* aes_task will not finish it, so do it here */
 741                 omap_aes_finish_req(dd, err);
 742                 tasklet_schedule(&dd->queue_task);
 743         }
 744
 745         return ret; /* return ret, which is enqueue return value */
 746 }
 747
 748 static void omap_aes_done_task(unsigned long data)
 749 {
 750         struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
 751         int err;
 752
 753         pr_debug("enter\n");
 754
 755         err = omap_aes_crypt_dma_stop(dd);
 756
 757         err = dd->err ? : err;
 758
 759         if (dd->total && !err) {
 760                 err = omap_aes_crypt_dma_start(dd);
 761                 if (!err)
 762                         return; /* DMA started. Not fininishing. */
 763         }
 764
 765         omap_aes_finish_req(dd, err);
 766         omap_aes_handle_queue(dd, NULL);
 767
 768         pr_debug("exit\n");
 769 }
 770
 771 static void omap_aes_queue_task(unsigned long data)
 772 {
 773         struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
 774
 775         omap_aes_handle_queue(dd, NULL);
 776 }
 777
 778 static int omap_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
 779 {
 780         struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(
 781                         crypto_ablkcipher_reqtfm(req));
 782         struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req);
 783         struct omap_aes_dev *dd;
 784
 785         pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes,
 786                   !!(mode & FLAGS_ENCRYPT),
 787                   !!(mode & FLAGS_CBC));
 788
 789         if (!IS_ALIGNED(req->nbytes, AES_BLOCK_SIZE)) {
 790                 pr_err("request size is not exact amount of AES blocks\n");
 791                 return -EINVAL;
 792         }
 793
 794         dd = omap_aes_find_dev(ctx);
 795         if (!dd)
 796                 return -ENODEV;
 797
 798         rctx->mode = mode;
 799
 800         return omap_aes_handle_queue(dd, req);
 801 }
 802
 803 /* ********************** ALG API ************************************ */
 804
 805 static int omap_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
 806                            unsigned int keylen)
 807 {
 808         struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
 809
 810         if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
 811                    keylen != AES_KEYSIZE_256)
 812                 return -EINVAL;
 813
 814         pr_debug("enter, keylen: %d\n", keylen);
 815
 816         memcpy(ctx->key, key, keylen);
 817         ctx->keylen = keylen;
 818
 819         return 0;
 820 }
 821
 822 static int omap_aes_ecb_encrypt(struct ablkcipher_request *req)
 823 {
 824         return omap_aes_crypt(req, FLAGS_ENCRYPT);
 825 }
 826
 827 static int omap_aes_ecb_decrypt(struct ablkcipher_request *req)
 828 {
 829         return omap_aes_crypt(req, 0);
 830 }
 831
 832 static int omap_aes_cbc_encrypt(struct ablkcipher_request *req)
 833 {
 834         return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
 835 }
 836
 837 static int omap_aes_cbc_decrypt(struct ablkcipher_request *req)
 838 {
 839         return omap_aes_crypt(req, FLAGS_CBC);
 840 }
 841
 842 static int omap_aes_ctr_encrypt(struct ablkcipher_request *req)
 843 {
 844         return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR);
 845 }
 846
 847 static int omap_aes_ctr_decrypt(struct ablkcipher_request *req)
 848 {
 849         return omap_aes_crypt(req, FLAGS_CTR);
 850 }
 851
 852 static int omap_aes_cra_init(struct crypto_tfm *tfm)
 853 {
 854         struct omap_aes_dev *dd = NULL;
 855
 856         /* Find AES device, currently picks the first device */
 857         spin_lock_bh(&list_lock);
 858         list_for_each_entry(dd, &dev_list, list) {
 859                 break;
 860         }
 861         spin_unlock_bh(&list_lock);
 862
 863         pm_runtime_get_sync(dd->dev);
 864         tfm->crt_ablkcipher.reqsize = sizeof(struct omap_aes_reqctx);
 865
 866         return 0;
 867 }
 868
 869 static void omap_aes_cra_exit(struct crypto_tfm *tfm)
 870 {
 871         struct omap_aes_dev *dd = NULL;
 872
 873         /* Find AES device, currently picks the first device */
 874         spin_lock_bh(&list_lock);
 875         list_for_each_entry(dd, &dev_list, list) {
 876                 break;
 877         }
 878         spin_unlock_bh(&list_lock);
 879
 880         pm_runtime_put_sync(dd->dev);
 881 }
 882
 883 /* ********************** ALGS ************************************ */
 884
 885 static struct crypto_alg algs_ecb_cbc[] = {
 886 {
 887         .cra_name               = "ecb(aes)",
 888         .cra_driver_name        = "ecb-aes-omap",
 889         .cra_priority           = 100,
 890         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
 891                                   CRYPTO_ALG_KERN_DRIVER_ONLY |
 892                                   CRYPTO_ALG_ASYNC,
 893         .cra_blocksize          = AES_BLOCK_SIZE,
 894         .cra_ctxsize            = sizeof(struct omap_aes_ctx),
 895         .cra_alignmask          = 0,
 896         .cra_type               = &crypto_ablkcipher_type,
 897         .cra_module             = THIS_MODULE,
 898         .cra_init               = omap_aes_cra_init,
 899         .cra_exit               = omap_aes_cra_exit,
 900         .cra_u.ablkcipher = {
 901                 .min_keysize    = AES_MIN_KEY_SIZE,
 902                 .max_keysize    = AES_MAX_KEY_SIZE,
 903                 .setkey         = omap_aes_setkey,
 904                 .encrypt        = omap_aes_ecb_encrypt,
 905                 .decrypt        = omap_aes_ecb_decrypt,
 906         }
 907 },
 908 {
 909         .cra_name               = "cbc(aes)",
 910         .cra_driver_name        = "cbc-aes-omap",
 911         .cra_priority           = 100,
 912         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
 913                                   CRYPTO_ALG_KERN_DRIVER_ONLY |
 914                                   CRYPTO_ALG_ASYNC,
 915         .cra_blocksize          = AES_BLOCK_SIZE,
 916         .cra_ctxsize            = sizeof(struct omap_aes_ctx),
 917         .cra_alignmask          = 0,
 918         .cra_type               = &crypto_ablkcipher_type,
 919         .cra_module             = THIS_MODULE,
 920         .cra_init               = omap_aes_cra_init,
 921         .cra_exit               = omap_aes_cra_exit,
 922         .cra_u.ablkcipher = {
 923                 .min_keysize    = AES_MIN_KEY_SIZE,
 924                 .max_keysize    = AES_MAX_KEY_SIZE,
 925                 .ivsize         = AES_BLOCK_SIZE,
 926                 .setkey         = omap_aes_setkey,
 927                 .encrypt        = omap_aes_cbc_encrypt,
 928                 .decrypt        = omap_aes_cbc_decrypt,
 929         }
 930 }
 931 };
 932
 933 static struct crypto_alg algs_ctr[] = {
 934 {
 935         .cra_name               = "ctr(aes)",
 936         .cra_driver_name        = "ctr-aes-omap",
 937         .cra_priority           = 100,
 938         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER |
 939                                   CRYPTO_ALG_KERN_DRIVER_ONLY |
 940                                   CRYPTO_ALG_ASYNC,
 941         .cra_blocksize          = AES_BLOCK_SIZE,
 942         .cra_ctxsize            = sizeof(struct omap_aes_ctx),
 943         .cra_alignmask          = 0,
 944         .cra_type               = &crypto_ablkcipher_type,
 945         .cra_module             = THIS_MODULE,
 946         .cra_init               = omap_aes_cra_init,
 947         .cra_exit               = omap_aes_cra_exit,
 948         .cra_u.ablkcipher = {
 949                 .min_keysize    = AES_MIN_KEY_SIZE,
 950                 .max_keysize    = AES_MAX_KEY_SIZE,
 951                 .geniv          = "eseqiv",
 952                 .ivsize         = AES_BLOCK_SIZE,
 953                 .setkey         = omap_aes_setkey,
 954                 .encrypt        = omap_aes_ctr_encrypt,
 955                 .decrypt        = omap_aes_ctr_decrypt,
 956         }
 957 } ,
 958 };
 959
 960 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = {
 961         {
 962                 .algs_list      = algs_ecb_cbc,
 963                 .size           = ARRAY_SIZE(algs_ecb_cbc),
 964         },
 965 };
 966
 967 static const struct omap_aes_pdata omap_aes_pdata_omap2 = {
 968         .algs_info      = omap_aes_algs_info_ecb_cbc,
 969         .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc),
 970         .trigger        = omap_aes_dma_trigger_omap2,
 971         .key_ofs        = 0x1c,
 972         .iv_ofs         = 0x20,
 973         .ctrl_ofs       = 0x30,
 974         .data_ofs       = 0x34,
 975         .rev_ofs        = 0x44,
 976         .mask_ofs       = 0x48,
 977         .dma_enable_in  = BIT(2),
 978         .dma_enable_out = BIT(3),
 979         .dma_start      = BIT(5),
 980         .major_mask     = 0xf0,
 981         .major_shift    = 4,
 982         .minor_mask     = 0x0f,
 983         .minor_shift    = 0,
 984 };
 985
 986 #ifdef CONFIG_OF
 987 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = {
 988         {
 989                 .algs_list      = algs_ecb_cbc,
 990                 .size           = ARRAY_SIZE(algs_ecb_cbc),
 991         },
 992         {
 993                 .algs_list      = algs_ctr,
 994                 .size           = ARRAY_SIZE(algs_ctr),
 995         },
 996 };
 997
 998 static const struct omap_aes_pdata omap_aes_pdata_omap3 = {
 999         .algs_info      = omap_aes_algs_info_ecb_cbc_ctr,
1000         .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
1001         .trigger        = omap_aes_dma_trigger_omap2,
1002         .key_ofs        = 0x1c,
1003         .iv_ofs         = 0x20,
1004         .ctrl_ofs       = 0x30,
1005         .data_ofs       = 0x34,
1006         .rev_ofs        = 0x44,
1007         .mask_ofs       = 0x48,
1008         .dma_enable_in  = BIT(2),
1009         .dma_enable_out = BIT(3),
1010         .dma_start      = BIT(5),
1011         .major_mask     = 0xf0,
1012         .major_shift    = 4,
1013         .minor_mask     = 0x0f,
1014         .minor_shift    = 0,
1015 };
1016
1017 static const struct omap_aes_pdata omap_aes_pdata_omap4 = {
1018         .algs_info      = omap_aes_algs_info_ecb_cbc_ctr,
1019         .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
1020         .trigger        = omap_aes_dma_trigger_omap4,
1021         .key_ofs        = 0x3c,
1022         .iv_ofs         = 0x40,
1023         .ctrl_ofs       = 0x50,
1024         .data_ofs       = 0x60,
1025         .rev_ofs        = 0x80,
1026         .mask_ofs       = 0x84,
1027         .dma_enable_in  = BIT(5),
1028         .dma_enable_out = BIT(6),
1029         .major_mask     = 0x0700,
1030         .major_shift    = 8,
1031         .minor_mask     = 0x003f,
1032         .minor_shift    = 0,
1033 };
1034
1035 static const struct of_device_id omap_aes_of_match[] = {
1036         {
1037                 .compatible     = "ti,omap2-aes",
1038                 .data           = &omap_aes_pdata_omap2,
1039         },
1040         {
1041                 .compatible     = "ti,omap3-aes",
1042                 .data           = &omap_aes_pdata_omap3,
1043         },
1044         {
1045                 .compatible     = "ti,omap4-aes",
1046                 .data           = &omap_aes_pdata_omap4,
1047         },
1048         {},
1049 };
1050 MODULE_DEVICE_TABLE(of, omap_aes_of_match);
1051
1052 static int omap_aes_get_res_of(struct omap_aes_dev *dd,
1053                 struct device *dev, struct resource *res)
1054 {
1055         struct device_node *node = dev->of_node;
1056         const struct of_device_id *match;
1057         int err = 0;
1058
1059         match = of_match_device(of_match_ptr(omap_aes_of_match), dev);
1060         if (!match) {
1061                 dev_err(dev, "no compatible OF match\n");
1062                 err = -EINVAL;
1063                 goto err;
1064         }
1065
1066         err = of_address_to_resource(node, 0, res);
1067         if (err < 0) {
1068                 dev_err(dev, "can't translate OF node address\n");
1069                 err = -EINVAL;
1070                 goto err;
1071         }
1072
1073         dd->dma_out = -1; /* Dummy value that's unused */
1074         dd->dma_in = -1; /* Dummy value that's unused */
1075
1076         dd->pdata = match->data;
1077
1078 err:
1079         return err;
1080 }
1081 #else
1082 static const struct of_device_id omap_aes_of_match[] = {
1083         {},
1084 };
1085
1086 static int omap_aes_get_res_of(struct omap_aes_dev *dd,
1087                 struct device *dev, struct resource *res)
1088 {
1089         return -EINVAL;
1090 }
1091 #endif
1092
1093 static int omap_aes_get_res_pdev(struct omap_aes_dev *dd,
1094                 struct platform_device *pdev, struct resource *res)
1095 {
1096         struct device *dev = &pdev->dev;
1097         struct resource *r;
1098         int err = 0;
1099
1100         /* Get the base address */
1101         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1102         if (!r) {
1103                 dev_err(dev, "no MEM resource info\n");
1104                 err = -ENODEV;
1105                 goto err;
1106         }
1107         memcpy(res, r, sizeof(*res));
1108
1109         /* Get the DMA out channel */
1110         r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1111         if (!r) {
1112                 dev_err(dev, "no DMA out resource info\n");
1113                 err = -ENODEV;
1114                 goto err;
1115         }
1116         dd->dma_out = r->start;
1117
1118         /* Get the DMA in channel */
1119         r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1120         if (!r) {
1121                 dev_err(dev, "no DMA in resource info\n");
1122                 err = -ENODEV;
1123                 goto err;
1124         }
1125         dd->dma_in = r->start;
1126
1127         /* Only OMAP2/3 can be non-DT */
1128         dd->pdata = &omap_aes_pdata_omap2;
1129
1130 err:
1131         return err;
1132 }
1133
1134 static int omap_aes_probe(struct platform_device *pdev)
1135 {
1136         struct device *dev = &pdev->dev;
1137         struct omap_aes_dev *dd;
1138         struct crypto_alg *algp;
1139         struct resource res;
1140         int err = -ENOMEM, i, j;
1141         u32 reg;
1142
1143         dd = kzalloc(sizeof(struct omap_aes_dev), GFP_KERNEL);
1144         if (dd == NULL) {
1145                 dev_err(dev, "unable to alloc data struct.\n");
1146                 goto err_data;
1147         }
1148         dd->dev = dev;
1149         platform_set_drvdata(pdev, dd);
1150
1151         spin_lock_init(&dd->lock);
1152         crypto_init_queue(&dd->queue, OMAP_AES_QUEUE_LENGTH);
1153
1154         err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) :
1155                                omap_aes_get_res_pdev(dd, pdev, &res);
1156         if (err)
1157                 goto err_res;
1158
1159         dd->io_base = devm_ioremap_resource(dev, &res);
1160         if (IS_ERR(dd->io_base)) {
1161                 err = PTR_ERR(dd->io_base);
1162                 goto err_res;
1163         }
1164         dd->phys_base = res.start;
1165
1166         pm_runtime_enable(dev);
1167         pm_runtime_get_sync(dev);
1168
1169         omap_aes_dma_stop(dd);
1170
1171         reg = omap_aes_read(dd, AES_REG_REV(dd));
1172
1173         pm_runtime_put_sync(dev);
1174
1175         dev_info(dev, "OMAP AES hw accel rev: %u.%u\n",
1176                  (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1177                  (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1178
1179         tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd);
1180         tasklet_init(&dd->queue_task, omap_aes_queue_task, (unsigned long)dd);
1181
1182         err = omap_aes_dma_init(dd);
1183         if (err)
1184                 goto err_dma;
1185
1186         INIT_LIST_HEAD(&dd->list);
1187         spin_lock(&list_lock);
1188         list_add_tail(&dd->list, &dev_list);
1189         spin_unlock(&list_lock);
1190
1191         for (i = 0; i < dd->pdata->algs_info_size; i++) {
1192                 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1193                         algp = &dd->pdata->algs_info[i].algs_list[j];
1194
1195                         pr_debug("reg alg: %s\n", algp->cra_name);
1196                         INIT_LIST_HEAD(&algp->cra_list);
1197
1198                         err = crypto_register_alg(algp);
1199                         if (err)
1200                                 goto err_algs;
1201
1202                         dd->pdata->algs_info[i].registered++;
1203                 }
1204         }
1205
1206         return 0;
1207 err_algs:
1208         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1209                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1210                         crypto_unregister_alg(
1211                                         &dd->pdata->algs_info[i].algs_list[j]);
1212         omap_aes_dma_cleanup(dd);
1213 err_dma:
1214         tasklet_kill(&dd->done_task);
1215         tasklet_kill(&dd->queue_task);
1216         pm_runtime_disable(dev);
1217 err_res:
1218         kfree(dd);
1219         dd = NULL;
1220 err_data:
1221         dev_err(dev, "initialization failed.\n");
1222         return err;
1223 }
1224
1225 static int omap_aes_remove(struct platform_device *pdev)
1226 {
1227         struct omap_aes_dev *dd = platform_get_drvdata(pdev);
1228         int i, j;
1229
1230         if (!dd)
1231                 return -ENODEV;
1232
1233         spin_lock(&list_lock);
1234         list_del(&dd->list);
1235         spin_unlock(&list_lock);
1236
1237         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1238                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1239                         crypto_unregister_alg(
1240                                         &dd->pdata->algs_info[i].algs_list[j]);
1241
1242         tasklet_kill(&dd->done_task);
1243         tasklet_kill(&dd->queue_task);
1244         omap_aes_dma_cleanup(dd);
1245         pm_runtime_disable(dd->dev);
1246         kfree(dd);
1247         dd = NULL;
1248
1249         return 0;
1250 }
1251
1252 #ifdef CONFIG_PM_SLEEP
1253 static int omap_aes_suspend(struct device *dev)
1254 {
1255         pm_runtime_put_sync(dev);
1256         return 0;
1257 }
1258
1259 static int omap_aes_resume(struct device *dev)
1260 {
1261         pm_runtime_get_sync(dev);
1262         return 0;
1263 }
1264 #endif
1265
1266 static const struct dev_pm_ops omap_aes_pm_ops = {
1267         SET_SYSTEM_SLEEP_PM_OPS(omap_aes_suspend, omap_aes_resume)
1268 };
1269
1270 static struct platform_driver omap_aes_driver = {
1271         .probe  = omap_aes_probe,
1272         .remove = omap_aes_remove,
1273         .driver = {
1274                 .name   = "omap-aes",
1275                 .owner  = THIS_MODULE,
1276                 .pm     = &omap_aes_pm_ops,
1277                 .of_match_table = omap_aes_of_match,
1278         },
1279 };
1280
1281 module_platform_driver(omap_aes_driver);
1282
1283 MODULE_DESCRIPTION("OMAP AES hw acceleration support.");
1284 MODULE_LICENSE("GPL v2");
1285 MODULE_AUTHOR("Dmitry Kasatkin");
1286