drivers/crypto/mv_cesa.c

   1 /*
   2  * Support for Marvell's crypto engine which can be found on some Orion5X
   3  * boards.
   4  *
   5  * Author: Sebastian Andrzej Siewior < sebastian at breakpoint dot cc >
   6  * License: GPLv2
   7  *
   8  */
   9 #include <crypto/aes.h>
  10 #include <crypto/algapi.h>
  11 #include <linux/crypto.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/kthread.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/scatterlist.h>
  17 #include <linux/slab.h>
  18 #include <crypto/internal/hash.h>
  19 #include <crypto/sha.h>
  20
  21 #include "mv_cesa.h"
  22
  23 #define MV_CESA "MV-CESA:"
  24 #define MAX_HW_HASH_SIZE        0xFFFF
  25
  26 /*
  27  * STM:
  28  *   /---------------------------------------\
  29  *   |                                       | request complete
  30  *  \./                                      |
  31  * IDLE -> new request -> BUSY -> done -> DEQUEUE
  32  *                         /°\               |
  33  *                          |                | more scatter entries
  34  *                          \________________/
  35  */
  36 enum engine_status {
  37         ENGINE_IDLE,
  38         ENGINE_BUSY,
  39         ENGINE_W_DEQUEUE,
  40 };
  41
  42 /**
  43  * struct req_progress - used for every crypt request
  44  * @src_sg_it:          sg iterator for src
  45  * @dst_sg_it:          sg iterator for dst
  46  * @sg_src_left:        bytes left in src to process (scatter list)
  47  * @src_start:          offset to add to src start position (scatter list)
  48  * @crypt_len:          length of current hw crypt/hash process
  49  * @hw_nbytes:          total bytes to process in hw for this request
  50  * @copy_back:          whether to copy data back (crypt) or not (hash)
  51  * @sg_dst_left:        bytes left dst to process in this scatter list
  52  * @dst_start:          offset to add to dst start position (scatter list)
  53  * @hw_processed_bytes: number of bytes processed by hw (request).
  54  *
  55  * sg helper are used to iterate over the scatterlist. Since the size of the
  56  * SRAM may be less than the scatter size, this struct struct is used to keep
  57  * track of progress within current scatterlist.
  58  */
  59 struct req_progress {
  60         struct sg_mapping_iter src_sg_it;
  61         struct sg_mapping_iter dst_sg_it;
  62         void (*complete) (void);
  63         void (*process) (int is_first);
  64
  65         /* src mostly */
  66         int sg_src_left;
  67         int src_start;
  68         int crypt_len;
  69         int hw_nbytes;
  70         /* dst mostly */
  71         int copy_back;
  72         int sg_dst_left;
  73         int dst_start;
  74         int hw_processed_bytes;
  75 };
  76
  77 struct crypto_priv {
  78         void __iomem *reg;
  79         void __iomem *sram;
  80         int irq;
  81         struct task_struct *queue_th;
  82
  83         /* the lock protects queue and eng_st */
  84         spinlock_t lock;
  85         struct crypto_queue queue;
  86         enum engine_status eng_st;
  87         struct crypto_async_request *cur_req;
  88         struct req_progress p;
  89         int max_req_size;
  90         int sram_size;
  91         int has_sha1;
  92         int has_hmac_sha1;
  93 };
  94
  95 static struct crypto_priv *cpg;
  96
  97 struct mv_ctx {
  98         u8 aes_enc_key[AES_KEY_LEN];
  99         u32 aes_dec_key[8];
 100         int key_len;
 101         u32 need_calc_aes_dkey;
 102 };
 103
 104 enum crypto_op {
 105         COP_AES_ECB,
 106         COP_AES_CBC,
 107 };
 108
 109 struct mv_req_ctx {
 110         enum crypto_op op;
 111         int decrypt;
 112 };
 113
 114 enum hash_op {
 115         COP_SHA1,
 116         COP_HMAC_SHA1
 117 };
 118
 119 struct mv_tfm_hash_ctx {
 120         struct crypto_shash *fallback;
 121         struct crypto_shash *base_hash;
 122         u32 ivs[2 * SHA1_DIGEST_SIZE / 4];
 123         int count_add;
 124         enum hash_op op;
 125 };
 126
 127 struct mv_req_hash_ctx {
 128         u64 count;
 129         u32 state[SHA1_DIGEST_SIZE / 4];
 130         u8 buffer[SHA1_BLOCK_SIZE];
 131         int first_hash;         /* marks that we don't have previous state */
 132         int last_chunk;         /* marks that this is the 'final' request */
 133         int extra_bytes;        /* unprocessed bytes in buffer */
 134         enum hash_op op;
 135         int count_add;
 136         struct scatterlist dummysg;
 137 };
 138
 139 static void compute_aes_dec_key(struct mv_ctx *ctx)
 140 {
 141         struct crypto_aes_ctx gen_aes_key;
 142         int key_pos;
 143
 144         if (!ctx->need_calc_aes_dkey)
 145                 return;
 146
 147         crypto_aes_expand_key(&gen_aes_key, ctx->aes_enc_key, ctx->key_len);
 148
 149         key_pos = ctx->key_len + 24;
 150         memcpy(ctx->aes_dec_key, &gen_aes_key.key_enc[key_pos], 4 * 4);
 151         switch (ctx->key_len) {
 152         case AES_KEYSIZE_256:
 153                 key_pos -= 2;
 154                 /* fall */
 155         case AES_KEYSIZE_192:
 156                 key_pos -= 2;
 157                 memcpy(&ctx->aes_dec_key[4], &gen_aes_key.key_enc[key_pos],
 158                                 4 * 4);
 159                 break;
 160         }
 161         ctx->need_calc_aes_dkey = 0;
 162 }
 163
 164 static int mv_setkey_aes(struct crypto_ablkcipher *cipher, const u8 *key,
 165                 unsigned int len)
 166 {
 167         struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
 168         struct mv_ctx *ctx = crypto_tfm_ctx(tfm);
 169
 170         switch (len) {
 171         case AES_KEYSIZE_128:
 172         case AES_KEYSIZE_192:
 173         case AES_KEYSIZE_256:
 174                 break;
 175         default:
 176                 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
 177                 return -EINVAL;
 178         }
 179         ctx->key_len = len;
 180         ctx->need_calc_aes_dkey = 1;
 181
 182         memcpy(ctx->aes_enc_key, key, AES_KEY_LEN);
 183         return 0;
 184 }
 185
 186 static void copy_src_to_buf(struct req_progress *p, char *dbuf, int len)
 187 {
 188         int ret;
 189         void *sbuf;
 190         int copied = 0;
 191
 192         while (1) {
 193                 if (!p->sg_src_left) {
 194                         ret = sg_miter_next(&p->src_sg_it);
 195                         BUG_ON(!ret);
 196                         p->sg_src_left = p->src_sg_it.length;
 197                         p->src_start = 0;
 198                 }
 199
 200                 sbuf = p->src_sg_it.addr + p->src_start;
 201
 202                 if (p->sg_src_left <= len - copied) {
 203                         memcpy(dbuf + copied, sbuf, p->sg_src_left);
 204                         copied += p->sg_src_left;
 205                         p->sg_src_left = 0;
 206                         if (copied >= len)
 207                                 break;
 208                 } else {
 209                         int copy_len = len - copied;
 210                         memcpy(dbuf + copied, sbuf, copy_len);
 211                         p->src_start += copy_len;
 212                         p->sg_src_left -= copy_len;
 213                         break;
 214                 }
 215         }
 216 }
 217
 218 static void setup_data_in(void)
 219 {
 220         struct req_progress *p = &cpg->p;
 221         int data_in_sram =
 222             min(p->hw_nbytes - p->hw_processed_bytes, cpg->max_req_size);
 223         copy_src_to_buf(p, cpg->sram + SRAM_DATA_IN_START + p->crypt_len,
 224                         data_in_sram - p->crypt_len);
 225         p->crypt_len = data_in_sram;
 226 }
 227
 228 static void mv_process_current_q(int first_block)
 229 {
 230         struct ablkcipher_request *req = ablkcipher_request_cast(cpg->cur_req);
 231         struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
 232         struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
 233         struct sec_accel_config op;
 234
 235         switch (req_ctx->op) {
 236         case COP_AES_ECB:
 237                 op.config = CFG_OP_CRYPT_ONLY | CFG_ENCM_AES | CFG_ENC_MODE_ECB;
 238                 break;
 239         case COP_AES_CBC:
 240         default:
 241                 op.config = CFG_OP_CRYPT_ONLY | CFG_ENCM_AES | CFG_ENC_MODE_CBC;
 242                 op.enc_iv = ENC_IV_POINT(SRAM_DATA_IV) |
 243                         ENC_IV_BUF_POINT(SRAM_DATA_IV_BUF);
 244                 if (first_block)
 245                         memcpy(cpg->sram + SRAM_DATA_IV, req->info, 16);
 246                 break;
 247         }
 248         if (req_ctx->decrypt) {
 249                 op.config |= CFG_DIR_DEC;
 250                 memcpy(cpg->sram + SRAM_DATA_KEY_P, ctx->aes_dec_key,
 251                                 AES_KEY_LEN);
 252         } else {
 253                 op.config |= CFG_DIR_ENC;
 254                 memcpy(cpg->sram + SRAM_DATA_KEY_P, ctx->aes_enc_key,
 255                                 AES_KEY_LEN);
 256         }
 257
 258         switch (ctx->key_len) {
 259         case AES_KEYSIZE_128:
 260                 op.config |= CFG_AES_LEN_128;
 261                 break;
 262         case AES_KEYSIZE_192:
 263                 op.config |= CFG_AES_LEN_192;
 264                 break;
 265         case AES_KEYSIZE_256:
 266                 op.config |= CFG_AES_LEN_256;
 267                 break;
 268         }
 269         op.enc_p = ENC_P_SRC(SRAM_DATA_IN_START) |
 270                 ENC_P_DST(SRAM_DATA_OUT_START);
 271         op.enc_key_p = SRAM_DATA_KEY_P;
 272
 273         setup_data_in();
 274         op.enc_len = cpg->p.crypt_len;
 275         memcpy(cpg->sram + SRAM_CONFIG, &op,
 276                         sizeof(struct sec_accel_config));
 277
 278         writel(SRAM_CONFIG, cpg->reg + SEC_ACCEL_DESC_P0);
 279         /* GO */
 280         writel(SEC_CMD_EN_SEC_ACCL0, cpg->reg + SEC_ACCEL_CMD);
 281
 282         /*
 283          * XXX: add timer if the interrupt does not occur for some mystery
 284          * reason
 285          */
 286 }
 287
 288 static void mv_crypto_algo_completion(void)
 289 {
 290         struct ablkcipher_request *req = ablkcipher_request_cast(cpg->cur_req);
 291         struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
 292
 293         sg_miter_stop(&cpg->p.src_sg_it);
 294         sg_miter_stop(&cpg->p.dst_sg_it);
 295
 296         if (req_ctx->op != COP_AES_CBC)
 297                 return ;
 298
 299         memcpy(req->info, cpg->sram + SRAM_DATA_IV_BUF, 16);
 300 }
 301
 302 static void mv_process_hash_current(int first_block)
 303 {
 304         struct ahash_request *req = ahash_request_cast(cpg->cur_req);
 305         struct mv_req_hash_ctx *req_ctx = ahash_request_ctx(req);
 306         struct req_progress *p = &cpg->p;
 307         struct sec_accel_config op = { 0 };
 308         int is_last;
 309
 310         switch (req_ctx->op) {
 311         case COP_SHA1:
 312         default:
 313                 op.config = CFG_OP_MAC_ONLY | CFG_MACM_SHA1;
 314                 break;
 315         case COP_HMAC_SHA1:
 316                 op.config = CFG_OP_MAC_ONLY | CFG_MACM_HMAC_SHA1;
 317                 break;
 318         }
 319
 320         op.mac_src_p =
 321                 MAC_SRC_DATA_P(SRAM_DATA_IN_START) | MAC_SRC_TOTAL_LEN((u32)
 322                 req_ctx->
 323                 count);
 324
 325         setup_data_in();
 326
 327         op.mac_digest =
 328                 MAC_DIGEST_P(SRAM_DIGEST_BUF) | MAC_FRAG_LEN(p->crypt_len);
 329         op.mac_iv =
 330                 MAC_INNER_IV_P(SRAM_HMAC_IV_IN) |
 331                 MAC_OUTER_IV_P(SRAM_HMAC_IV_OUT);
 332
 333         is_last = req_ctx->last_chunk
 334                 && (p->hw_processed_bytes + p->crypt_len >= p->hw_nbytes)
 335                 && (req_ctx->count <= MAX_HW_HASH_SIZE);
 336         if (req_ctx->first_hash) {
 337                 if (is_last)
 338                         op.config |= CFG_NOT_FRAG;
 339                 else
 340                         op.config |= CFG_FIRST_FRAG;
 341
 342                 req_ctx->first_hash = 0;
 343         } else {
 344                 if (is_last)
 345                         op.config |= CFG_LAST_FRAG;
 346                 else
 347                         op.config |= CFG_MID_FRAG;
 348         }
 349
 350         memcpy(cpg->sram + SRAM_CONFIG, &op, sizeof(struct sec_accel_config));
 351
 352         writel(SRAM_CONFIG, cpg->reg + SEC_ACCEL_DESC_P0);
 353         /* GO */
 354         writel(SEC_CMD_EN_SEC_ACCL0, cpg->reg + SEC_ACCEL_CMD);
 355
 356         /*
 357         * XXX: add timer if the interrupt does not occur for some mystery
 358         * reason
 359         */
 360 }
 361
 362 static inline int mv_hash_import_sha1_ctx(const struct mv_req_hash_ctx *ctx,
 363                                           struct shash_desc *desc)
 364 {
 365         int i;
 366         struct sha1_state shash_state;
 367
 368         shash_state.count = ctx->count + ctx->count_add;
 369         for (i = 0; i < 5; i++)
 370                 shash_state.state[i] = ctx->state[i];
 371         memcpy(shash_state.buffer, ctx->buffer, sizeof(shash_state.buffer));
 372         return crypto_shash_import(desc, &shash_state);
 373 }
 374
 375 static int mv_hash_final_fallback(struct ahash_request *req)
 376 {
 377         const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
 378         struct mv_req_hash_ctx *req_ctx = ahash_request_ctx(req);
 379         struct {
 380                 struct shash_desc shash;
 381                 char ctx[crypto_shash_descsize(tfm_ctx->fallback)];
 382         } desc;
 383         int rc;
 384
 385         desc.shash.tfm = tfm_ctx->fallback;
 386         desc.shash.flags = CRYPTO_TFM_REQ_MAY_SLEEP;
 387         if (unlikely(req_ctx->first_hash)) {
 388                 crypto_shash_init(&desc.shash);
 389                 crypto_shash_update(&desc.shash, req_ctx->buffer,
 390                                     req_ctx->extra_bytes);
 391         } else {
 392                 /* only SHA1 for now....
 393                  */
 394                 rc = mv_hash_import_sha1_ctx(req_ctx, &desc.shash);
 395                 if (rc)
 396                         goto out;
 397         }
 398         rc = crypto_shash_final(&desc.shash, req->result);
 399 out:
 400         return rc;
 401 }
 402
 403 static void mv_hash_algo_completion(void)
 404 {
 405         struct ahash_request *req = ahash_request_cast(cpg->cur_req);
 406         struct mv_req_hash_ctx *ctx = ahash_request_ctx(req);
 407
 408         if (ctx->extra_bytes)
 409                 copy_src_to_buf(&cpg->p, ctx->buffer, ctx->extra_bytes);
 410         sg_miter_stop(&cpg->p.src_sg_it);
 411
 412         ctx->state[0] = readl(cpg->reg + DIGEST_INITIAL_VAL_A);
 413         ctx->state[1] = readl(cpg->reg + DIGEST_INITIAL_VAL_B);
 414         ctx->state[2] = readl(cpg->reg + DIGEST_INITIAL_VAL_C);
 415         ctx->state[3] = readl(cpg->reg + DIGEST_INITIAL_VAL_D);
 416         ctx->state[4] = readl(cpg->reg + DIGEST_INITIAL_VAL_E);
 417
 418         if (likely(ctx->last_chunk)) {
 419                 if (likely(ctx->count <= MAX_HW_HASH_SIZE)) {
 420                         memcpy(req->result, cpg->sram + SRAM_DIGEST_BUF,
 421                                crypto_ahash_digestsize(crypto_ahash_reqtfm
 422                                                        (req)));
 423                 } else
 424                         mv_hash_final_fallback(req);
 425         }
 426 }
 427
 428 static void dequeue_complete_req(void)
 429 {
 430         struct crypto_async_request *req = cpg->cur_req;
 431         void *buf;
 432         int ret;
 433         cpg->p.hw_processed_bytes += cpg->p.crypt_len;
 434         if (cpg->p.copy_back) {
 435                 int need_copy_len = cpg->p.crypt_len;
 436                 int sram_offset = 0;
 437                 do {
 438                         int dst_copy;
 439
 440                         if (!cpg->p.sg_dst_left) {
 441                                 ret = sg_miter_next(&cpg->p.dst_sg_it);
 442                                 BUG_ON(!ret);
 443                                 cpg->p.sg_dst_left = cpg->p.dst_sg_it.length;
 444                                 cpg->p.dst_start = 0;
 445                         }
 446
 447                         buf = cpg->p.dst_sg_it.addr;
 448                         buf += cpg->p.dst_start;
 449
 450                         dst_copy = min(need_copy_len, cpg->p.sg_dst_left);
 451
 452                         memcpy(buf,
 453                                cpg->sram + SRAM_DATA_OUT_START + sram_offset,
 454                                dst_copy);
 455                         sram_offset += dst_copy;
 456                         cpg->p.sg_dst_left -= dst_copy;
 457                         need_copy_len -= dst_copy;
 458                         cpg->p.dst_start += dst_copy;
 459                 } while (need_copy_len > 0);
 460         }
 461
 462         cpg->p.crypt_len = 0;
 463
 464         BUG_ON(cpg->eng_st != ENGINE_W_DEQUEUE);
 465         if (cpg->p.hw_processed_bytes < cpg->p.hw_nbytes) {
 466                 /* process next scatter list entry */
 467                 cpg->eng_st = ENGINE_BUSY;
 468                 cpg->p.process(0);
 469         } else {
 470                 cpg->p.complete();
 471                 cpg->eng_st = ENGINE_IDLE;
 472                 local_bh_disable();
 473                 req->complete(req, 0);
 474                 local_bh_enable();
 475         }
 476 }
 477
 478 static int count_sgs(struct scatterlist *sl, unsigned int total_bytes)
 479 {
 480         int i = 0;
 481         size_t cur_len;
 482
 483         while (1) {
 484                 cur_len = sl[i].length;
 485                 ++i;
 486                 if (total_bytes > cur_len)
 487                         total_bytes -= cur_len;
 488                 else
 489                         break;
 490         }
 491
 492         return i;
 493 }
 494
 495 static void mv_start_new_crypt_req(struct ablkcipher_request *req)
 496 {
 497         struct req_progress *p = &cpg->p;
 498         int num_sgs;
 499
 500         cpg->cur_req = &req->base;
 501         memset(p, 0, sizeof(struct req_progress));
 502         p->hw_nbytes = req->nbytes;
 503         p->complete = mv_crypto_algo_completion;
 504         p->process = mv_process_current_q;
 505         p->copy_back = 1;
 506
 507         num_sgs = count_sgs(req->src, req->nbytes);
 508         sg_miter_start(&p->src_sg_it, req->src, num_sgs, SG_MITER_FROM_SG);
 509
 510         num_sgs = count_sgs(req->dst, req->nbytes);
 511         sg_miter_start(&p->dst_sg_it, req->dst, num_sgs, SG_MITER_TO_SG);
 512
 513         mv_process_current_q(1);
 514 }
 515
 516 static void mv_start_new_hash_req(struct ahash_request *req)
 517 {
 518         struct req_progress *p = &cpg->p;
 519         struct mv_req_hash_ctx *ctx = ahash_request_ctx(req);
 520         const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
 521         int num_sgs, hw_bytes, old_extra_bytes, rc;
 522         cpg->cur_req = &req->base;
 523         memset(p, 0, sizeof(struct req_progress));
 524         hw_bytes = req->nbytes + ctx->extra_bytes;
 525         old_extra_bytes = ctx->extra_bytes;
 526
 527         if (unlikely(ctx->extra_bytes)) {
 528                 memcpy(cpg->sram + SRAM_DATA_IN_START, ctx->buffer,
 529                        ctx->extra_bytes);
 530                 p->crypt_len = ctx->extra_bytes;
 531         }
 532
 533         memcpy(cpg->sram + SRAM_HMAC_IV_IN, tfm_ctx->ivs, sizeof(tfm_ctx->ivs));
 534
 535         if (unlikely(!ctx->first_hash)) {
 536                 writel(ctx->state[0], cpg->reg + DIGEST_INITIAL_VAL_A);
 537                 writel(ctx->state[1], cpg->reg + DIGEST_INITIAL_VAL_B);
 538                 writel(ctx->state[2], cpg->reg + DIGEST_INITIAL_VAL_C);
 539                 writel(ctx->state[3], cpg->reg + DIGEST_INITIAL_VAL_D);
 540                 writel(ctx->state[4], cpg->reg + DIGEST_INITIAL_VAL_E);
 541         }
 542
 543         ctx->extra_bytes = hw_bytes % SHA1_BLOCK_SIZE;
 544         if (ctx->extra_bytes != 0
 545             && (!ctx->last_chunk || ctx->count > MAX_HW_HASH_SIZE))
 546                 hw_bytes -= ctx->extra_bytes;
 547         else
 548                 ctx->extra_bytes = 0;
 549
 550         num_sgs = count_sgs(req->src, req->nbytes);
 551         sg_miter_start(&p->src_sg_it, req->src, num_sgs, SG_MITER_FROM_SG);
 552
 553         if (hw_bytes) {
 554                 p->hw_nbytes = hw_bytes;
 555                 p->complete = mv_hash_algo_completion;
 556                 p->process = mv_process_hash_current;
 557
 558                 mv_process_hash_current(1);
 559         } else {
 560                 copy_src_to_buf(p, ctx->buffer + old_extra_bytes,
 561                                 ctx->extra_bytes - old_extra_bytes);
 562                 sg_miter_stop(&p->src_sg_it);
 563                 if (ctx->last_chunk)
 564                         rc = mv_hash_final_fallback(req);
 565                 else
 566                         rc = 0;
 567                 cpg->eng_st = ENGINE_IDLE;
 568                 local_bh_disable();
 569                 req->base.complete(&req->base, rc);
 570                 local_bh_enable();
 571         }
 572 }
 573
 574 static int queue_manag(void *data)
 575 {
 576         cpg->eng_st = ENGINE_IDLE;
 577         do {
 578                 struct crypto_async_request *async_req = NULL;
 579                 struct crypto_async_request *backlog;
 580
 581                 __set_current_state(TASK_INTERRUPTIBLE);
 582
 583                 if (cpg->eng_st == ENGINE_W_DEQUEUE)
 584                         dequeue_complete_req();
 585
 586                 spin_lock_irq(&cpg->lock);
 587                 if (cpg->eng_st == ENGINE_IDLE) {
 588                         backlog = crypto_get_backlog(&cpg->queue);
 589                         async_req = crypto_dequeue_request(&cpg->queue);
 590                         if (async_req) {
 591                                 BUG_ON(cpg->eng_st != ENGINE_IDLE);
 592                                 cpg->eng_st = ENGINE_BUSY;
 593                         }
 594                 }
 595                 spin_unlock_irq(&cpg->lock);
 596
 597                 if (backlog) {
 598                         backlog->complete(backlog, -EINPROGRESS);
 599                         backlog = NULL;
 600                 }
 601
 602                 if (async_req) {
 603                         if (async_req->tfm->__crt_alg->cra_type !=
 604                             &crypto_ahash_type) {
 605                                 struct ablkcipher_request *req =
 606                                     ablkcipher_request_cast(async_req);
 607                                 mv_start_new_crypt_req(req);
 608                         } else {
 609                                 struct ahash_request *req =
 610                                     ahash_request_cast(async_req);
 611                                 mv_start_new_hash_req(req);
 612                         }
 613                         async_req = NULL;
 614                 }
 615
 616                 schedule();
 617
 618         } while (!kthread_should_stop());
 619         return 0;
 620 }
 621
 622 static int mv_handle_req(struct crypto_async_request *req)
 623 {
 624         unsigned long flags;
 625         int ret;
 626
 627         spin_lock_irqsave(&cpg->lock, flags);
 628         ret = crypto_enqueue_request(&cpg->queue, req);
 629         spin_unlock_irqrestore(&cpg->lock, flags);
 630         wake_up_process(cpg->queue_th);
 631         return ret;
 632 }
 633
 634 static int mv_enc_aes_ecb(struct ablkcipher_request *req)
 635 {
 636         struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
 637
 638         req_ctx->op = COP_AES_ECB;
 639         req_ctx->decrypt = 0;
 640
 641         return mv_handle_req(&req->base);
 642 }
 643
 644 static int mv_dec_aes_ecb(struct ablkcipher_request *req)
 645 {
 646         struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
 647         struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
 648
 649         req_ctx->op = COP_AES_ECB;
 650         req_ctx->decrypt = 1;
 651
 652         compute_aes_dec_key(ctx);
 653         return mv_handle_req(&req->base);
 654 }
 655
 656 static int mv_enc_aes_cbc(struct ablkcipher_request *req)
 657 {
 658         struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
 659
 660         req_ctx->op = COP_AES_CBC;
 661         req_ctx->decrypt = 0;
 662
 663         return mv_handle_req(&req->base);
 664 }
 665
 666 static int mv_dec_aes_cbc(struct ablkcipher_request *req)
 667 {
 668         struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
 669         struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
 670
 671         req_ctx->op = COP_AES_CBC;
 672         req_ctx->decrypt = 1;
 673
 674         compute_aes_dec_key(ctx);
 675         return mv_handle_req(&req->base);
 676 }
 677
 678 static int mv_cra_init(struct crypto_tfm *tfm)
 679 {
 680         tfm->crt_ablkcipher.reqsize = sizeof(struct mv_req_ctx);
 681         return 0;
 682 }
 683
 684 static void mv_init_hash_req_ctx(struct mv_req_hash_ctx *ctx, int op,
 685                                  int is_last, unsigned int req_len,
 686                                  int count_add)
 687 {
 688         memset(ctx, 0, sizeof(*ctx));
 689         ctx->op = op;
 690         ctx->count = req_len;
 691         ctx->first_hash = 1;
 692         ctx->last_chunk = is_last;
 693         ctx->count_add = count_add;
 694 }
 695
 696 static void mv_update_hash_req_ctx(struct mv_req_hash_ctx *ctx, int is_last,
 697                                    unsigned req_len)
 698 {
 699         ctx->last_chunk = is_last;
 700         ctx->count += req_len;
 701 }
 702
 703 static int mv_hash_init(struct ahash_request *req)
 704 {
 705         const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
 706         mv_init_hash_req_ctx(ahash_request_ctx(req), tfm_ctx->op, 0, 0,
 707                              tfm_ctx->count_add);
 708         return 0;
 709 }
 710
 711 static int mv_hash_update(struct ahash_request *req)
 712 {
 713         if (!req->nbytes)
 714                 return 0;
 715
 716         mv_update_hash_req_ctx(ahash_request_ctx(req), 0, req->nbytes);
 717         return mv_handle_req(&req->base);
 718 }
 719
 720 static int mv_hash_final(struct ahash_request *req)
 721 {
 722         struct mv_req_hash_ctx *ctx = ahash_request_ctx(req);
 723         /* dummy buffer of 4 bytes */
 724         sg_init_one(&ctx->dummysg, ctx->buffer, 4);
 725         /* I think I'm allowed to do that... */
 726         ahash_request_set_crypt(req, &ctx->dummysg, req->result, 0);
 727         mv_update_hash_req_ctx(ctx, 1, 0);
 728         return mv_handle_req(&req->base);
 729 }
 730
 731 static int mv_hash_finup(struct ahash_request *req)
 732 {
 733         if (!req->nbytes)
 734                 return mv_hash_final(req);
 735
 736         mv_update_hash_req_ctx(ahash_request_ctx(req), 1, req->nbytes);
 737         return mv_handle_req(&req->base);
 738 }
 739
 740 static int mv_hash_digest(struct ahash_request *req)
 741 {
 742         const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
 743         mv_init_hash_req_ctx(ahash_request_ctx(req), tfm_ctx->op, 1,
 744                              req->nbytes, tfm_ctx->count_add);
 745         return mv_handle_req(&req->base);
 746 }
 747
 748 static void mv_hash_init_ivs(struct mv_tfm_hash_ctx *ctx, const void *istate,
 749                              const void *ostate)
 750 {
 751         const struct sha1_state *isha1_state = istate, *osha1_state = ostate;
 752         int i;
 753         for (i = 0; i < 5; i++) {
 754                 ctx->ivs[i] = cpu_to_be32(isha1_state->state[i]);
 755                 ctx->ivs[i + 5] = cpu_to_be32(osha1_state->state[i]);
 756         }
 757 }
 758
 759 static int mv_hash_setkey(struct crypto_ahash *tfm, const u8 * key,
 760                           unsigned int keylen)
 761 {
 762         int rc;
 763         struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(&tfm->base);
 764         int bs, ds, ss;
 765
 766         if (!ctx->base_hash)
 767                 return 0;
 768
 769         rc = crypto_shash_setkey(ctx->fallback, key, keylen);
 770         if (rc)
 771                 return rc;
 772
 773         /* Can't see a way to extract the ipad/opad from the fallback tfm
 774            so I'm basically copying code from the hmac module */
 775         bs = crypto_shash_blocksize(ctx->base_hash);
 776         ds = crypto_shash_digestsize(ctx->base_hash);
 777         ss = crypto_shash_statesize(ctx->base_hash);
 778
 779         {
 780                 struct {
 781                         struct shash_desc shash;
 782                         char ctx[crypto_shash_descsize(ctx->base_hash)];
 783                 } desc;
 784                 unsigned int i;
 785                 char ipad[ss];
 786                 char opad[ss];
 787
 788                 desc.shash.tfm = ctx->base_hash;
 789                 desc.shash.flags = crypto_shash_get_flags(ctx->base_hash) &
 790                     CRYPTO_TFM_REQ_MAY_SLEEP;
 791
 792                 if (keylen > bs) {
 793                         int err;
 794
 795                         err =
 796                             crypto_shash_digest(&desc.shash, key, keylen, ipad);
 797                         if (err)
 798                                 return err;
 799
 800                         keylen = ds;
 801                 } else
 802                         memcpy(ipad, key, keylen);
 803
 804                 memset(ipad + keylen, 0, bs - keylen);
 805                 memcpy(opad, ipad, bs);
 806
 807                 for (i = 0; i < bs; i++) {
 808                         ipad[i] ^= 0x36;
 809                         opad[i] ^= 0x5c;
 810                 }
 811
 812                 rc = crypto_shash_init(&desc.shash) ? :
 813                     crypto_shash_update(&desc.shash, ipad, bs) ? :
 814                     crypto_shash_export(&desc.shash, ipad) ? :
 815                     crypto_shash_init(&desc.shash) ? :
 816                     crypto_shash_update(&desc.shash, opad, bs) ? :
 817                     crypto_shash_export(&desc.shash, opad);
 818
 819                 if (rc == 0)
 820                         mv_hash_init_ivs(ctx, ipad, opad);
 821
 822                 return rc;
 823         }
 824 }
 825
 826 static int mv_cra_hash_init(struct crypto_tfm *tfm, const char *base_hash_name,
 827                             enum hash_op op, int count_add)
 828 {
 829         const char *fallback_driver_name = tfm->__crt_alg->cra_name;
 830         struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(tfm);
 831         struct crypto_shash *fallback_tfm = NULL;
 832         struct crypto_shash *base_hash = NULL;
 833         int err = -ENOMEM;
 834
 835         ctx->op = op;
 836         ctx->count_add = count_add;
 837
 838         /* Allocate a fallback and abort if it failed. */
 839         fallback_tfm = crypto_alloc_shash(fallback_driver_name, 0,
 840                                           CRYPTO_ALG_NEED_FALLBACK);
 841         if (IS_ERR(fallback_tfm)) {
 842                 printk(KERN_WARNING MV_CESA
 843                        "Fallback driver '%s' could not be loaded!\n",
 844                        fallback_driver_name);
 845                 err = PTR_ERR(fallback_tfm);
 846                 goto out;
 847         }
 848         ctx->fallback = fallback_tfm;
 849
 850         if (base_hash_name) {
 851                 /* Allocate a hash to compute the ipad/opad of hmac. */
 852                 base_hash = crypto_alloc_shash(base_hash_name, 0,
 853                                                CRYPTO_ALG_NEED_FALLBACK);
 854                 if (IS_ERR(base_hash)) {
 855                         printk(KERN_WARNING MV_CESA
 856                                "Base driver '%s' could not be loaded!\n",
 857                                base_hash_name);
 858                         err = PTR_ERR(base_hash);
 859                         goto err_bad_base;
 860                 }
 861         }
 862         ctx->base_hash = base_hash;
 863
 864         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
 865                                  sizeof(struct mv_req_hash_ctx) +
 866                                  crypto_shash_descsize(ctx->fallback));
 867         return 0;
 868 err_bad_base:
 869         crypto_free_shash(fallback_tfm);
 870 out:
 871         return err;
 872 }
 873
 874 static void mv_cra_hash_exit(struct crypto_tfm *tfm)
 875 {
 876         struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(tfm);
 877
 878         crypto_free_shash(ctx->fallback);
 879         if (ctx->base_hash)
 880                 crypto_free_shash(ctx->base_hash);
 881 }
 882
 883 static int mv_cra_hash_sha1_init(struct crypto_tfm *tfm)
 884 {
 885         return mv_cra_hash_init(tfm, NULL, COP_SHA1, 0);
 886 }
 887
 888 static int mv_cra_hash_hmac_sha1_init(struct crypto_tfm *tfm)
 889 {
 890         return mv_cra_hash_init(tfm, "sha1", COP_HMAC_SHA1, SHA1_BLOCK_SIZE);
 891 }
 892
 893 irqreturn_t crypto_int(int irq, void *priv)
 894 {
 895         u32 val;
 896
 897         val = readl(cpg->reg + SEC_ACCEL_INT_STATUS);
 898         if (!(val & SEC_INT_ACCEL0_DONE))
 899                 return IRQ_NONE;
 900
 901         val &= ~SEC_INT_ACCEL0_DONE;
 902         writel(val, cpg->reg + FPGA_INT_STATUS);
 903         writel(val, cpg->reg + SEC_ACCEL_INT_STATUS);
 904         BUG_ON(cpg->eng_st != ENGINE_BUSY);
 905         cpg->eng_st = ENGINE_W_DEQUEUE;
 906         wake_up_process(cpg->queue_th);
 907         return IRQ_HANDLED;
 908 }
 909
 910 struct crypto_alg mv_aes_alg_ecb = {
 911         .cra_name               = "ecb(aes)",
 912         .cra_driver_name        = "mv-ecb-aes",
 913         .cra_priority   = 300,
 914         .cra_flags      = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
 915         .cra_blocksize  = 16,
 916         .cra_ctxsize    = sizeof(struct mv_ctx),
 917         .cra_alignmask  = 0,
 918         .cra_type       = &crypto_ablkcipher_type,
 919         .cra_module     = THIS_MODULE,
 920         .cra_init       = mv_cra_init,
 921         .cra_u          = {
 922                 .ablkcipher = {
 923                         .min_keysize    =       AES_MIN_KEY_SIZE,
 924                         .max_keysize    =       AES_MAX_KEY_SIZE,
 925                         .setkey         =       mv_setkey_aes,
 926                         .encrypt        =       mv_enc_aes_ecb,
 927                         .decrypt        =       mv_dec_aes_ecb,
 928                 },
 929         },
 930 };
 931
 932 struct crypto_alg mv_aes_alg_cbc = {
 933         .cra_name               = "cbc(aes)",
 934         .cra_driver_name        = "mv-cbc-aes",
 935         .cra_priority   = 300,
 936         .cra_flags      = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
 937         .cra_blocksize  = AES_BLOCK_SIZE,
 938         .cra_ctxsize    = sizeof(struct mv_ctx),
 939         .cra_alignmask  = 0,
 940         .cra_type       = &crypto_ablkcipher_type,
 941         .cra_module     = THIS_MODULE,
 942         .cra_init       = mv_cra_init,
 943         .cra_u          = {
 944                 .ablkcipher = {
 945                         .ivsize         =       AES_BLOCK_SIZE,
 946                         .min_keysize    =       AES_MIN_KEY_SIZE,
 947                         .max_keysize    =       AES_MAX_KEY_SIZE,
 948                         .setkey         =       mv_setkey_aes,
 949                         .encrypt        =       mv_enc_aes_cbc,
 950                         .decrypt        =       mv_dec_aes_cbc,
 951                 },
 952         },
 953 };
 954
 955 struct ahash_alg mv_sha1_alg = {
 956         .init = mv_hash_init,
 957         .update = mv_hash_update,
 958         .final = mv_hash_final,
 959         .finup = mv_hash_finup,
 960         .digest = mv_hash_digest,
 961         .halg = {
 962                  .digestsize = SHA1_DIGEST_SIZE,
 963                  .base = {
 964                           .cra_name = "sha1",
 965                           .cra_driver_name = "mv-sha1",
 966                           .cra_priority = 300,
 967                           .cra_flags =
 968                           CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
 969                           .cra_blocksize = SHA1_BLOCK_SIZE,
 970                           .cra_ctxsize = sizeof(struct mv_tfm_hash_ctx),
 971                           .cra_init = mv_cra_hash_sha1_init,
 972                           .cra_exit = mv_cra_hash_exit,
 973                           .cra_module = THIS_MODULE,
 974                           }
 975                  }
 976 };
 977
 978 struct ahash_alg mv_hmac_sha1_alg = {
 979         .init = mv_hash_init,
 980         .update = mv_hash_update,
 981         .final = mv_hash_final,
 982         .finup = mv_hash_finup,
 983         .digest = mv_hash_digest,
 984         .setkey = mv_hash_setkey,
 985         .halg = {
 986                  .digestsize = SHA1_DIGEST_SIZE,
 987                  .base = {
 988                           .cra_name = "hmac(sha1)",
 989                           .cra_driver_name = "mv-hmac-sha1",
 990                           .cra_priority = 300,
 991                           .cra_flags =
 992                           CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
 993                           .cra_blocksize = SHA1_BLOCK_SIZE,
 994                           .cra_ctxsize = sizeof(struct mv_tfm_hash_ctx),
 995                           .cra_init = mv_cra_hash_hmac_sha1_init,
 996                           .cra_exit = mv_cra_hash_exit,
 997                           .cra_module = THIS_MODULE,
 998                           }
 999                  }
1000 };
1001
1002 static int mv_probe(struct platform_device *pdev)
1003 {
1004         struct crypto_priv *cp;
1005         struct resource *res;
1006         int irq;
1007         int ret;
1008
1009         if (cpg) {
1010                 printk(KERN_ERR MV_CESA "Second crypto dev?\n");
1011                 return -EEXIST;
1012         }
1013
1014         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1015         if (!res)
1016                 return -ENXIO;
1017
1018         cp = kzalloc(sizeof(*cp), GFP_KERNEL);
1019         if (!cp)
1020                 return -ENOMEM;
1021
1022         spin_lock_init(&cp->lock);
1023         crypto_init_queue(&cp->queue, 50);
1024         cp->reg = ioremap(res->start, resource_size(res));
1025         if (!cp->reg) {
1026                 ret = -ENOMEM;
1027                 goto err;
1028         }
1029
1030         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
1031         if (!res) {
1032                 ret = -ENXIO;
1033                 goto err_unmap_reg;
1034         }
1035         cp->sram_size = resource_size(res);
1036         cp->max_req_size = cp->sram_size - SRAM_CFG_SPACE;
1037         cp->sram = ioremap(res->start, cp->sram_size);
1038         if (!cp->sram) {
1039                 ret = -ENOMEM;
1040                 goto err_unmap_reg;
1041         }
1042
1043         irq = platform_get_irq(pdev, 0);
1044         if (irq < 0 || irq == NO_IRQ) {
1045                 ret = irq;
1046                 goto err_unmap_sram;
1047         }
1048         cp->irq = irq;
1049
1050         platform_set_drvdata(pdev, cp);
1051         cpg = cp;
1052
1053         cp->queue_th = kthread_run(queue_manag, cp, "mv_crypto");
1054         if (IS_ERR(cp->queue_th)) {
1055                 ret = PTR_ERR(cp->queue_th);
1056                 goto err_unmap_sram;
1057         }
1058
1059         ret = request_irq(irq, crypto_int, IRQF_DISABLED, dev_name(&pdev->dev),
1060                         cp);
1061         if (ret)
1062                 goto err_thread;
1063
1064         writel(SEC_INT_ACCEL0_DONE, cpg->reg + SEC_ACCEL_INT_MASK);
1065         writel(SEC_CFG_STOP_DIG_ERR, cpg->reg + SEC_ACCEL_CFG);
1066
1067         ret = crypto_register_alg(&mv_aes_alg_ecb);
1068         if (ret)
1069                 goto err_irq;
1070
1071         ret = crypto_register_alg(&mv_aes_alg_cbc);
1072         if (ret)
1073                 goto err_unreg_ecb;
1074
1075         ret = crypto_register_ahash(&mv_sha1_alg);
1076         if (ret == 0)
1077                 cpg->has_sha1 = 1;
1078         else
1079                 printk(KERN_WARNING MV_CESA "Could not register sha1 driver\n");
1080
1081         ret = crypto_register_ahash(&mv_hmac_sha1_alg);
1082         if (ret == 0) {
1083                 cpg->has_hmac_sha1 = 1;
1084         } else {
1085                 printk(KERN_WARNING MV_CESA
1086                        "Could not register hmac-sha1 driver\n");
1087         }
1088
1089         return 0;
1090 err_unreg_ecb:
1091         crypto_unregister_alg(&mv_aes_alg_ecb);
1092 err_irq:
1093         free_irq(irq, cp);
1094 err_thread:
1095         kthread_stop(cp->queue_th);
1096 err_unmap_sram:
1097         iounmap(cp->sram);
1098 err_unmap_reg:
1099         iounmap(cp->reg);
1100 err:
1101         kfree(cp);
1102         cpg = NULL;
1103         platform_set_drvdata(pdev, NULL);
1104         return ret;
1105 }
1106
1107 static int mv_remove(struct platform_device *pdev)
1108 {
1109         struct crypto_priv *cp = platform_get_drvdata(pdev);
1110
1111         crypto_unregister_alg(&mv_aes_alg_ecb);
1112         crypto_unregister_alg(&mv_aes_alg_cbc);
1113         if (cp->has_sha1)
1114                 crypto_unregister_ahash(&mv_sha1_alg);
1115         if (cp->has_hmac_sha1)
1116                 crypto_unregister_ahash(&mv_hmac_sha1_alg);
1117         kthread_stop(cp->queue_th);
1118         free_irq(cp->irq, cp);
1119         memset(cp->sram, 0, cp->sram_size);
1120         iounmap(cp->sram);
1121         iounmap(cp->reg);
1122         kfree(cp);
1123         cpg = NULL;
1124         return 0;
1125 }
1126
1127 static struct platform_driver marvell_crypto = {
1128         .probe          = mv_probe,
1129         .remove         = mv_remove,
1130         .driver         = {
1131                 .owner  = THIS_MODULE,
1132                 .name   = "mv_crypto",
1133         },
1134 };
1135 MODULE_ALIAS("platform:mv_crypto");
1136
1137 static int __init mv_crypto_init(void)
1138 {
1139         return platform_driver_register(&marvell_crypto);
1140 }
1141 module_init(mv_crypto_init);
1142
1143 static void __exit mv_crypto_exit(void)
1144 {
1145         platform_driver_unregister(&marvell_crypto);
1146 }
1147 module_exit(mv_crypto_exit);
1148
1149 MODULE_AUTHOR("Sebastian Andrzej Siewior <sebastian@breakpoint.cc>");
1150 MODULE_DESCRIPTION("Support for Marvell's cryptographic engine");
1151 MODULE_LICENSE("GPL");