drivers/crypto/mv_cesa.c

   1 /*
   2  * Support for Marvell's crypto engine which can be found on some Orion5X
   3  * boards.
   4  *
   5  * Author: Sebastian Andrzej Siewior < sebastian at breakpoint dot cc >
   6  * License: GPLv2
   7  *
   8  */
   9 #include <crypto/aes.h>
  10 #include <crypto/algapi.h>
  11 #include <linux/crypto.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/kthread.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/scatterlist.h>
  17 #include <linux/slab.h>
  18 #include <crypto/internal/hash.h>
  19 #include <crypto/sha.h>
  20
  21 #include "mv_cesa.h"
  22
  23 #define MV_CESA "MV-CESA:"
  24 #define MAX_HW_HASH_SIZE        0xFFFF
  25
  26 /*
  27  * STM:
  28  *   /---------------------------------------\
  29  *   |                                       | request complete
  30  *  \./                                      |
  31  * IDLE -> new request -> BUSY -> done -> DEQUEUE
  32  *                         /°\               |
  33  *                          |                | more scatter entries
  34  *                          \________________/
  35  */
  36 enum engine_status {
  37         ENGINE_IDLE,
  38         ENGINE_BUSY,
  39         ENGINE_W_DEQUEUE,
  40 };
  41
  42 /**
  43  * struct req_progress - used for every crypt request
  44  * @src_sg_it:          sg iterator for src
  45  * @dst_sg_it:          sg iterator for dst
  46  * @sg_src_left:        bytes left in src to process (scatter list)
  47  * @src_start:          offset to add to src start position (scatter list)
  48  * @crypt_len:          length of current hw crypt/hash process
  49  * @hw_nbytes:          total bytes to process in hw for this request
  50  * @copy_back:          whether to copy data back (crypt) or not (hash)
  51  * @sg_dst_left:        bytes left dst to process in this scatter list
  52  * @dst_start:          offset to add to dst start position (scatter list)
  53  * @hw_processed_bytes: number of bytes processed by hw (request).
  54  *
  55  * sg helper are used to iterate over the scatterlist. Since the size of the
  56  * SRAM may be less than the scatter size, this struct struct is used to keep
  57  * track of progress within current scatterlist.
  58  */
  59 struct req_progress {
  60         struct sg_mapping_iter src_sg_it;
  61         struct sg_mapping_iter dst_sg_it;
  62         void (*complete) (void);
  63         void (*process) (int is_first);
  64
  65         /* src mostly */
  66         int sg_src_left;
  67         int src_start;
  68         int crypt_len;
  69         int hw_nbytes;
  70         /* dst mostly */
  71         int copy_back;
  72         int sg_dst_left;
  73         int dst_start;
  74         int hw_processed_bytes;
  75 };
  76
  77 struct crypto_priv {
  78         void __iomem *reg;
  79         void __iomem *sram;
  80         int irq;
  81         struct task_struct *queue_th;
  82
  83         /* the lock protects queue and eng_st */
  84         spinlock_t lock;
  85         struct crypto_queue queue;
  86         enum engine_status eng_st;
  87         struct crypto_async_request *cur_req;
  88         struct req_progress p;
  89         int max_req_size;
  90         int sram_size;
  91         int has_sha1;
  92         int has_hmac_sha1;
  93 };
  94
  95 static struct crypto_priv *cpg;
  96
  97 struct mv_ctx {
  98         u8 aes_enc_key[AES_KEY_LEN];
  99         u32 aes_dec_key[8];
 100         int key_len;
 101         u32 need_calc_aes_dkey;
 102 };
 103
 104 enum crypto_op {
 105         COP_AES_ECB,
 106         COP_AES_CBC,
 107 };
 108
 109 struct mv_req_ctx {
 110         enum crypto_op op;
 111         int decrypt;
 112 };
 113
 114 enum hash_op {
 115         COP_SHA1,
 116         COP_HMAC_SHA1
 117 };
 118
 119 struct mv_tfm_hash_ctx {
 120         struct crypto_shash *fallback;
 121         struct crypto_shash *base_hash;
 122         u32 ivs[2 * SHA1_DIGEST_SIZE / 4];
 123         int count_add;
 124         enum hash_op op;
 125 };
 126
 127 struct mv_req_hash_ctx {
 128         u64 count;
 129         u32 state[SHA1_DIGEST_SIZE / 4];
 130         u8 buffer[SHA1_BLOCK_SIZE];
 131         int first_hash;         /* marks that we don't have previous state */
 132         int last_chunk;         /* marks that this is the 'final' request */
 133         int extra_bytes;        /* unprocessed bytes in buffer */
 134         enum hash_op op;
 135         int count_add;
 136 };
 137
 138 static void compute_aes_dec_key(struct mv_ctx *ctx)
 139 {
 140         struct crypto_aes_ctx gen_aes_key;
 141         int key_pos;
 142
 143         if (!ctx->need_calc_aes_dkey)
 144                 return;
 145
 146         crypto_aes_expand_key(&gen_aes_key, ctx->aes_enc_key, ctx->key_len);
 147
 148         key_pos = ctx->key_len + 24;
 149         memcpy(ctx->aes_dec_key, &gen_aes_key.key_enc[key_pos], 4 * 4);
 150         switch (ctx->key_len) {
 151         case AES_KEYSIZE_256:
 152                 key_pos -= 2;
 153                 /* fall */
 154         case AES_KEYSIZE_192:
 155                 key_pos -= 2;
 156                 memcpy(&ctx->aes_dec_key[4], &gen_aes_key.key_enc[key_pos],
 157                                 4 * 4);
 158                 break;
 159         }
 160         ctx->need_calc_aes_dkey = 0;
 161 }
 162
 163 static int mv_setkey_aes(struct crypto_ablkcipher *cipher, const u8 *key,
 164                 unsigned int len)
 165 {
 166         struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
 167         struct mv_ctx *ctx = crypto_tfm_ctx(tfm);
 168
 169         switch (len) {
 170         case AES_KEYSIZE_128:
 171         case AES_KEYSIZE_192:
 172         case AES_KEYSIZE_256:
 173                 break;
 174         default:
 175                 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
 176                 return -EINVAL;
 177         }
 178         ctx->key_len = len;
 179         ctx->need_calc_aes_dkey = 1;
 180
 181         memcpy(ctx->aes_enc_key, key, AES_KEY_LEN);
 182         return 0;
 183 }
 184
 185 static void copy_src_to_buf(struct req_progress *p, char *dbuf, int len)
 186 {
 187         int ret;
 188         void *sbuf;
 189         int copy_len;
 190
 191         while (len) {
 192                 if (!p->sg_src_left) {
 193                         ret = sg_miter_next(&p->src_sg_it);
 194                         BUG_ON(!ret);
 195                         p->sg_src_left = p->src_sg_it.length;
 196                         p->src_start = 0;
 197                 }
 198
 199                 sbuf = p->src_sg_it.addr + p->src_start;
 200
 201                 copy_len = min(p->sg_src_left, len);
 202                 memcpy(dbuf, sbuf, copy_len);
 203
 204                 p->src_start += copy_len;
 205                 p->sg_src_left -= copy_len;
 206
 207                 len -= copy_len;
 208                 dbuf += copy_len;
 209         }
 210 }
 211
 212 static void setup_data_in(void)
 213 {
 214         struct req_progress *p = &cpg->p;
 215         int data_in_sram =
 216             min(p->hw_nbytes - p->hw_processed_bytes, cpg->max_req_size);
 217         copy_src_to_buf(p, cpg->sram + SRAM_DATA_IN_START + p->crypt_len,
 218                         data_in_sram - p->crypt_len);
 219         p->crypt_len = data_in_sram;
 220 }
 221
 222 static void mv_process_current_q(int first_block)
 223 {
 224         struct ablkcipher_request *req = ablkcipher_request_cast(cpg->cur_req);
 225         struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
 226         struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
 227         struct sec_accel_config op;
 228
 229         switch (req_ctx->op) {
 230         case COP_AES_ECB:
 231                 op.config = CFG_OP_CRYPT_ONLY | CFG_ENCM_AES | CFG_ENC_MODE_ECB;
 232                 break;
 233         case COP_AES_CBC:
 234         default:
 235                 op.config = CFG_OP_CRYPT_ONLY | CFG_ENCM_AES | CFG_ENC_MODE_CBC;
 236                 op.enc_iv = ENC_IV_POINT(SRAM_DATA_IV) |
 237                         ENC_IV_BUF_POINT(SRAM_DATA_IV_BUF);
 238                 if (first_block)
 239                         memcpy(cpg->sram + SRAM_DATA_IV, req->info, 16);
 240                 break;
 241         }
 242         if (req_ctx->decrypt) {
 243                 op.config |= CFG_DIR_DEC;
 244                 memcpy(cpg->sram + SRAM_DATA_KEY_P, ctx->aes_dec_key,
 245                                 AES_KEY_LEN);
 246         } else {
 247                 op.config |= CFG_DIR_ENC;
 248                 memcpy(cpg->sram + SRAM_DATA_KEY_P, ctx->aes_enc_key,
 249                                 AES_KEY_LEN);
 250         }
 251
 252         switch (ctx->key_len) {
 253         case AES_KEYSIZE_128:
 254                 op.config |= CFG_AES_LEN_128;
 255                 break;
 256         case AES_KEYSIZE_192:
 257                 op.config |= CFG_AES_LEN_192;
 258                 break;
 259         case AES_KEYSIZE_256:
 260                 op.config |= CFG_AES_LEN_256;
 261                 break;
 262         }
 263         op.enc_p = ENC_P_SRC(SRAM_DATA_IN_START) |
 264                 ENC_P_DST(SRAM_DATA_OUT_START);
 265         op.enc_key_p = SRAM_DATA_KEY_P;
 266
 267         setup_data_in();
 268         op.enc_len = cpg->p.crypt_len;
 269         memcpy(cpg->sram + SRAM_CONFIG, &op,
 270                         sizeof(struct sec_accel_config));
 271
 272         /* GO */
 273         writel(SEC_CMD_EN_SEC_ACCL0, cpg->reg + SEC_ACCEL_CMD);
 274
 275         /*
 276          * XXX: add timer if the interrupt does not occur for some mystery
 277          * reason
 278          */
 279 }
 280
 281 static void mv_crypto_algo_completion(void)
 282 {
 283         struct ablkcipher_request *req = ablkcipher_request_cast(cpg->cur_req);
 284         struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
 285
 286         sg_miter_stop(&cpg->p.src_sg_it);
 287         sg_miter_stop(&cpg->p.dst_sg_it);
 288
 289         if (req_ctx->op != COP_AES_CBC)
 290                 return ;
 291
 292         memcpy(req->info, cpg->sram + SRAM_DATA_IV_BUF, 16);
 293 }
 294
 295 static void mv_process_hash_current(int first_block)
 296 {
 297         struct ahash_request *req = ahash_request_cast(cpg->cur_req);
 298         const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
 299         struct mv_req_hash_ctx *req_ctx = ahash_request_ctx(req);
 300         struct req_progress *p = &cpg->p;
 301         struct sec_accel_config op = { 0 };
 302         int is_last;
 303
 304         switch (req_ctx->op) {
 305         case COP_SHA1:
 306         default:
 307                 op.config = CFG_OP_MAC_ONLY | CFG_MACM_SHA1;
 308                 break;
 309         case COP_HMAC_SHA1:
 310                 op.config = CFG_OP_MAC_ONLY | CFG_MACM_HMAC_SHA1;
 311                 memcpy(cpg->sram + SRAM_HMAC_IV_IN,
 312                                 tfm_ctx->ivs, sizeof(tfm_ctx->ivs));
 313                 break;
 314         }
 315
 316         op.mac_src_p =
 317                 MAC_SRC_DATA_P(SRAM_DATA_IN_START) | MAC_SRC_TOTAL_LEN((u32)
 318                 req_ctx->
 319                 count);
 320
 321         setup_data_in();
 322
 323         op.mac_digest =
 324                 MAC_DIGEST_P(SRAM_DIGEST_BUF) | MAC_FRAG_LEN(p->crypt_len);
 325         op.mac_iv =
 326                 MAC_INNER_IV_P(SRAM_HMAC_IV_IN) |
 327                 MAC_OUTER_IV_P(SRAM_HMAC_IV_OUT);
 328
 329         is_last = req_ctx->last_chunk
 330                 && (p->hw_processed_bytes + p->crypt_len >= p->hw_nbytes)
 331                 && (req_ctx->count <= MAX_HW_HASH_SIZE);
 332         if (req_ctx->first_hash) {
 333                 if (is_last)
 334                         op.config |= CFG_NOT_FRAG;
 335                 else
 336                         op.config |= CFG_FIRST_FRAG;
 337
 338                 req_ctx->first_hash = 0;
 339         } else {
 340                 if (is_last)
 341                         op.config |= CFG_LAST_FRAG;
 342                 else
 343                         op.config |= CFG_MID_FRAG;
 344
 345                 if (first_block) {
 346                         writel(req_ctx->state[0], cpg->reg + DIGEST_INITIAL_VAL_A);
 347                         writel(req_ctx->state[1], cpg->reg + DIGEST_INITIAL_VAL_B);
 348                         writel(req_ctx->state[2], cpg->reg + DIGEST_INITIAL_VAL_C);
 349                         writel(req_ctx->state[3], cpg->reg + DIGEST_INITIAL_VAL_D);
 350                         writel(req_ctx->state[4], cpg->reg + DIGEST_INITIAL_VAL_E);
 351                 }
 352         }
 353
 354         memcpy(cpg->sram + SRAM_CONFIG, &op, sizeof(struct sec_accel_config));
 355
 356         /* GO */
 357         writel(SEC_CMD_EN_SEC_ACCL0, cpg->reg + SEC_ACCEL_CMD);
 358
 359         /*
 360         * XXX: add timer if the interrupt does not occur for some mystery
 361         * reason
 362         */
 363 }
 364
 365 static inline int mv_hash_import_sha1_ctx(const struct mv_req_hash_ctx *ctx,
 366                                           struct shash_desc *desc)
 367 {
 368         int i;
 369         struct sha1_state shash_state;
 370
 371         shash_state.count = ctx->count + ctx->count_add;
 372         for (i = 0; i < 5; i++)
 373                 shash_state.state[i] = ctx->state[i];
 374         memcpy(shash_state.buffer, ctx->buffer, sizeof(shash_state.buffer));
 375         return crypto_shash_import(desc, &shash_state);
 376 }
 377
 378 static int mv_hash_final_fallback(struct ahash_request *req)
 379 {
 380         const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
 381         struct mv_req_hash_ctx *req_ctx = ahash_request_ctx(req);
 382         struct {
 383                 struct shash_desc shash;
 384                 char ctx[crypto_shash_descsize(tfm_ctx->fallback)];
 385         } desc;
 386         int rc;
 387
 388         desc.shash.tfm = tfm_ctx->fallback;
 389         desc.shash.flags = CRYPTO_TFM_REQ_MAY_SLEEP;
 390         if (unlikely(req_ctx->first_hash)) {
 391                 crypto_shash_init(&desc.shash);
 392                 crypto_shash_update(&desc.shash, req_ctx->buffer,
 393                                     req_ctx->extra_bytes);
 394         } else {
 395                 /* only SHA1 for now....
 396                  */
 397                 rc = mv_hash_import_sha1_ctx(req_ctx, &desc.shash);
 398                 if (rc)
 399                         goto out;
 400         }
 401         rc = crypto_shash_final(&desc.shash, req->result);
 402 out:
 403         return rc;
 404 }
 405
 406 static void mv_hash_algo_completion(void)
 407 {
 408         struct ahash_request *req = ahash_request_cast(cpg->cur_req);
 409         struct mv_req_hash_ctx *ctx = ahash_request_ctx(req);
 410
 411         if (ctx->extra_bytes)
 412                 copy_src_to_buf(&cpg->p, ctx->buffer, ctx->extra_bytes);
 413         sg_miter_stop(&cpg->p.src_sg_it);
 414
 415         if (likely(ctx->last_chunk)) {
 416                 if (likely(ctx->count <= MAX_HW_HASH_SIZE)) {
 417                         memcpy(req->result, cpg->sram + SRAM_DIGEST_BUF,
 418                                crypto_ahash_digestsize(crypto_ahash_reqtfm
 419                                                        (req)));
 420                 } else
 421                         mv_hash_final_fallback(req);
 422         } else {
 423                 ctx->state[0] = readl(cpg->reg + DIGEST_INITIAL_VAL_A);
 424                 ctx->state[1] = readl(cpg->reg + DIGEST_INITIAL_VAL_B);
 425                 ctx->state[2] = readl(cpg->reg + DIGEST_INITIAL_VAL_C);
 426                 ctx->state[3] = readl(cpg->reg + DIGEST_INITIAL_VAL_D);
 427                 ctx->state[4] = readl(cpg->reg + DIGEST_INITIAL_VAL_E);
 428         }
 429 }
 430
 431 static void dequeue_complete_req(void)
 432 {
 433         struct crypto_async_request *req = cpg->cur_req;
 434         void *buf;
 435         int ret;
 436         cpg->p.hw_processed_bytes += cpg->p.crypt_len;
 437         if (cpg->p.copy_back) {
 438                 int need_copy_len = cpg->p.crypt_len;
 439                 int sram_offset = 0;
 440                 do {
 441                         int dst_copy;
 442
 443                         if (!cpg->p.sg_dst_left) {
 444                                 ret = sg_miter_next(&cpg->p.dst_sg_it);
 445                                 BUG_ON(!ret);
 446                                 cpg->p.sg_dst_left = cpg->p.dst_sg_it.length;
 447                                 cpg->p.dst_start = 0;
 448                         }
 449
 450                         buf = cpg->p.dst_sg_it.addr;
 451                         buf += cpg->p.dst_start;
 452
 453                         dst_copy = min(need_copy_len, cpg->p.sg_dst_left);
 454
 455                         memcpy(buf,
 456                                cpg->sram + SRAM_DATA_OUT_START + sram_offset,
 457                                dst_copy);
 458                         sram_offset += dst_copy;
 459                         cpg->p.sg_dst_left -= dst_copy;
 460                         need_copy_len -= dst_copy;
 461                         cpg->p.dst_start += dst_copy;
 462                 } while (need_copy_len > 0);
 463         }
 464
 465         cpg->p.crypt_len = 0;
 466
 467         BUG_ON(cpg->eng_st != ENGINE_W_DEQUEUE);
 468         if (cpg->p.hw_processed_bytes < cpg->p.hw_nbytes) {
 469                 /* process next scatter list entry */
 470                 cpg->eng_st = ENGINE_BUSY;
 471                 cpg->p.process(0);
 472         } else {
 473                 cpg->p.complete();
 474                 cpg->eng_st = ENGINE_IDLE;
 475                 local_bh_disable();
 476                 req->complete(req, 0);
 477                 local_bh_enable();
 478         }
 479 }
 480
 481 static int count_sgs(struct scatterlist *sl, unsigned int total_bytes)
 482 {
 483         int i = 0;
 484         size_t cur_len;
 485
 486         while (sl) {
 487                 cur_len = sl[i].length;
 488                 ++i;
 489                 if (total_bytes > cur_len)
 490                         total_bytes -= cur_len;
 491                 else
 492                         break;
 493         }
 494
 495         return i;
 496 }
 497
 498 static void mv_start_new_crypt_req(struct ablkcipher_request *req)
 499 {
 500         struct req_progress *p = &cpg->p;
 501         int num_sgs;
 502
 503         cpg->cur_req = &req->base;
 504         memset(p, 0, sizeof(struct req_progress));
 505         p->hw_nbytes = req->nbytes;
 506         p->complete = mv_crypto_algo_completion;
 507         p->process = mv_process_current_q;
 508         p->copy_back = 1;
 509
 510         num_sgs = count_sgs(req->src, req->nbytes);
 511         sg_miter_start(&p->src_sg_it, req->src, num_sgs, SG_MITER_FROM_SG);
 512
 513         num_sgs = count_sgs(req->dst, req->nbytes);
 514         sg_miter_start(&p->dst_sg_it, req->dst, num_sgs, SG_MITER_TO_SG);
 515
 516         mv_process_current_q(1);
 517 }
 518
 519 static void mv_start_new_hash_req(struct ahash_request *req)
 520 {
 521         struct req_progress *p = &cpg->p;
 522         struct mv_req_hash_ctx *ctx = ahash_request_ctx(req);
 523         int num_sgs, hw_bytes, old_extra_bytes, rc;
 524         cpg->cur_req = &req->base;
 525         memset(p, 0, sizeof(struct req_progress));
 526         hw_bytes = req->nbytes + ctx->extra_bytes;
 527         old_extra_bytes = ctx->extra_bytes;
 528
 529         ctx->extra_bytes = hw_bytes % SHA1_BLOCK_SIZE;
 530         if (ctx->extra_bytes != 0
 531             && (!ctx->last_chunk || ctx->count > MAX_HW_HASH_SIZE))
 532                 hw_bytes -= ctx->extra_bytes;
 533         else
 534                 ctx->extra_bytes = 0;
 535
 536         num_sgs = count_sgs(req->src, req->nbytes);
 537         sg_miter_start(&p->src_sg_it, req->src, num_sgs, SG_MITER_FROM_SG);
 538
 539         if (hw_bytes) {
 540                 p->hw_nbytes = hw_bytes;
 541                 p->complete = mv_hash_algo_completion;
 542                 p->process = mv_process_hash_current;
 543
 544                 if (unlikely(old_extra_bytes)) {
 545                         memcpy(cpg->sram + SRAM_DATA_IN_START, ctx->buffer,
 546                                old_extra_bytes);
 547                         p->crypt_len = old_extra_bytes;
 548                 }
 549
 550                 mv_process_hash_current(1);
 551         } else {
 552                 copy_src_to_buf(p, ctx->buffer + old_extra_bytes,
 553                                 ctx->extra_bytes - old_extra_bytes);
 554                 sg_miter_stop(&p->src_sg_it);
 555                 if (ctx->last_chunk)
 556                         rc = mv_hash_final_fallback(req);
 557                 else
 558                         rc = 0;
 559                 cpg->eng_st = ENGINE_IDLE;
 560                 local_bh_disable();
 561                 req->base.complete(&req->base, rc);
 562                 local_bh_enable();
 563         }
 564 }
 565
 566 static int queue_manag(void *data)
 567 {
 568         cpg->eng_st = ENGINE_IDLE;
 569         do {
 570                 struct crypto_async_request *async_req = NULL;
 571                 struct crypto_async_request *backlog;
 572
 573                 __set_current_state(TASK_INTERRUPTIBLE);
 574
 575                 if (cpg->eng_st == ENGINE_W_DEQUEUE)
 576                         dequeue_complete_req();
 577
 578                 spin_lock_irq(&cpg->lock);
 579                 if (cpg->eng_st == ENGINE_IDLE) {
 580                         backlog = crypto_get_backlog(&cpg->queue);
 581                         async_req = crypto_dequeue_request(&cpg->queue);
 582                         if (async_req) {
 583                                 BUG_ON(cpg->eng_st != ENGINE_IDLE);
 584                                 cpg->eng_st = ENGINE_BUSY;
 585                         }
 586                 }
 587                 spin_unlock_irq(&cpg->lock);
 588
 589                 if (backlog) {
 590                         backlog->complete(backlog, -EINPROGRESS);
 591                         backlog = NULL;
 592                 }
 593
 594                 if (async_req) {
 595                         if (async_req->tfm->__crt_alg->cra_type !=
 596                             &crypto_ahash_type) {
 597                                 struct ablkcipher_request *req =
 598                                     ablkcipher_request_cast(async_req);
 599                                 mv_start_new_crypt_req(req);
 600                         } else {
 601                                 struct ahash_request *req =
 602                                     ahash_request_cast(async_req);
 603                                 mv_start_new_hash_req(req);
 604                         }
 605                         async_req = NULL;
 606                 }
 607
 608                 schedule();
 609
 610         } while (!kthread_should_stop());
 611         return 0;
 612 }
 613
 614 static int mv_handle_req(struct crypto_async_request *req)
 615 {
 616         unsigned long flags;
 617         int ret;
 618
 619         spin_lock_irqsave(&cpg->lock, flags);
 620         ret = crypto_enqueue_request(&cpg->queue, req);
 621         spin_unlock_irqrestore(&cpg->lock, flags);
 622         wake_up_process(cpg->queue_th);
 623         return ret;
 624 }
 625
 626 static int mv_enc_aes_ecb(struct ablkcipher_request *req)
 627 {
 628         struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
 629
 630         req_ctx->op = COP_AES_ECB;
 631         req_ctx->decrypt = 0;
 632
 633         return mv_handle_req(&req->base);
 634 }
 635
 636 static int mv_dec_aes_ecb(struct ablkcipher_request *req)
 637 {
 638         struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
 639         struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
 640
 641         req_ctx->op = COP_AES_ECB;
 642         req_ctx->decrypt = 1;
 643
 644         compute_aes_dec_key(ctx);
 645         return mv_handle_req(&req->base);
 646 }
 647
 648 static int mv_enc_aes_cbc(struct ablkcipher_request *req)
 649 {
 650         struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
 651
 652         req_ctx->op = COP_AES_CBC;
 653         req_ctx->decrypt = 0;
 654
 655         return mv_handle_req(&req->base);
 656 }
 657
 658 static int mv_dec_aes_cbc(struct ablkcipher_request *req)
 659 {
 660         struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
 661         struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
 662
 663         req_ctx->op = COP_AES_CBC;
 664         req_ctx->decrypt = 1;
 665
 666         compute_aes_dec_key(ctx);
 667         return mv_handle_req(&req->base);
 668 }
 669
 670 static int mv_cra_init(struct crypto_tfm *tfm)
 671 {
 672         tfm->crt_ablkcipher.reqsize = sizeof(struct mv_req_ctx);
 673         return 0;
 674 }
 675
 676 static void mv_init_hash_req_ctx(struct mv_req_hash_ctx *ctx, int op,
 677                                  int is_last, unsigned int req_len,
 678                                  int count_add)
 679 {
 680         memset(ctx, 0, sizeof(*ctx));
 681         ctx->op = op;
 682         ctx->count = req_len;
 683         ctx->first_hash = 1;
 684         ctx->last_chunk = is_last;
 685         ctx->count_add = count_add;
 686 }
 687
 688 static void mv_update_hash_req_ctx(struct mv_req_hash_ctx *ctx, int is_last,
 689                                    unsigned req_len)
 690 {
 691         ctx->last_chunk = is_last;
 692         ctx->count += req_len;
 693 }
 694
 695 static int mv_hash_init(struct ahash_request *req)
 696 {
 697         const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
 698         mv_init_hash_req_ctx(ahash_request_ctx(req), tfm_ctx->op, 0, 0,
 699                              tfm_ctx->count_add);
 700         return 0;
 701 }
 702
 703 static int mv_hash_update(struct ahash_request *req)
 704 {
 705         if (!req->nbytes)
 706                 return 0;
 707
 708         mv_update_hash_req_ctx(ahash_request_ctx(req), 0, req->nbytes);
 709         return mv_handle_req(&req->base);
 710 }
 711
 712 static int mv_hash_final(struct ahash_request *req)
 713 {
 714         struct mv_req_hash_ctx *ctx = ahash_request_ctx(req);
 715
 716         mv_update_hash_req_ctx(ctx, 1, 0);
 717         return mv_handle_req(&req->base);
 718 }
 719
 720 static int mv_hash_finup(struct ahash_request *req)
 721 {
 722         mv_update_hash_req_ctx(ahash_request_ctx(req), 1, req->nbytes);
 723         return mv_handle_req(&req->base);
 724 }
 725
 726 static int mv_hash_digest(struct ahash_request *req)
 727 {
 728         const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
 729         mv_init_hash_req_ctx(ahash_request_ctx(req), tfm_ctx->op, 1,
 730                              req->nbytes, tfm_ctx->count_add);
 731         return mv_handle_req(&req->base);
 732 }
 733
 734 static void mv_hash_init_ivs(struct mv_tfm_hash_ctx *ctx, const void *istate,
 735                              const void *ostate)
 736 {
 737         const struct sha1_state *isha1_state = istate, *osha1_state = ostate;
 738         int i;
 739         for (i = 0; i < 5; i++) {
 740                 ctx->ivs[i] = cpu_to_be32(isha1_state->state[i]);
 741                 ctx->ivs[i + 5] = cpu_to_be32(osha1_state->state[i]);
 742         }
 743 }
 744
 745 static int mv_hash_setkey(struct crypto_ahash *tfm, const u8 * key,
 746                           unsigned int keylen)
 747 {
 748         int rc;
 749         struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(&tfm->base);
 750         int bs, ds, ss;
 751
 752         if (!ctx->base_hash)
 753                 return 0;
 754
 755         rc = crypto_shash_setkey(ctx->fallback, key, keylen);
 756         if (rc)
 757                 return rc;
 758
 759         /* Can't see a way to extract the ipad/opad from the fallback tfm
 760            so I'm basically copying code from the hmac module */
 761         bs = crypto_shash_blocksize(ctx->base_hash);
 762         ds = crypto_shash_digestsize(ctx->base_hash);
 763         ss = crypto_shash_statesize(ctx->base_hash);
 764
 765         {
 766                 struct {
 767                         struct shash_desc shash;
 768                         char ctx[crypto_shash_descsize(ctx->base_hash)];
 769                 } desc;
 770                 unsigned int i;
 771                 char ipad[ss];
 772                 char opad[ss];
 773
 774                 desc.shash.tfm = ctx->base_hash;
 775                 desc.shash.flags = crypto_shash_get_flags(ctx->base_hash) &
 776                     CRYPTO_TFM_REQ_MAY_SLEEP;
 777
 778                 if (keylen > bs) {
 779                         int err;
 780
 781                         err =
 782                             crypto_shash_digest(&desc.shash, key, keylen, ipad);
 783                         if (err)
 784                                 return err;
 785
 786                         keylen = ds;
 787                 } else
 788                         memcpy(ipad, key, keylen);
 789
 790                 memset(ipad + keylen, 0, bs - keylen);
 791                 memcpy(opad, ipad, bs);
 792
 793                 for (i = 0; i < bs; i++) {
 794                         ipad[i] ^= 0x36;
 795                         opad[i] ^= 0x5c;
 796                 }
 797
 798                 rc = crypto_shash_init(&desc.shash) ? :
 799                     crypto_shash_update(&desc.shash, ipad, bs) ? :
 800                     crypto_shash_export(&desc.shash, ipad) ? :
 801                     crypto_shash_init(&desc.shash) ? :
 802                     crypto_shash_update(&desc.shash, opad, bs) ? :
 803                     crypto_shash_export(&desc.shash, opad);
 804
 805                 if (rc == 0)
 806                         mv_hash_init_ivs(ctx, ipad, opad);
 807
 808                 return rc;
 809         }
 810 }
 811
 812 static int mv_cra_hash_init(struct crypto_tfm *tfm, const char *base_hash_name,
 813                             enum hash_op op, int count_add)
 814 {
 815         const char *fallback_driver_name = tfm->__crt_alg->cra_name;
 816         struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(tfm);
 817         struct crypto_shash *fallback_tfm = NULL;
 818         struct crypto_shash *base_hash = NULL;
 819         int err = -ENOMEM;
 820
 821         ctx->op = op;
 822         ctx->count_add = count_add;
 823
 824         /* Allocate a fallback and abort if it failed. */
 825         fallback_tfm = crypto_alloc_shash(fallback_driver_name, 0,
 826                                           CRYPTO_ALG_NEED_FALLBACK);
 827         if (IS_ERR(fallback_tfm)) {
 828                 printk(KERN_WARNING MV_CESA
 829                        "Fallback driver '%s' could not be loaded!\n",
 830                        fallback_driver_name);
 831                 err = PTR_ERR(fallback_tfm);
 832                 goto out;
 833         }
 834         ctx->fallback = fallback_tfm;
 835
 836         if (base_hash_name) {
 837                 /* Allocate a hash to compute the ipad/opad of hmac. */
 838                 base_hash = crypto_alloc_shash(base_hash_name, 0,
 839                                                CRYPTO_ALG_NEED_FALLBACK);
 840                 if (IS_ERR(base_hash)) {
 841                         printk(KERN_WARNING MV_CESA
 842                                "Base driver '%s' could not be loaded!\n",
 843                                base_hash_name);
 844                         err = PTR_ERR(base_hash);
 845                         goto err_bad_base;
 846                 }
 847         }
 848         ctx->base_hash = base_hash;
 849
 850         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
 851                                  sizeof(struct mv_req_hash_ctx) +
 852                                  crypto_shash_descsize(ctx->fallback));
 853         return 0;
 854 err_bad_base:
 855         crypto_free_shash(fallback_tfm);
 856 out:
 857         return err;
 858 }
 859
 860 static void mv_cra_hash_exit(struct crypto_tfm *tfm)
 861 {
 862         struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(tfm);
 863
 864         crypto_free_shash(ctx->fallback);
 865         if (ctx->base_hash)
 866                 crypto_free_shash(ctx->base_hash);
 867 }
 868
 869 static int mv_cra_hash_sha1_init(struct crypto_tfm *tfm)
 870 {
 871         return mv_cra_hash_init(tfm, NULL, COP_SHA1, 0);
 872 }
 873
 874 static int mv_cra_hash_hmac_sha1_init(struct crypto_tfm *tfm)
 875 {
 876         return mv_cra_hash_init(tfm, "sha1", COP_HMAC_SHA1, SHA1_BLOCK_SIZE);
 877 }
 878
 879 irqreturn_t crypto_int(int irq, void *priv)
 880 {
 881         u32 val;
 882
 883         val = readl(cpg->reg + SEC_ACCEL_INT_STATUS);
 884         if (!(val & SEC_INT_ACCEL0_DONE))
 885                 return IRQ_NONE;
 886
 887         val &= ~SEC_INT_ACCEL0_DONE;
 888         writel(val, cpg->reg + FPGA_INT_STATUS);
 889         writel(val, cpg->reg + SEC_ACCEL_INT_STATUS);
 890         BUG_ON(cpg->eng_st != ENGINE_BUSY);
 891         cpg->eng_st = ENGINE_W_DEQUEUE;
 892         wake_up_process(cpg->queue_th);
 893         return IRQ_HANDLED;
 894 }
 895
 896 struct crypto_alg mv_aes_alg_ecb = {
 897         .cra_name               = "ecb(aes)",
 898         .cra_driver_name        = "mv-ecb-aes",
 899         .cra_priority   = 300,
 900         .cra_flags      = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
 901         .cra_blocksize  = 16,
 902         .cra_ctxsize    = sizeof(struct mv_ctx),
 903         .cra_alignmask  = 0,
 904         .cra_type       = &crypto_ablkcipher_type,
 905         .cra_module     = THIS_MODULE,
 906         .cra_init       = mv_cra_init,
 907         .cra_u          = {
 908                 .ablkcipher = {
 909                         .min_keysize    =       AES_MIN_KEY_SIZE,
 910                         .max_keysize    =       AES_MAX_KEY_SIZE,
 911                         .setkey         =       mv_setkey_aes,
 912                         .encrypt        =       mv_enc_aes_ecb,
 913                         .decrypt        =       mv_dec_aes_ecb,
 914                 },
 915         },
 916 };
 917
 918 struct crypto_alg mv_aes_alg_cbc = {
 919         .cra_name               = "cbc(aes)",
 920         .cra_driver_name        = "mv-cbc-aes",
 921         .cra_priority   = 300,
 922         .cra_flags      = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
 923         .cra_blocksize  = AES_BLOCK_SIZE,
 924         .cra_ctxsize    = sizeof(struct mv_ctx),
 925         .cra_alignmask  = 0,
 926         .cra_type       = &crypto_ablkcipher_type,
 927         .cra_module     = THIS_MODULE,
 928         .cra_init       = mv_cra_init,
 929         .cra_u          = {
 930                 .ablkcipher = {
 931                         .ivsize         =       AES_BLOCK_SIZE,
 932                         .min_keysize    =       AES_MIN_KEY_SIZE,
 933                         .max_keysize    =       AES_MAX_KEY_SIZE,
 934                         .setkey         =       mv_setkey_aes,
 935                         .encrypt        =       mv_enc_aes_cbc,
 936                         .decrypt        =       mv_dec_aes_cbc,
 937                 },
 938         },
 939 };
 940
 941 struct ahash_alg mv_sha1_alg = {
 942         .init = mv_hash_init,
 943         .update = mv_hash_update,
 944         .final = mv_hash_final,
 945         .finup = mv_hash_finup,
 946         .digest = mv_hash_digest,
 947         .halg = {
 948                  .digestsize = SHA1_DIGEST_SIZE,
 949                  .base = {
 950                           .cra_name = "sha1",
 951                           .cra_driver_name = "mv-sha1",
 952                           .cra_priority = 300,
 953                           .cra_flags =
 954                           CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
 955                           .cra_blocksize = SHA1_BLOCK_SIZE,
 956                           .cra_ctxsize = sizeof(struct mv_tfm_hash_ctx),
 957                           .cra_init = mv_cra_hash_sha1_init,
 958                           .cra_exit = mv_cra_hash_exit,
 959                           .cra_module = THIS_MODULE,
 960                           }
 961                  }
 962 };
 963
 964 struct ahash_alg mv_hmac_sha1_alg = {
 965         .init = mv_hash_init,
 966         .update = mv_hash_update,
 967         .final = mv_hash_final,
 968         .finup = mv_hash_finup,
 969         .digest = mv_hash_digest,
 970         .setkey = mv_hash_setkey,
 971         .halg = {
 972                  .digestsize = SHA1_DIGEST_SIZE,
 973                  .base = {
 974                           .cra_name = "hmac(sha1)",
 975                           .cra_driver_name = "mv-hmac-sha1",
 976                           .cra_priority = 300,
 977                           .cra_flags =
 978                           CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
 979                           .cra_blocksize = SHA1_BLOCK_SIZE,
 980                           .cra_ctxsize = sizeof(struct mv_tfm_hash_ctx),
 981                           .cra_init = mv_cra_hash_hmac_sha1_init,
 982                           .cra_exit = mv_cra_hash_exit,
 983                           .cra_module = THIS_MODULE,
 984                           }
 985                  }
 986 };
 987
 988 static int mv_probe(struct platform_device *pdev)
 989 {
 990         struct crypto_priv *cp;
 991         struct resource *res;
 992         int irq;
 993         int ret;
 994
 995         if (cpg) {
 996                 printk(KERN_ERR MV_CESA "Second crypto dev?\n");
 997                 return -EEXIST;
 998         }
 999
1000         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1001         if (!res)
1002                 return -ENXIO;
1003
1004         cp = kzalloc(sizeof(*cp), GFP_KERNEL);
1005         if (!cp)
1006                 return -ENOMEM;
1007
1008         spin_lock_init(&cp->lock);
1009         crypto_init_queue(&cp->queue, 50);
1010         cp->reg = ioremap(res->start, resource_size(res));
1011         if (!cp->reg) {
1012                 ret = -ENOMEM;
1013                 goto err;
1014         }
1015
1016         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
1017         if (!res) {
1018                 ret = -ENXIO;
1019                 goto err_unmap_reg;
1020         }
1021         cp->sram_size = resource_size(res);
1022         cp->max_req_size = cp->sram_size - SRAM_CFG_SPACE;
1023         cp->sram = ioremap(res->start, cp->sram_size);
1024         if (!cp->sram) {
1025                 ret = -ENOMEM;
1026                 goto err_unmap_reg;
1027         }
1028
1029         irq = platform_get_irq(pdev, 0);
1030         if (irq < 0 || irq == NO_IRQ) {
1031                 ret = irq;
1032                 goto err_unmap_sram;
1033         }
1034         cp->irq = irq;
1035
1036         platform_set_drvdata(pdev, cp);
1037         cpg = cp;
1038
1039         cp->queue_th = kthread_run(queue_manag, cp, "mv_crypto");
1040         if (IS_ERR(cp->queue_th)) {
1041                 ret = PTR_ERR(cp->queue_th);
1042                 goto err_unmap_sram;
1043         }
1044
1045         ret = request_irq(irq, crypto_int, IRQF_DISABLED, dev_name(&pdev->dev),
1046                         cp);
1047         if (ret)
1048                 goto err_thread;
1049
1050         writel(SEC_INT_ACCEL0_DONE, cpg->reg + SEC_ACCEL_INT_MASK);
1051         writel(SEC_CFG_STOP_DIG_ERR, cpg->reg + SEC_ACCEL_CFG);
1052         writel(SRAM_CONFIG, cpg->reg + SEC_ACCEL_DESC_P0);
1053
1054         ret = crypto_register_alg(&mv_aes_alg_ecb);
1055         if (ret) {
1056                 printk(KERN_WARNING MV_CESA
1057                        "Could not register aes-ecb driver\n");
1058                 goto err_irq;
1059         }
1060
1061         ret = crypto_register_alg(&mv_aes_alg_cbc);
1062         if (ret) {
1063                 printk(KERN_WARNING MV_CESA
1064                        "Could not register aes-cbc driver\n");
1065                 goto err_unreg_ecb;
1066         }
1067
1068         ret = crypto_register_ahash(&mv_sha1_alg);
1069         if (ret == 0)
1070                 cpg->has_sha1 = 1;
1071         else
1072                 printk(KERN_WARNING MV_CESA "Could not register sha1 driver\n");
1073
1074         ret = crypto_register_ahash(&mv_hmac_sha1_alg);
1075         if (ret == 0) {
1076                 cpg->has_hmac_sha1 = 1;
1077         } else {
1078                 printk(KERN_WARNING MV_CESA
1079                        "Could not register hmac-sha1 driver\n");
1080         }
1081
1082         return 0;
1083 err_unreg_ecb:
1084         crypto_unregister_alg(&mv_aes_alg_ecb);
1085 err_irq:
1086         free_irq(irq, cp);
1087 err_thread:
1088         kthread_stop(cp->queue_th);
1089 err_unmap_sram:
1090         iounmap(cp->sram);
1091 err_unmap_reg:
1092         iounmap(cp->reg);
1093 err:
1094         kfree(cp);
1095         cpg = NULL;
1096         platform_set_drvdata(pdev, NULL);
1097         return ret;
1098 }
1099
1100 static int mv_remove(struct platform_device *pdev)
1101 {
1102         struct crypto_priv *cp = platform_get_drvdata(pdev);
1103
1104         crypto_unregister_alg(&mv_aes_alg_ecb);
1105         crypto_unregister_alg(&mv_aes_alg_cbc);
1106         if (cp->has_sha1)
1107                 crypto_unregister_ahash(&mv_sha1_alg);
1108         if (cp->has_hmac_sha1)
1109                 crypto_unregister_ahash(&mv_hmac_sha1_alg);
1110         kthread_stop(cp->queue_th);
1111         free_irq(cp->irq, cp);
1112         memset(cp->sram, 0, cp->sram_size);
1113         iounmap(cp->sram);
1114         iounmap(cp->reg);
1115         kfree(cp);
1116         cpg = NULL;
1117         return 0;
1118 }
1119
1120 static struct platform_driver marvell_crypto = {
1121         .probe          = mv_probe,
1122         .remove         = mv_remove,
1123         .driver         = {
1124                 .owner  = THIS_MODULE,
1125                 .name   = "mv_crypto",
1126         },
1127 };
1128 MODULE_ALIAS("platform:mv_crypto");
1129
1130 static int __init mv_crypto_init(void)
1131 {
1132         return platform_driver_register(&marvell_crypto);
1133 }
1134 module_init(mv_crypto_init);
1135
1136 static void __exit mv_crypto_exit(void)
1137 {
1138         platform_driver_unregister(&marvell_crypto);
1139 }
1140 module_exit(mv_crypto_exit);
1141
1142 MODULE_AUTHOR("Sebastian Andrzej Siewior <sebastian@breakpoint.cc>");
1143 MODULE_DESCRIPTION("Support for Marvell's cryptographic engine");
1144 MODULE_LICENSE("GPL");