2 * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/mod_devicetable.h>
23 #include <linux/interrupt.h>
24 #include <linux/pci.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/highmem.h>
29 #include <linux/interrupt.h>
30 #include <linux/crypto.h>
32 #include <crypto/algapi.h>
33 #include <crypto/des.h>
35 #include <asm/kmap_types.h>
43 #define dprintk(f, a...) printk(f, ##a)
45 #define dprintk(f, a...) do {} while (0)
48 static atomic_t hifn_dev_number;
50 #define ACRYPTO_OP_DECRYPT 0
51 #define ACRYPTO_OP_ENCRYPT 1
52 #define ACRYPTO_OP_HMAC 2
53 #define ACRYPTO_OP_RNG 3
55 #define ACRYPTO_MODE_ECB 0
56 #define ACRYPTO_MODE_CBC 1
57 #define ACRYPTO_MODE_CFB 2
58 #define ACRYPTO_MODE_OFB 3
60 #define ACRYPTO_TYPE_AES_128 0
61 #define ACRYPTO_TYPE_AES_192 1
62 #define ACRYPTO_TYPE_AES_256 2
63 #define ACRYPTO_TYPE_3DES 3
64 #define ACRYPTO_TYPE_DES 4
66 #define PCI_VENDOR_ID_HIFN 0x13A3
67 #define PCI_DEVICE_ID_HIFN_7955 0x0020
68 #define PCI_DEVICE_ID_HIFN_7956 0x001d
70 /* I/O region sizes */
72 #define HIFN_BAR0_SIZE 0x1000
73 #define HIFN_BAR1_SIZE 0x2000
74 #define HIFN_BAR2_SIZE 0x8000
78 #define HIFN_DMA_CRA 0x0C /* DMA Command Ring Address */
79 #define HIFN_DMA_SDRA 0x1C /* DMA Source Data Ring Address */
80 #define HIFN_DMA_RRA 0x2C /* DMA Result Ring Address */
81 #define HIFN_DMA_DDRA 0x3C /* DMA Destination Data Ring Address */
82 #define HIFN_DMA_STCTL 0x40 /* DMA Status and Control */
83 #define HIFN_DMA_INTREN 0x44 /* DMA Interrupt Enable */
84 #define HIFN_DMA_CFG1 0x48 /* DMA Configuration #1 */
85 #define HIFN_DMA_CFG2 0x6C /* DMA Configuration #2 */
86 #define HIFN_CHIP_ID 0x98 /* Chip ID */
89 * Processing Unit Registers (offset from BASEREG0)
91 #define HIFN_0_PUDATA 0x00 /* Processing Unit Data */
92 #define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */
93 #define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */
94 #define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */
95 #define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */
96 #define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */
97 #define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */
98 #define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */
99 #define HIFN_0_SPACESIZE 0x20 /* Register space size */
101 /* Processing Unit Control Register (HIFN_0_PUCTRL) */
102 #define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */
103 #define HIFN_PUCTRL_STOP 0x0008 /* stop pu */
104 #define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */
105 #define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */
106 #define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */
108 /* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */
109 #define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */
110 #define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */
111 #define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
112 #define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
113 #define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */
114 #define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */
115 #define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */
116 #define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */
117 #define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */
118 #define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */
120 /* Processing Unit Configuration Register (HIFN_0_PUCNFG) */
121 #define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */
122 #define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */
123 #define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */
124 #define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */
125 #define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */
126 #define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */
127 #define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */
128 #define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */
129 #define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */
130 #define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */
131 #define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */
132 #define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */
133 #define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */
134 #define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */
135 #define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */
136 #define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */
137 #define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */
138 #define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */
139 #define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */
140 #define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */
141 #define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */
142 #define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */
143 #define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */
145 /* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */
146 #define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */
147 #define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */
148 #define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
149 #define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
150 #define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */
151 #define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */
152 #define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */
153 #define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */
154 #define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */
155 #define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */
157 /* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */
158 #define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */
159 #define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */
160 #define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
161 #define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
162 #define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */
163 #define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */
164 #define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */
165 #define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */
166 #define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */
167 #define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */
168 #define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */
169 #define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */
170 #define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */
171 #define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */
172 #define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */
173 #define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */
174 #define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */
176 /* FIFO Status Register (HIFN_0_FIFOSTAT) */
177 #define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */
178 #define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */
180 /* FIFO Configuration Register (HIFN_0_FIFOCNFG) */
181 #define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as 1 */
184 * DMA Interface Registers (offset from BASEREG1)
186 #define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */
187 #define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */
188 #define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */
189 #define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */
190 #define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */
191 #define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */
192 #define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */
193 #define HIFN_1_PLL 0x4c /* 795x: PLL config */
194 #define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */
195 #define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */
196 #define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */
197 #define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */
198 #define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */
199 #define HIFN_1_REVID 0x98 /* Revision ID */
200 #define HIFN_1_UNLOCK_SECRET1 0xf4
201 #define HIFN_1_UNLOCK_SECRET2 0xfc
202 #define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */
203 #define HIFN_1_PUB_BASE 0x300 /* Public Base Address */
204 #define HIFN_1_PUB_OPLEN 0x304 /* Public Operand Length */
205 #define HIFN_1_PUB_OP 0x308 /* Public Operand */
206 #define HIFN_1_PUB_STATUS 0x30c /* Public Status */
207 #define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */
208 #define HIFN_1_RNG_CONFIG 0x314 /* RNG config */
209 #define HIFN_1_RNG_DATA 0x318 /* RNG data */
210 #define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */
211 #define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */
213 /* DMA Status and Control Register (HIFN_1_DMA_CSR) */
214 #define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */
215 #define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */
216 #define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */
217 #define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */
218 #define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */
219 #define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */
220 #define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */
221 #define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */
222 #define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */
223 #define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */
224 #define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */
225 #define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */
226 #define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */
227 #define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */
228 #define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */
229 #define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */
230 #define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */
231 #define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */
232 #define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */
233 #define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */
234 #define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */
235 #define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */
236 #define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */
237 #define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */
238 #define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */
239 #define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */
240 #define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */
241 #define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */
242 #define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */
243 #define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */
244 #define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */
245 #define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */
246 #define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */
247 #define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */
248 #define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */
249 #define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */
250 #define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */
251 #define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */
253 /* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */
254 #define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */
255 #define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */
256 #define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */
257 #define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */
258 #define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */
259 #define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */
260 #define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */
261 #define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */
262 #define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */
263 #define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */
264 #define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */
265 #define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */
266 #define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */
267 #define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */
268 #define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */
269 #define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */
270 #define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */
271 #define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */
272 #define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */
273 #define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */
274 #define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */
275 #define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */
277 /* DMA Configuration Register (HIFN_1_DMA_CNFG) */
278 #define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */
279 #define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */
280 #define HIFN_DMACNFG_UNLOCK 0x00000800
281 #define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */
282 #define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */
283 #define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */
284 #define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */
285 #define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */
287 #define HIFN_PLL_7956 0x00001d18 /* 7956 PLL config value */
289 /* Public key reset register (HIFN_1_PUB_RESET) */
290 #define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */
292 /* Public base address register (HIFN_1_PUB_BASE) */
293 #define HIFN_PUBBASE_ADDR 0x00003fff /* base address */
295 /* Public operand length register (HIFN_1_PUB_OPLEN) */
296 #define HIFN_PUBOPLEN_MOD_M 0x0000007f /* modulus length mask */
297 #define HIFN_PUBOPLEN_MOD_S 0 /* modulus length shift */
298 #define HIFN_PUBOPLEN_EXP_M 0x0003ff80 /* exponent length mask */
299 #define HIFN_PUBOPLEN_EXP_S 7 /* exponent lenght shift */
300 #define HIFN_PUBOPLEN_RED_M 0x003c0000 /* reducend length mask */
301 #define HIFN_PUBOPLEN_RED_S 18 /* reducend length shift */
303 /* Public operation register (HIFN_1_PUB_OP) */
304 #define HIFN_PUBOP_AOFFSET_M 0x0000007f /* A offset mask */
305 #define HIFN_PUBOP_AOFFSET_S 0 /* A offset shift */
306 #define HIFN_PUBOP_BOFFSET_M 0x00000f80 /* B offset mask */
307 #define HIFN_PUBOP_BOFFSET_S 7 /* B offset shift */
308 #define HIFN_PUBOP_MOFFSET_M 0x0003f000 /* M offset mask */
309 #define HIFN_PUBOP_MOFFSET_S 12 /* M offset shift */
310 #define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */
311 #define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */
312 #define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */
313 #define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */
314 #define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */
315 #define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */
316 #define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */
317 #define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */
318 #define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */
319 #define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */
320 #define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */
321 #define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */
322 #define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular RED */
323 #define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular EXP */
325 /* Public status register (HIFN_1_PUB_STATUS) */
326 #define HIFN_PUBSTS_DONE 0x00000001 /* operation done */
327 #define HIFN_PUBSTS_CARRY 0x00000002 /* carry */
329 /* Public interrupt enable register (HIFN_1_PUB_IEN) */
330 #define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */
332 /* Random number generator config register (HIFN_1_RNG_CONFIG) */
333 #define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */
335 #define HIFN_NAMESIZE 32
336 #define HIFN_MAX_RESULT_ORDER 5
338 #define HIFN_D_CMD_RSIZE 24*4
339 #define HIFN_D_SRC_RSIZE 80*4
340 #define HIFN_D_DST_RSIZE 80*4
341 #define HIFN_D_RES_RSIZE 24*4
343 #define HIFN_QUEUE_LENGTH HIFN_D_CMD_RSIZE-5
345 #define AES_MIN_KEY_SIZE 16
346 #define AES_MAX_KEY_SIZE 32
348 #define HIFN_DES_KEY_LENGTH 8
349 #define HIFN_3DES_KEY_LENGTH 24
350 #define HIFN_MAX_CRYPT_KEY_LENGTH AES_MAX_KEY_SIZE
351 #define HIFN_IV_LENGTH 8
352 #define HIFN_AES_IV_LENGTH 16
353 #define HIFN_MAX_IV_LENGTH HIFN_AES_IV_LENGTH
355 #define HIFN_MAC_KEY_LENGTH 64
356 #define HIFN_MD5_LENGTH 16
357 #define HIFN_SHA1_LENGTH 20
358 #define HIFN_MAC_TRUNC_LENGTH 12
360 #define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260)
361 #define HIFN_MAX_RESULT (8 + 4 + 4 + 20 + 4)
362 #define HIFN_USED_RESULT 12
371 struct hifn_desc cmdr[HIFN_D_CMD_RSIZE+1];
372 struct hifn_desc srcr[HIFN_D_SRC_RSIZE+1];
373 struct hifn_desc dstr[HIFN_D_DST_RSIZE+1];
374 struct hifn_desc resr[HIFN_D_RES_RSIZE+1];
376 u8 command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND];
377 u8 result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT];
379 u64 test_src, test_dst;
382 * Our current positions for insertion and removal from the descriptor
385 volatile int cmdi, srci, dsti, resi;
386 volatile int cmdu, srcu, dstu, resu;
387 int cmdk, srck, dstk, resk;
390 #define HIFN_FLAG_CMD_BUSY (1<<0)
391 #define HIFN_FLAG_SRC_BUSY (1<<1)
392 #define HIFN_FLAG_DST_BUSY (1<<2)
393 #define HIFN_FLAG_RES_BUSY (1<<3)
394 #define HIFN_FLAG_OLD_KEY (1<<4)
396 #define HIFN_DEFAULT_ACTIVE_NUM 5
400 char name[HIFN_NAMESIZE];
404 struct pci_dev *pdev;
405 void __iomem *bar[3];
407 unsigned long result_mem;
415 void *sa[HIFN_D_RES_RSIZE];
423 struct delayed_work work;
425 unsigned long success;
426 unsigned long prev_success;
430 struct tasklet_struct tasklet;
432 struct crypto_queue queue;
433 struct list_head alg_list;
436 #define HIFN_D_LENGTH 0x0000ffff
437 #define HIFN_D_NOINVALID 0x01000000
438 #define HIFN_D_MASKDONEIRQ 0x02000000
439 #define HIFN_D_DESTOVER 0x04000000
440 #define HIFN_D_OVER 0x08000000
441 #define HIFN_D_LAST 0x20000000
442 #define HIFN_D_JUMP 0x40000000
443 #define HIFN_D_VALID 0x80000000
445 struct hifn_base_command
448 volatile u16 session_num;
449 volatile u16 total_source_count;
450 volatile u16 total_dest_count;
453 #define HIFN_BASE_CMD_COMP 0x0100 /* enable compression engine */
454 #define HIFN_BASE_CMD_PAD 0x0200 /* enable padding engine */
455 #define HIFN_BASE_CMD_MAC 0x0400 /* enable MAC engine */
456 #define HIFN_BASE_CMD_CRYPT 0x0800 /* enable crypt engine */
457 #define HIFN_BASE_CMD_DECODE 0x2000
458 #define HIFN_BASE_CMD_SRCLEN_M 0xc000
459 #define HIFN_BASE_CMD_SRCLEN_S 14
460 #define HIFN_BASE_CMD_DSTLEN_M 0x3000
461 #define HIFN_BASE_CMD_DSTLEN_S 12
462 #define HIFN_BASE_CMD_LENMASK_HI 0x30000
463 #define HIFN_BASE_CMD_LENMASK_LO 0x0ffff
466 * Structure to help build up the command data structure.
468 struct hifn_crypt_command
471 volatile u16 header_skip;
472 volatile u16 source_count;
473 volatile u16 reserved;
476 #define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */
477 #define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */
478 #define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */
479 #define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */
480 #define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */
481 #define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */
482 #define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */
483 #define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */
484 #define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */
485 #define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */
486 #define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */
487 #define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */
488 #define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */
489 #define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */
490 #define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */
491 #define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */
492 #define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */
493 #define HIFN_CRYPT_CMD_SRCLEN_M 0xc000
494 #define HIFN_CRYPT_CMD_SRCLEN_S 14
497 * Structure to help build up the command data structure.
499 struct hifn_mac_command
502 volatile u16 header_skip;
503 volatile u16 source_count;
504 volatile u16 reserved;
507 #define HIFN_MAC_CMD_ALG_MASK 0x0001
508 #define HIFN_MAC_CMD_ALG_SHA1 0x0000
509 #define HIFN_MAC_CMD_ALG_MD5 0x0001
510 #define HIFN_MAC_CMD_MODE_MASK 0x000c
511 #define HIFN_MAC_CMD_MODE_HMAC 0x0000
512 #define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004
513 #define HIFN_MAC_CMD_MODE_HASH 0x0008
514 #define HIFN_MAC_CMD_MODE_FULL 0x0004
515 #define HIFN_MAC_CMD_TRUNC 0x0010
516 #define HIFN_MAC_CMD_RESULT 0x0020
517 #define HIFN_MAC_CMD_APPEND 0x0040
518 #define HIFN_MAC_CMD_SRCLEN_M 0xc000
519 #define HIFN_MAC_CMD_SRCLEN_S 14
522 * MAC POS IPsec initiates authentication after encryption on encodes
523 * and before decryption on decodes.
525 #define HIFN_MAC_CMD_POS_IPSEC 0x0200
526 #define HIFN_MAC_CMD_NEW_KEY 0x0800
528 struct hifn_comp_command
531 volatile u16 header_skip;
532 volatile u16 source_count;
533 volatile u16 reserved;
536 #define HIFN_COMP_CMD_SRCLEN_M 0xc000
537 #define HIFN_COMP_CMD_SRCLEN_S 14
538 #define HIFN_COMP_CMD_ONE 0x0100 /* must be one */
539 #define HIFN_COMP_CMD_CLEARHIST 0x0010 /* clear history */
540 #define HIFN_COMP_CMD_UPDATEHIST 0x0008 /* update history */
541 #define HIFN_COMP_CMD_LZS_STRIP0 0x0004 /* LZS: strip zero */
542 #define HIFN_COMP_CMD_MPPC_RESTART 0x0004 /* MPPC: restart */
543 #define HIFN_COMP_CMD_ALG_MASK 0x0001 /* compression mode: */
544 #define HIFN_COMP_CMD_ALG_MPPC 0x0001 /* MPPC */
545 #define HIFN_COMP_CMD_ALG_LZS 0x0000 /* LZS */
547 struct hifn_base_result
550 volatile u16 session;
551 volatile u16 src_cnt; /* 15:0 of source count */
552 volatile u16 dst_cnt; /* 15:0 of dest count */
555 #define HIFN_BASE_RES_DSTOVERRUN 0x0200 /* destination overrun */
556 #define HIFN_BASE_RES_SRCLEN_M 0xc000 /* 17:16 of source count */
557 #define HIFN_BASE_RES_SRCLEN_S 14
558 #define HIFN_BASE_RES_DSTLEN_M 0x3000 /* 17:16 of dest count */
559 #define HIFN_BASE_RES_DSTLEN_S 12
561 struct hifn_comp_result
567 #define HIFN_COMP_RES_LCB_M 0xff00 /* longitudinal check byte */
568 #define HIFN_COMP_RES_LCB_S 8
569 #define HIFN_COMP_RES_RESTART 0x0004 /* MPPC: restart */
570 #define HIFN_COMP_RES_ENDMARKER 0x0002 /* LZS: end marker seen */
571 #define HIFN_COMP_RES_SRC_NOTZERO 0x0001 /* source expired */
573 struct hifn_mac_result
576 volatile u16 reserved;
577 /* followed by 0, 6, 8, or 10 u16's of the MAC, then crypt */
580 #define HIFN_MAC_RES_MISCOMPARE 0x0002 /* compare failed */
581 #define HIFN_MAC_RES_SRC_NOTZERO 0x0001 /* source expired */
583 struct hifn_crypt_result
586 volatile u16 reserved;
589 #define HIFN_CRYPT_RES_SRC_NOTZERO 0x0001 /* source expired */
591 #ifndef HIFN_POLL_FREQUENCY
592 #define HIFN_POLL_FREQUENCY 0x1
595 #ifndef HIFN_POLL_SCALAR
596 #define HIFN_POLL_SCALAR 0x0
599 #define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */
600 #define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */
602 struct hifn_crypto_alg
604 struct list_head entry;
605 struct crypto_alg alg;
606 struct hifn_device *dev;
609 #define ASYNC_SCATTERLIST_CACHE 16
611 #define ASYNC_FLAGS_MISALIGNED (1<<0)
613 struct ablkcipher_walk
615 struct scatterlist cache[ASYNC_SCATTERLIST_CACHE];
622 u8 key[HIFN_MAX_CRYPT_KEY_LENGTH], *iv;
623 struct hifn_device *dev;
624 unsigned int keysize, ivsize;
625 u8 op, type, mode, unused;
626 struct ablkcipher_walk walk;
630 #define crypto_alg_to_hifn(alg) container_of(alg, struct hifn_crypto_alg, alg)
632 static inline u32 hifn_read_0(struct hifn_device *dev, u32 reg)
636 ret = readl((char *)(dev->bar[0]) + reg);
641 static inline u32 hifn_read_1(struct hifn_device *dev, u32 reg)
645 ret = readl((char *)(dev->bar[1]) + reg);
650 static inline void hifn_write_0(struct hifn_device *dev, u32 reg, u32 val)
652 writel(val, (char *)(dev->bar[0]) + reg);
655 static inline void hifn_write_1(struct hifn_device *dev, u32 reg, u32 val)
657 writel(val, (char *)(dev->bar[1]) + reg);
660 static void hifn_wait_puc(struct hifn_device *dev)
665 for (i=10000; i > 0; --i) {
666 ret = hifn_read_0(dev, HIFN_0_PUCTRL);
667 if (!(ret & HIFN_PUCTRL_RESET))
674 dprintk("%s: Failed to reset PUC unit.\n", dev->name);
677 static void hifn_reset_puc(struct hifn_device *dev)
679 hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
683 static void hifn_stop_device(struct hifn_device *dev)
685 hifn_write_1(dev, HIFN_1_DMA_CSR,
686 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
687 HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS);
688 hifn_write_0(dev, HIFN_0_PUIER, 0);
689 hifn_write_1(dev, HIFN_1_DMA_IER, 0);
692 static void hifn_reset_dma(struct hifn_device *dev, int full)
694 hifn_stop_device(dev);
697 * Setting poll frequency and others to 0.
699 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
700 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
707 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE);
710 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE |
711 HIFN_DMACNFG_MSTRESET);
715 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
716 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
721 static u32 hifn_next_signature(u_int32_t a, u_int cnt)
726 for (i = 0; i < cnt; i++) {
736 a = (v & 1) ^ (a << 1);
742 static struct pci2id {
749 PCI_DEVICE_ID_HIFN_7955,
750 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
751 0x00, 0x00, 0x00, 0x00, 0x00 }
755 PCI_DEVICE_ID_HIFN_7956,
756 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
757 0x00, 0x00, 0x00, 0x00, 0x00 }
761 static int hifn_init_pubrng(struct hifn_device *dev)
765 hifn_write_1(dev, HIFN_1_PUB_RESET, hifn_read_1(dev, HIFN_1_PUB_RESET) |
768 for (i=100; i > 0; --i) {
771 if ((hifn_read_1(dev, HIFN_1_PUB_RESET) & HIFN_PUBRST_RESET) == 0)
776 dprintk("Chip %s: Failed to initialise public key engine.\n",
779 hifn_write_1(dev, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);
780 dev->dmareg |= HIFN_DMAIER_PUBDONE;
781 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
783 dprintk("Chip %s: Public key engine has been sucessfully "
784 "initialised.\n", dev->name);
791 hifn_write_1(dev, HIFN_1_RNG_CONFIG,
792 hifn_read_1(dev, HIFN_1_RNG_CONFIG) | HIFN_RNGCFG_ENA);
793 dprintk("Chip %s: RNG engine has been successfully initialised.\n",
799 static int hifn_enable_crypto(struct hifn_device *dev)
805 for (i = 0; i < sizeof(pci2id)/sizeof(pci2id[0]); i++) {
806 if (pci2id[i].pci_vendor == dev->pdev->vendor &&
807 pci2id[i].pci_prod == dev->pdev->device) {
808 offtbl = pci2id[i].card_id;
813 if (offtbl == NULL) {
814 dprintk("Chip %s: Unknown card!\n", dev->name);
818 dmacfg = hifn_read_1(dev, HIFN_1_DMA_CNFG);
820 hifn_write_1(dev, HIFN_1_DMA_CNFG,
821 HIFN_DMACNFG_UNLOCK | HIFN_DMACNFG_MSTRESET |
822 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
824 addr = hifn_read_1(dev, HIFN_1_UNLOCK_SECRET1);
826 hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, 0);
829 for (i=0; i<12; ++i) {
830 addr = hifn_next_signature(addr, offtbl[i] + 0x101);
831 hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, addr);
835 hifn_write_1(dev, HIFN_1_DMA_CNFG, dmacfg);
837 dprintk("Chip %s: %s.\n", dev->name, pci_name(dev->pdev));
842 static void hifn_init_dma(struct hifn_device *dev)
844 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
845 u32 dptr = dev->desc_dma;
848 for (i=0; i<HIFN_D_CMD_RSIZE; ++i)
849 dma->cmdr[i].p = __cpu_to_le32(dptr +
850 offsetof(struct hifn_dma, command_bufs[i][0]));
851 for (i=0; i<HIFN_D_RES_RSIZE; ++i)
852 dma->resr[i].p = __cpu_to_le32(dptr +
853 offsetof(struct hifn_dma, result_bufs[i][0]));
856 * Setup LAST descriptors.
858 dma->cmdr[HIFN_D_CMD_RSIZE].p = __cpu_to_le32(dptr +
859 offsetof(struct hifn_dma, cmdr[0]));
860 dma->srcr[HIFN_D_SRC_RSIZE].p = __cpu_to_le32(dptr +
861 offsetof(struct hifn_dma, srcr[0]));
862 dma->dstr[HIFN_D_DST_RSIZE].p = __cpu_to_le32(dptr +
863 offsetof(struct hifn_dma, dstr[0]));
864 dma->resr[HIFN_D_RES_RSIZE].p = __cpu_to_le32(dptr +
865 offsetof(struct hifn_dma, resr[0]));
867 dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0;
868 dma->cmdi = dma->srci = dma->dsti = dma->resi = 0;
869 dma->cmdk = dma->srck = dma->dstk = dma->resk = 0;
872 static void hifn_init_registers(struct hifn_device *dev)
874 u32 dptr = dev->desc_dma;
876 /* Initialization magic... */
877 hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
878 hifn_write_0(dev, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD);
879 hifn_write_0(dev, HIFN_0_PUIER, HIFN_PUIER_DSTOVER);
881 /* write all 4 ring address registers */
882 hifn_write_1(dev, HIFN_1_DMA_CRAR, __cpu_to_le32(dptr +
883 offsetof(struct hifn_dma, cmdr[0])));
884 hifn_write_1(dev, HIFN_1_DMA_SRAR, __cpu_to_le32(dptr +
885 offsetof(struct hifn_dma, srcr[0])));
886 hifn_write_1(dev, HIFN_1_DMA_DRAR, __cpu_to_le32(dptr +
887 offsetof(struct hifn_dma, dstr[0])));
888 hifn_write_1(dev, HIFN_1_DMA_RRAR, __cpu_to_le32(dptr +
889 offsetof(struct hifn_dma, resr[0])));
893 hifn_write_1(dev, HIFN_1_DMA_CSR,
894 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
895 HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS |
896 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
897 HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
898 HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
899 HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
900 HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
902 HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
905 HIFN_DMACSR_PUBDONE);
907 hifn_write_1(dev, HIFN_1_DMA_CSR,
908 HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
909 HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA |
910 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
911 HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
912 HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
913 HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
914 HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
916 HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
919 HIFN_DMACSR_PUBDONE);
921 hifn_read_1(dev, HIFN_1_DMA_CSR);
923 dev->dmareg |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT |
924 HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER |
925 HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT |
927 dev->dmareg &= ~HIFN_DMAIER_C_WAIT;
929 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
930 hifn_read_1(dev, HIFN_1_DMA_IER);
932 hifn_write_0(dev, HIFN_0_PUCNFG, HIFN_PUCNFG_ENCCNFG |
933 HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES |
934 HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 |
937 hifn_write_0(dev, HIFN_0_PUCNFG, 0x10342);
939 hifn_write_1(dev, HIFN_1_PLL, HIFN_PLL_7956);
941 hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
942 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
943 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST |
944 ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) |
945 ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL));
948 static int hifn_setup_base_command(struct hifn_device *dev, u8 *buf,
949 unsigned dlen, unsigned slen, u16 mask, u8 snum)
951 struct hifn_base_command *base_cmd;
954 base_cmd = (struct hifn_base_command *)buf_pos;
955 base_cmd->masks = __cpu_to_le16(mask);
956 base_cmd->total_source_count =
957 __cpu_to_le16(slen & HIFN_BASE_CMD_LENMASK_LO);
958 base_cmd->total_dest_count =
959 __cpu_to_le16(dlen & HIFN_BASE_CMD_LENMASK_LO);
963 base_cmd->session_num = __cpu_to_le16(snum |
964 ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) |
965 ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M));
967 return sizeof(struct hifn_base_command);
970 static int hifn_setup_crypto_command(struct hifn_device *dev,
971 u8 *buf, unsigned dlen, unsigned slen,
972 u8 *key, int keylen, u8 *iv, int ivsize, u16 mode)
974 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
975 struct hifn_crypt_command *cry_cmd;
979 cry_cmd = (struct hifn_crypt_command *)buf_pos;
981 cry_cmd->source_count = __cpu_to_le16(dlen & 0xffff);
983 cry_cmd->masks = __cpu_to_le16(mode |
984 ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) &
985 HIFN_CRYPT_CMD_SRCLEN_M));
986 cry_cmd->header_skip = 0;
987 cry_cmd->reserved = 0;
989 buf_pos += sizeof(struct hifn_crypt_command);
993 dev->dmareg |= HIFN_DMAIER_C_WAIT;
994 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
998 memcpy(buf_pos, key, keylen);
1002 memcpy(buf_pos, iv, ivsize);
1006 cmd_len = buf_pos - buf;
1011 static int hifn_setup_src_desc(struct hifn_device *dev, struct page *page,
1012 unsigned int offset, unsigned int size)
1014 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1018 addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_TODEVICE);
1022 dma->srcr[idx].p = __cpu_to_le32(addr);
1023 dma->srcr[idx].l = __cpu_to_le32(size) | HIFN_D_VALID |
1024 HIFN_D_MASKDONEIRQ | HIFN_D_NOINVALID | HIFN_D_LAST;
1026 if (++idx == HIFN_D_SRC_RSIZE) {
1027 dma->srcr[idx].l = __cpu_to_le32(HIFN_D_VALID |
1029 HIFN_D_MASKDONEIRQ | HIFN_D_LAST);
1036 if (!(dev->flags & HIFN_FLAG_SRC_BUSY)) {
1037 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA);
1038 dev->flags |= HIFN_FLAG_SRC_BUSY;
1044 static void hifn_setup_res_desc(struct hifn_device *dev)
1046 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1048 dma->resr[dma->resi].l = __cpu_to_le32(HIFN_USED_RESULT |
1049 HIFN_D_VALID | HIFN_D_LAST);
1051 * dma->resr[dma->resi].l = __cpu_to_le32(HIFN_MAX_RESULT | HIFN_D_VALID |
1052 * HIFN_D_LAST | HIFN_D_NOINVALID);
1055 if (++dma->resi == HIFN_D_RES_RSIZE) {
1056 dma->resr[HIFN_D_RES_RSIZE].l = __cpu_to_le32(HIFN_D_VALID |
1057 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ | HIFN_D_LAST);
1063 if (!(dev->flags & HIFN_FLAG_RES_BUSY)) {
1064 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA);
1065 dev->flags |= HIFN_FLAG_RES_BUSY;
1069 static void hifn_setup_dst_desc(struct hifn_device *dev, struct page *page,
1070 unsigned offset, unsigned size)
1072 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1076 addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_FROMDEVICE);
1079 dma->dstr[idx].p = __cpu_to_le32(addr);
1080 dma->dstr[idx].l = __cpu_to_le32(size | HIFN_D_VALID |
1081 HIFN_D_MASKDONEIRQ | HIFN_D_NOINVALID | HIFN_D_LAST);
1083 if (++idx == HIFN_D_DST_RSIZE) {
1084 dma->dstr[idx].l = __cpu_to_le32(HIFN_D_VALID |
1085 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ |
1086 HIFN_D_LAST | HIFN_D_NOINVALID);
1092 if (!(dev->flags & HIFN_FLAG_DST_BUSY)) {
1093 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA);
1094 dev->flags |= HIFN_FLAG_DST_BUSY;
1098 static int hifn_setup_dma(struct hifn_device *dev, struct page *spage, unsigned int soff,
1099 struct page *dpage, unsigned int doff, unsigned int nbytes, void *priv,
1100 struct hifn_context *ctx)
1102 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1103 int cmd_len, sa_idx;
1107 dprintk("%s: spage: %p, soffset: %u, dpage: %p, doffset: %u, nbytes: %u, priv: %p, ctx: %p.\n",
1108 dev->name, spage, soff, dpage, doff, nbytes, priv, ctx);
1112 hifn_setup_src_desc(dev, spage, soff, nbytes);
1114 buf_pos = buf = dma->command_bufs[dma->cmdi];
1118 case ACRYPTO_OP_DECRYPT:
1119 mask = HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE;
1121 case ACRYPTO_OP_ENCRYPT:
1122 mask = HIFN_BASE_CMD_CRYPT;
1124 case ACRYPTO_OP_HMAC:
1125 mask = HIFN_BASE_CMD_MAC;
1131 buf_pos += hifn_setup_base_command(dev, buf_pos, nbytes,
1132 nbytes, mask, dev->snum);
1134 if (ctx->op == ACRYPTO_OP_ENCRYPT || ctx->op == ACRYPTO_OP_DECRYPT) {
1138 md |= HIFN_CRYPT_CMD_NEW_KEY;
1139 if (ctx->iv && ctx->mode != ACRYPTO_MODE_ECB)
1140 md |= HIFN_CRYPT_CMD_NEW_IV;
1142 switch (ctx->mode) {
1143 case ACRYPTO_MODE_ECB:
1144 md |= HIFN_CRYPT_CMD_MODE_ECB;
1146 case ACRYPTO_MODE_CBC:
1147 md |= HIFN_CRYPT_CMD_MODE_CBC;
1149 case ACRYPTO_MODE_CFB:
1150 md |= HIFN_CRYPT_CMD_MODE_CFB;
1152 case ACRYPTO_MODE_OFB:
1153 md |= HIFN_CRYPT_CMD_MODE_OFB;
1159 switch (ctx->type) {
1160 case ACRYPTO_TYPE_AES_128:
1161 if (ctx->keysize != 16)
1163 md |= HIFN_CRYPT_CMD_KSZ_128 |
1164 HIFN_CRYPT_CMD_ALG_AES;
1166 case ACRYPTO_TYPE_AES_192:
1167 if (ctx->keysize != 24)
1169 md |= HIFN_CRYPT_CMD_KSZ_192 |
1170 HIFN_CRYPT_CMD_ALG_AES;
1172 case ACRYPTO_TYPE_AES_256:
1173 if (ctx->keysize != 32)
1175 md |= HIFN_CRYPT_CMD_KSZ_256 |
1176 HIFN_CRYPT_CMD_ALG_AES;
1178 case ACRYPTO_TYPE_3DES:
1179 if (ctx->keysize != 24)
1181 md |= HIFN_CRYPT_CMD_ALG_3DES;
1183 case ACRYPTO_TYPE_DES:
1184 if (ctx->keysize != 8)
1186 md |= HIFN_CRYPT_CMD_ALG_DES;
1192 buf_pos += hifn_setup_crypto_command(dev, buf_pos,
1193 nbytes, nbytes, ctx->key, ctx->keysize,
1194 ctx->iv, ctx->ivsize, md);
1197 dev->sa[sa_idx] = priv;
1199 cmd_len = buf_pos - buf;
1200 dma->cmdr[dma->cmdi].l = __cpu_to_le32(cmd_len | HIFN_D_VALID |
1201 HIFN_D_LAST | HIFN_D_MASKDONEIRQ);
1203 if (++dma->cmdi == HIFN_D_CMD_RSIZE) {
1204 dma->cmdr[dma->cmdi].l = __cpu_to_le32(HIFN_MAX_COMMAND |
1205 HIFN_D_VALID | HIFN_D_LAST |
1206 HIFN_D_MASKDONEIRQ | HIFN_D_JUMP);
1209 dma->cmdr[dma->cmdi-1].l |= __cpu_to_le32(HIFN_D_VALID);
1211 if (!(dev->flags & HIFN_FLAG_CMD_BUSY)) {
1212 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA);
1213 dev->flags |= HIFN_FLAG_CMD_BUSY;
1216 hifn_setup_dst_desc(dev, dpage, doff, nbytes);
1217 hifn_setup_res_desc(dev);
1225 static int ablkcipher_walk_init(struct ablkcipher_walk *w,
1226 int num, gfp_t gfp_flags)
1230 num = min(ASYNC_SCATTERLIST_CACHE, num);
1231 sg_init_table(w->cache, num);
1234 for (i=0; i<num; ++i) {
1235 struct page *page = alloc_page(gfp_flags);
1236 struct scatterlist *s;
1243 sg_set_page(s, page, PAGE_SIZE, 0);
1250 static void ablkcipher_walk_exit(struct ablkcipher_walk *w)
1254 for (i=0; i<w->num; ++i) {
1255 struct scatterlist *s = &w->cache[i];
1257 __free_page(sg_page(s));
1265 static int ablkcipher_add(void *daddr, unsigned int *drestp, struct scatterlist *src,
1266 unsigned int size, unsigned int *nbytesp)
1268 unsigned int copy, drest = *drestp, nbytes = *nbytesp;
1272 if (drest < size || size > nbytes)
1276 copy = min(drest, src->length);
1278 saddr = kmap_atomic(sg_page(src), KM_SOFTIRQ1);
1279 memcpy(daddr, saddr + src->offset, copy);
1280 kunmap_atomic(saddr, KM_SOFTIRQ1);
1287 dprintk("%s: copy: %u, size: %u, drest: %u, nbytes: %u.\n",
1288 __func__, copy, size, drest, nbytes);
1300 static int ablkcipher_walk(struct ablkcipher_request *req,
1301 struct ablkcipher_walk *w)
1303 unsigned blocksize =
1304 crypto_ablkcipher_blocksize(crypto_ablkcipher_reqtfm(req));
1305 unsigned alignmask =
1306 crypto_ablkcipher_alignmask(crypto_ablkcipher_reqtfm(req));
1307 struct scatterlist *src, *dst, *t;
1309 unsigned int nbytes = req->nbytes, offset, copy, diff;
1315 if (idx >= w->num && (w->flags & ASYNC_FLAGS_MISALIGNED))
1318 src = &req->src[idx];
1319 dst = &req->dst[idx];
1321 dprintk("\n%s: slen: %u, dlen: %u, soff: %u, doff: %u, offset: %u, "
1322 "blocksize: %u, nbytes: %u.\n",
1323 __func__, src->length, dst->length, src->offset,
1324 dst->offset, offset, blocksize, nbytes);
1326 if (src->length & (blocksize - 1) ||
1327 src->offset & (alignmask - 1) ||
1328 dst->length & (blocksize - 1) ||
1329 dst->offset & (alignmask - 1) ||
1331 unsigned slen = src->length - offset;
1332 unsigned dlen = PAGE_SIZE;
1336 daddr = kmap_atomic(sg_page(t), KM_SOFTIRQ0);
1337 err = ablkcipher_add(daddr, &dlen, src, slen, &nbytes);
1343 copy = slen & ~(blocksize - 1);
1344 diff = slen & (blocksize - 1);
1346 if (dlen < nbytes) {
1348 * Destination page does not have enough space
1349 * to put there additional blocksized chunk,
1350 * so we mark that page as containing only
1351 * blocksize aligned chunks:
1352 * t->length = (slen & ~(blocksize - 1));
1353 * and increase number of bytes to be processed
1360 * Temporary of course...
1361 * Kick author if you will catch this one.
1363 printk(KERN_ERR "%s: dlen: %u, nbytes: %u,"
1364 "slen: %u, offset: %u.\n",
1365 __func__, dlen, nbytes, slen, offset);
1366 printk(KERN_ERR "%s: please contact author to fix this "
1367 "issue, generally you should not catch "
1368 "this path under any condition but who "
1369 "knows how did you use crypto code.\n"
1370 "Thank you.\n", __func__);
1373 copy += diff + nbytes;
1375 src = &req->src[idx];
1377 err = ablkcipher_add(daddr + slen, &dlen, src, nbytes, &nbytes);
1387 kunmap_atomic(daddr, KM_SOFTIRQ0);
1389 nbytes -= src->length;
1399 kunmap_atomic(daddr, KM_SOFTIRQ0);
1403 static int hifn_setup_session(struct ablkcipher_request *req)
1405 struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
1406 struct hifn_device *dev = ctx->dev;
1407 struct page *spage, *dpage;
1408 unsigned long soff, doff, flags;
1409 unsigned int nbytes = req->nbytes, idx = 0, len;
1410 int err = -EINVAL, sg_num;
1411 struct scatterlist *src, *dst, *t;
1412 unsigned blocksize =
1413 crypto_ablkcipher_blocksize(crypto_ablkcipher_reqtfm(req));
1414 unsigned alignmask =
1415 crypto_ablkcipher_alignmask(crypto_ablkcipher_reqtfm(req));
1417 if (ctx->iv && !ctx->ivsize && ctx->mode != ACRYPTO_MODE_ECB)
1420 ctx->walk.flags = 0;
1423 src = &req->src[idx];
1424 dst = &req->dst[idx];
1426 if (src->length & (blocksize - 1) ||
1427 src->offset & (alignmask - 1) ||
1428 dst->length & (blocksize - 1) ||
1429 dst->offset & (alignmask - 1)) {
1430 ctx->walk.flags |= ASYNC_FLAGS_MISALIGNED;
1433 nbytes -= src->length;
1437 if (ctx->walk.flags & ASYNC_FLAGS_MISALIGNED) {
1438 err = ablkcipher_walk_init(&ctx->walk, idx, GFP_ATOMIC);
1443 nbytes = req->nbytes;
1446 sg_num = ablkcipher_walk(req, &ctx->walk);
1448 atomic_set(&ctx->sg_num, sg_num);
1450 spin_lock_irqsave(&dev->lock, flags);
1451 if (dev->started + sg_num > HIFN_QUEUE_LENGTH) {
1457 dev->started += sg_num;
1460 src = &req->src[idx];
1461 dst = &req->dst[idx];
1462 t = &ctx->walk.cache[idx];
1465 spage = dpage = sg_page(t);
1469 spage = sg_page(src);
1472 dpage = sg_page(dst);
1480 err = hifn_setup_dma(dev, spage, soff, dpage, doff, nbytes,
1488 dev->active = HIFN_DEFAULT_ACTIVE_NUM;
1489 spin_unlock_irqrestore(&dev->lock, flags);
1494 spin_unlock_irqrestore(&dev->lock, flags);
1496 if (err && printk_ratelimit())
1497 dprintk("%s: iv: %p [%d], key: %p [%d], mode: %u, op: %u, "
1498 "type: %u, err: %d.\n",
1499 dev->name, ctx->iv, ctx->ivsize,
1500 ctx->key, ctx->keysize,
1501 ctx->mode, ctx->op, ctx->type, err);
1506 static int hifn_test(struct hifn_device *dev, int encdec, u8 snum)
1510 struct hifn_context ctx;
1511 u8 fips_aes_ecb_from_zero[16] = {
1512 0x66, 0xE9, 0x4B, 0xD4,
1513 0xEF, 0x8A, 0x2C, 0x3B,
1514 0x88, 0x4C, 0xFA, 0x59,
1515 0xCA, 0x34, 0x2B, 0x2E};
1517 memset(src, 0, sizeof(src));
1518 memset(ctx.key, 0, sizeof(ctx.key));
1524 ctx.op = (encdec)?ACRYPTO_OP_ENCRYPT:ACRYPTO_OP_DECRYPT;
1525 ctx.mode = ACRYPTO_MODE_ECB;
1526 ctx.type = ACRYPTO_TYPE_AES_128;
1527 atomic_set(&ctx.sg_num, 1);
1529 err = hifn_setup_dma(dev,
1530 virt_to_page(src), offset_in_page(src),
1531 virt_to_page(src), offset_in_page(src),
1532 sizeof(src), NULL, &ctx);
1538 dprintk("%s: decoded: ", dev->name);
1539 for (n=0; n<sizeof(src); ++n)
1540 dprintk("%02x ", src[n]);
1542 dprintk("%s: FIPS : ", dev->name);
1543 for (n=0; n<sizeof(fips_aes_ecb_from_zero); ++n)
1544 dprintk("%02x ", fips_aes_ecb_from_zero[n]);
1547 if (!memcmp(src, fips_aes_ecb_from_zero, sizeof(fips_aes_ecb_from_zero))) {
1548 printk(KERN_INFO "%s: AES 128 ECB test has been successfully "
1549 "passed.\n", dev->name);
1554 printk(KERN_INFO "%s: AES 128 ECB test has been failed.\n", dev->name);
1558 static int hifn_start_device(struct hifn_device *dev)
1562 hifn_reset_dma(dev, 1);
1564 err = hifn_enable_crypto(dev);
1568 hifn_reset_puc(dev);
1572 hifn_init_registers(dev);
1574 hifn_init_pubrng(dev);
1579 static int ablkcipher_get(void *saddr, unsigned int *srestp, unsigned int offset,
1580 struct scatterlist *dst, unsigned int size, unsigned int *nbytesp)
1582 unsigned int srest = *srestp, nbytes = *nbytesp, copy;
1586 if (srest < size || size > nbytes)
1591 copy = min(dst->length, srest);
1593 daddr = kmap_atomic(sg_page(dst), KM_IRQ0);
1594 memcpy(daddr + dst->offset + offset, saddr, copy);
1595 kunmap_atomic(daddr, KM_IRQ0);
1603 dprintk("%s: copy: %u, size: %u, srest: %u, nbytes: %u.\n",
1604 __func__, copy, size, srest, nbytes);
1616 static void hifn_process_ready(struct ablkcipher_request *req, int error)
1618 struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
1619 struct hifn_device *dev;
1621 dprintk("%s: req: %p, ctx: %p.\n", __func__, req, ctx);
1624 dprintk("%s: req: %p, started: %d, sg_num: %d.\n",
1625 __func__, req, dev->started, atomic_read(&ctx->sg_num));
1627 if (--dev->started < 0)
1630 if (atomic_dec_and_test(&ctx->sg_num)) {
1631 unsigned int nbytes = req->nbytes;
1633 struct scatterlist *dst, *t;
1636 if (ctx->walk.flags & ASYNC_FLAGS_MISALIGNED) {
1638 t = &ctx->walk.cache[idx];
1639 dst = &req->dst[idx];
1641 dprintk("\n%s: sg_page(t): %p, t->length: %u, "
1642 "sg_page(dst): %p, dst->length: %u, "
1644 __func__, sg_page(t), t->length,
1645 sg_page(dst), dst->length, nbytes);
1648 nbytes -= dst->length;
1653 saddr = kmap_atomic(sg_page(t), KM_IRQ1);
1655 err = ablkcipher_get(saddr, &t->length, t->offset,
1656 dst, nbytes, &nbytes);
1658 kunmap_atomic(saddr, KM_IRQ1);
1663 kunmap_atomic(saddr, KM_IRQ1);
1666 ablkcipher_walk_exit(&ctx->walk);
1669 req->base.complete(&req->base, error);
1673 static void hifn_check_for_completion(struct hifn_device *dev, int error)
1676 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1678 for (i=0; i<HIFN_D_RES_RSIZE; ++i) {
1679 struct hifn_desc *d = &dma->resr[i];
1681 if (!(d->l & __cpu_to_le32(HIFN_D_VALID)) && dev->sa[i]) {
1684 hifn_process_ready(dev->sa[i], error);
1688 if (d->l & __cpu_to_le32(HIFN_D_DESTOVER | HIFN_D_OVER))
1689 if (printk_ratelimit())
1690 printk("%s: overflow detected [d: %u, o: %u] "
1691 "at %d resr: l: %08x, p: %08x.\n",
1693 !!(d->l & __cpu_to_le32(HIFN_D_DESTOVER)),
1694 !!(d->l & __cpu_to_le32(HIFN_D_OVER)),
1699 static void hifn_clear_rings(struct hifn_device *dev)
1701 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1704 dprintk("%s: ring cleanup 1: i: %d.%d.%d.%d, u: %d.%d.%d.%d, "
1705 "k: %d.%d.%d.%d.\n",
1707 dma->cmdi, dma->srci, dma->dsti, dma->resi,
1708 dma->cmdu, dma->srcu, dma->dstu, dma->resu,
1709 dma->cmdk, dma->srck, dma->dstk, dma->resk);
1711 i = dma->resk; u = dma->resu;
1713 if (dma->resr[i].l & __cpu_to_le32(HIFN_D_VALID))
1716 if (i != HIFN_D_RES_RSIZE)
1719 if (++i == (HIFN_D_RES_RSIZE + 1))
1722 dma->resk = i; dma->resu = u;
1724 i = dma->srck; u = dma->srcu;
1726 if (i == HIFN_D_SRC_RSIZE)
1728 if (dma->srcr[i].l & __cpu_to_le32(HIFN_D_VALID))
1732 dma->srck = i; dma->srcu = u;
1734 i = dma->cmdk; u = dma->cmdu;
1736 if (dma->cmdr[i].l & __cpu_to_le32(HIFN_D_VALID))
1738 if (i != HIFN_D_CMD_RSIZE)
1740 if (++i == (HIFN_D_CMD_RSIZE + 1))
1743 dma->cmdk = i; dma->cmdu = u;
1745 i = dma->dstk; u = dma->dstu;
1747 if (i == HIFN_D_DST_RSIZE)
1749 if (dma->dstr[i].l & __cpu_to_le32(HIFN_D_VALID))
1753 dma->dstk = i; dma->dstu = u;
1755 dprintk("%s: ring cleanup 2: i: %d.%d.%d.%d, u: %d.%d.%d.%d, "
1756 "k: %d.%d.%d.%d.\n",
1758 dma->cmdi, dma->srci, dma->dsti, dma->resi,
1759 dma->cmdu, dma->srcu, dma->dstu, dma->resu,
1760 dma->cmdk, dma->srck, dma->dstk, dma->resk);
1763 static void hifn_work(struct work_struct *work)
1765 struct delayed_work *dw = container_of(work, struct delayed_work, work);
1766 struct hifn_device *dev = container_of(dw, struct hifn_device, work);
1767 unsigned long flags;
1771 spin_lock_irqsave(&dev->lock, flags);
1772 if (dev->active == 0) {
1773 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1775 if (dma->cmdu == 0 && (dev->flags & HIFN_FLAG_CMD_BUSY)) {
1776 dev->flags &= ~HIFN_FLAG_CMD_BUSY;
1777 r |= HIFN_DMACSR_C_CTRL_DIS;
1779 if (dma->srcu == 0 && (dev->flags & HIFN_FLAG_SRC_BUSY)) {
1780 dev->flags &= ~HIFN_FLAG_SRC_BUSY;
1781 r |= HIFN_DMACSR_S_CTRL_DIS;
1783 if (dma->dstu == 0 && (dev->flags & HIFN_FLAG_DST_BUSY)) {
1784 dev->flags &= ~HIFN_FLAG_DST_BUSY;
1785 r |= HIFN_DMACSR_D_CTRL_DIS;
1787 if (dma->resu == 0 && (dev->flags & HIFN_FLAG_RES_BUSY)) {
1788 dev->flags &= ~HIFN_FLAG_RES_BUSY;
1789 r |= HIFN_DMACSR_R_CTRL_DIS;
1792 hifn_write_1(dev, HIFN_1_DMA_CSR, r);
1796 if (dev->prev_success == dev->success && dev->started)
1798 dev->prev_success = dev->success;
1799 spin_unlock_irqrestore(&dev->lock, flags);
1802 dprintk("%s: r: %08x, active: %d, started: %d, "
1803 "success: %lu: reset: %d.\n",
1804 dev->name, r, dev->active, dev->started,
1805 dev->success, reset);
1807 if (++dev->reset >= 5) {
1808 dprintk("%s: really hard reset.\n", dev->name);
1809 hifn_reset_dma(dev, 1);
1810 hifn_stop_device(dev);
1811 hifn_start_device(dev);
1815 spin_lock_irqsave(&dev->lock, flags);
1816 hifn_check_for_completion(dev, -EBUSY);
1817 hifn_clear_rings(dev);
1819 spin_unlock_irqrestore(&dev->lock, flags);
1822 schedule_delayed_work(&dev->work, HZ);
1825 static irqreturn_t hifn_interrupt(int irq, void *data)
1827 struct hifn_device *dev = (struct hifn_device *)data;
1828 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1829 u32 dmacsr, restart;
1831 dmacsr = hifn_read_1(dev, HIFN_1_DMA_CSR);
1833 dprintk("%s: 1 dmacsr: %08x, dmareg: %08x, res: %08x [%d], "
1834 "i: %d.%d.%d.%d, u: %d.%d.%d.%d.\n",
1835 dev->name, dmacsr, dev->dmareg, dmacsr & dev->dmareg, dma->cmdi,
1836 dma->cmdu, dma->srcu, dma->dstu, dma->resu,
1837 dma->cmdi, dma->srci, dma->dsti, dma->resi);
1839 if ((dmacsr & dev->dmareg) == 0)
1842 hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & dev->dmareg);
1844 if (dmacsr & HIFN_DMACSR_ENGINE)
1845 hifn_write_0(dev, HIFN_0_PUISR, hifn_read_0(dev, HIFN_0_PUISR));
1846 if (dmacsr & HIFN_DMACSR_PUBDONE)
1847 hifn_write_1(dev, HIFN_1_PUB_STATUS,
1848 hifn_read_1(dev, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE);
1850 restart = dmacsr & (HIFN_DMACSR_R_OVER | HIFN_DMACSR_D_OVER);
1852 u32 puisr = hifn_read_0(dev, HIFN_0_PUISR);
1854 if (printk_ratelimit())
1855 printk("%s: overflow: r: %d, d: %d, puisr: %08x, d: %u.\n",
1856 dev->name, !!(dmacsr & HIFN_DMACSR_R_OVER),
1857 !!(dmacsr & HIFN_DMACSR_D_OVER),
1858 puisr, !!(puisr & HIFN_PUISR_DSTOVER));
1859 if (!!(puisr & HIFN_PUISR_DSTOVER))
1860 hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
1861 hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & (HIFN_DMACSR_R_OVER |
1862 HIFN_DMACSR_D_OVER));
1865 restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT |
1866 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT);
1868 if (printk_ratelimit())
1869 printk("%s: abort: c: %d, s: %d, d: %d, r: %d.\n",
1870 dev->name, !!(dmacsr & HIFN_DMACSR_C_ABORT),
1871 !!(dmacsr & HIFN_DMACSR_S_ABORT),
1872 !!(dmacsr & HIFN_DMACSR_D_ABORT),
1873 !!(dmacsr & HIFN_DMACSR_R_ABORT));
1874 hifn_reset_dma(dev, 1);
1876 hifn_init_registers(dev);
1879 if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) {
1880 dprintk("%s: wait on command.\n", dev->name);
1881 dev->dmareg &= ~(HIFN_DMAIER_C_WAIT);
1882 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
1885 tasklet_schedule(&dev->tasklet);
1886 hifn_clear_rings(dev);
1891 static void hifn_flush(struct hifn_device *dev)
1893 unsigned long flags;
1894 struct crypto_async_request *async_req;
1895 struct hifn_context *ctx;
1896 struct ablkcipher_request *req;
1897 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1900 spin_lock_irqsave(&dev->lock, flags);
1901 for (i=0; i<HIFN_D_RES_RSIZE; ++i) {
1902 struct hifn_desc *d = &dma->resr[i];
1905 hifn_process_ready(dev->sa[i],
1906 (d->l & __cpu_to_le32(HIFN_D_VALID))?-ENODEV:0);
1910 while ((async_req = crypto_dequeue_request(&dev->queue))) {
1911 ctx = crypto_tfm_ctx(async_req->tfm);
1912 req = container_of(async_req, struct ablkcipher_request, base);
1914 hifn_process_ready(req, -ENODEV);
1916 spin_unlock_irqrestore(&dev->lock, flags);
1919 static int hifn_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
1922 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
1923 struct hifn_context *ctx = crypto_tfm_ctx(tfm);
1924 struct hifn_device *dev = ctx->dev;
1926 if (len > HIFN_MAX_CRYPT_KEY_LENGTH) {
1927 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
1931 if (len == HIFN_DES_KEY_LENGTH) {
1932 u32 tmp[DES_EXPKEY_WORDS];
1933 int ret = des_ekey(tmp, key);
1935 if (unlikely(ret == 0) && (tfm->crt_flags & CRYPTO_TFM_REQ_WEAK_KEY)) {
1936 tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY;
1941 dev->flags &= ~HIFN_FLAG_OLD_KEY;
1943 memcpy(ctx->key, key, len);
1949 static int hifn_handle_req(struct ablkcipher_request *req)
1951 struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
1952 struct hifn_device *dev = ctx->dev;
1955 if (dev->started + DIV_ROUND_UP(req->nbytes, PAGE_SIZE) <= HIFN_QUEUE_LENGTH)
1956 err = hifn_setup_session(req);
1958 if (err == -EAGAIN) {
1959 unsigned long flags;
1961 spin_lock_irqsave(&dev->lock, flags);
1962 err = ablkcipher_enqueue_request(&dev->queue, req);
1963 spin_unlock_irqrestore(&dev->lock, flags);
1969 static int hifn_setup_crypto_req(struct ablkcipher_request *req, u8 op,
1972 struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
1975 ivsize = crypto_ablkcipher_ivsize(crypto_ablkcipher_reqtfm(req));
1977 if (req->info && mode != ACRYPTO_MODE_ECB) {
1978 if (type == ACRYPTO_TYPE_AES_128)
1979 ivsize = HIFN_AES_IV_LENGTH;
1980 else if (type == ACRYPTO_TYPE_DES)
1981 ivsize = HIFN_DES_KEY_LENGTH;
1982 else if (type == ACRYPTO_TYPE_3DES)
1983 ivsize = HIFN_3DES_KEY_LENGTH;
1986 if (ctx->keysize != 16 && type == ACRYPTO_TYPE_AES_128) {
1987 if (ctx->keysize == 24)
1988 type = ACRYPTO_TYPE_AES_192;
1989 else if (ctx->keysize == 32)
1990 type = ACRYPTO_TYPE_AES_256;
1996 ctx->iv = req->info;
1997 ctx->ivsize = ivsize;
2000 * HEAVY TODO: needs to kick Herbert XU to write documentation.
2001 * HEAVY TODO: needs to kick Herbert XU to write documentation.
2002 * HEAVY TODO: needs to kick Herbert XU to write documentation.
2005 return hifn_handle_req(req);
2008 static int hifn_process_queue(struct hifn_device *dev)
2010 struct crypto_async_request *async_req;
2011 struct hifn_context *ctx;
2012 struct ablkcipher_request *req;
2013 unsigned long flags;
2016 while (dev->started < HIFN_QUEUE_LENGTH) {
2017 spin_lock_irqsave(&dev->lock, flags);
2018 async_req = crypto_dequeue_request(&dev->queue);
2019 spin_unlock_irqrestore(&dev->lock, flags);
2024 ctx = crypto_tfm_ctx(async_req->tfm);
2025 req = container_of(async_req, struct ablkcipher_request, base);
2027 err = hifn_handle_req(req);
2035 static int hifn_setup_crypto(struct ablkcipher_request *req, u8 op,
2039 struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
2040 struct hifn_device *dev = ctx->dev;
2042 err = hifn_setup_crypto_req(req, op, type, mode);
2046 if (dev->started < HIFN_QUEUE_LENGTH && dev->queue.qlen)
2047 err = hifn_process_queue(dev);
2053 * AES ecryption functions.
2055 static inline int hifn_encrypt_aes_ecb(struct ablkcipher_request *req)
2057 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2058 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_ECB);
2060 static inline int hifn_encrypt_aes_cbc(struct ablkcipher_request *req)
2062 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2063 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC);
2065 static inline int hifn_encrypt_aes_cfb(struct ablkcipher_request *req)
2067 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2068 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB);
2070 static inline int hifn_encrypt_aes_ofb(struct ablkcipher_request *req)
2072 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2073 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB);
2077 * AES decryption functions.
2079 static inline int hifn_decrypt_aes_ecb(struct ablkcipher_request *req)
2081 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2082 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_ECB);
2084 static inline int hifn_decrypt_aes_cbc(struct ablkcipher_request *req)
2086 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2087 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC);
2089 static inline int hifn_decrypt_aes_cfb(struct ablkcipher_request *req)
2091 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2092 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB);
2094 static inline int hifn_decrypt_aes_ofb(struct ablkcipher_request *req)
2096 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2097 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB);
2101 * DES ecryption functions.
2103 static inline int hifn_encrypt_des_ecb(struct ablkcipher_request *req)
2105 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2106 ACRYPTO_TYPE_DES, ACRYPTO_MODE_ECB);
2108 static inline int hifn_encrypt_des_cbc(struct ablkcipher_request *req)
2110 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2111 ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC);
2113 static inline int hifn_encrypt_des_cfb(struct ablkcipher_request *req)
2115 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2116 ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB);
2118 static inline int hifn_encrypt_des_ofb(struct ablkcipher_request *req)
2120 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2121 ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB);
2125 * DES decryption functions.
2127 static inline int hifn_decrypt_des_ecb(struct ablkcipher_request *req)
2129 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2130 ACRYPTO_TYPE_DES, ACRYPTO_MODE_ECB);
2132 static inline int hifn_decrypt_des_cbc(struct ablkcipher_request *req)
2134 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2135 ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC);
2137 static inline int hifn_decrypt_des_cfb(struct ablkcipher_request *req)
2139 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2140 ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB);
2142 static inline int hifn_decrypt_des_ofb(struct ablkcipher_request *req)
2144 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2145 ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB);
2149 * 3DES ecryption functions.
2151 static inline int hifn_encrypt_3des_ecb(struct ablkcipher_request *req)
2153 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2154 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_ECB);
2156 static inline int hifn_encrypt_3des_cbc(struct ablkcipher_request *req)
2158 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2159 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC);
2161 static inline int hifn_encrypt_3des_cfb(struct ablkcipher_request *req)
2163 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2164 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB);
2166 static inline int hifn_encrypt_3des_ofb(struct ablkcipher_request *req)
2168 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2169 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB);
2173 * 3DES decryption functions.
2175 static inline int hifn_decrypt_3des_ecb(struct ablkcipher_request *req)
2177 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2178 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_ECB);
2180 static inline int hifn_decrypt_3des_cbc(struct ablkcipher_request *req)
2182 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2183 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC);
2185 static inline int hifn_decrypt_3des_cfb(struct ablkcipher_request *req)
2187 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2188 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB);
2190 static inline int hifn_decrypt_3des_ofb(struct ablkcipher_request *req)
2192 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2193 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB);
2196 struct hifn_alg_template
2198 char name[CRYPTO_MAX_ALG_NAME];
2199 char drv_name[CRYPTO_MAX_ALG_NAME];
2201 struct ablkcipher_alg ablkcipher;
2204 static struct hifn_alg_template hifn_alg_templates[] = {
2206 * 3DES ECB, CBC, CFB and OFB modes.
2209 .name = "cfb(des3_ede)", .drv_name = "hifn-3des", .bsize = 8,
2211 .min_keysize = HIFN_3DES_KEY_LENGTH,
2212 .max_keysize = HIFN_3DES_KEY_LENGTH,
2213 .setkey = hifn_setkey,
2214 .encrypt = hifn_encrypt_3des_cfb,
2215 .decrypt = hifn_decrypt_3des_cfb,
2219 .name = "ofb(des3_ede)", .drv_name = "hifn-3des", .bsize = 8,
2221 .min_keysize = HIFN_3DES_KEY_LENGTH,
2222 .max_keysize = HIFN_3DES_KEY_LENGTH,
2223 .setkey = hifn_setkey,
2224 .encrypt = hifn_encrypt_3des_ofb,
2225 .decrypt = hifn_decrypt_3des_ofb,
2229 .name = "cbc(des3_ede)", .drv_name = "hifn-3des", .bsize = 8,
2231 .min_keysize = HIFN_3DES_KEY_LENGTH,
2232 .max_keysize = HIFN_3DES_KEY_LENGTH,
2233 .setkey = hifn_setkey,
2234 .encrypt = hifn_encrypt_3des_cbc,
2235 .decrypt = hifn_decrypt_3des_cbc,
2239 .name = "ecb(des3_ede)", .drv_name = "hifn-3des", .bsize = 8,
2241 .min_keysize = HIFN_3DES_KEY_LENGTH,
2242 .max_keysize = HIFN_3DES_KEY_LENGTH,
2243 .setkey = hifn_setkey,
2244 .encrypt = hifn_encrypt_3des_ecb,
2245 .decrypt = hifn_decrypt_3des_ecb,
2250 * DES ECB, CBC, CFB and OFB modes.
2253 .name = "cfb(des)", .drv_name = "hifn-des", .bsize = 8,
2255 .min_keysize = HIFN_DES_KEY_LENGTH,
2256 .max_keysize = HIFN_DES_KEY_LENGTH,
2257 .setkey = hifn_setkey,
2258 .encrypt = hifn_encrypt_des_cfb,
2259 .decrypt = hifn_decrypt_des_cfb,
2263 .name = "ofb(des)", .drv_name = "hifn-des", .bsize = 8,
2265 .min_keysize = HIFN_DES_KEY_LENGTH,
2266 .max_keysize = HIFN_DES_KEY_LENGTH,
2267 .setkey = hifn_setkey,
2268 .encrypt = hifn_encrypt_des_ofb,
2269 .decrypt = hifn_decrypt_des_ofb,
2273 .name = "cbc(des)", .drv_name = "hifn-des", .bsize = 8,
2275 .min_keysize = HIFN_DES_KEY_LENGTH,
2276 .max_keysize = HIFN_DES_KEY_LENGTH,
2277 .setkey = hifn_setkey,
2278 .encrypt = hifn_encrypt_des_cbc,
2279 .decrypt = hifn_decrypt_des_cbc,
2283 .name = "ecb(des)", .drv_name = "hifn-des", .bsize = 8,
2285 .min_keysize = HIFN_DES_KEY_LENGTH,
2286 .max_keysize = HIFN_DES_KEY_LENGTH,
2287 .setkey = hifn_setkey,
2288 .encrypt = hifn_encrypt_des_ecb,
2289 .decrypt = hifn_decrypt_des_ecb,
2294 * AES ECB, CBC, CFB and OFB modes.
2297 .name = "ecb(aes)", .drv_name = "hifn-aes", .bsize = 16,
2299 .min_keysize = AES_MIN_KEY_SIZE,
2300 .max_keysize = AES_MAX_KEY_SIZE,
2301 .setkey = hifn_setkey,
2302 .encrypt = hifn_encrypt_aes_ecb,
2303 .decrypt = hifn_decrypt_aes_ecb,
2307 .name = "cbc(aes)", .drv_name = "hifn-aes", .bsize = 16,
2309 .min_keysize = AES_MIN_KEY_SIZE,
2310 .max_keysize = AES_MAX_KEY_SIZE,
2311 .setkey = hifn_setkey,
2312 .encrypt = hifn_encrypt_aes_cbc,
2313 .decrypt = hifn_decrypt_aes_cbc,
2317 .name = "cfb(aes)", .drv_name = "hifn-aes", .bsize = 16,
2319 .min_keysize = AES_MIN_KEY_SIZE,
2320 .max_keysize = AES_MAX_KEY_SIZE,
2321 .setkey = hifn_setkey,
2322 .encrypt = hifn_encrypt_aes_cfb,
2323 .decrypt = hifn_decrypt_aes_cfb,
2327 .name = "ofb(aes)", .drv_name = "hifn-aes", .bsize = 16,
2329 .min_keysize = AES_MIN_KEY_SIZE,
2330 .max_keysize = AES_MAX_KEY_SIZE,
2331 .setkey = hifn_setkey,
2332 .encrypt = hifn_encrypt_aes_ofb,
2333 .decrypt = hifn_decrypt_aes_ofb,
2338 static int hifn_cra_init(struct crypto_tfm *tfm)
2340 struct crypto_alg *alg = tfm->__crt_alg;
2341 struct hifn_crypto_alg *ha = crypto_alg_to_hifn(alg);
2342 struct hifn_context *ctx = crypto_tfm_ctx(tfm);
2349 static int hifn_alg_alloc(struct hifn_device *dev, struct hifn_alg_template *t)
2351 struct hifn_crypto_alg *alg;
2354 alg = kzalloc(sizeof(struct hifn_crypto_alg), GFP_KERNEL);
2358 snprintf(alg->alg.cra_name, CRYPTO_MAX_ALG_NAME, "%s", t->name);
2359 snprintf(alg->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", t->drv_name);
2361 alg->alg.cra_priority = 300;
2362 alg->alg.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | CRYPTO_ALG_ASYNC;
2363 alg->alg.cra_blocksize = t->bsize;
2364 alg->alg.cra_ctxsize = sizeof(struct hifn_context);
2365 alg->alg.cra_alignmask = 15;
2367 alg->alg.cra_alignmask = 3;
2368 alg->alg.cra_type = &crypto_ablkcipher_type;
2369 alg->alg.cra_module = THIS_MODULE;
2370 alg->alg.cra_u.ablkcipher = t->ablkcipher;
2371 alg->alg.cra_init = hifn_cra_init;
2375 list_add_tail(&alg->entry, &dev->alg_list);
2377 err = crypto_register_alg(&alg->alg);
2379 list_del(&alg->entry);
2386 static void hifn_unregister_alg(struct hifn_device *dev)
2388 struct hifn_crypto_alg *a, *n;
2390 list_for_each_entry_safe(a, n, &dev->alg_list, entry) {
2391 list_del(&a->entry);
2392 crypto_unregister_alg(&a->alg);
2397 static int hifn_register_alg(struct hifn_device *dev)
2401 for (i=0; i<ARRAY_SIZE(hifn_alg_templates); ++i) {
2402 err = hifn_alg_alloc(dev, &hifn_alg_templates[i]);
2410 hifn_unregister_alg(dev);
2414 static void hifn_tasklet_callback(unsigned long data)
2416 struct hifn_device *dev = (struct hifn_device *)data;
2419 * This is ok to call this without lock being held,
2420 * althogh it modifies some parameters used in parallel,
2421 * (like dev->success), but they are used in process
2422 * context or update is atomic (like setting dev->sa[i] to NULL).
2424 hifn_check_for_completion(dev, 0);
2427 static int hifn_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2430 struct hifn_device *dev;
2433 err = pci_enable_device(pdev);
2436 pci_set_master(pdev);
2438 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2440 goto err_out_disable_pci_device;
2442 snprintf(name, sizeof(name), "hifn%d",
2443 atomic_inc_return(&hifn_dev_number)-1);
2445 err = pci_request_regions(pdev, name);
2447 goto err_out_disable_pci_device;
2449 if (pci_resource_len(pdev, 0) < HIFN_BAR0_SIZE ||
2450 pci_resource_len(pdev, 1) < HIFN_BAR1_SIZE ||
2451 pci_resource_len(pdev, 2) < HIFN_BAR2_SIZE) {
2452 dprintk("%s: Broken hardware - I/O regions are too small.\n",
2455 goto err_out_free_regions;
2458 dev = kzalloc(sizeof(struct hifn_device) + sizeof(struct crypto_alg),
2462 goto err_out_free_regions;
2465 INIT_LIST_HEAD(&dev->alg_list);
2467 snprintf(dev->name, sizeof(dev->name), "%s", name);
2468 spin_lock_init(&dev->lock);
2470 for (i=0; i<3; ++i) {
2471 unsigned long addr, size;
2473 addr = pci_resource_start(pdev, i);
2474 size = pci_resource_len(pdev, i);
2476 dev->bar[i] = ioremap_nocache(addr, size);
2478 goto err_out_unmap_bars;
2481 dev->result_mem = __get_free_pages(GFP_KERNEL, HIFN_MAX_RESULT_ORDER);
2482 if (!dev->result_mem) {
2483 dprintk("Failed to allocate %d pages for result_mem.\n",
2484 HIFN_MAX_RESULT_ORDER);
2485 goto err_out_unmap_bars;
2487 memset((void *)dev->result_mem, 0, PAGE_SIZE*(1<<HIFN_MAX_RESULT_ORDER));
2489 dev->dst = pci_map_single(pdev, (void *)dev->result_mem,
2490 PAGE_SIZE << HIFN_MAX_RESULT_ORDER, PCI_DMA_FROMDEVICE);
2492 dev->desc_virt = pci_alloc_consistent(pdev, sizeof(struct hifn_dma),
2494 if (!dev->desc_virt) {
2495 dprintk("Failed to allocate descriptor rings.\n");
2496 goto err_out_free_result_pages;
2498 memset(dev->desc_virt, 0, sizeof(struct hifn_dma));
2501 dev->irq = pdev->irq;
2503 for (i=0; i<HIFN_D_RES_RSIZE; ++i)
2506 pci_set_drvdata(pdev, dev);
2508 tasklet_init(&dev->tasklet, hifn_tasklet_callback, (unsigned long)dev);
2510 crypto_init_queue(&dev->queue, 1);
2512 err = request_irq(dev->irq, hifn_interrupt, IRQF_SHARED, dev->name, dev);
2514 dprintk("Failed to request IRQ%d: err: %d.\n", dev->irq, err);
2516 goto err_out_free_desc;
2519 err = hifn_start_device(dev);
2521 goto err_out_free_irq;
2523 err = hifn_test(dev, 1, 0);
2525 goto err_out_stop_device;
2527 err = hifn_register_alg(dev);
2529 goto err_out_stop_device;
2531 INIT_DELAYED_WORK(&dev->work, hifn_work);
2532 schedule_delayed_work(&dev->work, HZ);
2534 dprintk("HIFN crypto accelerator card at %s has been "
2535 "successfully registered as %s.\n",
2536 pci_name(pdev), dev->name);
2540 err_out_stop_device:
2541 hifn_reset_dma(dev, 1);
2542 hifn_stop_device(dev);
2544 free_irq(dev->irq, dev->name);
2545 tasklet_kill(&dev->tasklet);
2547 pci_free_consistent(pdev, sizeof(struct hifn_dma),
2548 dev->desc_virt, dev->desc_dma);
2550 err_out_free_result_pages:
2551 pci_unmap_single(pdev, dev->dst, PAGE_SIZE << HIFN_MAX_RESULT_ORDER,
2552 PCI_DMA_FROMDEVICE);
2553 free_pages(dev->result_mem, HIFN_MAX_RESULT_ORDER);
2558 iounmap(dev->bar[i]);
2560 err_out_free_regions:
2561 pci_release_regions(pdev);
2563 err_out_disable_pci_device:
2564 pci_disable_device(pdev);
2569 static void hifn_remove(struct pci_dev *pdev)
2572 struct hifn_device *dev;
2574 dev = pci_get_drvdata(pdev);
2577 cancel_delayed_work(&dev->work);
2578 flush_scheduled_work();
2580 hifn_unregister_alg(dev);
2581 hifn_reset_dma(dev, 1);
2582 hifn_stop_device(dev);
2584 free_irq(dev->irq, dev->name);
2585 tasklet_kill(&dev->tasklet);
2589 pci_free_consistent(pdev, sizeof(struct hifn_dma),
2590 dev->desc_virt, dev->desc_dma);
2591 pci_unmap_single(pdev, dev->dst,
2592 PAGE_SIZE << HIFN_MAX_RESULT_ORDER,
2593 PCI_DMA_FROMDEVICE);
2594 free_pages(dev->result_mem, HIFN_MAX_RESULT_ORDER);
2597 iounmap(dev->bar[i]);
2602 pci_release_regions(pdev);
2603 pci_disable_device(pdev);
2606 static struct pci_device_id hifn_pci_tbl[] = {
2607 { PCI_DEVICE(PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7955) },
2608 { PCI_DEVICE(PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7956) },
2611 MODULE_DEVICE_TABLE(pci, hifn_pci_tbl);
2613 static struct pci_driver hifn_pci_driver = {
2615 .id_table = hifn_pci_tbl,
2616 .probe = hifn_probe,
2617 .remove = __devexit_p(hifn_remove),
2620 static int __devinit hifn_init(void)
2624 err = pci_register_driver(&hifn_pci_driver);
2626 dprintk("Failed to register PCI driver for %s device.\n",
2627 hifn_pci_driver.name);
2631 printk(KERN_INFO "Driver for HIFN 795x crypto accelerator chip "
2632 "has been successfully registered.\n");
2637 static void __devexit hifn_fini(void)
2639 pci_unregister_driver(&hifn_pci_driver);
2641 printk(KERN_INFO "Driver for HIFN 795x crypto accelerator chip "
2642 "has been successfully unregistered.\n");
2645 module_init(hifn_init);
2646 module_exit(hifn_fini);
2648 MODULE_LICENSE("GPL");
2649 MODULE_AUTHOR("Evgeniy Polyakov <johnpol@2ka.mipt.ru>");
2650 MODULE_DESCRIPTION("Driver for HIFN 795x crypto accelerator chip.");