1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
4 * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
13 #include <dm/device-internal.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 static int riscv_cpu_get_desc(const struct udevice *dev, char *buf, int size)
24 isa = dev_read_string(dev, "riscv,isa");
25 if (size < (strlen(isa) + 1))
33 static int riscv_cpu_get_info(const struct udevice *dev, struct cpu_info *info)
41 /* First try getting the frequency from the assigned clock */
42 ret = clk_get_by_index((struct udevice *)dev, 0, &clk);
44 ret = clk_get_rate(&clk);
45 if (!IS_ERR_VALUE(ret))
51 dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq);
53 mmu = dev_read_string(dev, "mmu-type");
55 info->features |= BIT(CPU_FEAT_MMU);
57 /* check if I cache is present */
58 ret = dev_read_u32(dev, "i-cache-size", &i_cache_size);
60 /* if not found check if d-cache is present */
61 ret = dev_read_u32(dev, "d-cache-size", &d_cache_size);
63 /* if either I or D cache is present set L1 cache feature */
65 info->features |= BIT(CPU_FEAT_L1_CACHE);
70 static int riscv_cpu_get_count(const struct udevice *dev)
75 ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
76 const char *device_type;
78 /* skip if hart is marked as not available in the device tree */
79 if (!ofnode_is_available(node))
82 device_type = ofnode_read_string(node, "device_type");
85 if (strcmp(device_type, "cpu") == 0)
92 static int riscv_cpu_bind(struct udevice *dev)
94 struct cpu_plat *plat = dev_get_parent_plat(dev);
98 /* save the hart id */
99 plat->cpu_id = dev_read_addr(dev);
100 /* first examine the property in current cpu node */
101 ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq);
102 /* if not found, then look at the parent /cpus node */
104 dev_read_u32(dev->parent, "timebase-frequency",
105 &plat->timebase_freq);
108 * Bind riscv-timer driver on boot hart.
110 * We only instantiate one timer device which is enough for U-Boot.
111 * Pass the "timebase-frequency" value as the driver data for the
114 * Return value is not checked since it's possible that the timer
115 * driver is not included.
117 if (plat->cpu_id == gd->arch.boot_hart && plat->timebase_freq) {
118 drv = lists_driver_lookup_name("riscv_timer");
120 debug("Cannot find the timer driver, not included?\n");
124 device_bind_with_driver_data(dev, drv, "riscv_timer",
125 plat->timebase_freq, ofnode_null(),
132 static int riscv_cpu_probe(struct udevice *dev)
137 /* Get a clock if it exists */
138 ret = clk_get_by_index(dev, 0, &clk);
142 ret = clk_enable(&clk);
144 if (ret == -ENOSYS || ret == -ENOTSUPP)
150 static const struct cpu_ops riscv_cpu_ops = {
151 .get_desc = riscv_cpu_get_desc,
152 .get_info = riscv_cpu_get_info,
153 .get_count = riscv_cpu_get_count,
156 static const struct udevice_id riscv_cpu_ids[] = {
157 { .compatible = "riscv" },
161 U_BOOT_DRIVER(riscv_cpu) = {
164 .of_match = riscv_cpu_ids,
165 .bind = riscv_cpu_bind,
166 .probe = riscv_cpu_probe,
167 .ops = &riscv_cpu_ops,
168 .flags = DM_FLAG_PRE_RELOC,