drivers/cpu/bmips_cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
   4  *
   5  * Derived from linux/arch/mips/bcm63xx/cpu.c:
   6  *      Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   7  *      Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
   8  */
   9
  10 #include <common.h>
  11 #include <cpu.h>
  12 #include <dm.h>
  13 #include <errno.h>
  14 #include <init.h>
  15 #include <asm/io.h>
  16
  17 #define REV_CHIPID_SHIFT                16
  18 #define REV_CHIPID_MASK                 (0xffff << REV_CHIPID_SHIFT)
  19 #define REV_LONG_CHIPID_SHIFT           12
  20 #define REV_LONG_CHIPID_MASK            (0xfffff << REV_LONG_CHIPID_SHIFT)
  21 #define REV_REVID_SHIFT                 0
  22 #define REV_REVID_MASK                  (0xff << REV_REVID_SHIFT)
  23
  24 #define REG_BCM6328_OTP                 0x62c
  25 #define BCM6328_TP1_DISABLED            BIT(9)
  26
  27 #define REG_BCM6318_STRAP_OVRDBUS       0x900
  28 #define OVRDBUS_6318_FREQ_SHIFT         23
  29 #define OVRDBUS_6318_FREQ_MASK          (0x3 << OVRDBUS_6318_FREQ_SHIFT)
  30
  31 #define REG_BCM6328_MISC_STRAPBUS       0x1a40
  32 #define STRAPBUS_6328_FCVO_SHIFT        7
  33 #define STRAPBUS_6328_FCVO_MASK         (0x1f << STRAPBUS_6328_FCVO_SHIFT)
  34
  35 #define REG_BCM6348_PERF_MIPSPLLCFG     0x34
  36 #define MIPSPLLCFG_6348_M1CPU_SHIFT     6
  37 #define MIPSPLLCFG_6348_M1CPU_MASK      (0x7 << MIPSPLLCFG_6348_M1CPU_SHIFT)
  38 #define MIPSPLLCFG_6348_N2_SHIFT        15
  39 #define MIPSPLLCFG_6348_N2_MASK         (0x1F << MIPSPLLCFG_6348_N2_SHIFT)
  40 #define MIPSPLLCFG_6348_N1_SHIFT        20
  41 #define MIPSPLLCFG_6348_N1_MASK         (0x7 << MIPSPLLCFG_6348_N1_SHIFT)
  42
  43 #define REG_BCM6358_DDR_DMIPSPLLCFG     0x12b8
  44 #define DMIPSPLLCFG_6358_M1_SHIFT       0
  45 #define DMIPSPLLCFG_6358_M1_MASK        (0xff << DMIPSPLLCFG_6358_M1_SHIFT)
  46 #define DMIPSPLLCFG_6358_N1_SHIFT       23
  47 #define DMIPSPLLCFG_6358_N1_MASK        (0x3f << DMIPSPLLCFG_6358_N1_SHIFT)
  48 #define DMIPSPLLCFG_6358_N2_SHIFT       29
  49 #define DMIPSPLLCFG_6358_N2_MASK        (0x7 << DMIPSPLLCFG_6358_N2_SHIFT)
  50
  51 #define REG_BCM6362_MISC_STRAPBUS       0x1814
  52 #define STRAPBUS_6362_FCVO_SHIFT        1
  53 #define STRAPBUS_6362_FCVO_MASK         (0x1f << STRAPBUS_6362_FCVO_SHIFT)
  54
  55 #define REG_BCM6368_DDR_DMIPSPLLCFG     0x12a0
  56 #define DMIPSPLLCFG_6368_P1_SHIFT       0
  57 #define DMIPSPLLCFG_6368_P1_MASK        (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
  58 #define DMIPSPLLCFG_6368_P2_SHIFT       4
  59 #define DMIPSPLLCFG_6368_P2_MASK        (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
  60 #define DMIPSPLLCFG_6368_NDIV_SHIFT     16
  61 #define DMIPSPLLCFG_6368_NDIV_MASK      (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
  62 #define REG_BCM6368_DDR_DMIPSPLLDIV     0x12a4
  63 #define DMIPSPLLDIV_6368_MDIV_SHIFT     0
  64 #define DMIPSPLLDIV_6368_MDIV_MASK      (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
  65
  66 #define REG_BCM63268_MISC_STRAPBUS      0x1814
  67 #define STRAPBUS_63268_FCVO_SHIFT       21
  68 #define STRAPBUS_63268_FCVO_MASK        (0xf << STRAPBUS_63268_FCVO_SHIFT)
  69
  70 #define REG_BCM6838_OTP_BRCMBITS0       0x440
  71 #define VIPER_6838_FREQ_SHIFT           18
  72 #define VIPER_6838_FREQ_MASK            (0x7 << VIPER_6838_FREQ_SHIFT)
  73
  74 struct bmips_cpu_priv;
  75
  76 struct bmips_cpu_hw {
  77         int (*get_cpu_desc)(struct bmips_cpu_priv *priv, char *buf, int size);
  78         ulong (*get_cpu_freq)(struct bmips_cpu_priv *);
  79         int (*get_cpu_count)(struct bmips_cpu_priv *);
  80 };
  81
  82 struct bmips_cpu_priv {
  83         void __iomem *regs;
  84         const struct bmips_cpu_hw *hw;
  85 };
  86
  87 /* Specific CPU Ops */
  88 static int bmips_short_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
  89                                 int size)
  90 {
  91         unsigned short cpu_id;
  92         unsigned char cpu_rev;
  93         u32 val;
  94
  95         val = readl_be(priv->regs);
  96         cpu_id = (val & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
  97         cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT;
  98
  99         snprintf(buf, size, "BCM%04X%02X", cpu_id, cpu_rev);
 100
 101         return 0;
 102 }
 103
 104 static int bmips_long_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
 105                                 int size)
 106 {
 107         unsigned int cpu_id;
 108         unsigned char cpu_rev;
 109         u32 val;
 110
 111         val = readl_be(priv->regs);
 112         cpu_id = (val & REV_LONG_CHIPID_MASK) >> REV_LONG_CHIPID_SHIFT;
 113         cpu_rev = (val & REV_REVID_MASK) >> REV_REVID_SHIFT;
 114
 115         snprintf(buf, size, "BCM%05X%02X", cpu_id, cpu_rev);
 116
 117         return 0;
 118 }
 119
 120 static ulong bcm3380_get_cpu_freq(struct bmips_cpu_priv *priv)
 121 {
 122         return 333000000;
 123 }
 124
 125 static ulong bcm6318_get_cpu_freq(struct bmips_cpu_priv *priv)
 126 {
 127         unsigned int mips_pll_fcvo;
 128
 129         mips_pll_fcvo = readl_be(priv->regs + REG_BCM6318_STRAP_OVRDBUS);
 130         mips_pll_fcvo = (mips_pll_fcvo & OVRDBUS_6318_FREQ_MASK)
 131                         >> OVRDBUS_6318_FREQ_SHIFT;
 132
 133         switch (mips_pll_fcvo) {
 134         case 0:
 135                 return 166000000;
 136         case 1:
 137                 return 400000000;
 138         case 2:
 139                 return 250000000;
 140         case 3:
 141                 return 333000000;
 142         default:
 143                 return 0;
 144         }
 145 }
 146
 147 static ulong bcm6328_get_cpu_freq(struct bmips_cpu_priv *priv)
 148 {
 149         unsigned int mips_pll_fcvo;
 150
 151         mips_pll_fcvo = readl_be(priv->regs + REG_BCM6328_MISC_STRAPBUS);
 152         mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6328_FCVO_MASK)
 153                         >> STRAPBUS_6328_FCVO_SHIFT;
 154
 155         switch (mips_pll_fcvo) {
 156         case 0x12:
 157         case 0x14:
 158         case 0x19:
 159                 return 160000000;
 160         case 0x1c:
 161                 return 192000000;
 162         case 0x13:
 163         case 0x15:
 164                 return 200000000;
 165         case 0x1a:
 166                 return 384000000;
 167         case 0x16:
 168                 return 400000000;
 169         default:
 170                 return 320000000;
 171         }
 172 }
 173
 174 static ulong bcm6338_get_cpu_freq(struct bmips_cpu_priv *priv)
 175 {
 176         return 240000000;
 177 }
 178
 179 static ulong bcm6348_get_cpu_freq(struct bmips_cpu_priv *priv)
 180 {
 181         unsigned int tmp, n1, n2, m1;
 182
 183         tmp = readl_be(priv->regs + REG_BCM6348_PERF_MIPSPLLCFG);
 184         n1 = (tmp & MIPSPLLCFG_6348_N1_MASK) >> MIPSPLLCFG_6348_N1_SHIFT;
 185         n2 = (tmp & MIPSPLLCFG_6348_N2_MASK) >> MIPSPLLCFG_6348_N2_SHIFT;
 186         m1 = (tmp & MIPSPLLCFG_6348_M1CPU_MASK) >> MIPSPLLCFG_6348_M1CPU_SHIFT;
 187
 188         return (16 * 1000000 * (n1 + 1) * (n2 + 2)) / (m1 + 1);
 189 }
 190
 191 static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv)
 192 {
 193         unsigned int tmp, n1, n2, m1;
 194
 195         tmp = readl_be(priv->regs + REG_BCM6358_DDR_DMIPSPLLCFG);
 196         n1 = (tmp & DMIPSPLLCFG_6358_N1_MASK) >> DMIPSPLLCFG_6358_N1_SHIFT;
 197         n2 = (tmp & DMIPSPLLCFG_6358_N2_MASK) >> DMIPSPLLCFG_6358_N2_SHIFT;
 198         m1 = (tmp & DMIPSPLLCFG_6358_M1_MASK) >> DMIPSPLLCFG_6358_M1_SHIFT;
 199
 200         return (16 * 1000000 * n1 * n2) / m1;
 201 }
 202
 203 static ulong bcm6362_get_cpu_freq(struct bmips_cpu_priv *priv)
 204 {
 205         unsigned int mips_pll_fcvo;
 206
 207         mips_pll_fcvo = readl_be(priv->regs + REG_BCM6362_MISC_STRAPBUS);
 208         mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6362_FCVO_MASK)
 209                         >> STRAPBUS_6362_FCVO_SHIFT;
 210
 211         switch (mips_pll_fcvo) {
 212         case 0x03:
 213         case 0x0b:
 214         case 0x13:
 215         case 0x1b:
 216                 return 240000000;
 217         case 0x04:
 218         case 0x0c:
 219         case 0x14:
 220         case 0x1c:
 221                 return 160000000;
 222         case 0x05:
 223         case 0x0e:
 224         case 0x16:
 225         case 0x1e:
 226         case 0x1f:
 227                 return 400000000;
 228         case 0x06:
 229                 return 440000000;
 230         case 0x07:
 231         case 0x17:
 232                 return 384000000;
 233         case 0x15:
 234         case 0x1d:
 235                 return 200000000;
 236         default:
 237                 return 320000000;
 238         }
 239 }
 240
 241 static ulong bcm6368_get_cpu_freq(struct bmips_cpu_priv *priv)
 242 {
 243         unsigned int tmp, p1, p2, ndiv, m1;
 244
 245         tmp = readl_be(priv->regs + REG_BCM6368_DDR_DMIPSPLLCFG);
 246         p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >> DMIPSPLLCFG_6368_P1_SHIFT;
 247         p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >> DMIPSPLLCFG_6368_P2_SHIFT;
 248         ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >>
 249                DMIPSPLLCFG_6368_NDIV_SHIFT;
 250
 251         tmp = readl_be(priv->regs + REG_BCM6368_DDR_DMIPSPLLDIV);
 252         m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >> DMIPSPLLDIV_6368_MDIV_SHIFT;
 253
 254         return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
 255 }
 256
 257 static ulong bcm63268_get_cpu_freq(struct bmips_cpu_priv *priv)
 258 {
 259         unsigned int mips_pll_fcvo;
 260
 261         mips_pll_fcvo = readl_be(priv->regs + REG_BCM63268_MISC_STRAPBUS);
 262         mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_63268_FCVO_MASK)
 263                         >> STRAPBUS_63268_FCVO_SHIFT;
 264
 265         switch (mips_pll_fcvo) {
 266         case 0x3:
 267         case 0xe:
 268                 return 320000000;
 269         case 0xa:
 270                 return 333000000;
 271         case 0x2:
 272         case 0xb:
 273         case 0xf:
 274                 return 400000000;
 275         default:
 276                 return 0;
 277         }
 278 }
 279
 280 static ulong bcm6838_get_cpu_freq(struct bmips_cpu_priv *priv)
 281 {
 282         unsigned int mips_viper_freq;
 283
 284         mips_viper_freq = readl_be(priv->regs + REG_BCM6838_OTP_BRCMBITS0);
 285         mips_viper_freq = (mips_viper_freq & VIPER_6838_FREQ_MASK)
 286                 >> VIPER_6838_FREQ_SHIFT;
 287
 288         switch (mips_viper_freq) {
 289         case 0x0:
 290                 return 600000000;
 291         case 0x1:
 292                 return 400000000;
 293         case 0x2:
 294                 return 240000000;
 295         default:
 296                 return 0;
 297         }
 298 }
 299
 300 static int bcm6328_get_cpu_count(struct bmips_cpu_priv *priv)
 301 {
 302         u32 val = readl_be(priv->regs + REG_BCM6328_OTP);
 303
 304         if (val & BCM6328_TP1_DISABLED)
 305                 return 1;
 306         else
 307                 return 2;
 308 }
 309
 310 static int bcm6345_get_cpu_count(struct bmips_cpu_priv *priv)
 311 {
 312         return 1;
 313 }
 314
 315 static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv)
 316 {
 317         return 2;
 318 }
 319
 320 static const struct bmips_cpu_hw bmips_cpu_bcm3380 = {
 321         .get_cpu_desc = bmips_short_cpu_desc,
 322         .get_cpu_freq = bcm3380_get_cpu_freq,
 323         .get_cpu_count = bcm6358_get_cpu_count,
 324 };
 325
 326 static const struct bmips_cpu_hw bmips_cpu_bcm6318 = {
 327         .get_cpu_desc = bmips_short_cpu_desc,
 328         .get_cpu_freq = bcm6318_get_cpu_freq,
 329         .get_cpu_count = bcm6345_get_cpu_count,
 330 };
 331
 332 static const struct bmips_cpu_hw bmips_cpu_bcm6328 = {
 333         .get_cpu_desc = bmips_long_cpu_desc,
 334         .get_cpu_freq = bcm6328_get_cpu_freq,
 335         .get_cpu_count = bcm6328_get_cpu_count,
 336 };
 337
 338 static const struct bmips_cpu_hw bmips_cpu_bcm6338 = {
 339         .get_cpu_desc = bmips_short_cpu_desc,
 340         .get_cpu_freq = bcm6338_get_cpu_freq,
 341         .get_cpu_count = bcm6345_get_cpu_count,
 342 };
 343
 344 static const struct bmips_cpu_hw bmips_cpu_bcm6348 = {
 345         .get_cpu_desc = bmips_short_cpu_desc,
 346         .get_cpu_freq = bcm6348_get_cpu_freq,
 347         .get_cpu_count = bcm6345_get_cpu_count,
 348 };
 349
 350 static const struct bmips_cpu_hw bmips_cpu_bcm6358 = {
 351         .get_cpu_desc = bmips_short_cpu_desc,
 352         .get_cpu_freq = bcm6358_get_cpu_freq,
 353         .get_cpu_count = bcm6358_get_cpu_count,
 354 };
 355
 356 static const struct bmips_cpu_hw bmips_cpu_bcm6362 = {
 357         .get_cpu_desc = bmips_short_cpu_desc,
 358         .get_cpu_freq = bcm6362_get_cpu_freq,
 359         .get_cpu_count = bcm6358_get_cpu_count,
 360 };
 361
 362 static const struct bmips_cpu_hw bmips_cpu_bcm6368 = {
 363         .get_cpu_desc = bmips_short_cpu_desc,
 364         .get_cpu_freq = bcm6368_get_cpu_freq,
 365         .get_cpu_count = bcm6358_get_cpu_count,
 366 };
 367
 368 static const struct bmips_cpu_hw bmips_cpu_bcm63268 = {
 369         .get_cpu_desc = bmips_long_cpu_desc,
 370         .get_cpu_freq = bcm63268_get_cpu_freq,
 371         .get_cpu_count = bcm6358_get_cpu_count,
 372 };
 373
 374 static const struct bmips_cpu_hw bmips_cpu_bcm6838 = {
 375         .get_cpu_desc = bmips_short_cpu_desc,
 376         .get_cpu_freq = bcm6838_get_cpu_freq,
 377         .get_cpu_count = bcm6358_get_cpu_count,
 378 };
 379
 380 /* Generic CPU Ops */
 381 static int bmips_cpu_get_desc(struct udevice *dev, char *buf, int size)
 382 {
 383         struct bmips_cpu_priv *priv = dev_get_priv(dev);
 384         const struct bmips_cpu_hw *hw = priv->hw;
 385
 386         return hw->get_cpu_desc(priv, buf, size);
 387 }
 388
 389 static int bmips_cpu_get_info(struct udevice *dev, struct cpu_info *info)
 390 {
 391         struct bmips_cpu_priv *priv = dev_get_priv(dev);
 392         const struct bmips_cpu_hw *hw = priv->hw;
 393
 394         info->cpu_freq = hw->get_cpu_freq(priv);
 395         info->features = BIT(CPU_FEAT_L1_CACHE);
 396         info->features |= BIT(CPU_FEAT_MMU);
 397         info->features |= BIT(CPU_FEAT_DEVICE_ID);
 398
 399         return 0;
 400 }
 401
 402 static int bmips_cpu_get_count(struct udevice *dev)
 403 {
 404         struct bmips_cpu_priv *priv = dev_get_priv(dev);
 405         const struct bmips_cpu_hw *hw = priv->hw;
 406
 407         return hw->get_cpu_count(priv);
 408 }
 409
 410 static int bmips_cpu_get_vendor(struct udevice *dev, char *buf, int size)
 411 {
 412         snprintf(buf, size, "Broadcom");
 413
 414         return 0;
 415 }
 416
 417 static const struct cpu_ops bmips_cpu_ops = {
 418         .get_desc = bmips_cpu_get_desc,
 419         .get_info = bmips_cpu_get_info,
 420         .get_count = bmips_cpu_get_count,
 421         .get_vendor = bmips_cpu_get_vendor,
 422 };
 423
 424 /* BMIPS CPU driver */
 425 int bmips_cpu_bind(struct udevice *dev)
 426 {
 427         struct cpu_platdata *plat = dev_get_parent_platdata(dev);
 428
 429         plat->cpu_id = dev_read_u32_default(dev, "reg", -1);
 430         plat->device_id = read_c0_prid();
 431
 432         return 0;
 433 }
 434
 435 int bmips_cpu_probe(struct udevice *dev)
 436 {
 437         struct bmips_cpu_priv *priv = dev_get_priv(dev);
 438         const struct bmips_cpu_hw *hw =
 439                 (const struct bmips_cpu_hw *)dev_get_driver_data(dev);
 440
 441         priv->regs = dev_remap_addr(dev_get_parent(dev));
 442         if (!priv->regs)
 443                 return -EINVAL;
 444
 445         priv->hw = hw;
 446
 447         return 0;
 448 }
 449
 450 static const struct udevice_id bmips_cpu_ids[] = {
 451         {
 452                 .compatible = "brcm,bcm3380-cpu",
 453                 .data = (ulong)&bmips_cpu_bcm3380,
 454         }, {
 455                 .compatible = "brcm,bcm6318-cpu",
 456                 .data = (ulong)&bmips_cpu_bcm6318,
 457         }, {
 458                 .compatible = "brcm,bcm6328-cpu",
 459                 .data = (ulong)&bmips_cpu_bcm6328,
 460         }, {
 461                 .compatible = "brcm,bcm6338-cpu",
 462                 .data = (ulong)&bmips_cpu_bcm6338,
 463         }, {
 464                 .compatible = "brcm,bcm6348-cpu",
 465                 .data = (ulong)&bmips_cpu_bcm6348,
 466         }, {
 467                 .compatible = "brcm,bcm6358-cpu",
 468                 .data = (ulong)&bmips_cpu_bcm6358,
 469         }, {
 470                 .compatible = "brcm,bcm6362-cpu",
 471                 .data = (ulong)&bmips_cpu_bcm6362,
 472         }, {
 473                 .compatible = "brcm,bcm6368-cpu",
 474                 .data = (ulong)&bmips_cpu_bcm6368,
 475         }, {
 476                 .compatible = "brcm,bcm63268-cpu",
 477                 .data = (ulong)&bmips_cpu_bcm63268,
 478         }, {
 479                 .compatible = "brcm,bcm6838-cpu",
 480                 .data = (ulong)&bmips_cpu_bcm6838,
 481         },
 482         { /* sentinel */ }
 483 };
 484
 485 U_BOOT_DRIVER(bmips_cpu_drv) = {
 486         .name = "bmips_cpu",
 487         .id = UCLASS_CPU,
 488         .of_match = bmips_cpu_ids,
 489         .bind = bmips_cpu_bind,
 490         .probe = bmips_cpu_probe,
 491         .priv_auto_alloc_size = sizeof(struct bmips_cpu_priv),
 492         .ops = &bmips_cpu_ops,
 493         .flags = DM_FLAG_PRE_RELOC,
 494 };
 495
 496 #ifdef CONFIG_DISPLAY_CPUINFO
 497 int print_cpuinfo(void)
 498 {
 499         struct cpu_info cpu;
 500         struct udevice *dev;
 501         int err;
 502         char desc[100];
 503
 504         err = uclass_get_device(UCLASS_CPU, 0, &dev);
 505         if (err)
 506                 return 0;
 507
 508         err = cpu_get_info(dev, &cpu);
 509         if (err)
 510                 return 0;
 511
 512         err = cpu_get_desc(dev, desc, sizeof(desc));
 513         if (err)
 514                 return 0;
 515
 516         printf("Chip ID: %s, MIPS: ", desc);
 517         print_freq(cpu.cpu_freq, "\n");
 518
 519         return 0;
 520 }
 521 #endif