2 * SuperH Timer Support - TMU
4 * Copyright (C) 2009 Magnus Damm
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/ioport.h>
25 #include <linux/delay.h>
27 #include <linux/clk.h>
28 #include <linux/irq.h>
29 #include <linux/err.h>
30 #include <linux/clocksource.h>
31 #include <linux/clockchips.h>
32 #include <linux/sh_timer.h>
33 #include <linux/slab.h>
36 void __iomem *mapbase;
38 struct irqaction irqaction;
39 struct platform_device *pdev;
41 unsigned long periodic;
42 struct clock_event_device ced;
43 struct clocksource cs;
46 static DEFINE_SPINLOCK(sh_tmu_lock);
48 #define TSTR -1 /* shared register */
49 #define TCOR 0 /* channel register */
50 #define TCNT 1 /* channel register */
51 #define TCR 2 /* channel register */
53 static inline unsigned long sh_tmu_read(struct sh_tmu_priv *p, int reg_nr)
55 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
56 void __iomem *base = p->mapbase;
60 return ioread8(base - cfg->channel_offset);
65 return ioread16(base + offs);
67 return ioread32(base + offs);
70 static inline void sh_tmu_write(struct sh_tmu_priv *p, int reg_nr,
73 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
74 void __iomem *base = p->mapbase;
78 iowrite8(value, base - cfg->channel_offset);
85 iowrite16(value, base + offs);
87 iowrite32(value, base + offs);
90 static void sh_tmu_start_stop_ch(struct sh_tmu_priv *p, int start)
92 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
93 unsigned long flags, value;
95 /* start stop register shared by multiple timer channels */
96 spin_lock_irqsave(&sh_tmu_lock, flags);
97 value = sh_tmu_read(p, TSTR);
100 value |= 1 << cfg->timer_bit;
102 value &= ~(1 << cfg->timer_bit);
104 sh_tmu_write(p, TSTR, value);
105 spin_unlock_irqrestore(&sh_tmu_lock, flags);
108 static int sh_tmu_enable(struct sh_tmu_priv *p)
113 ret = clk_enable(p->clk);
115 dev_err(&p->pdev->dev, "cannot enable clock\n");
119 /* make sure channel is disabled */
120 sh_tmu_start_stop_ch(p, 0);
122 /* maximum timeout */
123 sh_tmu_write(p, TCOR, 0xffffffff);
124 sh_tmu_write(p, TCNT, 0xffffffff);
126 /* configure channel to parent clock / 4, irq off */
127 p->rate = clk_get_rate(p->clk) / 4;
128 sh_tmu_write(p, TCR, 0x0000);
131 sh_tmu_start_stop_ch(p, 1);
136 static void sh_tmu_disable(struct sh_tmu_priv *p)
138 /* disable channel */
139 sh_tmu_start_stop_ch(p, 0);
141 /* disable interrupts in TMU block */
142 sh_tmu_write(p, TCR, 0x0000);
148 static void sh_tmu_set_next(struct sh_tmu_priv *p, unsigned long delta,
152 sh_tmu_start_stop_ch(p, 0);
154 /* acknowledge interrupt */
157 /* enable interrupt */
158 sh_tmu_write(p, TCR, 0x0020);
160 /* reload delta value in case of periodic timer */
162 sh_tmu_write(p, TCOR, delta);
164 sh_tmu_write(p, TCOR, 0xffffffff);
166 sh_tmu_write(p, TCNT, delta);
169 sh_tmu_start_stop_ch(p, 1);
172 static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
174 struct sh_tmu_priv *p = dev_id;
176 /* disable or acknowledge interrupt */
177 if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT)
178 sh_tmu_write(p, TCR, 0x0000);
180 sh_tmu_write(p, TCR, 0x0020);
182 /* notify clockevent layer */
183 p->ced.event_handler(&p->ced);
187 static struct sh_tmu_priv *cs_to_sh_tmu(struct clocksource *cs)
189 return container_of(cs, struct sh_tmu_priv, cs);
192 static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
194 struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
196 return sh_tmu_read(p, TCNT) ^ 0xffffffff;
199 static int sh_tmu_clocksource_enable(struct clocksource *cs)
201 struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
204 ret = sh_tmu_enable(p);
208 /* TODO: calculate good shift from rate and counter bit width */
210 cs->mult = clocksource_hz2mult(p->rate, cs->shift);
214 static void sh_tmu_clocksource_disable(struct clocksource *cs)
216 sh_tmu_disable(cs_to_sh_tmu(cs));
219 static int sh_tmu_register_clocksource(struct sh_tmu_priv *p,
220 char *name, unsigned long rating)
222 struct clocksource *cs = &p->cs;
226 cs->read = sh_tmu_clocksource_read;
227 cs->enable = sh_tmu_clocksource_enable;
228 cs->disable = sh_tmu_clocksource_disable;
229 cs->mask = CLOCKSOURCE_MASK(32);
230 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
231 dev_info(&p->pdev->dev, "used as clock source\n");
232 clocksource_register(cs);
236 static struct sh_tmu_priv *ced_to_sh_tmu(struct clock_event_device *ced)
238 return container_of(ced, struct sh_tmu_priv, ced);
241 static void sh_tmu_clock_event_start(struct sh_tmu_priv *p, int periodic)
243 struct clock_event_device *ced = &p->ced;
247 /* TODO: calculate good shift from rate and counter bit width */
250 ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
251 ced->max_delta_ns = clockevent_delta2ns(0xffffffff, ced);
252 ced->min_delta_ns = 5000;
255 p->periodic = (p->rate + HZ/2) / HZ;
256 sh_tmu_set_next(p, p->periodic, 1);
260 static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
261 struct clock_event_device *ced)
263 struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
266 /* deal with old setting first */
268 case CLOCK_EVT_MODE_PERIODIC:
269 case CLOCK_EVT_MODE_ONESHOT:
278 case CLOCK_EVT_MODE_PERIODIC:
279 dev_info(&p->pdev->dev, "used for periodic clock events\n");
280 sh_tmu_clock_event_start(p, 1);
282 case CLOCK_EVT_MODE_ONESHOT:
283 dev_info(&p->pdev->dev, "used for oneshot clock events\n");
284 sh_tmu_clock_event_start(p, 0);
286 case CLOCK_EVT_MODE_UNUSED:
290 case CLOCK_EVT_MODE_SHUTDOWN:
296 static int sh_tmu_clock_event_next(unsigned long delta,
297 struct clock_event_device *ced)
299 struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
301 BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
303 /* program new delta value */
304 sh_tmu_set_next(p, delta, 0);
308 static void sh_tmu_register_clockevent(struct sh_tmu_priv *p,
309 char *name, unsigned long rating)
311 struct clock_event_device *ced = &p->ced;
314 memset(ced, 0, sizeof(*ced));
317 ced->features = CLOCK_EVT_FEAT_PERIODIC;
318 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
319 ced->rating = rating;
320 ced->cpumask = cpumask_of(0);
321 ced->set_next_event = sh_tmu_clock_event_next;
322 ced->set_mode = sh_tmu_clock_event_mode;
324 dev_info(&p->pdev->dev, "used for clock events\n");
325 clockevents_register_device(ced);
327 ret = setup_irq(p->irqaction.irq, &p->irqaction);
329 dev_err(&p->pdev->dev, "failed to request irq %d\n",
335 static int sh_tmu_register(struct sh_tmu_priv *p, char *name,
336 unsigned long clockevent_rating,
337 unsigned long clocksource_rating)
339 if (clockevent_rating)
340 sh_tmu_register_clockevent(p, name, clockevent_rating);
341 else if (clocksource_rating)
342 sh_tmu_register_clocksource(p, name, clocksource_rating);
347 static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
349 struct sh_timer_config *cfg = pdev->dev.platform_data;
350 struct resource *res;
354 memset(p, 0, sizeof(*p));
358 dev_err(&p->pdev->dev, "missing platform data\n");
362 platform_set_drvdata(pdev, p);
364 res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
366 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
370 irq = platform_get_irq(p->pdev, 0);
372 dev_err(&p->pdev->dev, "failed to get irq\n");
376 /* map memory, let mapbase point to our channel */
377 p->mapbase = ioremap_nocache(res->start, resource_size(res));
378 if (p->mapbase == NULL) {
379 dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
383 /* setup data for setup_irq() (too early for request_irq()) */
384 p->irqaction.name = dev_name(&p->pdev->dev);
385 p->irqaction.handler = sh_tmu_interrupt;
386 p->irqaction.dev_id = p;
387 p->irqaction.irq = irq;
388 p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
389 IRQF_IRQPOLL | IRQF_NOBALANCING;
391 /* get hold of clock */
392 p->clk = clk_get(&p->pdev->dev, "tmu_fck");
393 if (IS_ERR(p->clk)) {
394 dev_warn(&p->pdev->dev, "using deprecated clock lookup\n");
395 p->clk = clk_get(&p->pdev->dev, cfg->clk);
396 if (IS_ERR(p->clk)) {
397 dev_err(&p->pdev->dev, "cannot get clock\n");
398 ret = PTR_ERR(p->clk);
403 return sh_tmu_register(p, (char *)dev_name(&p->pdev->dev),
404 cfg->clockevent_rating,
405 cfg->clocksource_rating);
412 static int __devinit sh_tmu_probe(struct platform_device *pdev)
414 struct sh_tmu_priv *p = platform_get_drvdata(pdev);
418 dev_info(&pdev->dev, "kept as earlytimer\n");
422 p = kmalloc(sizeof(*p), GFP_KERNEL);
424 dev_err(&pdev->dev, "failed to allocate driver data\n");
428 ret = sh_tmu_setup(p, pdev);
431 platform_set_drvdata(pdev, NULL);
436 static int __devexit sh_tmu_remove(struct platform_device *pdev)
438 return -EBUSY; /* cannot unregister clockevent and clocksource */
441 static struct platform_driver sh_tmu_device_driver = {
442 .probe = sh_tmu_probe,
443 .remove = __devexit_p(sh_tmu_remove),
449 static int __init sh_tmu_init(void)
451 return platform_driver_register(&sh_tmu_device_driver);
454 static void __exit sh_tmu_exit(void)
456 platform_driver_unregister(&sh_tmu_device_driver);
459 early_platform_init("earlytimer", &sh_tmu_device_driver);
460 module_init(sh_tmu_init);
461 module_exit(sh_tmu_exit);
463 MODULE_AUTHOR("Magnus Damm");
464 MODULE_DESCRIPTION("SuperH TMU Timer Driver");
465 MODULE_LICENSE("GPL v2");