1 #include <linux/clocksource.h>
2 #include <linux/string.h>
3 #include <linux/errno.h>
4 #include <linux/timex.h>
5 #include <linux/init.h>
7 #include <asm/pgtable.h>
10 #include <asm/mach_timer.h>
12 #define CYCLONE_CBAR_ADDR 0xFEB00CD0 /* base address ptr */
13 #define CYCLONE_PMCC_OFFSET 0x51A0 /* offset to control register */
14 #define CYCLONE_MPCS_OFFSET 0x51A8 /* offset to select register */
15 #define CYCLONE_MPMC_OFFSET 0x51D0 /* offset to count register */
16 #define CYCLONE_TIMER_FREQ 99780000 /* 100Mhz, but not really */
17 #define CYCLONE_TIMER_MASK CLOCKSOURCE_MASK(32) /* 32 bit mask */
20 static void __iomem *cyclone_ptr;
22 static cycle_t read_cyclone(struct clocksource *cs)
24 return (cycle_t)readl(cyclone_ptr);
27 static struct clocksource clocksource_cyclone = {
31 .mask = CYCLONE_TIMER_MASK,
34 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
37 static int __init init_cyclone_clocksource(void)
39 unsigned long base; /* saved value from CBAR */
41 u32 __iomem* volatile cyclone_timer; /* Cyclone MPMC0 register */
45 /* make sure we're on a summit box: */
49 printk(KERN_INFO "Summit chipset: Starting Cyclone Counter.\n");
51 /* find base address: */
52 offset = CYCLONE_CBAR_ADDR;
53 reg = ioremap_nocache(offset, sizeof(reg));
55 printk(KERN_ERR "Summit chipset: Could not find valid CBAR register.\n");
58 /* even on 64bit systems, this is only 32bits: */
61 printk(KERN_ERR "Summit chipset: Could not find valid CBAR value.\n");
67 offset = base + CYCLONE_PMCC_OFFSET;
68 reg = ioremap_nocache(offset, sizeof(reg));
70 printk(KERN_ERR "Summit chipset: Could not find valid PMCC register.\n");
73 writel(0x00000001,reg);
77 offset = base + CYCLONE_MPCS_OFFSET;
78 reg = ioremap_nocache(offset, sizeof(reg));
80 printk(KERN_ERR "Summit chipset: Could not find valid MPCS register.\n");
83 writel(0x00000001,reg);
86 /* map in cyclone_timer: */
87 offset = base + CYCLONE_MPMC_OFFSET;
88 cyclone_timer = ioremap_nocache(offset, sizeof(u64));
90 printk(KERN_ERR "Summit chipset: Could not find valid MPMC register.\n");
94 /* quick test to make sure its ticking: */
95 for (i = 0; i < 3; i++){
96 u32 old = readl(cyclone_timer);
102 if (readl(cyclone_timer) == old) {
103 printk(KERN_ERR "Summit chipset: Counter not counting! DISABLED\n");
104 iounmap(cyclone_timer);
105 cyclone_timer = NULL;
109 cyclone_ptr = cyclone_timer;
111 /* sort out mult/shift values: */
112 clocksource_cyclone.shift = 22;
113 clocksource_cyclone.mult = clocksource_hz2mult(CYCLONE_TIMER_FREQ,
114 clocksource_cyclone.shift);
116 return clocksource_register(&clocksource_cyclone);
119 arch_initcall(init_cyclone_clocksource);