drivers/clk/tegra/clk-tegra30.c

   1 /*
   2  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/delay.h>
  19 #include <linux/clk.h>
  20 #include <linux/clk-provider.h>
  21 #include <linux/clkdev.h>
  22 #include <linux/of.h>
  23 #include <linux/of_address.h>
  24 #include <linux/clk/tegra.h>
  25 #include <linux/tegra-powergate.h>
  26
  27 #include "clk.h"
  28
  29 #define RST_DEVICES_L 0x004
  30 #define RST_DEVICES_H 0x008
  31 #define RST_DEVICES_U 0x00c
  32 #define RST_DEVICES_V 0x358
  33 #define RST_DEVICES_W 0x35c
  34 #define RST_DEVICES_SET_L 0x300
  35 #define RST_DEVICES_CLR_L 0x304
  36 #define RST_DEVICES_SET_H 0x308
  37 #define RST_DEVICES_CLR_H 0x30c
  38 #define RST_DEVICES_SET_U 0x310
  39 #define RST_DEVICES_CLR_U 0x314
  40 #define RST_DEVICES_SET_V 0x430
  41 #define RST_DEVICES_CLR_V 0x434
  42 #define RST_DEVICES_SET_W 0x438
  43 #define RST_DEVICES_CLR_W 0x43c
  44 #define RST_DEVICES_NUM 5
  45
  46 #define CLK_OUT_ENB_L 0x010
  47 #define CLK_OUT_ENB_H 0x014
  48 #define CLK_OUT_ENB_U 0x018
  49 #define CLK_OUT_ENB_V 0x360
  50 #define CLK_OUT_ENB_W 0x364
  51 #define CLK_OUT_ENB_SET_L 0x320
  52 #define CLK_OUT_ENB_CLR_L 0x324
  53 #define CLK_OUT_ENB_SET_H 0x328
  54 #define CLK_OUT_ENB_CLR_H 0x32c
  55 #define CLK_OUT_ENB_SET_U 0x330
  56 #define CLK_OUT_ENB_CLR_U 0x334
  57 #define CLK_OUT_ENB_SET_V 0x440
  58 #define CLK_OUT_ENB_CLR_V 0x444
  59 #define CLK_OUT_ENB_SET_W 0x448
  60 #define CLK_OUT_ENB_CLR_W 0x44c
  61 #define CLK_OUT_ENB_NUM 5
  62
  63 #define OSC_CTRL                        0x50
  64 #define OSC_CTRL_OSC_FREQ_MASK          (0xF<<28)
  65 #define OSC_CTRL_OSC_FREQ_13MHZ         (0X0<<28)
  66 #define OSC_CTRL_OSC_FREQ_19_2MHZ       (0X4<<28)
  67 #define OSC_CTRL_OSC_FREQ_12MHZ         (0X8<<28)
  68 #define OSC_CTRL_OSC_FREQ_26MHZ         (0XC<<28)
  69 #define OSC_CTRL_OSC_FREQ_16_8MHZ       (0X1<<28)
  70 #define OSC_CTRL_OSC_FREQ_38_4MHZ       (0X5<<28)
  71 #define OSC_CTRL_OSC_FREQ_48MHZ         (0X9<<28)
  72 #define OSC_CTRL_MASK                   (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
  73
  74 #define OSC_CTRL_PLL_REF_DIV_MASK       (3<<26)
  75 #define OSC_CTRL_PLL_REF_DIV_1          (0<<26)
  76 #define OSC_CTRL_PLL_REF_DIV_2          (1<<26)
  77 #define OSC_CTRL_PLL_REF_DIV_4          (2<<26)
  78
  79 #define OSC_FREQ_DET                    0x58
  80 #define OSC_FREQ_DET_TRIG               BIT(31)
  81
  82 #define OSC_FREQ_DET_STATUS             0x5c
  83 #define OSC_FREQ_DET_BUSY               BIT(31)
  84 #define OSC_FREQ_DET_CNT_MASK           0xffff
  85
  86 #define CCLKG_BURST_POLICY 0x368
  87 #define SUPER_CCLKG_DIVIDER 0x36c
  88 #define CCLKLP_BURST_POLICY 0x370
  89 #define SUPER_CCLKLP_DIVIDER 0x374
  90 #define SCLK_BURST_POLICY 0x028
  91 #define SUPER_SCLK_DIVIDER 0x02c
  92
  93 #define SYSTEM_CLK_RATE 0x030
  94
  95 #define PLLC_BASE 0x80
  96 #define PLLC_MISC 0x8c
  97 #define PLLM_BASE 0x90
  98 #define PLLM_MISC 0x9c
  99 #define PLLP_BASE 0xa0
 100 #define PLLP_MISC 0xac
 101 #define PLLX_BASE 0xe0
 102 #define PLLX_MISC 0xe4
 103 #define PLLD_BASE 0xd0
 104 #define PLLD_MISC 0xdc
 105 #define PLLD2_BASE 0x4b8
 106 #define PLLD2_MISC 0x4bc
 107 #define PLLE_BASE 0xe8
 108 #define PLLE_MISC 0xec
 109 #define PLLA_BASE 0xb0
 110 #define PLLA_MISC 0xbc
 111 #define PLLU_BASE 0xc0
 112 #define PLLU_MISC 0xcc
 113
 114 #define PLL_MISC_LOCK_ENABLE 18
 115 #define PLLDU_MISC_LOCK_ENABLE 22
 116 #define PLLE_MISC_LOCK_ENABLE 9
 117
 118 #define PLL_BASE_LOCK 27
 119 #define PLLE_MISC_LOCK 11
 120
 121 #define PLLE_AUX 0x48c
 122 #define PLLC_OUT 0x84
 123 #define PLLM_OUT 0x94
 124 #define PLLP_OUTA 0xa4
 125 #define PLLP_OUTB 0xa8
 126 #define PLLA_OUT 0xb4
 127
 128 #define AUDIO_SYNC_CLK_I2S0 0x4a0
 129 #define AUDIO_SYNC_CLK_I2S1 0x4a4
 130 #define AUDIO_SYNC_CLK_I2S2 0x4a8
 131 #define AUDIO_SYNC_CLK_I2S3 0x4ac
 132 #define AUDIO_SYNC_CLK_I2S4 0x4b0
 133 #define AUDIO_SYNC_CLK_SPDIF 0x4b4
 134
 135 #define PMC_CLK_OUT_CNTRL 0x1a8
 136
 137 #define CLK_SOURCE_I2S0 0x1d8
 138 #define CLK_SOURCE_I2S1 0x100
 139 #define CLK_SOURCE_I2S2 0x104
 140 #define CLK_SOURCE_I2S3 0x3bc
 141 #define CLK_SOURCE_I2S4 0x3c0
 142 #define CLK_SOURCE_SPDIF_OUT 0x108
 143 #define CLK_SOURCE_SPDIF_IN 0x10c
 144 #define CLK_SOURCE_PWM 0x110
 145 #define CLK_SOURCE_D_AUDIO 0x3d0
 146 #define CLK_SOURCE_DAM0 0x3d8
 147 #define CLK_SOURCE_DAM1 0x3dc
 148 #define CLK_SOURCE_DAM2 0x3e0
 149 #define CLK_SOURCE_HDA 0x428
 150 #define CLK_SOURCE_HDA2CODEC_2X 0x3e4
 151 #define CLK_SOURCE_SBC1 0x134
 152 #define CLK_SOURCE_SBC2 0x118
 153 #define CLK_SOURCE_SBC3 0x11c
 154 #define CLK_SOURCE_SBC4 0x1b4
 155 #define CLK_SOURCE_SBC5 0x3c8
 156 #define CLK_SOURCE_SBC6 0x3cc
 157 #define CLK_SOURCE_SATA_OOB 0x420
 158 #define CLK_SOURCE_SATA 0x424
 159 #define CLK_SOURCE_NDFLASH 0x160
 160 #define CLK_SOURCE_NDSPEED 0x3f8
 161 #define CLK_SOURCE_VFIR 0x168
 162 #define CLK_SOURCE_SDMMC1 0x150
 163 #define CLK_SOURCE_SDMMC2 0x154
 164 #define CLK_SOURCE_SDMMC3 0x1bc
 165 #define CLK_SOURCE_SDMMC4 0x164
 166 #define CLK_SOURCE_VDE 0x1c8
 167 #define CLK_SOURCE_CSITE 0x1d4
 168 #define CLK_SOURCE_LA 0x1f8
 169 #define CLK_SOURCE_OWR 0x1cc
 170 #define CLK_SOURCE_NOR 0x1d0
 171 #define CLK_SOURCE_MIPI 0x174
 172 #define CLK_SOURCE_I2C1 0x124
 173 #define CLK_SOURCE_I2C2 0x198
 174 #define CLK_SOURCE_I2C3 0x1b8
 175 #define CLK_SOURCE_I2C4 0x3c4
 176 #define CLK_SOURCE_I2C5 0x128
 177 #define CLK_SOURCE_UARTA 0x178
 178 #define CLK_SOURCE_UARTB 0x17c
 179 #define CLK_SOURCE_UARTC 0x1a0
 180 #define CLK_SOURCE_UARTD 0x1c0
 181 #define CLK_SOURCE_UARTE 0x1c4
 182 #define CLK_SOURCE_VI 0x148
 183 #define CLK_SOURCE_VI_SENSOR 0x1a8
 184 #define CLK_SOURCE_3D 0x158
 185 #define CLK_SOURCE_3D2 0x3b0
 186 #define CLK_SOURCE_2D 0x15c
 187 #define CLK_SOURCE_EPP 0x16c
 188 #define CLK_SOURCE_MPE 0x170
 189 #define CLK_SOURCE_HOST1X 0x180
 190 #define CLK_SOURCE_CVE 0x140
 191 #define CLK_SOURCE_TVO 0x188
 192 #define CLK_SOURCE_DTV 0x1dc
 193 #define CLK_SOURCE_HDMI 0x18c
 194 #define CLK_SOURCE_TVDAC 0x194
 195 #define CLK_SOURCE_DISP1 0x138
 196 #define CLK_SOURCE_DISP2 0x13c
 197 #define CLK_SOURCE_DSIB 0xd0
 198 #define CLK_SOURCE_TSENSOR 0x3b8
 199 #define CLK_SOURCE_ACTMON 0x3e8
 200 #define CLK_SOURCE_EXTERN1 0x3ec
 201 #define CLK_SOURCE_EXTERN2 0x3f0
 202 #define CLK_SOURCE_EXTERN3 0x3f4
 203 #define CLK_SOURCE_I2CSLOW 0x3fc
 204 #define CLK_SOURCE_SE 0x42c
 205 #define CLK_SOURCE_MSELECT 0x3b4
 206 #define CLK_SOURCE_EMC 0x19c
 207
 208 #define AUDIO_SYNC_DOUBLER 0x49c
 209
 210 #define PMC_CTRL 0
 211 #define PMC_CTRL_BLINK_ENB 7
 212
 213 #define PMC_DPD_PADS_ORIDE 0x1c
 214 #define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
 215 #define PMC_BLINK_TIMER 0x40
 216
 217 #define UTMIP_PLL_CFG2 0x488
 218 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
 219 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
 220 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
 221 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
 222 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
 223
 224 #define UTMIP_PLL_CFG1 0x484
 225 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
 226 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
 227 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
 228 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
 229 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
 230
 231 /* Tegra CPU clock and reset control regs */
 232 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX          0x4c
 233 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET      0x340
 234 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR      0x344
 235 #define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR    0x34c
 236 #define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS     0x470
 237
 238 #define CPU_CLOCK(cpu)  (0x1 << (8 + cpu))
 239 #define CPU_RESET(cpu)  (0x1111ul << (cpu))
 240
 241 #define CLK_RESET_CCLK_BURST    0x20
 242 #define CLK_RESET_CCLK_DIVIDER  0x24
 243 #define CLK_RESET_PLLX_BASE     0xe0
 244 #define CLK_RESET_PLLX_MISC     0xe4
 245
 246 #define CLK_RESET_SOURCE_CSITE  0x1d4
 247
 248 #define CLK_RESET_CCLK_BURST_POLICY_SHIFT       28
 249 #define CLK_RESET_CCLK_RUN_POLICY_SHIFT         4
 250 #define CLK_RESET_CCLK_IDLE_POLICY_SHIFT        0
 251 #define CLK_RESET_CCLK_IDLE_POLICY              1
 252 #define CLK_RESET_CCLK_RUN_POLICY               2
 253 #define CLK_RESET_CCLK_BURST_POLICY_PLLX        8
 254
 255 #ifdef CONFIG_PM_SLEEP
 256 static struct cpu_clk_suspend_context {
 257         u32 pllx_misc;
 258         u32 pllx_base;
 259
 260         u32 cpu_burst;
 261         u32 clk_csite_src;
 262         u32 cclk_divider;
 263 } tegra30_cpu_clk_sctx;
 264 #endif
 265
 266 static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
 267
 268 static void __iomem *clk_base;
 269 static void __iomem *pmc_base;
 270 static unsigned long input_freq;
 271
 272 static DEFINE_SPINLOCK(clk_doubler_lock);
 273 static DEFINE_SPINLOCK(clk_out_lock);
 274 static DEFINE_SPINLOCK(pll_div_lock);
 275 static DEFINE_SPINLOCK(cml_lock);
 276 static DEFINE_SPINLOCK(pll_d_lock);
 277 static DEFINE_SPINLOCK(sysrate_lock);
 278
 279 #define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
 280                             _clk_num, _regs, _gate_flags, _clk_id)      \
 281         TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset,     \
 282                         30, 2, 0, 0, 8, 1, 0, _regs, _clk_num,          \
 283                         periph_clk_enb_refcnt, _gate_flags, _clk_id)
 284
 285 #define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \
 286                             _clk_num, _regs, _gate_flags, _clk_id)      \
 287         TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset,     \
 288                         30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,     \
 289                         _regs, _clk_num, periph_clk_enb_refcnt,         \
 290                         _gate_flags, _clk_id)
 291
 292 #define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \
 293                              _clk_num, _regs, _gate_flags, _clk_id)     \
 294         TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset,     \
 295                         29, 3, 0, 0, 8, 1, 0, _regs, _clk_num,          \
 296                         periph_clk_enb_refcnt, _gate_flags, _clk_id)
 297
 298 #define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \
 299                             _clk_num, _regs, _gate_flags, _clk_id)      \
 300         TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset,     \
 301                         30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,    \
 302                         _clk_num, periph_clk_enb_refcnt, _gate_flags,   \
 303                         _clk_id)
 304
 305 #define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\
 306                              _clk_num, _regs, _clk_id)                  \
 307         TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset,     \
 308                         30, 2, 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs,  \
 309                         _clk_num, periph_clk_enb_refcnt, 0, _clk_id)
 310
 311 #define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \
 312                               _mux_shift, _mux_width, _clk_num, _regs,  \
 313                               _gate_flags, _clk_id)                     \
 314         TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset,     \
 315                         _mux_shift, _mux_width, 0, 0, 0, 0, 0, _regs,   \
 316                         _clk_num, periph_clk_enb_refcnt, _gate_flags,   \
 317                         _clk_id)
 318
 319 /*
 320  * IDs assigned here must be in sync with DT bindings definition
 321  * for Tegra30 clocks.
 322  */
 323 enum tegra30_clk {
 324         cpu, rtc = 4, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1, ndflash,
 325         sdmmc1, sdmmc4, pwm = 17, i2s2, epp, gr2d = 21, usbd, isp, gr3d,
 326         disp2 = 26, disp1, host1x, vcp, i2s0, cop_cache, mc, ahbdma, apbdma,
 327         kbc = 36, statmon, pmc, kfuse = 40, sbc1, nor, sbc2 = 44, sbc3 = 46,
 328         i2c5, dsia, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
 329         usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
 330         pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2cslow,
 331         dsib, irama = 84, iramb, iramc, iramd, cram2, audio_2x = 90, csus = 92,
 332         cdev1, cdev2, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4,
 333         i2c4, sbc5, sbc6, d_audio, apbif, dam0, dam1, dam2, hda2codec_2x,
 334         atomics, audio0_2x, audio1_2x, audio2_2x, audio3_2x, audio4_2x,
 335         spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda,
 336         se = 127, hda2hdmi, sata_cold, uartb = 160, vfir, spdif_in, spdif_out,
 337         vi, vi_sensor, fuse, fuse_burn, cve, tvo, clk_32k, clk_m, clk_m_div2,
 338         clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_m, pll_m_out1, pll_p,
 339         pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_a, pll_a_out0,
 340         pll_d, pll_d_out0, pll_d2, pll_d2_out0, pll_u, pll_x, pll_x_out0, pll_e,
 341         spdif_in_sync, i2s0_sync, i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync,
 342         vimclk_sync, audio0, audio1, audio2, audio3, audio4, spdif, clk_out_1,
 343         clk_out_2, clk_out_3, sclk, blink, cclk_g, cclk_lp, twd, cml0, cml1,
 344         hclk, pclk, clk_out_1_mux = 300, clk_max
 345 };
 346
 347 static struct clk *clks[clk_max];
 348 static struct clk_onecell_data clk_data;
 349
 350 /*
 351  * Structure defining the fields for USB UTMI clocks Parameters.
 352  */
 353 struct utmi_clk_param {
 354         /* Oscillator Frequency in KHz */
 355         u32 osc_frequency;
 356         /* UTMIP PLL Enable Delay Count  */
 357         u8 enable_delay_count;
 358         /* UTMIP PLL Stable count */
 359         u8 stable_count;
 360         /*  UTMIP PLL Active delay count */
 361         u8 active_delay_count;
 362         /* UTMIP PLL Xtal frequency count */
 363         u8 xtal_freq_count;
 364 };
 365
 366 static const struct utmi_clk_param utmi_parameters[] = {
 367 /*      OSC_FREQUENCY, ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */
 368         {13000000,     0x02,       0x33,       0x05,       0x7F},
 369         {19200000,     0x03,       0x4B,       0x06,       0xBB},
 370         {12000000,     0x02,       0x2F,       0x04,       0x76},
 371         {26000000,     0x04,       0x66,       0x09,       0xFE},
 372         {16800000,     0x03,       0x41,       0x0A,       0xA4},
 373 };
 374
 375 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
 376         { 12000000, 1040000000, 520,  6, 1, 8},
 377         { 13000000, 1040000000, 480,  6, 1, 8},
 378         { 16800000, 1040000000, 495,  8, 1, 8}, /* actual: 1039.5 MHz */
 379         { 19200000, 1040000000, 325,  6, 1, 6},
 380         { 26000000, 1040000000, 520, 13, 1, 8},
 381
 382         { 12000000, 832000000, 416,  6, 1, 8},
 383         { 13000000, 832000000, 832, 13, 1, 8},
 384         { 16800000, 832000000, 396,  8, 1, 8},  /* actual: 831.6 MHz */
 385         { 19200000, 832000000, 260,  6, 1, 8},
 386         { 26000000, 832000000, 416, 13, 1, 8},
 387
 388         { 12000000, 624000000, 624, 12, 1, 8},
 389         { 13000000, 624000000, 624, 13, 1, 8},
 390         { 16800000, 600000000, 520, 14, 1, 8},
 391         { 19200000, 624000000, 520, 16, 1, 8},
 392         { 26000000, 624000000, 624, 26, 1, 8},
 393
 394         { 12000000, 600000000, 600, 12, 1, 8},
 395         { 13000000, 600000000, 600, 13, 1, 8},
 396         { 16800000, 600000000, 500, 14, 1, 8},
 397         { 19200000, 600000000, 375, 12, 1, 6},
 398         { 26000000, 600000000, 600, 26, 1, 8},
 399
 400         { 12000000, 520000000, 520, 12, 1, 8},
 401         { 13000000, 520000000, 520, 13, 1, 8},
 402         { 16800000, 520000000, 495, 16, 1, 8},  /* actual: 519.75 MHz */
 403         { 19200000, 520000000, 325, 12, 1, 6},
 404         { 26000000, 520000000, 520, 26, 1, 8},
 405
 406         { 12000000, 416000000, 416, 12, 1, 8},
 407         { 13000000, 416000000, 416, 13, 1, 8},
 408         { 16800000, 416000000, 396, 16, 1, 8},  /* actual: 415.8 MHz */
 409         { 19200000, 416000000, 260, 12, 1, 6},
 410         { 26000000, 416000000, 416, 26, 1, 8},
 411         { 0, 0, 0, 0, 0, 0 },
 412 };
 413
 414 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
 415         { 12000000, 666000000, 666, 12, 1, 8},
 416         { 13000000, 666000000, 666, 13, 1, 8},
 417         { 16800000, 666000000, 555, 14, 1, 8},
 418         { 19200000, 666000000, 555, 16, 1, 8},
 419         { 26000000, 666000000, 666, 26, 1, 8},
 420         { 12000000, 600000000, 600, 12, 1, 8},
 421         { 13000000, 600000000, 600, 13, 1, 8},
 422         { 16800000, 600000000, 500, 14, 1, 8},
 423         { 19200000, 600000000, 375, 12, 1, 6},
 424         { 26000000, 600000000, 600, 26, 1, 8},
 425         { 0, 0, 0, 0, 0, 0 },
 426 };
 427
 428 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
 429         { 12000000, 216000000, 432, 12, 2, 8},
 430         { 13000000, 216000000, 432, 13, 2, 8},
 431         { 16800000, 216000000, 360, 14, 2, 8},
 432         { 19200000, 216000000, 360, 16, 2, 8},
 433         { 26000000, 216000000, 432, 26, 2, 8},
 434         { 0, 0, 0, 0, 0, 0 },
 435 };
 436
 437 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
 438         { 9600000, 564480000, 294, 5, 1, 4},
 439         { 9600000, 552960000, 288, 5, 1, 4},
 440         { 9600000, 24000000,  5,   2, 1, 1},
 441
 442         { 28800000, 56448000, 49, 25, 1, 1},
 443         { 28800000, 73728000, 64, 25, 1, 1},
 444         { 28800000, 24000000,  5,  6, 1, 1},
 445         { 0, 0, 0, 0, 0, 0 },
 446 };
 447
 448 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
 449         { 12000000, 216000000, 216, 12, 1, 4},
 450         { 13000000, 216000000, 216, 13, 1, 4},
 451         { 16800000, 216000000, 180, 14, 1, 4},
 452         { 19200000, 216000000, 180, 16, 1, 4},
 453         { 26000000, 216000000, 216, 26, 1, 4},
 454
 455         { 12000000, 594000000, 594, 12, 1, 8},
 456         { 13000000, 594000000, 594, 13, 1, 8},
 457         { 16800000, 594000000, 495, 14, 1, 8},
 458         { 19200000, 594000000, 495, 16, 1, 8},
 459         { 26000000, 594000000, 594, 26, 1, 8},
 460
 461         { 12000000, 1000000000, 1000, 12, 1, 12},
 462         { 13000000, 1000000000, 1000, 13, 1, 12},
 463         { 19200000, 1000000000, 625,  12, 1, 8},
 464         { 26000000, 1000000000, 1000, 26, 1, 12},
 465
 466         { 0, 0, 0, 0, 0, 0 },
 467 };
 468
 469 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
 470         { 12000000, 480000000, 960, 12, 2, 12},
 471         { 13000000, 480000000, 960, 13, 2, 12},
 472         { 16800000, 480000000, 400, 7,  2, 5},
 473         { 19200000, 480000000, 200, 4,  2, 3},
 474         { 26000000, 480000000, 960, 26, 2, 12},
 475         { 0, 0, 0, 0, 0, 0 },
 476 };
 477
 478 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
 479         /* 1.7 GHz */
 480         { 12000000, 1700000000, 850,  6,  1, 8},
 481         { 13000000, 1700000000, 915,  7,  1, 8},        /* actual: 1699.2 MHz */
 482         { 16800000, 1700000000, 708,  7,  1, 8},        /* actual: 1699.2 MHz */
 483         { 19200000, 1700000000, 885,  10, 1, 8},        /* actual: 1699.2 MHz */
 484         { 26000000, 1700000000, 850,  13, 1, 8},
 485
 486         /* 1.6 GHz */
 487         { 12000000, 1600000000, 800,  6,  1, 8},
 488         { 13000000, 1600000000, 738,  6,  1, 8},        /* actual: 1599.0 MHz */
 489         { 16800000, 1600000000, 857,  9,  1, 8},        /* actual: 1599.7 MHz */
 490         { 19200000, 1600000000, 500,  6,  1, 8},
 491         { 26000000, 1600000000, 800,  13, 1, 8},
 492
 493         /* 1.5 GHz */
 494         { 12000000, 1500000000, 750,  6,  1, 8},
 495         { 13000000, 1500000000, 923,  8,  1, 8},        /* actual: 1499.8 MHz */
 496         { 16800000, 1500000000, 625,  7,  1, 8},
 497         { 19200000, 1500000000, 625,  8,  1, 8},
 498         { 26000000, 1500000000, 750,  13, 1, 8},
 499
 500         /* 1.4 GHz */
 501         { 12000000, 1400000000, 700,  6,  1, 8},
 502         { 13000000, 1400000000, 969,  9,  1, 8},        /* actual: 1399.7 MHz */
 503         { 16800000, 1400000000, 1000, 12, 1, 8},
 504         { 19200000, 1400000000, 875,  12, 1, 8},
 505         { 26000000, 1400000000, 700,  13, 1, 8},
 506
 507         /* 1.3 GHz */
 508         { 12000000, 1300000000, 975,  9,  1, 8},
 509         { 13000000, 1300000000, 1000, 10, 1, 8},
 510         { 16800000, 1300000000, 928,  12, 1, 8},        /* actual: 1299.2 MHz */
 511         { 19200000, 1300000000, 812,  12, 1, 8},        /* actual: 1299.2 MHz */
 512         { 26000000, 1300000000, 650,  13, 1, 8},
 513
 514         /* 1.2 GHz */
 515         { 12000000, 1200000000, 1000, 10, 1, 8},
 516         { 13000000, 1200000000, 923,  10, 1, 8},        /* actual: 1199.9 MHz */
 517         { 16800000, 1200000000, 1000, 14, 1, 8},
 518         { 19200000, 1200000000, 1000, 16, 1, 8},
 519         { 26000000, 1200000000, 600,  13, 1, 8},
 520
 521         /* 1.1 GHz */
 522         { 12000000, 1100000000, 825,  9,  1, 8},
 523         { 13000000, 1100000000, 846,  10, 1, 8},        /* actual: 1099.8 MHz */
 524         { 16800000, 1100000000, 982,  15, 1, 8},        /* actual: 1099.8 MHz */
 525         { 19200000, 1100000000, 859,  15, 1, 8},        /* actual: 1099.5 MHz */
 526         { 26000000, 1100000000, 550,  13, 1, 8},
 527
 528         /* 1 GHz */
 529         { 12000000, 1000000000, 1000, 12, 1, 8},
 530         { 13000000, 1000000000, 1000, 13, 1, 8},
 531         { 16800000, 1000000000, 833,  14, 1, 8},        /* actual: 999.6 MHz */
 532         { 19200000, 1000000000, 625,  12, 1, 8},
 533         { 26000000, 1000000000, 1000, 26, 1, 8},
 534
 535         { 0, 0, 0, 0, 0, 0 },
 536 };
 537
 538 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
 539         /* PLLE special case: use cpcon field to store cml divider value */
 540         { 12000000,  100000000, 150, 1,  18, 11},
 541         { 216000000, 100000000, 200, 18, 24, 13},
 542         { 0, 0, 0, 0, 0, 0 },
 543 };
 544
 545 /* PLL parameters */
 546 static struct tegra_clk_pll_params pll_c_params = {
 547         .input_min = 2000000,
 548         .input_max = 31000000,
 549         .cf_min = 1000000,
 550         .cf_max = 6000000,
 551         .vco_min = 20000000,
 552         .vco_max = 1400000000,
 553         .base_reg = PLLC_BASE,
 554         .misc_reg = PLLC_MISC,
 555         .lock_bit_idx = PLL_BASE_LOCK,
 556         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 557         .lock_delay = 300,
 558 };
 559
 560 static struct tegra_clk_pll_params pll_m_params = {
 561         .input_min = 2000000,
 562         .input_max = 31000000,
 563         .cf_min = 1000000,
 564         .cf_max = 6000000,
 565         .vco_min = 20000000,
 566         .vco_max = 1200000000,
 567         .base_reg = PLLM_BASE,
 568         .misc_reg = PLLM_MISC,
 569         .lock_bit_idx = PLL_BASE_LOCK,
 570         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 571         .lock_delay = 300,
 572 };
 573
 574 static struct tegra_clk_pll_params pll_p_params = {
 575         .input_min = 2000000,
 576         .input_max = 31000000,
 577         .cf_min = 1000000,
 578         .cf_max = 6000000,
 579         .vco_min = 20000000,
 580         .vco_max = 1400000000,
 581         .base_reg = PLLP_BASE,
 582         .misc_reg = PLLP_MISC,
 583         .lock_bit_idx = PLL_BASE_LOCK,
 584         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 585         .lock_delay = 300,
 586 };
 587
 588 static struct tegra_clk_pll_params pll_a_params = {
 589         .input_min = 2000000,
 590         .input_max = 31000000,
 591         .cf_min = 1000000,
 592         .cf_max = 6000000,
 593         .vco_min = 20000000,
 594         .vco_max = 1400000000,
 595         .base_reg = PLLA_BASE,
 596         .misc_reg = PLLA_MISC,
 597         .lock_bit_idx = PLL_BASE_LOCK,
 598         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 599         .lock_delay = 300,
 600 };
 601
 602 static struct tegra_clk_pll_params pll_d_params = {
 603         .input_min = 2000000,
 604         .input_max = 40000000,
 605         .cf_min = 1000000,
 606         .cf_max = 6000000,
 607         .vco_min = 40000000,
 608         .vco_max = 1000000000,
 609         .base_reg = PLLD_BASE,
 610         .misc_reg = PLLD_MISC,
 611         .lock_bit_idx = PLL_BASE_LOCK,
 612         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
 613         .lock_delay = 1000,
 614 };
 615
 616 static struct tegra_clk_pll_params pll_d2_params = {
 617         .input_min = 2000000,
 618         .input_max = 40000000,
 619         .cf_min = 1000000,
 620         .cf_max = 6000000,
 621         .vco_min = 40000000,
 622         .vco_max = 1000000000,
 623         .base_reg = PLLD2_BASE,
 624         .misc_reg = PLLD2_MISC,
 625         .lock_bit_idx = PLL_BASE_LOCK,
 626         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
 627         .lock_delay = 1000,
 628 };
 629
 630 static struct tegra_clk_pll_params pll_u_params = {
 631         .input_min = 2000000,
 632         .input_max = 40000000,
 633         .cf_min = 1000000,
 634         .cf_max = 6000000,
 635         .vco_min = 48000000,
 636         .vco_max = 960000000,
 637         .base_reg = PLLU_BASE,
 638         .misc_reg = PLLU_MISC,
 639         .lock_bit_idx = PLL_BASE_LOCK,
 640         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
 641         .lock_delay = 1000,
 642 };
 643
 644 static struct tegra_clk_pll_params pll_x_params = {
 645         .input_min = 2000000,
 646         .input_max = 31000000,
 647         .cf_min = 1000000,
 648         .cf_max = 6000000,
 649         .vco_min = 20000000,
 650         .vco_max = 1700000000,
 651         .base_reg = PLLX_BASE,
 652         .misc_reg = PLLX_MISC,
 653         .lock_bit_idx = PLL_BASE_LOCK,
 654         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 655         .lock_delay = 300,
 656 };
 657
 658 static struct tegra_clk_pll_params pll_e_params = {
 659         .input_min = 12000000,
 660         .input_max = 216000000,
 661         .cf_min = 12000000,
 662         .cf_max = 12000000,
 663         .vco_min = 1200000000,
 664         .vco_max = 2400000000U,
 665         .base_reg = PLLE_BASE,
 666         .misc_reg = PLLE_MISC,
 667         .lock_bit_idx = PLLE_MISC_LOCK,
 668         .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
 669         .lock_delay = 300,
 670 };
 671
 672 /* Peripheral clock registers */
 673 static struct tegra_clk_periph_regs periph_l_regs = {
 674         .enb_reg = CLK_OUT_ENB_L,
 675         .enb_set_reg = CLK_OUT_ENB_SET_L,
 676         .enb_clr_reg = CLK_OUT_ENB_CLR_L,
 677         .rst_reg = RST_DEVICES_L,
 678         .rst_set_reg = RST_DEVICES_SET_L,
 679         .rst_clr_reg = RST_DEVICES_CLR_L,
 680 };
 681
 682 static struct tegra_clk_periph_regs periph_h_regs = {
 683         .enb_reg = CLK_OUT_ENB_H,
 684         .enb_set_reg = CLK_OUT_ENB_SET_H,
 685         .enb_clr_reg = CLK_OUT_ENB_CLR_H,
 686         .rst_reg = RST_DEVICES_H,
 687         .rst_set_reg = RST_DEVICES_SET_H,
 688         .rst_clr_reg = RST_DEVICES_CLR_H,
 689 };
 690
 691 static struct tegra_clk_periph_regs periph_u_regs = {
 692         .enb_reg = CLK_OUT_ENB_U,
 693         .enb_set_reg = CLK_OUT_ENB_SET_U,
 694         .enb_clr_reg = CLK_OUT_ENB_CLR_U,
 695         .rst_reg = RST_DEVICES_U,
 696         .rst_set_reg = RST_DEVICES_SET_U,
 697         .rst_clr_reg = RST_DEVICES_CLR_U,
 698 };
 699
 700 static struct tegra_clk_periph_regs periph_v_regs = {
 701         .enb_reg = CLK_OUT_ENB_V,
 702         .enb_set_reg = CLK_OUT_ENB_SET_V,
 703         .enb_clr_reg = CLK_OUT_ENB_CLR_V,
 704         .rst_reg = RST_DEVICES_V,
 705         .rst_set_reg = RST_DEVICES_SET_V,
 706         .rst_clr_reg = RST_DEVICES_CLR_V,
 707 };
 708
 709 static struct tegra_clk_periph_regs periph_w_regs = {
 710         .enb_reg = CLK_OUT_ENB_W,
 711         .enb_set_reg = CLK_OUT_ENB_SET_W,
 712         .enb_clr_reg = CLK_OUT_ENB_CLR_W,
 713         .rst_reg = RST_DEVICES_W,
 714         .rst_set_reg = RST_DEVICES_SET_W,
 715         .rst_clr_reg = RST_DEVICES_CLR_W,
 716 };
 717
 718 static void tegra30_clk_measure_input_freq(void)
 719 {
 720         u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL);
 721         u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK;
 722         u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
 723
 724         switch (auto_clk_control) {
 725         case OSC_CTRL_OSC_FREQ_12MHZ:
 726                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
 727                 input_freq = 12000000;
 728                 break;
 729         case OSC_CTRL_OSC_FREQ_13MHZ:
 730                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
 731                 input_freq = 13000000;
 732                 break;
 733         case OSC_CTRL_OSC_FREQ_19_2MHZ:
 734                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
 735                 input_freq = 19200000;
 736                 break;
 737         case OSC_CTRL_OSC_FREQ_26MHZ:
 738                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
 739                 input_freq = 26000000;
 740                 break;
 741         case OSC_CTRL_OSC_FREQ_16_8MHZ:
 742                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
 743                 input_freq = 16800000;
 744                 break;
 745         case OSC_CTRL_OSC_FREQ_38_4MHZ:
 746                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2);
 747                 input_freq = 38400000;
 748                 break;
 749         case OSC_CTRL_OSC_FREQ_48MHZ:
 750                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
 751                 input_freq = 48000000;
 752                 break;
 753         default:
 754                 pr_err("Unexpected auto clock control value %d",
 755                         auto_clk_control);
 756                 BUG();
 757                 return;
 758         }
 759 }
 760
 761 static unsigned int tegra30_get_pll_ref_div(void)
 762 {
 763         u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) &
 764                                         OSC_CTRL_PLL_REF_DIV_MASK;
 765
 766         switch (pll_ref_div) {
 767         case OSC_CTRL_PLL_REF_DIV_1:
 768                 return 1;
 769         case OSC_CTRL_PLL_REF_DIV_2:
 770                 return 2;
 771         case OSC_CTRL_PLL_REF_DIV_4:
 772                 return 4;
 773         default:
 774                 pr_err("Invalid pll ref divider %d", pll_ref_div);
 775                 BUG();
 776         }
 777         return 0;
 778 }
 779
 780 static void tegra30_utmi_param_configure(void)
 781 {
 782         u32 reg;
 783         int i;
 784
 785         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
 786                 if (input_freq == utmi_parameters[i].osc_frequency)
 787                         break;
 788         }
 789
 790         if (i >= ARRAY_SIZE(utmi_parameters)) {
 791                 pr_err("%s: Unexpected input rate %lu\n", __func__, input_freq);
 792                 return;
 793         }
 794
 795         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
 796
 797         /* Program UTMIP PLL stable and active counts */
 798         reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
 799         reg |= UTMIP_PLL_CFG2_STABLE_COUNT(
 800                         utmi_parameters[i].stable_count);
 801
 802         reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
 803
 804         reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(
 805                         utmi_parameters[i].active_delay_count);
 806
 807         /* Remove power downs from UTMIP PLL control bits */
 808         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
 809         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
 810         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
 811
 812         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
 813
 814         /* Program UTMIP PLL delay and oscillator frequency counts */
 815         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
 816         reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
 817
 818         reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(
 819                 utmi_parameters[i].enable_delay_count);
 820
 821         reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
 822         reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(
 823                 utmi_parameters[i].xtal_freq_count);
 824
 825         /* Remove power downs from UTMIP PLL control bits */
 826         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
 827         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
 828         reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
 829
 830         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
 831 }
 832
 833 static const char *pll_e_parents[] = {"pll_ref", "pll_p"};
 834
 835 static void __init tegra30_pll_init(void)
 836 {
 837         struct clk *clk;
 838
 839         /* PLLC */
 840         clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
 841                             0, &pll_c_params,
 842                             TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
 843                             pll_c_freq_table, NULL);
 844         clk_register_clkdev(clk, "pll_c", NULL);
 845         clks[pll_c] = clk;
 846
 847         /* PLLC_OUT1 */
 848         clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
 849                                 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
 850                                 8, 8, 1, NULL);
 851         clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
 852                                 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
 853                                 0, NULL);
 854         clk_register_clkdev(clk, "pll_c_out1", NULL);
 855         clks[pll_c_out1] = clk;
 856
 857         /* PLLP */
 858         clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc_base, 0,
 859                             408000000, &pll_p_params,
 860                             TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON |
 861                             TEGRA_PLL_USE_LOCK, pll_p_freq_table, NULL);
 862         clk_register_clkdev(clk, "pll_p", NULL);
 863         clks[pll_p] = clk;
 864
 865         /* PLLP_OUT1 */
 866         clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p",
 867                                 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
 868                                 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1,
 869                                 &pll_div_lock);
 870         clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div",
 871                                 clk_base + PLLP_OUTA, 1, 0,
 872                                 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
 873                                 &pll_div_lock);
 874         clk_register_clkdev(clk, "pll_p_out1", NULL);
 875         clks[pll_p_out1] = clk;
 876
 877         /* PLLP_OUT2 */
 878         clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
 879                                 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
 880                                 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
 881                                 &pll_div_lock);
 882         clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
 883                                 clk_base + PLLP_OUTA, 17, 16,
 884                                 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
 885                                 &pll_div_lock);
 886         clk_register_clkdev(clk, "pll_p_out2", NULL);
 887         clks[pll_p_out2] = clk;
 888
 889         /* PLLP_OUT3 */
 890         clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p",
 891                                 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
 892                                 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1,
 893                                 &pll_div_lock);
 894         clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div",
 895                                 clk_base + PLLP_OUTB, 1, 0,
 896                                 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
 897                                 &pll_div_lock);
 898         clk_register_clkdev(clk, "pll_p_out3", NULL);
 899         clks[pll_p_out3] = clk;
 900
 901         /* PLLP_OUT4 */
 902         clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p",
 903                                 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
 904                                 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
 905                                 &pll_div_lock);
 906         clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div",
 907                                 clk_base + PLLP_OUTB, 17, 16,
 908                                 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
 909                                 &pll_div_lock);
 910         clk_register_clkdev(clk, "pll_p_out4", NULL);
 911         clks[pll_p_out4] = clk;
 912
 913         /* PLLM */
 914         clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,
 915                             CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0,
 916                             &pll_m_params, TEGRA_PLLM | TEGRA_PLL_HAS_CPCON |
 917                             TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK,
 918                             pll_m_freq_table, NULL);
 919         clk_register_clkdev(clk, "pll_m", NULL);
 920         clks[pll_m] = clk;
 921
 922         /* PLLM_OUT1 */
 923         clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
 924                                 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
 925                                 8, 8, 1, NULL);
 926         clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
 927                                 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
 928                                 CLK_SET_RATE_PARENT, 0, NULL);
 929         clk_register_clkdev(clk, "pll_m_out1", NULL);
 930         clks[pll_m_out1] = clk;
 931
 932         /* PLLX */
 933         clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0,
 934                             0, &pll_x_params, TEGRA_PLL_HAS_CPCON |
 935                             TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK,
 936                             pll_x_freq_table, NULL);
 937         clk_register_clkdev(clk, "pll_x", NULL);
 938         clks[pll_x] = clk;
 939
 940         /* PLLX_OUT0 */
 941         clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
 942                                         CLK_SET_RATE_PARENT, 1, 2);
 943         clk_register_clkdev(clk, "pll_x_out0", NULL);
 944         clks[pll_x_out0] = clk;
 945
 946         /* PLLU */
 947         clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0,
 948                             0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON |
 949                             TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK,
 950                             pll_u_freq_table,
 951                             NULL);
 952         clk_register_clkdev(clk, "pll_u", NULL);
 953         clks[pll_u] = clk;
 954
 955         tegra30_utmi_param_configure();
 956
 957         /* PLLD */
 958         clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,
 959                             0, &pll_d_params, TEGRA_PLL_HAS_CPCON |
 960                             TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK,
 961                             pll_d_freq_table, &pll_d_lock);
 962         clk_register_clkdev(clk, "pll_d", NULL);
 963         clks[pll_d] = clk;
 964
 965         /* PLLD_OUT0 */
 966         clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
 967                                         CLK_SET_RATE_PARENT, 1, 2);
 968         clk_register_clkdev(clk, "pll_d_out0", NULL);
 969         clks[pll_d_out0] = clk;
 970
 971         /* PLLD2 */
 972         clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,
 973                             0, &pll_d2_params, TEGRA_PLL_HAS_CPCON |
 974                             TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK,
 975                             pll_d_freq_table, NULL);
 976         clk_register_clkdev(clk, "pll_d2", NULL);
 977         clks[pll_d2] = clk;
 978
 979         /* PLLD2_OUT0 */
 980         clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
 981                                         CLK_SET_RATE_PARENT, 1, 2);
 982         clk_register_clkdev(clk, "pll_d2_out0", NULL);
 983         clks[pll_d2_out0] = clk;
 984
 985         /* PLLA */
 986         clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc_base,
 987                             0, 0, &pll_a_params, TEGRA_PLL_HAS_CPCON |
 988                             TEGRA_PLL_USE_LOCK, pll_a_freq_table, NULL);
 989         clk_register_clkdev(clk, "pll_a", NULL);
 990         clks[pll_a] = clk;
 991
 992         /* PLLA_OUT0 */
 993         clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
 994                                 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
 995                                 8, 8, 1, NULL);
 996         clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
 997                                 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
 998                                 CLK_SET_RATE_PARENT, 0, NULL);
 999         clk_register_clkdev(clk, "pll_a_out0", NULL);
1000         clks[pll_a_out0] = clk;
1001
1002         /* PLLE */
1003         clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents,
1004                                ARRAY_SIZE(pll_e_parents), 0,
1005                                clk_base + PLLE_AUX, 2, 1, 0, NULL);
1006         clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
1007                              CLK_GET_RATE_NOCACHE, 100000000, &pll_e_params,
1008                              TEGRA_PLLE_CONFIGURE, pll_e_freq_table, NULL);
1009         clk_register_clkdev(clk, "pll_e", NULL);
1010         clks[pll_e] = clk;
1011 }
1012
1013 static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync",
1014         "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",};
1015 static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
1016                                           "clk_m_div4", "extern1", };
1017 static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
1018                                           "clk_m_div4", "extern2", };
1019 static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
1020                                           "clk_m_div4", "extern3", };
1021
1022 static void __init tegra30_audio_clk_init(void)
1023 {
1024         struct clk *clk;
1025
1026         /* spdif_in_sync */
1027         clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000,
1028                                              24000000);
1029         clk_register_clkdev(clk, "spdif_in_sync", NULL);
1030         clks[spdif_in_sync] = clk;
1031
1032         /* i2s0_sync */
1033         clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000);
1034         clk_register_clkdev(clk, "i2s0_sync", NULL);
1035         clks[i2s0_sync] = clk;
1036
1037         /* i2s1_sync */
1038         clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000);
1039         clk_register_clkdev(clk, "i2s1_sync", NULL);
1040         clks[i2s1_sync] = clk;
1041
1042         /* i2s2_sync */
1043         clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000);
1044         clk_register_clkdev(clk, "i2s2_sync", NULL);
1045         clks[i2s2_sync] = clk;
1046
1047         /* i2s3_sync */
1048         clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000);
1049         clk_register_clkdev(clk, "i2s3_sync", NULL);
1050         clks[i2s3_sync] = clk;
1051
1052         /* i2s4_sync */
1053         clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000);
1054         clk_register_clkdev(clk, "i2s4_sync", NULL);
1055         clks[i2s4_sync] = clk;
1056
1057         /* vimclk_sync */
1058         clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000);
1059         clk_register_clkdev(clk, "vimclk_sync", NULL);
1060         clks[vimclk_sync] = clk;
1061
1062         /* audio0 */
1063         clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
1064                                 ARRAY_SIZE(mux_audio_sync_clk), 0,
1065                                 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, NULL);
1066         clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0,
1067                                 clk_base + AUDIO_SYNC_CLK_I2S0, 4,
1068                                 CLK_GATE_SET_TO_DISABLE, NULL);
1069         clk_register_clkdev(clk, "audio0", NULL);
1070         clks[audio0] = clk;
1071
1072         /* audio1 */
1073         clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
1074                                 ARRAY_SIZE(mux_audio_sync_clk), 0,
1075                                 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, NULL);
1076         clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0,
1077                                 clk_base + AUDIO_SYNC_CLK_I2S1, 4,
1078                                 CLK_GATE_SET_TO_DISABLE, NULL);
1079         clk_register_clkdev(clk, "audio1", NULL);
1080         clks[audio1] = clk;
1081
1082         /* audio2 */
1083         clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
1084                                 ARRAY_SIZE(mux_audio_sync_clk), 0,
1085                                 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, NULL);
1086         clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0,
1087                                 clk_base + AUDIO_SYNC_CLK_I2S2, 4,
1088                                 CLK_GATE_SET_TO_DISABLE, NULL);
1089         clk_register_clkdev(clk, "audio2", NULL);
1090         clks[audio2] = clk;
1091
1092         /* audio3 */
1093         clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
1094                                 ARRAY_SIZE(mux_audio_sync_clk), 0,
1095                                 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, NULL);
1096         clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0,
1097                                 clk_base + AUDIO_SYNC_CLK_I2S3, 4,
1098                                 CLK_GATE_SET_TO_DISABLE, NULL);
1099         clk_register_clkdev(clk, "audio3", NULL);
1100         clks[audio3] = clk;
1101
1102         /* audio4 */
1103         clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
1104                                 ARRAY_SIZE(mux_audio_sync_clk), 0,
1105                                 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, NULL);
1106         clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0,
1107                                 clk_base + AUDIO_SYNC_CLK_I2S4, 4,
1108                                 CLK_GATE_SET_TO_DISABLE, NULL);
1109         clk_register_clkdev(clk, "audio4", NULL);
1110         clks[audio4] = clk;
1111
1112         /* spdif */
1113         clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
1114                                 ARRAY_SIZE(mux_audio_sync_clk), 0,
1115                                 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, NULL);
1116         clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0,
1117                                 clk_base + AUDIO_SYNC_CLK_SPDIF, 4,
1118                                 CLK_GATE_SET_TO_DISABLE, NULL);
1119         clk_register_clkdev(clk, "spdif", NULL);
1120         clks[spdif] = clk;
1121
1122         /* audio0_2x */
1123         clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0",
1124                                         CLK_SET_RATE_PARENT, 2, 1);
1125         clk = tegra_clk_register_divider("audio0_div", "audio0_doubler",
1126                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1, 0,
1127                                 &clk_doubler_lock);
1128         clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div",
1129                                     TEGRA_PERIPH_NO_RESET, clk_base,
1130                                     CLK_SET_RATE_PARENT, 113, &periph_v_regs,
1131                                     periph_clk_enb_refcnt);
1132         clk_register_clkdev(clk, "audio0_2x", NULL);
1133         clks[audio0_2x] = clk;
1134
1135         /* audio1_2x */
1136         clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1",
1137                                         CLK_SET_RATE_PARENT, 2, 1);
1138         clk = tegra_clk_register_divider("audio1_div", "audio1_doubler",
1139                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1, 0,
1140                                 &clk_doubler_lock);
1141         clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div",
1142                                     TEGRA_PERIPH_NO_RESET, clk_base,
1143                                     CLK_SET_RATE_PARENT, 114, &periph_v_regs,
1144                                     periph_clk_enb_refcnt);
1145         clk_register_clkdev(clk, "audio1_2x", NULL);
1146         clks[audio1_2x] = clk;
1147
1148         /* audio2_2x */
1149         clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2",
1150                                         CLK_SET_RATE_PARENT, 2, 1);
1151         clk = tegra_clk_register_divider("audio2_div", "audio2_doubler",
1152                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1, 0,
1153                                 &clk_doubler_lock);
1154         clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div",
1155                                     TEGRA_PERIPH_NO_RESET, clk_base,
1156                                     CLK_SET_RATE_PARENT, 115, &periph_v_regs,
1157                                     periph_clk_enb_refcnt);
1158         clk_register_clkdev(clk, "audio2_2x", NULL);
1159         clks[audio2_2x] = clk;
1160
1161         /* audio3_2x */
1162         clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3",
1163                                         CLK_SET_RATE_PARENT, 2, 1);
1164         clk = tegra_clk_register_divider("audio3_div", "audio3_doubler",
1165                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1, 0,
1166                                 &clk_doubler_lock);
1167         clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div",
1168                                     TEGRA_PERIPH_NO_RESET, clk_base,
1169                                     CLK_SET_RATE_PARENT, 116, &periph_v_regs,
1170                                     periph_clk_enb_refcnt);
1171         clk_register_clkdev(clk, "audio3_2x", NULL);
1172         clks[audio3_2x] = clk;
1173
1174         /* audio4_2x */
1175         clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4",
1176                                         CLK_SET_RATE_PARENT, 2, 1);
1177         clk = tegra_clk_register_divider("audio4_div", "audio4_doubler",
1178                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1, 0,
1179                                 &clk_doubler_lock);
1180         clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div",
1181                                     TEGRA_PERIPH_NO_RESET, clk_base,
1182                                     CLK_SET_RATE_PARENT, 117, &periph_v_regs,
1183                                     periph_clk_enb_refcnt);
1184         clk_register_clkdev(clk, "audio4_2x", NULL);
1185         clks[audio4_2x] = clk;
1186
1187         /* spdif_2x */
1188         clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif",
1189                                         CLK_SET_RATE_PARENT, 2, 1);
1190         clk = tegra_clk_register_divider("spdif_div", "spdif_doubler",
1191                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1, 0,
1192                                 &clk_doubler_lock);
1193         clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div",
1194                                     TEGRA_PERIPH_NO_RESET, clk_base,
1195                                     CLK_SET_RATE_PARENT, 118, &periph_v_regs,
1196                                     periph_clk_enb_refcnt);
1197         clk_register_clkdev(clk, "spdif_2x", NULL);
1198         clks[spdif_2x] = clk;
1199 }
1200
1201 static void __init tegra30_pmc_clk_init(void)
1202 {
1203         struct clk *clk;
1204
1205         /* clk_out_1 */
1206         clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
1207                                ARRAY_SIZE(clk_out1_parents), 0,
1208                                pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
1209                                &clk_out_lock);
1210         clks[clk_out_1_mux] = clk;
1211         clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0,
1212                                 pmc_base + PMC_CLK_OUT_CNTRL, 2, 0,
1213                                 &clk_out_lock);
1214         clk_register_clkdev(clk, "extern1", "clk_out_1");
1215         clks[clk_out_1] = clk;
1216
1217         /* clk_out_2 */
1218         clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
1219                                ARRAY_SIZE(clk_out1_parents), 0,
1220                                pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
1221                                &clk_out_lock);
1222         clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,
1223                                 pmc_base + PMC_CLK_OUT_CNTRL, 10, 0,
1224                                 &clk_out_lock);
1225         clk_register_clkdev(clk, "extern2", "clk_out_2");
1226         clks[clk_out_2] = clk;
1227
1228         /* clk_out_3 */
1229         clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
1230                                ARRAY_SIZE(clk_out1_parents), 0,
1231                                pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
1232                                &clk_out_lock);
1233         clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,
1234                                 pmc_base + PMC_CLK_OUT_CNTRL, 18, 0,
1235                                 &clk_out_lock);
1236         clk_register_clkdev(clk, "extern3", "clk_out_3");
1237         clks[clk_out_3] = clk;
1238
1239         /* blink */
1240         writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
1241         clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
1242                                 pmc_base + PMC_DPD_PADS_ORIDE,
1243                                 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
1244         clk = clk_register_gate(NULL, "blink", "blink_override", 0,
1245                                 pmc_base + PMC_CTRL,
1246                                 PMC_CTRL_BLINK_ENB, 0, NULL);
1247         clk_register_clkdev(clk, "blink", NULL);
1248         clks[blink] = clk;
1249
1250 }
1251
1252 static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1253                                         "pll_p_cclkg", "pll_p_out4_cclkg",
1254                                         "pll_p_out3_cclkg", "unused", "pll_x" };
1255 static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1256                                          "pll_p_cclklp", "pll_p_out4_cclklp",
1257                                          "pll_p_out3_cclklp", "unused", "pll_x",
1258                                          "pll_x_out0" };
1259 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
1260                                       "pll_p_out3", "pll_p_out2", "unused",
1261                                       "clk_32k", "pll_m_out1" };
1262
1263 static void __init tegra30_super_clk_init(void)
1264 {
1265         struct clk *clk;
1266
1267         /*
1268          * Clock input to cclk_g divided from pll_p using
1269          * U71 divider of cclk_g.
1270          */
1271         clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p",
1272                                 clk_base + SUPER_CCLKG_DIVIDER, 0,
1273                                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1274         clk_register_clkdev(clk, "pll_p_cclkg", NULL);
1275
1276         /*
1277          * Clock input to cclk_g divided from pll_p_out3 using
1278          * U71 divider of cclk_g.
1279          */
1280         clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3",
1281                                 clk_base + SUPER_CCLKG_DIVIDER, 0,
1282                                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1283         clk_register_clkdev(clk, "pll_p_out3_cclkg", NULL);
1284
1285         /*
1286          * Clock input to cclk_g divided from pll_p_out4 using
1287          * U71 divider of cclk_g.
1288          */
1289         clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4",
1290                                 clk_base + SUPER_CCLKG_DIVIDER, 0,
1291                                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1292         clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL);
1293
1294         /* CCLKG */
1295         clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents,
1296                                   ARRAY_SIZE(cclk_g_parents),
1297                                   CLK_SET_RATE_PARENT,
1298                                   clk_base + CCLKG_BURST_POLICY,
1299                                   0, 4, 0, 0, NULL);
1300         clk_register_clkdev(clk, "cclk_g", NULL);
1301         clks[cclk_g] = clk;
1302
1303         /*
1304          * Clock input to cclk_lp divided from pll_p using
1305          * U71 divider of cclk_lp.
1306          */
1307         clk = tegra_clk_register_divider("pll_p_cclklp", "pll_p",
1308                                 clk_base + SUPER_CCLKLP_DIVIDER, 0,
1309                                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1310         clk_register_clkdev(clk, "pll_p_cclklp", NULL);
1311
1312         /*
1313          * Clock input to cclk_lp divided from pll_p_out3 using
1314          * U71 divider of cclk_lp.
1315          */
1316         clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3",
1317                                 clk_base + SUPER_CCLKG_DIVIDER, 0,
1318                                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1319         clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);
1320
1321         /*
1322          * Clock input to cclk_lp divided from pll_p_out4 using
1323          * U71 divider of cclk_lp.
1324          */
1325         clk = tegra_clk_register_divider("pll_p_out4_cclklp", "pll_p_out4",
1326                                 clk_base + SUPER_CCLKLP_DIVIDER, 0,
1327                                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1328         clk_register_clkdev(clk, "pll_p_out4_cclklp", NULL);
1329
1330         /* CCLKLP */
1331         clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
1332                                   ARRAY_SIZE(cclk_lp_parents),
1333                                   CLK_SET_RATE_PARENT,
1334                                   clk_base + CCLKLP_BURST_POLICY,
1335                                   TEGRA_DIVIDER_2, 4, 8, 9,
1336                               NULL);
1337         clk_register_clkdev(clk, "cclk_lp", NULL);
1338         clks[cclk_lp] = clk;
1339
1340         /* SCLK */
1341         clk = tegra_clk_register_super_mux("sclk", sclk_parents,
1342                                   ARRAY_SIZE(sclk_parents),
1343                                   CLK_SET_RATE_PARENT,
1344                                   clk_base + SCLK_BURST_POLICY,
1345                                   0, 4, 0, 0, NULL);
1346         clk_register_clkdev(clk, "sclk", NULL);
1347         clks[sclk] = clk;
1348
1349         /* HCLK */
1350         clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
1351                                    clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
1352                                    &sysrate_lock);
1353         clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT,
1354                                 clk_base + SYSTEM_CLK_RATE, 7,
1355                                 CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
1356         clk_register_clkdev(clk, "hclk", NULL);
1357         clks[hclk] = clk;
1358
1359         /* PCLK */
1360         clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
1361                                    clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
1362                                    &sysrate_lock);
1363         clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT,
1364                                 clk_base + SYSTEM_CLK_RATE, 3,
1365                                 CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
1366         clk_register_clkdev(clk, "pclk", NULL);
1367         clks[pclk] = clk;
1368
1369         /* twd */
1370         clk = clk_register_fixed_factor(NULL, "twd", "cclk_g",
1371                                         CLK_SET_RATE_PARENT, 1, 2);
1372         clk_register_clkdev(clk, "twd", NULL);
1373         clks[twd] = clk;
1374 }
1375
1376 static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p",
1377                                          "clk_m" };
1378 static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
1379 static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" };
1380 static const char *i2s0_parents[] = { "pll_a_out0", "audio0_2x", "pll_p",
1381                                       "clk_m" };
1382 static const char *i2s1_parents[] = { "pll_a_out0", "audio1_2x", "pll_p",
1383                                       "clk_m" };
1384 static const char *i2s2_parents[] = { "pll_a_out0", "audio2_2x", "pll_p",
1385                                       "clk_m" };
1386 static const char *i2s3_parents[] = { "pll_a_out0", "audio3_2x", "pll_p",
1387                                       "clk_m" };
1388 static const char *i2s4_parents[] = { "pll_a_out0", "audio4_2x", "pll_p",
1389                                       "clk_m" };
1390 static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p",
1391                                            "clk_m" };
1392 static const char *spdif_in_parents[] = { "pll_p", "pll_c", "pll_m" };
1393 static const char *mux_pllpc_clk32k_clkm[] = { "pll_p", "pll_c", "clk_32k",
1394                                                "clk_m" };
1395 static const char *mux_pllpc_clkm_clk32k[] = { "pll_p", "pll_c", "clk_m",
1396                                                "clk_32k" };
1397 static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" };
1398 static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d_out0", "pll_c",
1399                                          "clk_m" };
1400 static const char *mux_pllp_clkm[] = { "pll_p", "unused", "unused", "clk_m" };
1401 static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0",
1402                                              "pll_a_out0", "pll_c",
1403                                              "pll_d2_out0", "clk_m" };
1404 static const char *mux_plla_clk32k_pllp_clkm_plle[] = { "pll_a_out0",
1405                                                         "clk_32k", "pll_p",
1406                                                         "clk_m", "pll_e" };
1407 static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0",
1408                                                   "pll_d2_out0" };
1409
1410 static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1411         TEGRA_INIT_DATA_MUX("i2s0",     NULL,           "tegra30-i2s.0",        i2s0_parents,           CLK_SOURCE_I2S0,        30,     &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s0),
1412         TEGRA_INIT_DATA_MUX("i2s1",     NULL,           "tegra30-i2s.1",        i2s1_parents,           CLK_SOURCE_I2S1,        11,     &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1),
1413         TEGRA_INIT_DATA_MUX("i2s2",     NULL,           "tegra30-i2s.2",        i2s2_parents,           CLK_SOURCE_I2S2,        18,     &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2),
1414         TEGRA_INIT_DATA_MUX("i2s3",     NULL,           "tegra30-i2s.3",        i2s3_parents,           CLK_SOURCE_I2S3,        101,    &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s3),
1415         TEGRA_INIT_DATA_MUX("i2s4",     NULL,           "tegra30-i2s.4",        i2s4_parents,           CLK_SOURCE_I2S4,        102,    &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s4),
1416         TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out",   "tegra30-spdif",        spdif_out_parents,      CLK_SOURCE_SPDIF_OUT,   10,     &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out),
1417         TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in",     "tegra30-spdif",        spdif_in_parents,       CLK_SOURCE_SPDIF_IN,    10,     &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in),
1418         TEGRA_INIT_DATA_MUX("d_audio",  "d_audio",      "tegra30-ahub",         mux_pllacp_clkm,        CLK_SOURCE_D_AUDIO,     106,    &periph_v_regs, 0, d_audio),
1419         TEGRA_INIT_DATA_MUX("dam0",     NULL,           "tegra30-dam.0",        mux_pllacp_clkm,        CLK_SOURCE_DAM0,        108,    &periph_v_regs, 0, dam0),
1420         TEGRA_INIT_DATA_MUX("dam1",     NULL,           "tegra30-dam.1",        mux_pllacp_clkm,        CLK_SOURCE_DAM1,        109,    &periph_v_regs, 0, dam1),
1421         TEGRA_INIT_DATA_MUX("dam2",     NULL,           "tegra30-dam.2",        mux_pllacp_clkm,        CLK_SOURCE_DAM2,        110,    &periph_v_regs, 0, dam2),
1422         TEGRA_INIT_DATA_MUX("hda",      "hda",          "tegra30-hda",          mux_pllpcm_clkm,        CLK_SOURCE_HDA,         125,    &periph_v_regs, 0, hda),
1423         TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda",         mux_pllpcm_clkm,        CLK_SOURCE_HDA2CODEC_2X, 111,   &periph_v_regs, 0, hda2codec_2x),
1424         TEGRA_INIT_DATA_MUX("sbc1",     NULL,           "spi_tegra.0",          mux_pllpcm_clkm,        CLK_SOURCE_SBC1,        41,     &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
1425         TEGRA_INIT_DATA_MUX("sbc2",     NULL,           "spi_tegra.1",          mux_pllpcm_clkm,        CLK_SOURCE_SBC2,        44,     &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2),
1426         TEGRA_INIT_DATA_MUX("sbc3",     NULL,           "spi_tegra.2",          mux_pllpcm_clkm,        CLK_SOURCE_SBC3,        46,     &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3),
1427         TEGRA_INIT_DATA_MUX("sbc4",     NULL,           "spi_tegra.3",          mux_pllpcm_clkm,        CLK_SOURCE_SBC4,        68,     &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4),
1428         TEGRA_INIT_DATA_MUX("sbc5",     NULL,           "spi_tegra.4",          mux_pllpcm_clkm,        CLK_SOURCE_SBC5,        104,    &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5),
1429         TEGRA_INIT_DATA_MUX("sbc6",     NULL,           "spi_tegra.5",          mux_pllpcm_clkm,        CLK_SOURCE_SBC6,        105,    &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6),
1430         TEGRA_INIT_DATA_MUX("sata_oob", NULL,           "tegra_sata_oob",       mux_pllpcm_clkm,        CLK_SOURCE_SATA_OOB,    123,    &periph_v_regs, TEGRA_PERIPH_ON_APB, sata_oob),
1431         TEGRA_INIT_DATA_MUX("sata",     NULL,           "tegra_sata",           mux_pllpcm_clkm,        CLK_SOURCE_SATA,        124,    &periph_v_regs, TEGRA_PERIPH_ON_APB, sata),
1432         TEGRA_INIT_DATA_MUX("ndflash",  NULL,           "tegra_nand",           mux_pllpcm_clkm,        CLK_SOURCE_NDFLASH,     13,     &periph_l_regs, TEGRA_PERIPH_ON_APB, ndflash),
1433         TEGRA_INIT_DATA_MUX("ndspeed",  NULL,           "tegra_nand_speed",     mux_pllpcm_clkm,        CLK_SOURCE_NDSPEED,     80,     &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed),
1434         TEGRA_INIT_DATA_MUX("vfir",     NULL,           "vfir",                 mux_pllpcm_clkm,        CLK_SOURCE_VFIR,        7,      &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir),
1435         TEGRA_INIT_DATA_MUX("csite",    NULL,           "csite",                mux_pllpcm_clkm,        CLK_SOURCE_CSITE,       73,     &periph_u_regs, TEGRA_PERIPH_ON_APB, csite),
1436         TEGRA_INIT_DATA_MUX("la",       NULL,           "la",                   mux_pllpcm_clkm,        CLK_SOURCE_LA,          76,     &periph_u_regs, TEGRA_PERIPH_ON_APB, la),
1437         TEGRA_INIT_DATA_MUX("owr",      NULL,           "tegra_w1",             mux_pllpcm_clkm,        CLK_SOURCE_OWR,         71,     &periph_u_regs, TEGRA_PERIPH_ON_APB, owr),
1438         TEGRA_INIT_DATA_MUX("mipi",     NULL,           "mipi",                 mux_pllpcm_clkm,        CLK_SOURCE_MIPI,        50,     &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi),
1439         TEGRA_INIT_DATA_MUX("tsensor",  NULL,           "tegra-tsensor",        mux_pllpc_clkm_clk32k,  CLK_SOURCE_TSENSOR,     100,    &periph_v_regs, TEGRA_PERIPH_ON_APB, tsensor),
1440         TEGRA_INIT_DATA_MUX("i2cslow",  NULL,           "i2cslow",              mux_pllpc_clk32k_clkm,  CLK_SOURCE_I2CSLOW,     81,     &periph_u_regs, TEGRA_PERIPH_ON_APB, i2cslow),
1441         TEGRA_INIT_DATA_INT("vde",      NULL,           "vde",                  mux_pllpcm_clkm,        CLK_SOURCE_VDE,         61,     &periph_h_regs, 0, vde),
1442         TEGRA_INIT_DATA_INT("vi",       "vi",           "tegra_camera",         mux_pllmcpa,            CLK_SOURCE_VI,          20,     &periph_l_regs, 0, vi),
1443         TEGRA_INIT_DATA_INT("epp",      NULL,           "epp",                  mux_pllmcpa,            CLK_SOURCE_EPP,         19,     &periph_l_regs, 0, epp),
1444         TEGRA_INIT_DATA_INT("mpe",      NULL,           "mpe",                  mux_pllmcpa,            CLK_SOURCE_MPE,         60,     &periph_h_regs, 0, mpe),
1445         TEGRA_INIT_DATA_INT("host1x",   NULL,           "host1x",               mux_pllmcpa,            CLK_SOURCE_HOST1X,      28,     &periph_l_regs, 0, host1x),
1446         TEGRA_INIT_DATA_INT("3d",       NULL,           "3d",                   mux_pllmcpa,            CLK_SOURCE_3D,          24,     &periph_l_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d),
1447         TEGRA_INIT_DATA_INT("3d2",      NULL,           "3d2",                  mux_pllmcpa,            CLK_SOURCE_3D2,         98,     &periph_v_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d2),
1448         TEGRA_INIT_DATA_INT("2d",       NULL,           "2d",                   mux_pllmcpa,            CLK_SOURCE_2D,          21,     &periph_l_regs, 0, gr2d),
1449         TEGRA_INIT_DATA_INT("se",       NULL,           "se",                   mux_pllpcm_clkm,        CLK_SOURCE_SE,          127,    &periph_v_regs, 0, se),
1450         TEGRA_INIT_DATA_MUX("mselect",  NULL,           "mselect",              mux_pllp_clkm,          CLK_SOURCE_MSELECT,     99,     &periph_v_regs, 0, mselect),
1451         TEGRA_INIT_DATA_MUX("nor",      NULL,           "tegra-nor",            mux_pllpcm_clkm,        CLK_SOURCE_NOR,         42,     &periph_h_regs, 0, nor),
1452         TEGRA_INIT_DATA_MUX("sdmmc1",   NULL,           "sdhci-tegra.0",        mux_pllpcm_clkm,        CLK_SOURCE_SDMMC1,      14,     &periph_l_regs, 0, sdmmc1),
1453         TEGRA_INIT_DATA_MUX("sdmmc2",   NULL,           "sdhci-tegra.1",        mux_pllpcm_clkm,        CLK_SOURCE_SDMMC2,      9,      &periph_l_regs, 0, sdmmc2),
1454         TEGRA_INIT_DATA_MUX("sdmmc3",   NULL,           "sdhci-tegra.2",        mux_pllpcm_clkm,        CLK_SOURCE_SDMMC3,      69,     &periph_u_regs, 0, sdmmc3),
1455         TEGRA_INIT_DATA_MUX("sdmmc4",   NULL,           "sdhci-tegra.3",        mux_pllpcm_clkm,        CLK_SOURCE_SDMMC4,      15,     &periph_l_regs, 0, sdmmc4),
1456         TEGRA_INIT_DATA_MUX("cve",      NULL,           "cve",                  mux_pllpdc_clkm,        CLK_SOURCE_CVE,         49,     &periph_h_regs, 0, cve),
1457         TEGRA_INIT_DATA_MUX("tvo",      NULL,           "tvo",                  mux_pllpdc_clkm,        CLK_SOURCE_TVO,         49,     &periph_h_regs, 0, tvo),
1458         TEGRA_INIT_DATA_MUX("tvdac",    NULL,           "tvdac",                mux_pllpdc_clkm,        CLK_SOURCE_TVDAC,       53,     &periph_h_regs, 0, tvdac),
1459         TEGRA_INIT_DATA_MUX("actmon",   NULL,           "actmon",               mux_pllpc_clk32k_clkm,  CLK_SOURCE_ACTMON,      119,    &periph_v_regs, 0, actmon),
1460         TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor",   "tegra_camera",         mux_pllmcpa,            CLK_SOURCE_VI_SENSOR,   20,     &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor),
1461         TEGRA_INIT_DATA_DIV16("i2c1",   "div-clk",      "tegra-i2c.0",          mux_pllp_clkm,          CLK_SOURCE_I2C1,        12,     &periph_l_regs, TEGRA_PERIPH_ON_APB, i2c1),
1462         TEGRA_INIT_DATA_DIV16("i2c2",   "div-clk",      "tegra-i2c.1",          mux_pllp_clkm,          CLK_SOURCE_I2C2,        54,     &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c2),
1463         TEGRA_INIT_DATA_DIV16("i2c3",   "div-clk",      "tegra-i2c.2",          mux_pllp_clkm,          CLK_SOURCE_I2C3,        67,     &periph_u_regs, TEGRA_PERIPH_ON_APB, i2c3),
1464         TEGRA_INIT_DATA_DIV16("i2c4",   "div-clk",      "tegra-i2c.3",          mux_pllp_clkm,          CLK_SOURCE_I2C4,        103,    &periph_v_regs, TEGRA_PERIPH_ON_APB, i2c4),
1465         TEGRA_INIT_DATA_DIV16("i2c5",   "div-clk",      "tegra-i2c.4",          mux_pllp_clkm,          CLK_SOURCE_I2C5,        47,     &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c5),
1466         TEGRA_INIT_DATA_UART("uarta",   NULL,           "tegra_uart.0",         mux_pllpcm_clkm,        CLK_SOURCE_UARTA,       6,      &periph_l_regs, uarta),
1467         TEGRA_INIT_DATA_UART("uartb",   NULL,           "tegra_uart.1",         mux_pllpcm_clkm,        CLK_SOURCE_UARTB,       7,      &periph_l_regs, uartb),
1468         TEGRA_INIT_DATA_UART("uartc",   NULL,           "tegra_uart.2",         mux_pllpcm_clkm,        CLK_SOURCE_UARTC,       55,     &periph_h_regs, uartc),
1469         TEGRA_INIT_DATA_UART("uartd",   NULL,           "tegra_uart.3",         mux_pllpcm_clkm,        CLK_SOURCE_UARTD,       65,     &periph_u_regs, uartd),
1470         TEGRA_INIT_DATA_UART("uarte",   NULL,           "tegra_uart.4",         mux_pllpcm_clkm,        CLK_SOURCE_UARTE,       66,     &periph_u_regs, uarte),
1471         TEGRA_INIT_DATA_MUX8("hdmi",    NULL,           "hdmi",                 mux_pllpmdacd2_clkm,    CLK_SOURCE_HDMI,        51,     &periph_h_regs, 0, hdmi),
1472         TEGRA_INIT_DATA_MUX8("extern1", NULL,           "extern1",              mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN1,     120,    &periph_v_regs, 0, extern1),
1473         TEGRA_INIT_DATA_MUX8("extern2", NULL,           "extern2",              mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN2,     121,    &periph_v_regs, 0, extern2),
1474         TEGRA_INIT_DATA_MUX8("extern3", NULL,           "extern3",              mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN3,     122,    &periph_v_regs, 0, extern3),
1475         TEGRA_INIT_DATA("pwm",          NULL,           "pwm",                  mux_pllpc_clk32k_clkm,  CLK_SOURCE_PWM,         28, 2, 0, 0, 8, 1, 0, &periph_l_regs, 17, periph_clk_enb_refcnt, 0, pwm),
1476 };
1477
1478 static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
1479         TEGRA_INIT_DATA_NODIV("disp1",  NULL, "tegradc.0", mux_pllpmdacd2_clkm,      CLK_SOURCE_DISP1,  29, 3, 27, &periph_l_regs, 0, disp1),
1480         TEGRA_INIT_DATA_NODIV("disp2",  NULL, "tegradc.1", mux_pllpmdacd2_clkm,      CLK_SOURCE_DISP2,  29, 3, 26, &periph_l_regs, 0, disp2),
1481         TEGRA_INIT_DATA_NODIV("dsib",   NULL, "tegradc.1", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB,   25, 1, 82, &periph_u_regs, 0, dsib),
1482 };
1483
1484 static void __init tegra30_periph_clk_init(void)
1485 {
1486         struct tegra_periph_init_data *data;
1487         struct clk *clk;
1488         int i;
1489
1490         /* apbdma */
1491         clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base, 0, 34,
1492                                     &periph_h_regs, periph_clk_enb_refcnt);
1493         clk_register_clkdev(clk, NULL, "tegra-apbdma");
1494         clks[apbdma] = clk;
1495
1496         /* rtc */
1497         clk = tegra_clk_register_periph_gate("rtc", "clk_32k",
1498                                     TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1499                                     clk_base, 0, 4, &periph_l_regs,
1500                                     periph_clk_enb_refcnt);
1501         clk_register_clkdev(clk, NULL, "rtc-tegra");
1502         clks[rtc] = clk;
1503
1504         /* timer */
1505         clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, 0,
1506                                     5, &periph_l_regs, periph_clk_enb_refcnt);
1507         clk_register_clkdev(clk, NULL, "timer");
1508         clks[timer] = clk;
1509
1510         /* kbc */
1511         clk = tegra_clk_register_periph_gate("kbc", "clk_32k",
1512                                     TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1513                                     clk_base, 0, 36, &periph_h_regs,
1514                                     periph_clk_enb_refcnt);
1515         clk_register_clkdev(clk, NULL, "tegra-kbc");
1516         clks[kbc] = clk;
1517
1518         /* csus */
1519         clk = tegra_clk_register_periph_gate("csus", "clk_m",
1520                                     TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1521                                     clk_base, 0, 92, &periph_u_regs,
1522                                     periph_clk_enb_refcnt);
1523         clk_register_clkdev(clk, "csus", "tengra_camera");
1524         clks[csus] = clk;
1525
1526         /* vcp */
1527         clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0, 29,
1528                                     &periph_l_regs, periph_clk_enb_refcnt);
1529         clk_register_clkdev(clk, "vcp", "tegra-avp");
1530         clks[vcp] = clk;
1531
1532         /* bsea */
1533         clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base, 0,
1534                                     62, &periph_h_regs, periph_clk_enb_refcnt);
1535         clk_register_clkdev(clk, "bsea", "tegra-avp");
1536         clks[bsea] = clk;
1537
1538         /* bsev */
1539         clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base, 0,
1540                                     63, &periph_h_regs, periph_clk_enb_refcnt);
1541         clk_register_clkdev(clk, "bsev", "tegra-aes");
1542         clks[bsev] = clk;
1543
1544         /* usbd */
1545         clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0,
1546                                     22, &periph_l_regs, periph_clk_enb_refcnt);
1547         clk_register_clkdev(clk, NULL, "fsl-tegra-udc");
1548         clks[usbd] = clk;
1549
1550         /* usb2 */
1551         clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0,
1552                                     58, &periph_h_regs, periph_clk_enb_refcnt);
1553         clk_register_clkdev(clk, NULL, "tegra-ehci.1");
1554         clks[usb2] = clk;
1555
1556         /* usb3 */
1557         clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0,
1558                                     59, &periph_h_regs, periph_clk_enb_refcnt);
1559         clk_register_clkdev(clk, NULL, "tegra-ehci.2");
1560         clks[usb3] = clk;
1561
1562         /* dsia */
1563         clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,
1564                                     0, 48, &periph_h_regs,
1565                                     periph_clk_enb_refcnt);
1566         clk_register_clkdev(clk, "dsia", "tegradc.0");
1567         clks[dsia] = clk;
1568
1569         /* csi */
1570         clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base,
1571                                     0, 52, &periph_h_regs,
1572                                     periph_clk_enb_refcnt);
1573         clk_register_clkdev(clk, "csi", "tegra_camera");
1574         clks[csi] = clk;
1575
1576         /* isp */
1577         clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23,
1578                                     &periph_l_regs, periph_clk_enb_refcnt);
1579         clk_register_clkdev(clk, "isp", "tegra_camera");
1580         clks[isp] = clk;
1581
1582         /* pcie */
1583         clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,
1584                                     70, &periph_u_regs, periph_clk_enb_refcnt);
1585         clk_register_clkdev(clk, "pcie", "tegra-pcie");
1586         clks[pcie] = clk;
1587
1588         /* afi */
1589         clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
1590                                     &periph_u_regs, periph_clk_enb_refcnt);
1591         clk_register_clkdev(clk, "afi", "tegra-pcie");
1592         clks[afi] = clk;
1593
1594         /* kfuse */
1595         clk = tegra_clk_register_periph_gate("kfuse", "clk_m",
1596                                     TEGRA_PERIPH_ON_APB,
1597                                     clk_base, 0, 40, &periph_h_regs,
1598                                     periph_clk_enb_refcnt);
1599         clk_register_clkdev(clk, NULL, "kfuse-tegra");
1600         clks[kfuse] = clk;
1601
1602         /* fuse */
1603         clk = tegra_clk_register_periph_gate("fuse", "clk_m",
1604                                     TEGRA_PERIPH_ON_APB,
1605                                     clk_base, 0, 39, &periph_h_regs,
1606                                     periph_clk_enb_refcnt);
1607         clk_register_clkdev(clk, "fuse", "fuse-tegra");
1608         clks[fuse] = clk;
1609
1610         /* fuse_burn */
1611         clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m",
1612                                     TEGRA_PERIPH_ON_APB,
1613                                     clk_base, 0, 39, &periph_h_regs,
1614                                     periph_clk_enb_refcnt);
1615         clk_register_clkdev(clk, "fuse_burn", "fuse-tegra");
1616         clks[fuse_burn] = clk;
1617
1618         /* apbif */
1619         clk = tegra_clk_register_periph_gate("apbif", "clk_m", 0,
1620                                     clk_base, 0, 107, &periph_v_regs,
1621                                     periph_clk_enb_refcnt);
1622         clk_register_clkdev(clk, "apbif", "tegra30-ahub");
1623         clks[apbif] = clk;
1624
1625         /* hda2hdmi */
1626         clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m",
1627                                     TEGRA_PERIPH_ON_APB,
1628                                     clk_base, 0, 128, &periph_w_regs,
1629                                     periph_clk_enb_refcnt);
1630         clk_register_clkdev(clk, "hda2hdmi", "tegra30-hda");
1631         clks[hda2hdmi] = clk;
1632
1633         /* sata_cold */
1634         clk = tegra_clk_register_periph_gate("sata_cold", "clk_m",
1635                                     TEGRA_PERIPH_ON_APB,
1636                                     clk_base, 0, 129, &periph_w_regs,
1637                                     periph_clk_enb_refcnt);
1638         clk_register_clkdev(clk, NULL, "tegra_sata_cold");
1639         clks[sata_cold] = clk;
1640
1641         /* dtv */
1642         clk = tegra_clk_register_periph_gate("dtv", "clk_m",
1643                                     TEGRA_PERIPH_ON_APB,
1644                                     clk_base, 0, 79, &periph_u_regs,
1645                                     periph_clk_enb_refcnt);
1646         clk_register_clkdev(clk, NULL, "dtv");
1647         clks[dtv] = clk;
1648
1649         /* emc */
1650         clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1651                                ARRAY_SIZE(mux_pllmcp_clkm), 0,
1652                                clk_base + CLK_SOURCE_EMC,
1653                                30, 2, 0, NULL);
1654         clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
1655                                     57, &periph_h_regs, periph_clk_enb_refcnt);
1656         clk_register_clkdev(clk, "emc", NULL);
1657         clks[emc] = clk;
1658
1659         for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1660                 data = &tegra_periph_clk_list[i];
1661                 clk = tegra_clk_register_periph(data->name, data->parent_names,
1662                                 data->num_parents, &data->periph,
1663                                 clk_base, data->offset);
1664                 clk_register_clkdev(clk, data->con_id, data->dev_id);
1665                 clks[data->clk_id] = clk;
1666         }
1667
1668         for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
1669                 data = &tegra_periph_nodiv_clk_list[i];
1670                 clk = tegra_clk_register_periph_nodiv(data->name,
1671                                         data->parent_names,
1672                                         data->num_parents, &data->periph,
1673                                         clk_base, data->offset);
1674                 clk_register_clkdev(clk, data->con_id, data->dev_id);
1675                 clks[data->clk_id] = clk;
1676         }
1677 }
1678
1679 static void __init tegra30_fixed_clk_init(void)
1680 {
1681         struct clk *clk;
1682
1683         /* clk_32k */
1684         clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
1685                                 32768);
1686         clk_register_clkdev(clk, "clk_32k", NULL);
1687         clks[clk_32k] = clk;
1688
1689         /* clk_m_div2 */
1690         clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
1691                                 CLK_SET_RATE_PARENT, 1, 2);
1692         clk_register_clkdev(clk, "clk_m_div2", NULL);
1693         clks[clk_m_div2] = clk;
1694
1695         /* clk_m_div4 */
1696         clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
1697                                 CLK_SET_RATE_PARENT, 1, 4);
1698         clk_register_clkdev(clk, "clk_m_div4", NULL);
1699         clks[clk_m_div4] = clk;
1700
1701         /* cml0 */
1702         clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1703                                 0, 0, &cml_lock);
1704         clk_register_clkdev(clk, "cml0", NULL);
1705         clks[cml0] = clk;
1706
1707         /* cml1 */
1708         clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1709                                 1, 0, &cml_lock);
1710         clk_register_clkdev(clk, "cml1", NULL);
1711         clks[cml1] = clk;
1712
1713         /* pciex */
1714         clk = clk_register_fixed_rate(NULL, "pciex", "pll_e", 0, 100000000);
1715         clk_register_clkdev(clk, "pciex", NULL);
1716         clks[pciex] = clk;
1717 }
1718
1719 static void __init tegra30_osc_clk_init(void)
1720 {
1721         struct clk *clk;
1722         unsigned int pll_ref_div;
1723
1724         tegra30_clk_measure_input_freq();
1725
1726         /* clk_m */
1727         clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
1728                                 input_freq);
1729         clk_register_clkdev(clk, "clk_m", NULL);
1730         clks[clk_m] = clk;
1731
1732         /* pll_ref */
1733         pll_ref_div = tegra30_get_pll_ref_div();
1734         clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
1735                                 CLK_SET_RATE_PARENT, 1, pll_ref_div);
1736         clk_register_clkdev(clk, "pll_ref", NULL);
1737         clks[pll_ref] = clk;
1738 }
1739
1740 /* Tegra30 CPU clock and reset control functions */
1741 static void tegra30_wait_cpu_in_reset(u32 cpu)
1742 {
1743         unsigned int reg;
1744
1745         do {
1746                 reg = readl(clk_base +
1747                             TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1748                 cpu_relax();
1749         } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
1750
1751         return;
1752 }
1753
1754 static void tegra30_put_cpu_in_reset(u32 cpu)
1755 {
1756         writel(CPU_RESET(cpu),
1757                clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1758         dmb();
1759 }
1760
1761 static void tegra30_cpu_out_of_reset(u32 cpu)
1762 {
1763         writel(CPU_RESET(cpu),
1764                clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
1765         wmb();
1766 }
1767
1768
1769 static void tegra30_enable_cpu_clock(u32 cpu)
1770 {
1771         unsigned int reg;
1772
1773         writel(CPU_CLOCK(cpu),
1774                clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1775         reg = readl(clk_base +
1776                     TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1777 }
1778
1779 static void tegra30_disable_cpu_clock(u32 cpu)
1780 {
1781
1782         unsigned int reg;
1783
1784         reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1785         writel(reg | CPU_CLOCK(cpu),
1786                clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1787 }
1788
1789 #ifdef CONFIG_PM_SLEEP
1790 static bool tegra30_cpu_rail_off_ready(void)
1791 {
1792         unsigned int cpu_rst_status;
1793         int cpu_pwr_status;
1794
1795         cpu_rst_status = readl(clk_base +
1796                                 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1797         cpu_pwr_status = tegra_powergate_is_powered(TEGRA_POWERGATE_CPU1) ||
1798                          tegra_powergate_is_powered(TEGRA_POWERGATE_CPU2) ||
1799                          tegra_powergate_is_powered(TEGRA_POWERGATE_CPU3);
1800
1801         if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status)
1802                 return false;
1803
1804         return true;
1805 }
1806
1807 static void tegra30_cpu_clock_suspend(void)
1808 {
1809         /* switch coresite to clk_m, save off original source */
1810         tegra30_cpu_clk_sctx.clk_csite_src =
1811                                 readl(clk_base + CLK_RESET_SOURCE_CSITE);
1812         writel(3<<30, clk_base + CLK_RESET_SOURCE_CSITE);
1813
1814         tegra30_cpu_clk_sctx.cpu_burst =
1815                                 readl(clk_base + CLK_RESET_CCLK_BURST);
1816         tegra30_cpu_clk_sctx.pllx_base =
1817                                 readl(clk_base + CLK_RESET_PLLX_BASE);
1818         tegra30_cpu_clk_sctx.pllx_misc =
1819                                 readl(clk_base + CLK_RESET_PLLX_MISC);
1820         tegra30_cpu_clk_sctx.cclk_divider =
1821                                 readl(clk_base + CLK_RESET_CCLK_DIVIDER);
1822 }
1823
1824 static void tegra30_cpu_clock_resume(void)
1825 {
1826         unsigned int reg, policy;
1827
1828         /* Is CPU complex already running on PLLX? */
1829         reg = readl(clk_base + CLK_RESET_CCLK_BURST);
1830         policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF;
1831
1832         if (policy == CLK_RESET_CCLK_IDLE_POLICY)
1833                 reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF;
1834         else if (policy == CLK_RESET_CCLK_RUN_POLICY)
1835                 reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF;
1836         else
1837                 BUG();
1838
1839         if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {
1840                 /* restore PLLX settings if CPU is on different PLL */
1841                 writel(tegra30_cpu_clk_sctx.pllx_misc,
1842                                         clk_base + CLK_RESET_PLLX_MISC);
1843                 writel(tegra30_cpu_clk_sctx.pllx_base,
1844                                         clk_base + CLK_RESET_PLLX_BASE);
1845
1846                 /* wait for PLL stabilization if PLLX was enabled */
1847                 if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30))
1848                         udelay(300);
1849         }
1850
1851         /*
1852          * Restore original burst policy setting for calls resulting from CPU
1853          * LP2 in idle or system suspend.
1854          */
1855         writel(tegra30_cpu_clk_sctx.cclk_divider,
1856                                         clk_base + CLK_RESET_CCLK_DIVIDER);
1857         writel(tegra30_cpu_clk_sctx.cpu_burst,
1858                                         clk_base + CLK_RESET_CCLK_BURST);
1859
1860         writel(tegra30_cpu_clk_sctx.clk_csite_src,
1861                                         clk_base + CLK_RESET_SOURCE_CSITE);
1862 }
1863 #endif
1864
1865 static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
1866         .wait_for_reset = tegra30_wait_cpu_in_reset,
1867         .put_in_reset   = tegra30_put_cpu_in_reset,
1868         .out_of_reset   = tegra30_cpu_out_of_reset,
1869         .enable_clock   = tegra30_enable_cpu_clock,
1870         .disable_clock  = tegra30_disable_cpu_clock,
1871 #ifdef CONFIG_PM_SLEEP
1872         .rail_off_ready = tegra30_cpu_rail_off_ready,
1873         .suspend        = tegra30_cpu_clock_suspend,
1874         .resume         = tegra30_cpu_clock_resume,
1875 #endif
1876 };
1877
1878 static __initdata struct tegra_clk_init_table init_table[] = {
1879         {uarta, pll_p, 408000000, 0},
1880         {uartb, pll_p, 408000000, 0},
1881         {uartc, pll_p, 408000000, 0},
1882         {uartd, pll_p, 408000000, 0},
1883         {uarte, pll_p, 408000000, 0},
1884         {pll_a, clk_max, 564480000, 1},
1885         {pll_a_out0, clk_max, 11289600, 1},
1886         {extern1, pll_a_out0, 0, 1},
1887         {clk_out_1_mux, extern1, 0, 0},
1888         {clk_out_1, clk_max, 0, 1},
1889         {blink, clk_max, 0, 1},
1890         {i2s0, pll_a_out0, 11289600, 0},
1891         {i2s1, pll_a_out0, 11289600, 0},
1892         {i2s2, pll_a_out0, 11289600, 0},
1893         {i2s3, pll_a_out0, 11289600, 0},
1894         {i2s4, pll_a_out0, 11289600, 0},
1895         {sdmmc1, pll_p, 48000000, 0},
1896         {sdmmc2, pll_p, 48000000, 0},
1897         {sdmmc3, pll_p, 48000000, 0},
1898         {pll_m, clk_max, 0, 1},
1899         {pclk, clk_max, 0, 1},
1900         {csite, clk_max, 0, 1},
1901         {emc, clk_max, 0, 1},
1902         {mselect, clk_max, 0, 1},
1903         {sbc1, pll_p, 100000000, 0},
1904         {sbc2, pll_p, 100000000, 0},
1905         {sbc3, pll_p, 100000000, 0},
1906         {sbc4, pll_p, 100000000, 0},
1907         {sbc5, pll_p, 100000000, 0},
1908         {sbc6, pll_p, 100000000, 0},
1909         {host1x, pll_c, 150000000, 0},
1910         {disp1, pll_p, 600000000, 0},
1911         {disp2, pll_p, 600000000, 0},
1912         {twd, clk_max, 0, 1},
1913         {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */
1914 };
1915
1916 /*
1917  * Some clocks may be used by different drivers depending on the board
1918  * configuration.  List those here to register them twice in the clock lookup
1919  * table under two names.
1920  */
1921 static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1922         TEGRA_CLK_DUPLICATE(usbd, "utmip-pad", NULL),
1923         TEGRA_CLK_DUPLICATE(usbd, "tegra-ehci.0", NULL),
1924         TEGRA_CLK_DUPLICATE(usbd, "tegra-otg", NULL),
1925         TEGRA_CLK_DUPLICATE(bsev, "tegra-avp", "bsev"),
1926         TEGRA_CLK_DUPLICATE(bsev, "nvavp", "bsev"),
1927         TEGRA_CLK_DUPLICATE(vde, "tegra-aes", "vde"),
1928         TEGRA_CLK_DUPLICATE(bsea, "tegra-aes", "bsea"),
1929         TEGRA_CLK_DUPLICATE(bsea, "nvavp", "bsea"),
1930         TEGRA_CLK_DUPLICATE(cml1, "tegra_sata_cml", NULL),
1931         TEGRA_CLK_DUPLICATE(cml0, "tegra_pcie", "cml"),
1932         TEGRA_CLK_DUPLICATE(pciex, "tegra_pcie", "pciex"),
1933         TEGRA_CLK_DUPLICATE(vcp, "nvavp", "vcp"),
1934         TEGRA_CLK_DUPLICATE(clk_max, NULL, NULL), /* MUST be the last entry */
1935 };
1936
1937 static const struct of_device_id pmc_match[] __initconst = {
1938         { .compatible = "nvidia,tegra30-pmc" },
1939         {},
1940 };
1941
1942 void __init tegra30_clock_init(struct device_node *np)
1943 {
1944         struct device_node *node;
1945         int i;
1946
1947         clk_base = of_iomap(np, 0);
1948         if (!clk_base) {
1949                 pr_err("ioremap tegra30 CAR failed\n");
1950                 return;
1951         }
1952
1953         node = of_find_matching_node(NULL, pmc_match);
1954         if (!node) {
1955                 pr_err("Failed to find pmc node\n");
1956                 BUG();
1957         }
1958
1959         pmc_base = of_iomap(node, 0);
1960         if (!pmc_base) {
1961                 pr_err("Can't map pmc registers\n");
1962                 BUG();
1963         }
1964
1965         tegra30_osc_clk_init();
1966         tegra30_fixed_clk_init();
1967         tegra30_pll_init();
1968         tegra30_super_clk_init();
1969         tegra30_periph_clk_init();
1970         tegra30_audio_clk_init();
1971         tegra30_pmc_clk_init();
1972
1973         for (i = 0; i < ARRAY_SIZE(clks); i++) {
1974                 if (IS_ERR(clks[i])) {
1975                         pr_err("Tegra30 clk %d: register failed with %ld\n",
1976                                i, PTR_ERR(clks[i]));
1977                         BUG();
1978                 }
1979                 if (!clks[i])
1980                         clks[i] = ERR_PTR(-EINVAL);
1981         }
1982
1983         tegra_init_dup_clks(tegra_clk_duplicates, clks, clk_max);
1984
1985         clk_data.clks = clks;
1986         clk_data.clk_num = ARRAY_SIZE(clks);
1987         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
1988
1989         tegra_init_from_table(init_table, clks, clk_max);
1990
1991         tegra_cpu_car_ops = &tegra30_cpu_car_ops;
1992 }