drivers/clk/tegra/clk-tegra114.c

   1 /*
   2  * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/clk-provider.h>
  20 #include <linux/clkdev.h>
  21 #include <linux/of.h>
  22 #include <linux/of_address.h>
  23 #include <linux/delay.h>
  24 #include <linux/export.h>
  25 #include <linux/clk/tegra.h>
  26
  27 #include "clk.h"
  28
  29 #define RST_DEVICES_L                   0x004
  30 #define RST_DEVICES_H                   0x008
  31 #define RST_DEVICES_U                   0x00C
  32 #define RST_DFLL_DVCO                   0x2F4
  33 #define RST_DEVICES_V                   0x358
  34 #define RST_DEVICES_W                   0x35C
  35 #define RST_DEVICES_X                   0x28C
  36 #define RST_DEVICES_SET_L               0x300
  37 #define RST_DEVICES_CLR_L               0x304
  38 #define RST_DEVICES_SET_H               0x308
  39 #define RST_DEVICES_CLR_H               0x30c
  40 #define RST_DEVICES_SET_U               0x310
  41 #define RST_DEVICES_CLR_U               0x314
  42 #define RST_DEVICES_SET_V               0x430
  43 #define RST_DEVICES_CLR_V               0x434
  44 #define RST_DEVICES_SET_W               0x438
  45 #define RST_DEVICES_CLR_W               0x43c
  46 #define CPU_FINETRIM_SELECT             0x4d4   /* override default prop dlys */
  47 #define CPU_FINETRIM_DR                 0x4d8   /* rise->rise prop dly A */
  48 #define CPU_FINETRIM_R                  0x4e4   /* rise->rise prop dly inc A */
  49 #define RST_DEVICES_NUM                 5
  50
  51 /* RST_DFLL_DVCO bitfields */
  52 #define DVFS_DFLL_RESET_SHIFT           0
  53
  54 /* CPU_FINETRIM_SELECT and CPU_FINETRIM_DR bitfields */
  55 #define CPU_FINETRIM_1_FCPU_1           BIT(0)  /* fcpu0 */
  56 #define CPU_FINETRIM_1_FCPU_2           BIT(1)  /* fcpu1 */
  57 #define CPU_FINETRIM_1_FCPU_3           BIT(2)  /* fcpu2 */
  58 #define CPU_FINETRIM_1_FCPU_4           BIT(3)  /* fcpu3 */
  59 #define CPU_FINETRIM_1_FCPU_5           BIT(4)  /* fl2 */
  60 #define CPU_FINETRIM_1_FCPU_6           BIT(5)  /* ftop */
  61
  62 /* CPU_FINETRIM_R bitfields */
  63 #define CPU_FINETRIM_R_FCPU_1_SHIFT     0               /* fcpu0 */
  64 #define CPU_FINETRIM_R_FCPU_1_MASK      (0x3 << CPU_FINETRIM_R_FCPU_1_SHIFT)
  65 #define CPU_FINETRIM_R_FCPU_2_SHIFT     2               /* fcpu1 */
  66 #define CPU_FINETRIM_R_FCPU_2_MASK      (0x3 << CPU_FINETRIM_R_FCPU_2_SHIFT)
  67 #define CPU_FINETRIM_R_FCPU_3_SHIFT     4               /* fcpu2 */
  68 #define CPU_FINETRIM_R_FCPU_3_MASK      (0x3 << CPU_FINETRIM_R_FCPU_3_SHIFT)
  69 #define CPU_FINETRIM_R_FCPU_4_SHIFT     6               /* fcpu3 */
  70 #define CPU_FINETRIM_R_FCPU_4_MASK      (0x3 << CPU_FINETRIM_R_FCPU_4_SHIFT)
  71 #define CPU_FINETRIM_R_FCPU_5_SHIFT     8               /* fl2 */
  72 #define CPU_FINETRIM_R_FCPU_5_MASK      (0x3 << CPU_FINETRIM_R_FCPU_5_SHIFT)
  73 #define CPU_FINETRIM_R_FCPU_6_SHIFT     10              /* ftop */
  74 #define CPU_FINETRIM_R_FCPU_6_MASK      (0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT)
  75
  76 #define CLK_OUT_ENB_L                   0x010
  77 #define CLK_OUT_ENB_H                   0x014
  78 #define CLK_OUT_ENB_U                   0x018
  79 #define CLK_OUT_ENB_V                   0x360
  80 #define CLK_OUT_ENB_W                   0x364
  81 #define CLK_OUT_ENB_X                   0x280
  82 #define CLK_OUT_ENB_SET_L               0x320
  83 #define CLK_OUT_ENB_CLR_L               0x324
  84 #define CLK_OUT_ENB_SET_H               0x328
  85 #define CLK_OUT_ENB_CLR_H               0x32c
  86 #define CLK_OUT_ENB_SET_U               0x330
  87 #define CLK_OUT_ENB_CLR_U               0x334
  88 #define CLK_OUT_ENB_SET_V               0x440
  89 #define CLK_OUT_ENB_CLR_V               0x444
  90 #define CLK_OUT_ENB_SET_W               0x448
  91 #define CLK_OUT_ENB_CLR_W               0x44c
  92 #define CLK_OUT_ENB_SET_X               0x284
  93 #define CLK_OUT_ENB_CLR_X               0x288
  94 #define CLK_OUT_ENB_NUM                 6
  95
  96 #define PLLC_BASE 0x80
  97 #define PLLC_MISC2 0x88
  98 #define PLLC_MISC 0x8c
  99 #define PLLC2_BASE 0x4e8
 100 #define PLLC2_MISC 0x4ec
 101 #define PLLC3_BASE 0x4fc
 102 #define PLLC3_MISC 0x500
 103 #define PLLM_BASE 0x90
 104 #define PLLM_MISC 0x9c
 105 #define PLLP_BASE 0xa0
 106 #define PLLP_MISC 0xac
 107 #define PLLX_BASE 0xe0
 108 #define PLLX_MISC 0xe4
 109 #define PLLX_MISC2 0x514
 110 #define PLLX_MISC3 0x518
 111 #define PLLD_BASE 0xd0
 112 #define PLLD_MISC 0xdc
 113 #define PLLD2_BASE 0x4b8
 114 #define PLLD2_MISC 0x4bc
 115 #define PLLE_BASE 0xe8
 116 #define PLLE_MISC 0xec
 117 #define PLLA_BASE 0xb0
 118 #define PLLA_MISC 0xbc
 119 #define PLLU_BASE 0xc0
 120 #define PLLU_MISC 0xcc
 121 #define PLLRE_BASE 0x4c4
 122 #define PLLRE_MISC 0x4c8
 123
 124 #define PLL_MISC_LOCK_ENABLE 18
 125 #define PLLC_MISC_LOCK_ENABLE 24
 126 #define PLLDU_MISC_LOCK_ENABLE 22
 127 #define PLLE_MISC_LOCK_ENABLE 9
 128 #define PLLRE_MISC_LOCK_ENABLE 30
 129
 130 #define PLLC_IDDQ_BIT 26
 131 #define PLLX_IDDQ_BIT 3
 132 #define PLLRE_IDDQ_BIT 16
 133
 134 #define PLL_BASE_LOCK BIT(27)
 135 #define PLLE_MISC_LOCK BIT(11)
 136 #define PLLRE_MISC_LOCK BIT(24)
 137 #define PLLCX_BASE_LOCK (BIT(26)|BIT(27))
 138
 139 #define PLLE_AUX 0x48c
 140 #define PLLC_OUT 0x84
 141 #define PLLM_OUT 0x94
 142 #define PLLP_OUTA 0xa4
 143 #define PLLP_OUTB 0xa8
 144 #define PLLA_OUT 0xb4
 145
 146 #define AUDIO_SYNC_CLK_I2S0 0x4a0
 147 #define AUDIO_SYNC_CLK_I2S1 0x4a4
 148 #define AUDIO_SYNC_CLK_I2S2 0x4a8
 149 #define AUDIO_SYNC_CLK_I2S3 0x4ac
 150 #define AUDIO_SYNC_CLK_I2S4 0x4b0
 151 #define AUDIO_SYNC_CLK_SPDIF 0x4b4
 152
 153 #define AUDIO_SYNC_DOUBLER 0x49c
 154
 155 #define PMC_CLK_OUT_CNTRL 0x1a8
 156 #define PMC_DPD_PADS_ORIDE 0x1c
 157 #define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
 158 #define PMC_CTRL 0
 159 #define PMC_CTRL_BLINK_ENB 7
 160 #define PMC_BLINK_TIMER 0x40
 161
 162 #define OSC_CTRL                        0x50
 163 #define OSC_CTRL_OSC_FREQ_SHIFT         28
 164 #define OSC_CTRL_PLL_REF_DIV_SHIFT      26
 165
 166 #define PLLXC_SW_MAX_P                  6
 167
 168 #define CCLKG_BURST_POLICY 0x368
 169 #define CCLKLP_BURST_POLICY 0x370
 170 #define SCLK_BURST_POLICY 0x028
 171 #define SYSTEM_CLK_RATE 0x030
 172
 173 #define UTMIP_PLL_CFG2 0x488
 174 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
 175 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
 176 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
 177 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
 178 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
 179
 180 #define UTMIP_PLL_CFG1 0x484
 181 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
 182 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
 183 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
 184 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
 185 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
 186 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
 187 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
 188
 189 #define UTMIPLL_HW_PWRDN_CFG0                   0x52c
 190 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE   BIT(25)
 191 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE        BIT(24)
 192 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET       BIT(6)
 193 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE     BIT(5)
 194 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL      BIT(4)
 195 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL  BIT(2)
 196 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE     BIT(1)
 197 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL        BIT(0)
 198
 199 #define CLK_SOURCE_I2S0 0x1d8
 200 #define CLK_SOURCE_I2S1 0x100
 201 #define CLK_SOURCE_I2S2 0x104
 202 #define CLK_SOURCE_NDFLASH 0x160
 203 #define CLK_SOURCE_I2S3 0x3bc
 204 #define CLK_SOURCE_I2S4 0x3c0
 205 #define CLK_SOURCE_SPDIF_OUT 0x108
 206 #define CLK_SOURCE_SPDIF_IN 0x10c
 207 #define CLK_SOURCE_PWM 0x110
 208 #define CLK_SOURCE_ADX 0x638
 209 #define CLK_SOURCE_AMX 0x63c
 210 #define CLK_SOURCE_HDA 0x428
 211 #define CLK_SOURCE_HDA2CODEC_2X 0x3e4
 212 #define CLK_SOURCE_SBC1 0x134
 213 #define CLK_SOURCE_SBC2 0x118
 214 #define CLK_SOURCE_SBC3 0x11c
 215 #define CLK_SOURCE_SBC4 0x1b4
 216 #define CLK_SOURCE_SBC5 0x3c8
 217 #define CLK_SOURCE_SBC6 0x3cc
 218 #define CLK_SOURCE_SATA_OOB 0x420
 219 #define CLK_SOURCE_SATA 0x424
 220 #define CLK_SOURCE_NDSPEED 0x3f8
 221 #define CLK_SOURCE_VFIR 0x168
 222 #define CLK_SOURCE_SDMMC1 0x150
 223 #define CLK_SOURCE_SDMMC2 0x154
 224 #define CLK_SOURCE_SDMMC3 0x1bc
 225 #define CLK_SOURCE_SDMMC4 0x164
 226 #define CLK_SOURCE_VDE 0x1c8
 227 #define CLK_SOURCE_CSITE 0x1d4
 228 #define CLK_SOURCE_LA 0x1f8
 229 #define CLK_SOURCE_TRACE 0x634
 230 #define CLK_SOURCE_OWR 0x1cc
 231 #define CLK_SOURCE_NOR 0x1d0
 232 #define CLK_SOURCE_MIPI 0x174
 233 #define CLK_SOURCE_I2C1 0x124
 234 #define CLK_SOURCE_I2C2 0x198
 235 #define CLK_SOURCE_I2C3 0x1b8
 236 #define CLK_SOURCE_I2C4 0x3c4
 237 #define CLK_SOURCE_I2C5 0x128
 238 #define CLK_SOURCE_UARTA 0x178
 239 #define CLK_SOURCE_UARTB 0x17c
 240 #define CLK_SOURCE_UARTC 0x1a0
 241 #define CLK_SOURCE_UARTD 0x1c0
 242 #define CLK_SOURCE_UARTE 0x1c4
 243 #define CLK_SOURCE_UARTA_DBG 0x178
 244 #define CLK_SOURCE_UARTB_DBG 0x17c
 245 #define CLK_SOURCE_UARTC_DBG 0x1a0
 246 #define CLK_SOURCE_UARTD_DBG 0x1c0
 247 #define CLK_SOURCE_UARTE_DBG 0x1c4
 248 #define CLK_SOURCE_3D 0x158
 249 #define CLK_SOURCE_2D 0x15c
 250 #define CLK_SOURCE_VI_SENSOR 0x1a8
 251 #define CLK_SOURCE_VI 0x148
 252 #define CLK_SOURCE_EPP 0x16c
 253 #define CLK_SOURCE_MSENC 0x1f0
 254 #define CLK_SOURCE_TSEC 0x1f4
 255 #define CLK_SOURCE_HOST1X 0x180
 256 #define CLK_SOURCE_HDMI 0x18c
 257 #define CLK_SOURCE_DISP1 0x138
 258 #define CLK_SOURCE_DISP2 0x13c
 259 #define CLK_SOURCE_CILAB 0x614
 260 #define CLK_SOURCE_CILCD 0x618
 261 #define CLK_SOURCE_CILE 0x61c
 262 #define CLK_SOURCE_DSIALP 0x620
 263 #define CLK_SOURCE_DSIBLP 0x624
 264 #define CLK_SOURCE_TSENSOR 0x3b8
 265 #define CLK_SOURCE_D_AUDIO 0x3d0
 266 #define CLK_SOURCE_DAM0 0x3d8
 267 #define CLK_SOURCE_DAM1 0x3dc
 268 #define CLK_SOURCE_DAM2 0x3e0
 269 #define CLK_SOURCE_ACTMON 0x3e8
 270 #define CLK_SOURCE_EXTERN1 0x3ec
 271 #define CLK_SOURCE_EXTERN2 0x3f0
 272 #define CLK_SOURCE_EXTERN3 0x3f4
 273 #define CLK_SOURCE_I2CSLOW 0x3fc
 274 #define CLK_SOURCE_SE 0x42c
 275 #define CLK_SOURCE_MSELECT 0x3b4
 276 #define CLK_SOURCE_DFLL_REF 0x62c
 277 #define CLK_SOURCE_DFLL_SOC 0x630
 278 #define CLK_SOURCE_SOC_THERM 0x644
 279 #define CLK_SOURCE_XUSB_HOST_SRC 0x600
 280 #define CLK_SOURCE_XUSB_FALCON_SRC 0x604
 281 #define CLK_SOURCE_XUSB_FS_SRC 0x608
 282 #define CLK_SOURCE_XUSB_SS_SRC 0x610
 283 #define CLK_SOURCE_XUSB_DEV_SRC 0x60c
 284 #define CLK_SOURCE_EMC 0x19c
 285
 286 /* PLLM override registers */
 287 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
 288 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
 289
 290 static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
 291
 292 static void __iomem *clk_base;
 293 static void __iomem *pmc_base;
 294
 295 static DEFINE_SPINLOCK(pll_d_lock);
 296 static DEFINE_SPINLOCK(pll_d2_lock);
 297 static DEFINE_SPINLOCK(pll_u_lock);
 298 static DEFINE_SPINLOCK(pll_div_lock);
 299 static DEFINE_SPINLOCK(pll_re_lock);
 300 static DEFINE_SPINLOCK(clk_doubler_lock);
 301 static DEFINE_SPINLOCK(clk_out_lock);
 302 static DEFINE_SPINLOCK(sysrate_lock);
 303
 304 static struct div_nmp pllxc_nmp = {
 305         .divm_shift = 0,
 306         .divm_width = 8,
 307         .divn_shift = 8,
 308         .divn_width = 8,
 309         .divp_shift = 20,
 310         .divp_width = 4,
 311 };
 312
 313 static struct pdiv_map pllxc_p[] = {
 314         { .pdiv = 1, .hw_val = 0 },
 315         { .pdiv = 2, .hw_val = 1 },
 316         { .pdiv = 3, .hw_val = 2 },
 317         { .pdiv = 4, .hw_val = 3 },
 318         { .pdiv = 5, .hw_val = 4 },
 319         { .pdiv = 6, .hw_val = 5 },
 320         { .pdiv = 8, .hw_val = 6 },
 321         { .pdiv = 10, .hw_val = 7 },
 322         { .pdiv = 12, .hw_val = 8 },
 323         { .pdiv = 16, .hw_val = 9 },
 324         { .pdiv = 12, .hw_val = 10 },
 325         { .pdiv = 16, .hw_val = 11 },
 326         { .pdiv = 20, .hw_val = 12 },
 327         { .pdiv = 24, .hw_val = 13 },
 328         { .pdiv = 32, .hw_val = 14 },
 329         { .pdiv = 0, .hw_val = 0 },
 330 };
 331
 332 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
 333         { 12000000, 624000000, 104, 0, 2},
 334         { 12000000, 600000000, 100, 0, 2},
 335         { 13000000, 600000000,  92, 0, 2},      /* actual: 598.0 MHz */
 336         { 16800000, 600000000,  71, 0, 2},      /* actual: 596.4 MHz */
 337         { 19200000, 600000000,  62, 0, 2},      /* actual: 595.2 MHz */
 338         { 26000000, 600000000,  92, 1, 2},      /* actual: 598.0 MHz */
 339         { 0, 0, 0, 0, 0, 0 },
 340 };
 341
 342 static struct tegra_clk_pll_params pll_c_params = {
 343         .input_min = 12000000,
 344         .input_max = 800000000,
 345         .cf_min = 12000000,
 346         .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
 347         .vco_min = 600000000,
 348         .vco_max = 1400000000,
 349         .base_reg = PLLC_BASE,
 350         .misc_reg = PLLC_MISC,
 351         .lock_mask = PLL_BASE_LOCK,
 352         .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE,
 353         .lock_delay = 300,
 354         .iddq_reg = PLLC_MISC,
 355         .iddq_bit_idx = PLLC_IDDQ_BIT,
 356         .max_p = PLLXC_SW_MAX_P,
 357         .dyn_ramp_reg = PLLC_MISC2,
 358         .stepa_shift = 17,
 359         .stepb_shift = 9,
 360         .pdiv_tohw = pllxc_p,
 361         .div_nmp = &pllxc_nmp,
 362 };
 363
 364 static struct div_nmp pllcx_nmp = {
 365         .divm_shift = 0,
 366         .divm_width = 2,
 367         .divn_shift = 8,
 368         .divn_width = 8,
 369         .divp_shift = 20,
 370         .divp_width = 3,
 371 };
 372
 373 static struct pdiv_map pllc_p[] = {
 374         { .pdiv = 1, .hw_val = 0 },
 375         { .pdiv = 2, .hw_val = 1 },
 376         { .pdiv = 4, .hw_val = 3 },
 377         { .pdiv = 8, .hw_val = 5 },
 378         { .pdiv = 16, .hw_val = 7 },
 379         { .pdiv = 0, .hw_val = 0 },
 380 };
 381
 382 static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
 383         {12000000, 600000000, 100, 0, 2},
 384         {13000000, 600000000, 92, 0, 2},        /* actual: 598.0 MHz */
 385         {16800000, 600000000, 71, 0, 2},        /* actual: 596.4 MHz */
 386         {19200000, 600000000, 62, 0, 2},        /* actual: 595.2 MHz */
 387         {26000000, 600000000, 92, 1, 2},        /* actual: 598.0 MHz */
 388         {0, 0, 0, 0, 0, 0},
 389 };
 390
 391 static struct tegra_clk_pll_params pll_c2_params = {
 392         .input_min = 12000000,
 393         .input_max = 48000000,
 394         .cf_min = 12000000,
 395         .cf_max = 19200000,
 396         .vco_min = 600000000,
 397         .vco_max = 1200000000,
 398         .base_reg = PLLC2_BASE,
 399         .misc_reg = PLLC2_MISC,
 400         .lock_mask = PLL_BASE_LOCK,
 401         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 402         .lock_delay = 300,
 403         .pdiv_tohw = pllc_p,
 404         .div_nmp = &pllcx_nmp,
 405         .max_p = 7,
 406         .ext_misc_reg[0] = 0x4f0,
 407         .ext_misc_reg[1] = 0x4f4,
 408         .ext_misc_reg[2] = 0x4f8,
 409 };
 410
 411 static struct tegra_clk_pll_params pll_c3_params = {
 412         .input_min = 12000000,
 413         .input_max = 48000000,
 414         .cf_min = 12000000,
 415         .cf_max = 19200000,
 416         .vco_min = 600000000,
 417         .vco_max = 1200000000,
 418         .base_reg = PLLC3_BASE,
 419         .misc_reg = PLLC3_MISC,
 420         .lock_mask = PLL_BASE_LOCK,
 421         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 422         .lock_delay = 300,
 423         .pdiv_tohw = pllc_p,
 424         .div_nmp = &pllcx_nmp,
 425         .max_p = 7,
 426         .ext_misc_reg[0] = 0x504,
 427         .ext_misc_reg[1] = 0x508,
 428         .ext_misc_reg[2] = 0x50c,
 429 };
 430
 431 static struct div_nmp pllm_nmp = {
 432         .divm_shift = 0,
 433         .divm_width = 8,
 434         .override_divm_shift = 0,
 435         .divn_shift = 8,
 436         .divn_width = 8,
 437         .override_divn_shift = 8,
 438         .divp_shift = 20,
 439         .divp_width = 1,
 440         .override_divp_shift = 27,
 441 };
 442
 443 static struct pdiv_map pllm_p[] = {
 444         { .pdiv = 1, .hw_val = 0 },
 445         { .pdiv = 2, .hw_val = 1 },
 446         { .pdiv = 0, .hw_val = 0 },
 447 };
 448
 449 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
 450         {12000000, 800000000, 66, 0, 1},        /* actual: 792.0 MHz */
 451         {13000000, 800000000, 61, 0, 1},        /* actual: 793.0 MHz */
 452         {16800000, 800000000, 47, 0, 1},        /* actual: 789.6 MHz */
 453         {19200000, 800000000, 41, 0, 1},        /* actual: 787.2 MHz */
 454         {26000000, 800000000, 61, 1, 1},        /* actual: 793.0 MHz */
 455         {0, 0, 0, 0, 0, 0},
 456 };
 457
 458 static struct tegra_clk_pll_params pll_m_params = {
 459         .input_min = 12000000,
 460         .input_max = 500000000,
 461         .cf_min = 12000000,
 462         .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
 463         .vco_min = 400000000,
 464         .vco_max = 1066000000,
 465         .base_reg = PLLM_BASE,
 466         .misc_reg = PLLM_MISC,
 467         .lock_mask = PLL_BASE_LOCK,
 468         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 469         .lock_delay = 300,
 470         .max_p = 2,
 471         .pdiv_tohw = pllm_p,
 472         .div_nmp = &pllm_nmp,
 473         .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
 474         .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
 475 };
 476
 477 static struct div_nmp pllp_nmp = {
 478         .divm_shift = 0,
 479         .divm_width = 5,
 480         .divn_shift = 8,
 481         .divn_width = 10,
 482         .divp_shift = 20,
 483         .divp_width = 3,
 484 };
 485
 486 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
 487         {12000000, 216000000, 432, 12, 1, 8},
 488         {13000000, 216000000, 432, 13, 1, 8},
 489         {16800000, 216000000, 360, 14, 1, 8},
 490         {19200000, 216000000, 360, 16, 1, 8},
 491         {26000000, 216000000, 432, 26, 1, 8},
 492         {0, 0, 0, 0, 0, 0},
 493 };
 494
 495 static struct tegra_clk_pll_params pll_p_params = {
 496         .input_min = 2000000,
 497         .input_max = 31000000,
 498         .cf_min = 1000000,
 499         .cf_max = 6000000,
 500         .vco_min = 200000000,
 501         .vco_max = 700000000,
 502         .base_reg = PLLP_BASE,
 503         .misc_reg = PLLP_MISC,
 504         .lock_mask = PLL_BASE_LOCK,
 505         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 506         .lock_delay = 300,
 507         .div_nmp = &pllp_nmp,
 508 };
 509
 510 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
 511         {9600000, 282240000, 147, 5, 0, 4},
 512         {9600000, 368640000, 192, 5, 0, 4},
 513         {9600000, 240000000, 200, 8, 0, 8},
 514
 515         {28800000, 282240000, 245, 25, 0, 8},
 516         {28800000, 368640000, 320, 25, 0, 8},
 517         {28800000, 240000000, 200, 24, 0, 8},
 518         {0, 0, 0, 0, 0, 0},
 519 };
 520
 521
 522 static struct tegra_clk_pll_params pll_a_params = {
 523         .input_min = 2000000,
 524         .input_max = 31000000,
 525         .cf_min = 1000000,
 526         .cf_max = 6000000,
 527         .vco_min = 200000000,
 528         .vco_max = 700000000,
 529         .base_reg = PLLA_BASE,
 530         .misc_reg = PLLA_MISC,
 531         .lock_mask = PLL_BASE_LOCK,
 532         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 533         .lock_delay = 300,
 534         .div_nmp = &pllp_nmp,
 535 };
 536
 537 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
 538         {12000000, 216000000, 864, 12, 2, 12},
 539         {13000000, 216000000, 864, 13, 2, 12},
 540         {16800000, 216000000, 720, 14, 2, 12},
 541         {19200000, 216000000, 720, 16, 2, 12},
 542         {26000000, 216000000, 864, 26, 2, 12},
 543
 544         {12000000, 594000000, 594, 12, 0, 12},
 545         {13000000, 594000000, 594, 13, 0, 12},
 546         {16800000, 594000000, 495, 14, 0, 12},
 547         {19200000, 594000000, 495, 16, 0, 12},
 548         {26000000, 594000000, 594, 26, 0, 12},
 549
 550         {12000000, 1000000000, 1000, 12, 0, 12},
 551         {13000000, 1000000000, 1000, 13, 0, 12},
 552         {19200000, 1000000000, 625, 12, 0, 12},
 553         {26000000, 1000000000, 1000, 26, 0, 12},
 554
 555         {0, 0, 0, 0, 0, 0},
 556 };
 557
 558 static struct tegra_clk_pll_params pll_d_params = {
 559         .input_min = 2000000,
 560         .input_max = 40000000,
 561         .cf_min = 1000000,
 562         .cf_max = 6000000,
 563         .vco_min = 500000000,
 564         .vco_max = 1000000000,
 565         .base_reg = PLLD_BASE,
 566         .misc_reg = PLLD_MISC,
 567         .lock_mask = PLL_BASE_LOCK,
 568         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
 569         .lock_delay = 1000,
 570         .div_nmp = &pllp_nmp,
 571 };
 572
 573 static struct tegra_clk_pll_params pll_d2_params = {
 574         .input_min = 2000000,
 575         .input_max = 40000000,
 576         .cf_min = 1000000,
 577         .cf_max = 6000000,
 578         .vco_min = 500000000,
 579         .vco_max = 1000000000,
 580         .base_reg = PLLD2_BASE,
 581         .misc_reg = PLLD2_MISC,
 582         .lock_mask = PLL_BASE_LOCK,
 583         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
 584         .lock_delay = 1000,
 585         .div_nmp = &pllp_nmp,
 586 };
 587
 588 static struct pdiv_map pllu_p[] = {
 589         { .pdiv = 1, .hw_val = 1 },
 590         { .pdiv = 2, .hw_val = 0 },
 591         { .pdiv = 0, .hw_val = 0 },
 592 };
 593
 594 static struct div_nmp pllu_nmp = {
 595         .divm_shift = 0,
 596         .divm_width = 5,
 597         .divn_shift = 8,
 598         .divn_width = 10,
 599         .divp_shift = 20,
 600         .divp_width = 1,
 601 };
 602
 603 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
 604         {12000000, 480000000, 960, 12, 0, 12},
 605         {13000000, 480000000, 960, 13, 0, 12},
 606         {16800000, 480000000, 400, 7, 0, 5},
 607         {19200000, 480000000, 200, 4, 0, 3},
 608         {26000000, 480000000, 960, 26, 0, 12},
 609         {0, 0, 0, 0, 0, 0},
 610 };
 611
 612 static struct tegra_clk_pll_params pll_u_params = {
 613         .input_min = 2000000,
 614         .input_max = 40000000,
 615         .cf_min = 1000000,
 616         .cf_max = 6000000,
 617         .vco_min = 480000000,
 618         .vco_max = 960000000,
 619         .base_reg = PLLU_BASE,
 620         .misc_reg = PLLU_MISC,
 621         .lock_mask = PLL_BASE_LOCK,
 622         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
 623         .lock_delay = 1000,
 624         .pdiv_tohw = pllu_p,
 625         .div_nmp = &pllu_nmp,
 626 };
 627
 628 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
 629         /* 1 GHz */
 630         {12000000, 1000000000, 83, 0, 1},       /* actual: 996.0 MHz */
 631         {13000000, 1000000000, 76, 0, 1},       /* actual: 988.0 MHz */
 632         {16800000, 1000000000, 59, 0, 1},       /* actual: 991.2 MHz */
 633         {19200000, 1000000000, 52, 0, 1},       /* actual: 998.4 MHz */
 634         {26000000, 1000000000, 76, 1, 1},       /* actual: 988.0 MHz */
 635
 636         {0, 0, 0, 0, 0, 0},
 637 };
 638
 639 static struct tegra_clk_pll_params pll_x_params = {
 640         .input_min = 12000000,
 641         .input_max = 800000000,
 642         .cf_min = 12000000,
 643         .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
 644         .vco_min = 700000000,
 645         .vco_max = 2400000000U,
 646         .base_reg = PLLX_BASE,
 647         .misc_reg = PLLX_MISC,
 648         .lock_mask = PLL_BASE_LOCK,
 649         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
 650         .lock_delay = 300,
 651         .iddq_reg = PLLX_MISC3,
 652         .iddq_bit_idx = PLLX_IDDQ_BIT,
 653         .max_p = PLLXC_SW_MAX_P,
 654         .dyn_ramp_reg = PLLX_MISC2,
 655         .stepa_shift = 16,
 656         .stepb_shift = 24,
 657         .pdiv_tohw = pllxc_p,
 658         .div_nmp = &pllxc_nmp,
 659 };
 660
 661 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
 662         /* PLLE special case: use cpcon field to store cml divider value */
 663         {336000000, 100000000, 100, 21, 16, 11},
 664         {312000000, 100000000, 200, 26, 24, 13},
 665         {0, 0, 0, 0, 0, 0},
 666 };
 667
 668 static struct div_nmp plle_nmp = {
 669         .divm_shift = 0,
 670         .divm_width = 8,
 671         .divn_shift = 8,
 672         .divn_width = 8,
 673         .divp_shift = 24,
 674         .divp_width = 4,
 675 };
 676
 677 static struct tegra_clk_pll_params pll_e_params = {
 678         .input_min = 12000000,
 679         .input_max = 1000000000,
 680         .cf_min = 12000000,
 681         .cf_max = 75000000,
 682         .vco_min = 1600000000,
 683         .vco_max = 2400000000U,
 684         .base_reg = PLLE_BASE,
 685         .misc_reg = PLLE_MISC,
 686         .aux_reg = PLLE_AUX,
 687         .lock_mask = PLLE_MISC_LOCK,
 688         .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
 689         .lock_delay = 300,
 690         .div_nmp = &plle_nmp,
 691 };
 692
 693 static struct div_nmp pllre_nmp = {
 694         .divm_shift = 0,
 695         .divm_width = 8,
 696         .divn_shift = 8,
 697         .divn_width = 8,
 698         .divp_shift = 16,
 699         .divp_width = 4,
 700 };
 701
 702 static struct tegra_clk_pll_params pll_re_vco_params = {
 703         .input_min = 12000000,
 704         .input_max = 1000000000,
 705         .cf_min = 12000000,
 706         .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
 707         .vco_min = 300000000,
 708         .vco_max = 600000000,
 709         .base_reg = PLLRE_BASE,
 710         .misc_reg = PLLRE_MISC,
 711         .lock_mask = PLLRE_MISC_LOCK,
 712         .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
 713         .lock_delay = 300,
 714         .iddq_reg = PLLRE_MISC,
 715         .iddq_bit_idx = PLLRE_IDDQ_BIT,
 716         .div_nmp = &pllre_nmp,
 717 };
 718
 719 /* Peripheral clock registers */
 720
 721 static struct tegra_clk_periph_regs periph_l_regs = {
 722         .enb_reg = CLK_OUT_ENB_L,
 723         .enb_set_reg = CLK_OUT_ENB_SET_L,
 724         .enb_clr_reg = CLK_OUT_ENB_CLR_L,
 725         .rst_reg = RST_DEVICES_L,
 726         .rst_set_reg = RST_DEVICES_SET_L,
 727         .rst_clr_reg = RST_DEVICES_CLR_L,
 728 };
 729
 730 static struct tegra_clk_periph_regs periph_h_regs = {
 731         .enb_reg = CLK_OUT_ENB_H,
 732         .enb_set_reg = CLK_OUT_ENB_SET_H,
 733         .enb_clr_reg = CLK_OUT_ENB_CLR_H,
 734         .rst_reg = RST_DEVICES_H,
 735         .rst_set_reg = RST_DEVICES_SET_H,
 736         .rst_clr_reg = RST_DEVICES_CLR_H,
 737 };
 738
 739 static struct tegra_clk_periph_regs periph_u_regs = {
 740         .enb_reg = CLK_OUT_ENB_U,
 741         .enb_set_reg = CLK_OUT_ENB_SET_U,
 742         .enb_clr_reg = CLK_OUT_ENB_CLR_U,
 743         .rst_reg = RST_DEVICES_U,
 744         .rst_set_reg = RST_DEVICES_SET_U,
 745         .rst_clr_reg = RST_DEVICES_CLR_U,
 746 };
 747
 748 static struct tegra_clk_periph_regs periph_v_regs = {
 749         .enb_reg = CLK_OUT_ENB_V,
 750         .enb_set_reg = CLK_OUT_ENB_SET_V,
 751         .enb_clr_reg = CLK_OUT_ENB_CLR_V,
 752         .rst_reg = RST_DEVICES_V,
 753         .rst_set_reg = RST_DEVICES_SET_V,
 754         .rst_clr_reg = RST_DEVICES_CLR_V,
 755 };
 756
 757 static struct tegra_clk_periph_regs periph_w_regs = {
 758         .enb_reg = CLK_OUT_ENB_W,
 759         .enb_set_reg = CLK_OUT_ENB_SET_W,
 760         .enb_clr_reg = CLK_OUT_ENB_CLR_W,
 761         .rst_reg = RST_DEVICES_W,
 762         .rst_set_reg = RST_DEVICES_SET_W,
 763         .rst_clr_reg = RST_DEVICES_CLR_W,
 764 };
 765
 766 /* possible OSC frequencies in Hz */
 767 static unsigned long tegra114_input_freq[] = {
 768         [0] = 13000000,
 769         [1] = 16800000,
 770         [4] = 19200000,
 771         [5] = 38400000,
 772         [8] = 12000000,
 773         [9] = 48000000,
 774         [12] = 260000000,
 775 };
 776
 777 #define MASK(x) (BIT(x) - 1)
 778
 779 #define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
 780                             _clk_num, _regs, _gate_flags, _clk_id)      \
 781         TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
 782                         30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num,    \
 783                         periph_clk_enb_refcnt, _gate_flags, _clk_id,    \
 784                         _parents##_idx, 0)
 785
 786 #define TEGRA_INIT_DATA_MUX_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\
 787                             _clk_num, _regs, _gate_flags, _clk_id, flags)\
 788         TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
 789                         30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num,    \
 790                         periph_clk_enb_refcnt, _gate_flags, _clk_id,    \
 791                         _parents##_idx, flags)
 792
 793 #define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \
 794                              _clk_num, _regs, _gate_flags, _clk_id)     \
 795         TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
 796                         29, MASK(3), 0, 0, 8, 1, 0, _regs, _clk_num,    \
 797                         periph_clk_enb_refcnt, _gate_flags, _clk_id,    \
 798                         _parents##_idx, 0)
 799
 800 #define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \
 801                             _clk_num, _regs, _gate_flags, _clk_id)      \
 802         TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
 803                         30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
 804                         _clk_num, periph_clk_enb_refcnt, _gate_flags,   \
 805                         _clk_id, _parents##_idx, 0)
 806
 807 #define TEGRA_INIT_DATA_INT_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\
 808                             _clk_num, _regs, _gate_flags, _clk_id, flags)\
 809         TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
 810                         30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
 811                         _clk_num, periph_clk_enb_refcnt, _gate_flags,   \
 812                         _clk_id, _parents##_idx, flags)
 813
 814 #define TEGRA_INIT_DATA_INT8(_name, _con_id, _dev_id, _parents, _offset,\
 815                             _clk_num, _regs, _gate_flags, _clk_id)      \
 816         TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
 817                         29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
 818                         _clk_num, periph_clk_enb_refcnt, _gate_flags,   \
 819                         _clk_id, _parents##_idx, 0)
 820
 821 #define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\
 822                              _clk_num, _regs, _clk_id)                  \
 823         TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
 824                         30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs,\
 825                         _clk_num, periph_clk_enb_refcnt, 0, _clk_id,    \
 826                         _parents##_idx, 0)
 827
 828 #define TEGRA_INIT_DATA_I2C(_name, _con_id, _dev_id, _parents, _offset,\
 829                              _clk_num, _regs, _clk_id)                  \
 830         TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
 831                         30, MASK(2), 0, 0, 16, 0, 0, _regs, _clk_num,   \
 832                         periph_clk_enb_refcnt, 0, _clk_id, _parents##_idx, 0)
 833
 834 #define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \
 835                               _mux_shift, _mux_mask, _clk_num, _regs,   \
 836                               _gate_flags, _clk_id)                     \
 837         TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
 838                         _mux_shift, _mux_mask, 0, 0, 0, 0, 0, _regs,    \
 839                         _clk_num, periph_clk_enb_refcnt, _gate_flags,   \
 840                         _clk_id, _parents##_idx, 0)
 841
 842 #define TEGRA_INIT_DATA_XUSB(_name, _con_id, _dev_id, _parents, _offset, \
 843                              _clk_num, _regs, _gate_flags, _clk_id)      \
 844         TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset, \
 845                         29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \
 846                         _clk_num, periph_clk_enb_refcnt, _gate_flags,    \
 847                         _clk_id, _parents##_idx, 0)
 848
 849 #define TEGRA_INIT_DATA_AUDIO(_name, _con_id, _dev_id, _offset,  _clk_num,\
 850                                  _regs, _gate_flags, _clk_id)           \
 851         TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, mux_d_audio_clk, \
 852                         _offset, 16, 0xE01F, 0, 0, 8, 1, 0, _regs, _clk_num, \
 853                         periph_clk_enb_refcnt, _gate_flags , _clk_id,   \
 854                         mux_d_audio_clk_idx, 0)
 855
 856 enum tegra114_clk {
 857         rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12,
 858         ndflash = 13, sdmmc1 = 14, sdmmc4 = 15, pwm = 17, i2s2 = 18, epp = 19,
 859         gr_2d = 21, usbd = 22, isp = 23, gr_3d = 24, disp2 = 26, disp1 = 27,
 860         host1x = 28, vcp = 29, i2s0 = 30, apbdma = 34, kbc = 36, kfuse = 40,
 861         sbc1 = 41, nor = 42, sbc2 = 44, sbc3 = 46, i2c5 = 47, dsia = 48,
 862         mipi = 50, hdmi = 51, csi = 52, i2c2 = 54, uartc = 55, mipi_cal = 56,
 863         emc, usb2, usb3, vde = 61, bsea = 62, bsev = 63, uartd = 65,
 864         i2c3 = 67, sbc4 = 68, sdmmc3 = 69, owr = 71, csite = 73,
 865         la = 76, trace = 77, soc_therm = 78, dtv = 79, ndspeed = 80,
 866         i2cslow = 81, dsib = 82, tsec = 83, xusb_host = 89, msenc = 91,
 867         csus = 92, mselect = 99, tsensor = 100, i2s3 = 101, i2s4 = 102,
 868         i2c4 = 103, sbc5 = 104, sbc6 = 105, d_audio, apbif = 107, dam0, dam1,
 869         dam2, hda2codec_2x = 111, audio0_2x = 113, audio1_2x, audio2_2x,
 870         audio3_2x, audio4_2x, spdif_2x, actmon = 119, extern1 = 120,
 871         extern2 = 121, extern3 = 122, hda = 125, se = 127, hda2hdmi = 128,
 872         cilab = 144, cilcd = 145, cile = 146, dsialp = 147, dsiblp = 148,
 873         dds = 150, dp2 = 152, amx = 153, adx = 154, xusb_ss = 156, uartb = 192,
 874         vfir, spdif_in, spdif_out, vi, vi_sensor, fuse, fuse_burn, clk_32k,
 875         clk_m, clk_m_div2, clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_c2,
 876         pll_c3, pll_m, pll_m_out1, pll_p, pll_p_out1, pll_p_out2, pll_p_out3,
 877         pll_p_out4, pll_a, pll_a_out0, pll_d, pll_d_out0, pll_d2, pll_d2_out0,
 878         pll_u, pll_u_480M, pll_u_60M, pll_u_48M, pll_u_12M, pll_x, pll_x_out0,
 879         pll_re_vco, pll_re_out, pll_e_out0, spdif_in_sync, i2s0_sync,
 880         i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync, vimclk_sync, audio0,
 881         audio1, audio2, audio3, audio4, spdif, clk_out_1, clk_out_2, clk_out_3,
 882         blink, xusb_host_src = 252, xusb_falcon_src, xusb_fs_src, xusb_ss_src,
 883         xusb_dev_src, xusb_dev, xusb_hs_src, sclk, hclk, pclk, cclk_g, cclk_lp,
 884         dfll_ref = 264, dfll_soc,
 885
 886         /* Mux clocks */
 887
 888         audio0_mux = 300, audio1_mux, audio2_mux, audio3_mux, audio4_mux,
 889         spdif_mux, clk_out_1_mux, clk_out_2_mux, clk_out_3_mux, dsia_mux,
 890         dsib_mux, clk_max,
 891 };
 892
 893 struct utmi_clk_param {
 894         /* Oscillator Frequency in KHz */
 895         u32 osc_frequency;
 896         /* UTMIP PLL Enable Delay Count  */
 897         u8 enable_delay_count;
 898         /* UTMIP PLL Stable count */
 899         u8 stable_count;
 900         /*  UTMIP PLL Active delay count */
 901         u8 active_delay_count;
 902         /* UTMIP PLL Xtal frequency count */
 903         u8 xtal_freq_count;
 904 };
 905
 906 static const struct utmi_clk_param utmi_parameters[] = {
 907         {.osc_frequency = 13000000, .enable_delay_count = 0x02,
 908          .stable_count = 0x33, .active_delay_count = 0x05,
 909          .xtal_freq_count = 0x7F},
 910         {.osc_frequency = 19200000, .enable_delay_count = 0x03,
 911          .stable_count = 0x4B, .active_delay_count = 0x06,
 912          .xtal_freq_count = 0xBB},
 913         {.osc_frequency = 12000000, .enable_delay_count = 0x02,
 914          .stable_count = 0x2F, .active_delay_count = 0x04,
 915          .xtal_freq_count = 0x76},
 916         {.osc_frequency = 26000000, .enable_delay_count = 0x04,
 917          .stable_count = 0x66, .active_delay_count = 0x09,
 918          .xtal_freq_count = 0xFE},
 919         {.osc_frequency = 16800000, .enable_delay_count = 0x03,
 920          .stable_count = 0x41, .active_delay_count = 0x0A,
 921          .xtal_freq_count = 0xA4},
 922 };
 923
 924 /* peripheral mux definitions */
 925
 926 #define MUX_I2S_SPDIF(_id)                                              \
 927 static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \
 928                                                            #_id, "pll_p",\
 929                                                            "clk_m"};
 930 MUX_I2S_SPDIF(audio0)
 931 MUX_I2S_SPDIF(audio1)
 932 MUX_I2S_SPDIF(audio2)
 933 MUX_I2S_SPDIF(audio3)
 934 MUX_I2S_SPDIF(audio4)
 935 MUX_I2S_SPDIF(audio)
 936
 937 #define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL
 938 #define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL
 939 #define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL
 940 #define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL
 941 #define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL
 942 #define mux_pllaout0_audio_2x_pllp_clkm_idx NULL
 943
 944 static const char *mux_pllp_pllc_pllm_clkm[] = {
 945         "pll_p", "pll_c", "pll_m", "clk_m"
 946 };
 947 #define mux_pllp_pllc_pllm_clkm_idx NULL
 948
 949 static const char *mux_pllp_pllc_pllm[] = { "pll_p", "pll_c", "pll_m" };
 950 #define mux_pllp_pllc_pllm_idx NULL
 951
 952 static const char *mux_pllp_pllc_clk32_clkm[] = {
 953         "pll_p", "pll_c", "clk_32k", "clk_m"
 954 };
 955 #define mux_pllp_pllc_clk32_clkm_idx NULL
 956
 957 static const char *mux_plla_pllc_pllp_clkm[] = {
 958         "pll_a_out0", "pll_c", "pll_p", "clk_m"
 959 };
 960 #define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx
 961
 962 static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = {
 963         "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m"
 964 };
 965 static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = {
 966         [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
 967 };
 968
 969 static const char *mux_pllp_clkm[] = {
 970         "pll_p", "clk_m"
 971 };
 972 static u32 mux_pllp_clkm_idx[] = {
 973         [0] = 0, [1] = 3,
 974 };
 975
 976 static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
 977         "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
 978 };
 979 #define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx
 980
 981 static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
 982         "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c",
 983         "pll_d2_out0", "clk_m"
 984 };
 985 #define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL
 986
 987 static const char *mux_pllm_pllc_pllp_plla[] = {
 988         "pll_m", "pll_c", "pll_p", "pll_a_out0"
 989 };
 990 #define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx
 991
 992 static const char *mux_pllp_pllc_clkm[] = {
 993         "pll_p", "pll_c", "pll_m"
 994 };
 995 static u32 mux_pllp_pllc_clkm_idx[] = {
 996         [0] = 0, [1] = 1, [2] = 3,
 997 };
 998
 999 static const char *mux_pllp_pllc_clkm_clk32[] = {
1000         "pll_p", "pll_c", "clk_m", "clk_32k"
1001 };
1002 #define mux_pllp_pllc_clkm_clk32_idx NULL
1003
1004 static const char *mux_plla_clk32_pllp_clkm_plle[] = {
1005         "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0"
1006 };
1007 #define mux_plla_clk32_pllp_clkm_plle_idx NULL
1008
1009 static const char *mux_clkm_pllp_pllc_pllre[] = {
1010         "clk_m", "pll_p", "pll_c", "pll_re_out"
1011 };
1012 static u32 mux_clkm_pllp_pllc_pllre_idx[] = {
1013         [0] = 0, [1] = 1, [2] = 3, [3] = 5,
1014 };
1015
1016 static const char *mux_clkm_48M_pllp_480M[] = {
1017         "clk_m", "pll_u_48M", "pll_p", "pll_u_480M"
1018 };
1019 #define mux_clkm_48M_pllp_480M_idx NULL
1020
1021 static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = {
1022         "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref"
1023 };
1024 static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = {
1025         [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7,
1026 };
1027
1028 static const char *mux_plld_out0_plld2_out0[] = {
1029         "pll_d_out0", "pll_d2_out0",
1030 };
1031 #define mux_plld_out0_plld2_out0_idx NULL
1032
1033 static const char *mux_d_audio_clk[] = {
1034         "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync",
1035         "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
1036 };
1037 static u32 mux_d_audio_clk_idx[] = {
1038         [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001,
1039         [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007,
1040 };
1041
1042 static const char *mux_pllmcp_clkm[] = {
1043         "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud",
1044 };
1045
1046 static const struct clk_div_table pll_re_div_table[] = {
1047         { .val = 0, .div = 1 },
1048         { .val = 1, .div = 2 },
1049         { .val = 2, .div = 3 },
1050         { .val = 3, .div = 4 },
1051         { .val = 4, .div = 5 },
1052         { .val = 5, .div = 6 },
1053         { .val = 0, .div = 0 },
1054 };
1055
1056 static struct clk *clks[clk_max];
1057 static struct clk_onecell_data clk_data;
1058
1059 static unsigned long osc_freq;
1060 static unsigned long pll_ref_freq;
1061
1062 static int __init tegra114_osc_clk_init(void __iomem *clk_base)
1063 {
1064         struct clk *clk;
1065         u32 val, pll_ref_div;
1066
1067         val = readl_relaxed(clk_base + OSC_CTRL);
1068
1069         osc_freq = tegra114_input_freq[val >> OSC_CTRL_OSC_FREQ_SHIFT];
1070         if (!osc_freq) {
1071                 WARN_ON(1);
1072                 return -EINVAL;
1073         }
1074
1075         /* clk_m */
1076         clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
1077                                       osc_freq);
1078         clk_register_clkdev(clk, "clk_m", NULL);
1079         clks[clk_m] = clk;
1080
1081         /* pll_ref */
1082         val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
1083         pll_ref_div = 1 << val;
1084         clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
1085                                         CLK_SET_RATE_PARENT, 1, pll_ref_div);
1086         clk_register_clkdev(clk, "pll_ref", NULL);
1087         clks[pll_ref] = clk;
1088
1089         pll_ref_freq = osc_freq / pll_ref_div;
1090
1091         return 0;
1092 }
1093
1094 static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
1095 {
1096         struct clk *clk;
1097
1098         /* clk_32k */
1099         clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
1100                                       32768);
1101         clk_register_clkdev(clk, "clk_32k", NULL);
1102         clks[clk_32k] = clk;
1103
1104         /* clk_m_div2 */
1105         clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
1106                                         CLK_SET_RATE_PARENT, 1, 2);
1107         clk_register_clkdev(clk, "clk_m_div2", NULL);
1108         clks[clk_m_div2] = clk;
1109
1110         /* clk_m_div4 */
1111         clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
1112                                         CLK_SET_RATE_PARENT, 1, 4);
1113         clk_register_clkdev(clk, "clk_m_div4", NULL);
1114         clks[clk_m_div4] = clk;
1115
1116 }
1117
1118 static __init void tegra114_utmi_param_configure(void __iomem *clk_base)
1119 {
1120         u32 reg;
1121         int i;
1122
1123         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1124                 if (osc_freq == utmi_parameters[i].osc_frequency)
1125                         break;
1126         }
1127
1128         if (i >= ARRAY_SIZE(utmi_parameters)) {
1129                 pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
1130                        osc_freq);
1131                 return;
1132         }
1133
1134         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
1135
1136         /* Program UTMIP PLL stable and active counts */
1137         /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
1138         reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1139         reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
1140
1141         reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1142
1143         reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].
1144                                             active_delay_count);
1145
1146         /* Remove power downs from UTMIP PLL control bits */
1147         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1148         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1149         reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1150
1151         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
1152
1153         /* Program UTMIP PLL delay and oscillator frequency counts */
1154         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1155         reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1156
1157         reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].
1158                                             enable_delay_count);
1159
1160         reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1161         reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].
1162                                            xtal_freq_count);
1163
1164         /* Remove power downs from UTMIP PLL control bits */
1165         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1166         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1167         reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1168         reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1169         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1170
1171         /* Setup HW control of UTMIPLL */
1172         reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1173         reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1174         reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1175         reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1176         writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1177
1178         reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1179         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1180         reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1181         writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1182
1183         udelay(1);
1184
1185         /* Setup SW override of UTMIPLL assuming USB2.0
1186            ports are assigned to USB2 */
1187         reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1188         reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1189         reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1190         writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1191
1192         udelay(1);
1193
1194         /* Enable HW control UTMIPLL */
1195         reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1196         reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1197         writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1198 }
1199
1200 static void __init _clip_vco_min(struct tegra_clk_pll_params *pll_params)
1201 {
1202         pll_params->vco_min =
1203                 DIV_ROUND_UP(pll_params->vco_min, pll_ref_freq) * pll_ref_freq;
1204 }
1205
1206 static int __init _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
1207                                       void __iomem *clk_base)
1208 {
1209         u32 val;
1210         u32 step_a, step_b;
1211
1212         switch (pll_ref_freq) {
1213         case 12000000:
1214         case 13000000:
1215         case 26000000:
1216                 step_a = 0x2B;
1217                 step_b = 0x0B;
1218                 break;
1219         case 16800000:
1220                 step_a = 0x1A;
1221                 step_b = 0x09;
1222                 break;
1223         case 19200000:
1224                 step_a = 0x12;
1225                 step_b = 0x08;
1226                 break;
1227         default:
1228                 pr_err("%s: Unexpected reference rate %lu\n",
1229                         __func__, pll_ref_freq);
1230                 WARN_ON(1);
1231                 return -EINVAL;
1232         }
1233
1234         val = step_a << pll_params->stepa_shift;
1235         val |= step_b << pll_params->stepb_shift;
1236         writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
1237
1238         return 0;
1239 }
1240
1241 static void __init _init_iddq(struct tegra_clk_pll_params *pll_params,
1242                               void __iomem *clk_base)
1243 {
1244         u32 val, val_iddq;
1245
1246         val = readl_relaxed(clk_base + pll_params->base_reg);
1247         val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
1248
1249         if (val & BIT(30))
1250                 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
1251         else {
1252                 val_iddq |= BIT(pll_params->iddq_bit_idx);
1253                 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
1254         }
1255 }
1256
1257 static void __init tegra114_pll_init(void __iomem *clk_base,
1258                                      void __iomem *pmc)
1259 {
1260         u32 val;
1261         struct clk *clk;
1262
1263         /* PLLC */
1264         _clip_vco_min(&pll_c_params);
1265         if (_setup_dynamic_ramp(&pll_c_params, clk_base) >= 0) {
1266                 _init_iddq(&pll_c_params, clk_base);
1267                 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
1268                                 pmc, 0, 0, &pll_c_params, TEGRA_PLL_USE_LOCK,
1269                                 pll_c_freq_table, NULL);
1270                 clk_register_clkdev(clk, "pll_c", NULL);
1271                 clks[pll_c] = clk;
1272
1273                 /* PLLC_OUT1 */
1274                 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
1275                                 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1276                                 8, 8, 1, NULL);
1277                 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
1278                                         clk_base + PLLC_OUT, 1, 0,
1279                                         CLK_SET_RATE_PARENT, 0, NULL);
1280                 clk_register_clkdev(clk, "pll_c_out1", NULL);
1281                 clks[pll_c_out1] = clk;
1282         }
1283
1284         /* PLLC2 */
1285         _clip_vco_min(&pll_c2_params);
1286         clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, 0,
1287                              &pll_c2_params, TEGRA_PLL_USE_LOCK,
1288                              pll_cx_freq_table, NULL);
1289         clk_register_clkdev(clk, "pll_c2", NULL);
1290         clks[pll_c2] = clk;
1291
1292         /* PLLC3 */
1293         _clip_vco_min(&pll_c3_params);
1294         clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, 0,
1295                              &pll_c3_params, TEGRA_PLL_USE_LOCK,
1296                              pll_cx_freq_table, NULL);
1297         clk_register_clkdev(clk, "pll_c3", NULL);
1298         clks[pll_c3] = clk;
1299
1300         /* PLLP */
1301         clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc, 0,
1302                             408000000, &pll_p_params,
1303                             TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK,
1304                             pll_p_freq_table, NULL);
1305         clk_register_clkdev(clk, "pll_p", NULL);
1306         clks[pll_p] = clk;
1307
1308         /* PLLP_OUT1 */
1309         clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p",
1310                                 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
1311                                 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock);
1312         clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div",
1313                                 clk_base + PLLP_OUTA, 1, 0,
1314                                 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1315                                 &pll_div_lock);
1316         clk_register_clkdev(clk, "pll_p_out1", NULL);
1317         clks[pll_p_out1] = clk;
1318
1319         /* PLLP_OUT2 */
1320         clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
1321                                 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
1322                                 TEGRA_DIVIDER_ROUND_UP | TEGRA_DIVIDER_INT, 24,
1323                                 8, 1, &pll_div_lock);
1324         clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
1325                                 clk_base + PLLP_OUTA, 17, 16,
1326                                 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1327                                 &pll_div_lock);
1328         clk_register_clkdev(clk, "pll_p_out2", NULL);
1329         clks[pll_p_out2] = clk;
1330
1331         /* PLLP_OUT3 */
1332         clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p",
1333                                 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
1334                                 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock);
1335         clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div",
1336                                 clk_base + PLLP_OUTB, 1, 0,
1337                                 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1338                                 &pll_div_lock);
1339         clk_register_clkdev(clk, "pll_p_out3", NULL);
1340         clks[pll_p_out3] = clk;
1341
1342         /* PLLP_OUT4 */
1343         clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p",
1344                                 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
1345                                 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
1346                                 &pll_div_lock);
1347         clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div",
1348                                 clk_base + PLLP_OUTB, 17, 16,
1349                                 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1350                                 &pll_div_lock);
1351         clk_register_clkdev(clk, "pll_p_out4", NULL);
1352         clks[pll_p_out4] = clk;
1353
1354         /* PLLM */
1355         _clip_vco_min(&pll_m_params);
1356         clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
1357                              CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0,
1358                              &pll_m_params, TEGRA_PLL_USE_LOCK,
1359                              pll_m_freq_table, NULL);
1360         clk_register_clkdev(clk, "pll_m", NULL);
1361         clks[pll_m] = clk;
1362
1363         /* PLLM_OUT1 */
1364         clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
1365                                 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1366                                 8, 8, 1, NULL);
1367         clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
1368                                 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
1369                                 CLK_SET_RATE_PARENT, 0, NULL);
1370         clk_register_clkdev(clk, "pll_m_out1", NULL);
1371         clks[pll_m_out1] = clk;
1372
1373         /* PLLM_UD */
1374         clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
1375                                         CLK_SET_RATE_PARENT, 1, 1);
1376
1377         /* PLLX */
1378         _clip_vco_min(&pll_x_params);
1379         if (_setup_dynamic_ramp(&pll_x_params, clk_base) >= 0) {
1380                 _init_iddq(&pll_x_params, clk_base);
1381                 clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base,
1382                                 pmc, CLK_IGNORE_UNUSED, 0, &pll_x_params,
1383                                 TEGRA_PLL_USE_LOCK, pll_x_freq_table, NULL);
1384                 clk_register_clkdev(clk, "pll_x", NULL);
1385                 clks[pll_x] = clk;
1386         }
1387
1388         /* PLLX_OUT0 */
1389         clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
1390                                         CLK_SET_RATE_PARENT, 1, 2);
1391         clk_register_clkdev(clk, "pll_x_out0", NULL);
1392         clks[pll_x_out0] = clk;
1393
1394         /* PLLU */
1395         val = readl(clk_base + pll_u_params.base_reg);
1396         val &= ~BIT(24); /* disable PLLU_OVERRIDE */
1397         writel(val, clk_base + pll_u_params.base_reg);
1398
1399         clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0,
1400                             0, &pll_u_params, TEGRA_PLLU |
1401                             TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
1402                             TEGRA_PLL_USE_LOCK, pll_u_freq_table, &pll_u_lock);
1403         clk_register_clkdev(clk, "pll_u", NULL);
1404         clks[pll_u] = clk;
1405
1406         tegra114_utmi_param_configure(clk_base);
1407
1408         /* PLLU_480M */
1409         clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
1410                                 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
1411                                 22, 0, &pll_u_lock);
1412         clk_register_clkdev(clk, "pll_u_480M", NULL);
1413         clks[pll_u_480M] = clk;
1414
1415         /* PLLU_60M */
1416         clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
1417                                         CLK_SET_RATE_PARENT, 1, 8);
1418         clk_register_clkdev(clk, "pll_u_60M", NULL);
1419         clks[pll_u_60M] = clk;
1420
1421         /* PLLU_48M */
1422         clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
1423                                         CLK_SET_RATE_PARENT, 1, 10);
1424         clk_register_clkdev(clk, "pll_u_48M", NULL);
1425         clks[pll_u_48M] = clk;
1426
1427         /* PLLU_12M */
1428         clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
1429                                         CLK_SET_RATE_PARENT, 1, 40);
1430         clk_register_clkdev(clk, "pll_u_12M", NULL);
1431         clks[pll_u_12M] = clk;
1432
1433         /* PLLD */
1434         clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
1435                             0, &pll_d_params,
1436                             TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
1437                             TEGRA_PLL_USE_LOCK, pll_d_freq_table, &pll_d_lock);
1438         clk_register_clkdev(clk, "pll_d", NULL);
1439         clks[pll_d] = clk;
1440
1441         /* PLLD_OUT0 */
1442         clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
1443                                         CLK_SET_RATE_PARENT, 1, 2);
1444         clk_register_clkdev(clk, "pll_d_out0", NULL);
1445         clks[pll_d_out0] = clk;
1446
1447         /* PLLD2 */
1448         clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0,
1449                             0, &pll_d2_params,
1450                             TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
1451                             TEGRA_PLL_USE_LOCK, pll_d_freq_table, &pll_d2_lock);
1452         clk_register_clkdev(clk, "pll_d2", NULL);
1453         clks[pll_d2] = clk;
1454
1455         /* PLLD2_OUT0 */
1456         clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
1457                                         CLK_SET_RATE_PARENT, 1, 2);
1458         clk_register_clkdev(clk, "pll_d2_out0", NULL);
1459         clks[pll_d2_out0] = clk;
1460
1461         /* PLLA */
1462         clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc, 0,
1463                             0, &pll_a_params, TEGRA_PLL_HAS_CPCON |
1464                             TEGRA_PLL_USE_LOCK, pll_a_freq_table, NULL);
1465         clk_register_clkdev(clk, "pll_a", NULL);
1466         clks[pll_a] = clk;
1467
1468         /* PLLA_OUT0 */
1469         clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
1470                                 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1471                                 8, 8, 1, NULL);
1472         clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
1473                                 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
1474                                 CLK_SET_RATE_PARENT, 0, NULL);
1475         clk_register_clkdev(clk, "pll_a_out0", NULL);
1476         clks[pll_a_out0] = clk;
1477
1478         /* PLLRE */
1479         _clip_vco_min(&pll_re_vco_params);
1480         clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
1481                              0, 0, &pll_re_vco_params, TEGRA_PLL_USE_LOCK,
1482                              NULL, &pll_re_lock, pll_ref_freq);
1483         clk_register_clkdev(clk, "pll_re_vco", NULL);
1484         clks[pll_re_vco] = clk;
1485
1486         clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
1487                                          clk_base + PLLRE_BASE, 16, 4, 0,
1488                                          pll_re_div_table, &pll_re_lock);
1489         clk_register_clkdev(clk, "pll_re_out", NULL);
1490         clks[pll_re_out] = clk;
1491
1492         /* PLLE */
1493         clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_re_vco",
1494                                       clk_base, 0, 100000000, &pll_e_params,
1495                                       pll_e_freq_table, NULL);
1496         clk_register_clkdev(clk, "pll_e_out0", NULL);
1497         clks[pll_e_out0] = clk;
1498 }
1499
1500 static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync",
1501         "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
1502 };
1503
1504 static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
1505         "clk_m_div4", "extern1",
1506 };
1507
1508 static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
1509         "clk_m_div4", "extern2",
1510 };
1511
1512 static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
1513         "clk_m_div4", "extern3",
1514 };
1515
1516 static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1517 {
1518         struct clk *clk;
1519
1520         /* spdif_in_sync */
1521         clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000,
1522                                              24000000);
1523         clk_register_clkdev(clk, "spdif_in_sync", NULL);
1524         clks[spdif_in_sync] = clk;
1525
1526         /* i2s0_sync */
1527         clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000);
1528         clk_register_clkdev(clk, "i2s0_sync", NULL);
1529         clks[i2s0_sync] = clk;
1530
1531         /* i2s1_sync */
1532         clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000);
1533         clk_register_clkdev(clk, "i2s1_sync", NULL);
1534         clks[i2s1_sync] = clk;
1535
1536         /* i2s2_sync */
1537         clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000);
1538         clk_register_clkdev(clk, "i2s2_sync", NULL);
1539         clks[i2s2_sync] = clk;
1540
1541         /* i2s3_sync */
1542         clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000);
1543         clk_register_clkdev(clk, "i2s3_sync", NULL);
1544         clks[i2s3_sync] = clk;
1545
1546         /* i2s4_sync */
1547         clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000);
1548         clk_register_clkdev(clk, "i2s4_sync", NULL);
1549         clks[i2s4_sync] = clk;
1550
1551         /* vimclk_sync */
1552         clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000);
1553         clk_register_clkdev(clk, "vimclk_sync", NULL);
1554         clks[vimclk_sync] = clk;
1555
1556         /* audio0 */
1557         clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
1558                                ARRAY_SIZE(mux_audio_sync_clk), 0,
1559                                clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0,
1560                                NULL);
1561         clks[audio0_mux] = clk;
1562         clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0,
1563                                 clk_base + AUDIO_SYNC_CLK_I2S0, 4,
1564                                 CLK_GATE_SET_TO_DISABLE, NULL);
1565         clk_register_clkdev(clk, "audio0", NULL);
1566         clks[audio0] = clk;
1567
1568         /* audio1 */
1569         clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
1570                                ARRAY_SIZE(mux_audio_sync_clk), 0,
1571                                clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0,
1572                                NULL);
1573         clks[audio1_mux] = clk;
1574         clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0,
1575                                 clk_base + AUDIO_SYNC_CLK_I2S1, 4,
1576                                 CLK_GATE_SET_TO_DISABLE, NULL);
1577         clk_register_clkdev(clk, "audio1", NULL);
1578         clks[audio1] = clk;
1579
1580         /* audio2 */
1581         clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
1582                                ARRAY_SIZE(mux_audio_sync_clk), 0,
1583                                clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0,
1584                                NULL);
1585         clks[audio2_mux] = clk;
1586         clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0,
1587                                 clk_base + AUDIO_SYNC_CLK_I2S2, 4,
1588                                 CLK_GATE_SET_TO_DISABLE, NULL);
1589         clk_register_clkdev(clk, "audio2", NULL);
1590         clks[audio2] = clk;
1591
1592         /* audio3 */
1593         clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
1594                                ARRAY_SIZE(mux_audio_sync_clk), 0,
1595                                clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0,
1596                                NULL);
1597         clks[audio3_mux] = clk;
1598         clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0,
1599                                 clk_base + AUDIO_SYNC_CLK_I2S3, 4,
1600                                 CLK_GATE_SET_TO_DISABLE, NULL);
1601         clk_register_clkdev(clk, "audio3", NULL);
1602         clks[audio3] = clk;
1603
1604         /* audio4 */
1605         clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
1606                                ARRAY_SIZE(mux_audio_sync_clk), 0,
1607                                clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0,
1608                                NULL);
1609         clks[audio4_mux] = clk;
1610         clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0,
1611                                 clk_base + AUDIO_SYNC_CLK_I2S4, 4,
1612                                 CLK_GATE_SET_TO_DISABLE, NULL);
1613         clk_register_clkdev(clk, "audio4", NULL);
1614         clks[audio4] = clk;
1615
1616         /* spdif */
1617         clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
1618                                ARRAY_SIZE(mux_audio_sync_clk), 0,
1619                                clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0,
1620                                NULL);
1621         clks[spdif_mux] = clk;
1622         clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0,
1623                                 clk_base + AUDIO_SYNC_CLK_SPDIF, 4,
1624                                 CLK_GATE_SET_TO_DISABLE, NULL);
1625         clk_register_clkdev(clk, "spdif", NULL);
1626         clks[spdif] = clk;
1627
1628         /* audio0_2x */
1629         clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0",
1630                                         CLK_SET_RATE_PARENT, 2, 1);
1631         clk = tegra_clk_register_divider("audio0_div", "audio0_doubler",
1632                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1,
1633                                 0, &clk_doubler_lock);
1634         clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div",
1635                                   TEGRA_PERIPH_NO_RESET, clk_base,
1636                                   CLK_SET_RATE_PARENT, 113, &periph_v_regs,
1637                                   periph_clk_enb_refcnt);
1638         clk_register_clkdev(clk, "audio0_2x", NULL);
1639         clks[audio0_2x] = clk;
1640
1641         /* audio1_2x */
1642         clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1",
1643                                         CLK_SET_RATE_PARENT, 2, 1);
1644         clk = tegra_clk_register_divider("audio1_div", "audio1_doubler",
1645                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1,
1646                                 0, &clk_doubler_lock);
1647         clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div",
1648                                   TEGRA_PERIPH_NO_RESET, clk_base,
1649                                   CLK_SET_RATE_PARENT, 114, &periph_v_regs,
1650                                   periph_clk_enb_refcnt);
1651         clk_register_clkdev(clk, "audio1_2x", NULL);
1652         clks[audio1_2x] = clk;
1653
1654         /* audio2_2x */
1655         clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2",
1656                                         CLK_SET_RATE_PARENT, 2, 1);
1657         clk = tegra_clk_register_divider("audio2_div", "audio2_doubler",
1658                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1,
1659                                 0, &clk_doubler_lock);
1660         clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div",
1661                                   TEGRA_PERIPH_NO_RESET, clk_base,
1662                                   CLK_SET_RATE_PARENT, 115, &periph_v_regs,
1663                                   periph_clk_enb_refcnt);
1664         clk_register_clkdev(clk, "audio2_2x", NULL);
1665         clks[audio2_2x] = clk;
1666
1667         /* audio3_2x */
1668         clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3",
1669                                         CLK_SET_RATE_PARENT, 2, 1);
1670         clk = tegra_clk_register_divider("audio3_div", "audio3_doubler",
1671                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1,
1672                                 0, &clk_doubler_lock);
1673         clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div",
1674                                   TEGRA_PERIPH_NO_RESET, clk_base,
1675                                   CLK_SET_RATE_PARENT, 116, &periph_v_regs,
1676                                   periph_clk_enb_refcnt);
1677         clk_register_clkdev(clk, "audio3_2x", NULL);
1678         clks[audio3_2x] = clk;
1679
1680         /* audio4_2x */
1681         clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4",
1682                                         CLK_SET_RATE_PARENT, 2, 1);
1683         clk = tegra_clk_register_divider("audio4_div", "audio4_doubler",
1684                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1,
1685                                 0, &clk_doubler_lock);
1686         clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div",
1687                                   TEGRA_PERIPH_NO_RESET, clk_base,
1688                                   CLK_SET_RATE_PARENT, 117, &periph_v_regs,
1689                                   periph_clk_enb_refcnt);
1690         clk_register_clkdev(clk, "audio4_2x", NULL);
1691         clks[audio4_2x] = clk;
1692
1693         /* spdif_2x */
1694         clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif",
1695                                         CLK_SET_RATE_PARENT, 2, 1);
1696         clk = tegra_clk_register_divider("spdif_div", "spdif_doubler",
1697                                 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1,
1698                                 0, &clk_doubler_lock);
1699         clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div",
1700                                   TEGRA_PERIPH_NO_RESET, clk_base,
1701                                   CLK_SET_RATE_PARENT, 118,
1702                                   &periph_v_regs, periph_clk_enb_refcnt);
1703         clk_register_clkdev(clk, "spdif_2x", NULL);
1704         clks[spdif_2x] = clk;
1705 }
1706
1707 static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
1708 {
1709         struct clk *clk;
1710
1711         /* clk_out_1 */
1712         clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
1713                                ARRAY_SIZE(clk_out1_parents), 0,
1714                                pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
1715                                &clk_out_lock);
1716         clks[clk_out_1_mux] = clk;
1717         clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0,
1718                                 pmc_base + PMC_CLK_OUT_CNTRL, 2, 0,
1719                                 &clk_out_lock);
1720         clk_register_clkdev(clk, "extern1", "clk_out_1");
1721         clks[clk_out_1] = clk;
1722
1723         /* clk_out_2 */
1724         clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
1725                                ARRAY_SIZE(clk_out2_parents), 0,
1726                                pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
1727                                &clk_out_lock);
1728         clks[clk_out_2_mux] = clk;
1729         clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,
1730                                 pmc_base + PMC_CLK_OUT_CNTRL, 10, 0,
1731                                 &clk_out_lock);
1732         clk_register_clkdev(clk, "extern2", "clk_out_2");
1733         clks[clk_out_2] = clk;
1734
1735         /* clk_out_3 */
1736         clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
1737                                ARRAY_SIZE(clk_out3_parents), 0,
1738                                pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
1739                                &clk_out_lock);
1740         clks[clk_out_3_mux] = clk;
1741         clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,
1742                                 pmc_base + PMC_CLK_OUT_CNTRL, 18, 0,
1743                                 &clk_out_lock);
1744         clk_register_clkdev(clk, "extern3", "clk_out_3");
1745         clks[clk_out_3] = clk;
1746
1747         /* blink */
1748         /* clear the blink timer register to directly output clk_32k */
1749         writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
1750         clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
1751                                 pmc_base + PMC_DPD_PADS_ORIDE,
1752                                 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
1753         clk = clk_register_gate(NULL, "blink", "blink_override", 0,
1754                                 pmc_base + PMC_CTRL,
1755                                 PMC_CTRL_BLINK_ENB, 0, NULL);
1756         clk_register_clkdev(clk, "blink", NULL);
1757         clks[blink] = clk;
1758
1759 }
1760
1761 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
1762                                "pll_p", "pll_p_out2", "unused",
1763                                "clk_32k", "pll_m_out1" };
1764
1765 static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1766                                         "pll_p", "pll_p_out4", "unused",
1767                                         "unused", "pll_x" };
1768
1769 static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1770                                          "pll_p", "pll_p_out4", "unused",
1771                                          "unused", "pll_x", "pll_x_out0" };
1772
1773 static void __init tegra114_super_clk_init(void __iomem *clk_base)
1774 {
1775         struct clk *clk;
1776
1777         /* CCLKG */
1778         clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents,
1779                                         ARRAY_SIZE(cclk_g_parents),
1780                                         CLK_SET_RATE_PARENT,
1781                                         clk_base + CCLKG_BURST_POLICY,
1782                                         0, 4, 0, 0, NULL);
1783         clk_register_clkdev(clk, "cclk_g", NULL);
1784         clks[cclk_g] = clk;
1785
1786         /* CCLKLP */
1787         clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
1788                                         ARRAY_SIZE(cclk_lp_parents),
1789                                         CLK_SET_RATE_PARENT,
1790                                         clk_base + CCLKLP_BURST_POLICY,
1791                                         0, 4, 8, 9, NULL);
1792         clk_register_clkdev(clk, "cclk_lp", NULL);
1793         clks[cclk_lp] = clk;
1794
1795         /* SCLK */
1796         clk = tegra_clk_register_super_mux("sclk", sclk_parents,
1797                                         ARRAY_SIZE(sclk_parents),
1798                                         CLK_SET_RATE_PARENT,
1799                                         clk_base + SCLK_BURST_POLICY,
1800                                         0, 4, 0, 0, NULL);
1801         clk_register_clkdev(clk, "sclk", NULL);
1802         clks[sclk] = clk;
1803
1804         /* HCLK */
1805         clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
1806                                    clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
1807                                    &sysrate_lock);
1808         clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT |
1809                                 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE,
1810                                 7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
1811         clk_register_clkdev(clk, "hclk", NULL);
1812         clks[hclk] = clk;
1813
1814         /* PCLK */
1815         clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
1816                                    clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
1817                                    &sysrate_lock);
1818         clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT |
1819                                 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE,
1820                                 3, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
1821         clk_register_clkdev(clk, "pclk", NULL);
1822         clks[pclk] = clk;
1823 }
1824
1825 static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1826         TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s0),
1827         TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1),
1828         TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2),
1829         TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s3),
1830         TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s4),
1831         TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out),
1832         TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in),
1833         TEGRA_INIT_DATA_MUX("pwm", NULL, "pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, &periph_l_regs, TEGRA_PERIPH_ON_APB, pwm),
1834         TEGRA_INIT_DATA_MUX("adx", NULL, "adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, &periph_w_regs, TEGRA_PERIPH_ON_APB, adx),
1835         TEGRA_INIT_DATA_MUX("amx", NULL, "amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, &periph_w_regs, TEGRA_PERIPH_ON_APB, amx),
1836         TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, &periph_v_regs, TEGRA_PERIPH_ON_APB, hda),
1837         TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, &periph_v_regs, TEGRA_PERIPH_ON_APB, hda2codec_2x),
1838         TEGRA_INIT_DATA_MUX("sbc1", NULL, "tegra11-spi.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
1839         TEGRA_INIT_DATA_MUX("sbc2", NULL, "tegra11-spi.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2),
1840         TEGRA_INIT_DATA_MUX("sbc3", NULL, "tegra11-spi.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3),
1841         TEGRA_INIT_DATA_MUX("sbc4", NULL, "tegra11-spi.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4),
1842         TEGRA_INIT_DATA_MUX("sbc5", NULL, "tegra11-spi.4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5),
1843         TEGRA_INIT_DATA_MUX("sbc6", NULL, "tegra11-spi.5", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6),
1844         TEGRA_INIT_DATA_MUX8("ndflash", NULL, "tegra_nand", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed),
1845         TEGRA_INIT_DATA_MUX8("ndspeed", NULL, "tegra_nand_speed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed),
1846         TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir),
1847         TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1),
1848         TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2),
1849         TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3),
1850         TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4),
1851         TEGRA_INIT_DATA_INT("vde", NULL, "vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde),
1852         TEGRA_INIT_DATA_MUX_FLAGS("csite", NULL, "csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, TEGRA_PERIPH_ON_APB, csite, CLK_IGNORE_UNUSED),
1853         TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, TEGRA_PERIPH_ON_APB, la),
1854         TEGRA_INIT_DATA_MUX("trace", NULL, "trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, &periph_u_regs, TEGRA_PERIPH_ON_APB, trace),
1855         TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr),
1856         TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor),
1857         TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi),
1858         TEGRA_INIT_DATA_I2C("i2c1", "div-clk", "tegra11-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, i2c1),
1859         TEGRA_INIT_DATA_I2C("i2c2", "div-clk", "tegra11-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, i2c2),
1860         TEGRA_INIT_DATA_I2C("i2c3", "div-clk", "tegra11-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, i2c3),
1861         TEGRA_INIT_DATA_I2C("i2c4", "div-clk", "tegra11-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, &periph_v_regs, i2c4),
1862         TEGRA_INIT_DATA_I2C("i2c5", "div-clk", "tegra11-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, &periph_h_regs, i2c5),
1863         TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, &periph_l_regs, uarta),
1864         TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, uartb),
1865         TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, uartc),
1866         TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, uartd),
1867         TEGRA_INIT_DATA_INT("3d", NULL, "3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, &periph_l_regs, 0, gr_3d),
1868         TEGRA_INIT_DATA_INT("2d", NULL, "2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr_2d),
1869         TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor),
1870         TEGRA_INIT_DATA_INT8("vi", "vi", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi),
1871         TEGRA_INIT_DATA_INT8("epp", NULL, "epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp),
1872         TEGRA_INIT_DATA_INT8("msenc", NULL, "msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, &periph_u_regs, TEGRA_PERIPH_WAR_1005168, msenc),
1873         TEGRA_INIT_DATA_INT8("tsec", NULL, "tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, &periph_u_regs, 0, tsec),
1874         TEGRA_INIT_DATA_INT8("host1x", NULL, "host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x),
1875         TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi),
1876         TEGRA_INIT_DATA_MUX("cilab", "cilab", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, &periph_w_regs, 0, cilab),
1877         TEGRA_INIT_DATA_MUX("cilcd", "cilcd", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, &periph_w_regs, 0, cilcd),
1878         TEGRA_INIT_DATA_MUX("cile", "cile", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, &periph_w_regs, 0, cile),
1879         TEGRA_INIT_DATA_MUX("dsialp", "dsialp", "tegradc.0", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, &periph_w_regs, 0, dsialp),
1880         TEGRA_INIT_DATA_MUX("dsiblp", "dsiblp", "tegradc.1", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, &periph_w_regs, 0, dsiblp),
1881         TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, &periph_v_regs, TEGRA_PERIPH_ON_APB, tsensor),
1882         TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, &periph_v_regs, 0, actmon),
1883         TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, &periph_v_regs, 0, extern1),
1884         TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, &periph_v_regs, 0, extern2),
1885         TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, &periph_v_regs, 0, extern3),
1886         TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2cslow),
1887         TEGRA_INIT_DATA_INT8("se", NULL, "se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, &periph_v_regs, TEGRA_PERIPH_ON_APB, se),
1888         TEGRA_INIT_DATA_INT_FLAGS("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, &periph_v_regs, 0, mselect, CLK_IGNORE_UNUSED),
1889         TEGRA_INIT_DATA_MUX("dfll_ref", "ref", "t114_dfll", mux_pllp_clkm, CLK_SOURCE_DFLL_REF, 155, &periph_w_regs, TEGRA_PERIPH_ON_APB, dfll_ref),
1890         TEGRA_INIT_DATA_MUX("dfll_soc", "soc", "t114_dfll", mux_pllp_clkm, CLK_SOURCE_DFLL_SOC, 155, &periph_w_regs, TEGRA_PERIPH_ON_APB, dfll_soc),
1891         TEGRA_INIT_DATA_MUX8("soc_therm", NULL, "soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, &periph_u_regs, TEGRA_PERIPH_ON_APB, soc_therm),
1892         TEGRA_INIT_DATA_XUSB("xusb_host_src", "host_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, &periph_w_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, xusb_host_src),
1893         TEGRA_INIT_DATA_XUSB("xusb_falcon_src", "falcon_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_falcon_src),
1894         TEGRA_INIT_DATA_XUSB("xusb_fs_src", "fs_src", "tegra_xhci", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_fs_src),
1895         TEGRA_INIT_DATA_XUSB("xusb_ss_src", "ss_src", "tegra_xhci", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_ss_src),
1896         TEGRA_INIT_DATA_XUSB("xusb_dev_src", "dev_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, &periph_u_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, xusb_dev_src),
1897         TEGRA_INIT_DATA_AUDIO("d_audio", "d_audio", "tegra30-ahub", CLK_SOURCE_D_AUDIO, 106, &periph_v_regs, TEGRA_PERIPH_ON_APB, d_audio),
1898         TEGRA_INIT_DATA_AUDIO("dam0", NULL, "tegra30-dam.0", CLK_SOURCE_DAM0, 108, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam0),
1899         TEGRA_INIT_DATA_AUDIO("dam1", NULL, "tegra30-dam.1", CLK_SOURCE_DAM1, 109, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam1),
1900         TEGRA_INIT_DATA_AUDIO("dam2", NULL, "tegra30-dam.2", CLK_SOURCE_DAM2, 110, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam2),
1901 };
1902
1903 static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
1904         TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, &periph_l_regs, 0, disp1),
1905         TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, &periph_l_regs, 0, disp2),
1906 };
1907
1908 static __init void tegra114_periph_clk_init(void __iomem *clk_base)
1909 {
1910         struct tegra_periph_init_data *data;
1911         struct clk *clk;
1912         int i;
1913         u32 val;
1914
1915         /* apbdma */
1916         clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base,
1917                                   0, 34, &periph_h_regs,
1918                                   periph_clk_enb_refcnt);
1919         clks[apbdma] = clk;
1920
1921         /* rtc */
1922         clk = tegra_clk_register_periph_gate("rtc", "clk_32k",
1923                                     TEGRA_PERIPH_ON_APB |
1924                                     TEGRA_PERIPH_NO_RESET, clk_base,
1925                                     0, 4, &periph_l_regs,
1926                                     periph_clk_enb_refcnt);
1927         clk_register_clkdev(clk, NULL, "rtc-tegra");
1928         clks[rtc] = clk;
1929
1930         /* kbc */
1931         clk = tegra_clk_register_periph_gate("kbc", "clk_32k",
1932                                     TEGRA_PERIPH_ON_APB |
1933                                     TEGRA_PERIPH_NO_RESET, clk_base,
1934                                     0, 36, &periph_h_regs,
1935                                     periph_clk_enb_refcnt);
1936         clks[kbc] = clk;
1937
1938         /* timer */
1939         clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base,
1940                                   0, 5, &periph_l_regs,
1941                                   periph_clk_enb_refcnt);
1942         clk_register_clkdev(clk, NULL, "timer");
1943         clks[timer] = clk;
1944
1945         /* kfuse */
1946         clk = tegra_clk_register_periph_gate("kfuse", "clk_m",
1947                                   TEGRA_PERIPH_ON_APB, clk_base,  0, 40,
1948                                   &periph_h_regs, periph_clk_enb_refcnt);
1949         clks[kfuse] = clk;
1950
1951         /* fuse */
1952         clk = tegra_clk_register_periph_gate("fuse", "clk_m",
1953                                   TEGRA_PERIPH_ON_APB, clk_base,  0, 39,
1954                                   &periph_h_regs, periph_clk_enb_refcnt);
1955         clks[fuse] = clk;
1956
1957         /* fuse_burn */
1958         clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m",
1959                                   TEGRA_PERIPH_ON_APB, clk_base,  0, 39,
1960                                   &periph_h_regs, periph_clk_enb_refcnt);
1961         clks[fuse_burn] = clk;
1962
1963         /* apbif */
1964         clk = tegra_clk_register_periph_gate("apbif", "clk_m",
1965                                   TEGRA_PERIPH_ON_APB, clk_base,  0, 107,
1966                                   &periph_v_regs, periph_clk_enb_refcnt);
1967         clks[apbif] = clk;
1968
1969         /* hda2hdmi */
1970         clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m",
1971                                     TEGRA_PERIPH_ON_APB, clk_base,  0, 128,
1972                                     &periph_w_regs, periph_clk_enb_refcnt);
1973         clks[hda2hdmi] = clk;
1974
1975         /* vcp */
1976         clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base,  0,
1977                                   29, &periph_l_regs,
1978                                   periph_clk_enb_refcnt);
1979         clks[vcp] = clk;
1980
1981         /* bsea */
1982         clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base,
1983                                   0, 62, &periph_h_regs,
1984                                   periph_clk_enb_refcnt);
1985         clks[bsea] = clk;
1986
1987         /* bsev */
1988         clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base,
1989                                   0, 63, &periph_h_regs,
1990                                   periph_clk_enb_refcnt);
1991         clks[bsev] = clk;
1992
1993         /* mipi-cal */
1994         clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base,
1995                                    0, 56, &periph_h_regs,
1996                                   periph_clk_enb_refcnt);
1997         clks[mipi_cal] = clk;
1998
1999         /* usbd */
2000         clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base,
2001                                   0, 22, &periph_l_regs,
2002                                   periph_clk_enb_refcnt);
2003         clks[usbd] = clk;
2004
2005         /* usb2 */
2006         clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base,
2007                                   0, 58, &periph_h_regs,
2008                                   periph_clk_enb_refcnt);
2009         clks[usb2] = clk;
2010
2011         /* usb3 */
2012         clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base,
2013                                   0, 59, &periph_h_regs,
2014                                   periph_clk_enb_refcnt);
2015         clks[usb3] = clk;
2016
2017         /* csi */
2018         clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base,
2019                                    0, 52, &periph_h_regs,
2020                                   periph_clk_enb_refcnt);
2021         clks[csi] = clk;
2022
2023         /* isp */
2024         clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0,
2025                                   23, &periph_l_regs,
2026                                   periph_clk_enb_refcnt);
2027         clks[isp] = clk;
2028
2029         /* csus */
2030         clk = tegra_clk_register_periph_gate("csus", "clk_m",
2031                                   TEGRA_PERIPH_NO_RESET, clk_base, 0, 92,
2032                                   &periph_u_regs, periph_clk_enb_refcnt);
2033         clks[csus] = clk;
2034
2035         /* dds */
2036         clk = tegra_clk_register_periph_gate("dds", "clk_m",
2037                                   TEGRA_PERIPH_ON_APB, clk_base, 0, 150,
2038                                   &periph_w_regs, periph_clk_enb_refcnt);
2039         clks[dds] = clk;
2040
2041         /* dp2 */
2042         clk = tegra_clk_register_periph_gate("dp2", "clk_m",
2043                                   TEGRA_PERIPH_ON_APB, clk_base, 0, 152,
2044                                   &periph_w_regs, periph_clk_enb_refcnt);
2045         clks[dp2] = clk;
2046
2047         /* dtv */
2048         clk = tegra_clk_register_periph_gate("dtv", "clk_m",
2049                                     TEGRA_PERIPH_ON_APB, clk_base, 0, 79,
2050                                     &periph_u_regs, periph_clk_enb_refcnt);
2051         clks[dtv] = clk;
2052
2053         /* dsia */
2054         clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
2055                                ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
2056                                clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
2057         clks[dsia_mux] = clk;
2058         clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
2059                                     0, 48, &periph_h_regs,
2060                                     periph_clk_enb_refcnt);
2061         clks[dsia] = clk;
2062
2063         /* dsib */
2064         clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
2065                                ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
2066                                clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
2067         clks[dsib_mux] = clk;
2068         clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
2069                                     0, 82, &periph_u_regs,
2070                                     periph_clk_enb_refcnt);
2071         clks[dsib] = clk;
2072
2073         /* xusb_hs_src */
2074         val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
2075         val |= BIT(25); /* always select PLLU_60M */
2076         writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC);
2077
2078         clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0,
2079                                         1, 1);
2080         clks[xusb_hs_src] = clk;
2081
2082         /* xusb_host */
2083         clk = tegra_clk_register_periph_gate("xusb_host", "xusb_host_src", 0,
2084                                     clk_base, 0, 89, &periph_u_regs,
2085                                     periph_clk_enb_refcnt);
2086         clks[xusb_host] = clk;
2087
2088         /* xusb_ss */
2089         clk = tegra_clk_register_periph_gate("xusb_ss", "xusb_ss_src", 0,
2090                                     clk_base, 0, 156, &periph_w_regs,
2091                                     periph_clk_enb_refcnt);
2092         clks[xusb_host] = clk;
2093
2094         /* xusb_dev */
2095         clk = tegra_clk_register_periph_gate("xusb_dev", "xusb_dev_src", 0,
2096                                     clk_base, 0, 95, &periph_u_regs,
2097                                     periph_clk_enb_refcnt);
2098         clks[xusb_dev] = clk;
2099
2100         /* emc */
2101         clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
2102                                ARRAY_SIZE(mux_pllmcp_clkm), 0,
2103                                clk_base + CLK_SOURCE_EMC,
2104                                29, 3, 0, NULL);
2105         clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base,
2106                                 CLK_IGNORE_UNUSED, 57, &periph_h_regs,
2107                                 periph_clk_enb_refcnt);
2108         clks[emc] = clk;
2109
2110         for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
2111                 data = &tegra_periph_clk_list[i];
2112                 clk = tegra_clk_register_periph(data->name, data->parent_names,
2113                                 data->num_parents, &data->periph,
2114                                 clk_base, data->offset, data->flags);
2115                 clks[data->clk_id] = clk;
2116         }
2117
2118         for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
2119                 data = &tegra_periph_nodiv_clk_list[i];
2120                 clk = tegra_clk_register_periph_nodiv(data->name,
2121                                 data->parent_names, data->num_parents,
2122                                 &data->periph, clk_base, data->offset);
2123                 clks[data->clk_id] = clk;
2124         }
2125 }
2126
2127 static struct tegra_cpu_car_ops tegra114_cpu_car_ops;
2128
2129 static const struct of_device_id pmc_match[] __initconst = {
2130         { .compatible = "nvidia,tegra114-pmc" },
2131         {},
2132 };
2133
2134 /*
2135  * dfll_soc/dfll_ref apparently must be kept enabled, otherwise I2C5
2136  * breaks
2137  */
2138 static __initdata struct tegra_clk_init_table init_table[] = {
2139         {uarta, pll_p, 408000000, 0},
2140         {uartb, pll_p, 408000000, 0},
2141         {uartc, pll_p, 408000000, 0},
2142         {uartd, pll_p, 408000000, 0},
2143         {pll_a, clk_max, 564480000, 1},
2144         {pll_a_out0, clk_max, 11289600, 1},
2145         {extern1, pll_a_out0, 0, 1},
2146         {clk_out_1_mux, extern1, 0, 1},
2147         {clk_out_1, clk_max, 0, 1},
2148         {i2s0, pll_a_out0, 11289600, 0},
2149         {i2s1, pll_a_out0, 11289600, 0},
2150         {i2s2, pll_a_out0, 11289600, 0},
2151         {i2s3, pll_a_out0, 11289600, 0},
2152         {i2s4, pll_a_out0, 11289600, 0},
2153         {dfll_soc, pll_p, 51000000, 1},
2154         {dfll_ref, pll_p, 51000000, 1},
2155         {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */
2156 };
2157
2158 static void __init tegra114_clock_apply_init_table(void)
2159 {
2160         tegra_init_from_table(init_table, clks, clk_max);
2161 }
2162
2163
2164 /**
2165  * tegra114_car_barrier - wait for pending writes to the CAR to complete
2166  *
2167  * Wait for any outstanding writes to the CAR MMIO space from this CPU
2168  * to complete before continuing execution.  No return value.
2169  */
2170 static void tegra114_car_barrier(void)
2171 {
2172         wmb();          /* probably unnecessary */
2173         readl_relaxed(clk_base + CPU_FINETRIM_SELECT);
2174 }
2175
2176 /**
2177  * tegra114_clock_tune_cpu_trimmers_high - use high-voltage propagation delays
2178  *
2179  * When the CPU rail voltage is in the high-voltage range, use the
2180  * built-in hardwired clock propagation delays in the CPU clock
2181  * shaper.  No return value.
2182  */
2183 void tegra114_clock_tune_cpu_trimmers_high(void)
2184 {
2185         u32 select = 0;
2186
2187         /* Use hardwired rise->rise & fall->fall clock propagation delays */
2188         select |= ~(CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
2189                     CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
2190                     CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
2191         writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
2192
2193         tegra114_car_barrier();
2194 }
2195 EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_high);
2196
2197 /**
2198  * tegra114_clock_tune_cpu_trimmers_low - use low-voltage propagation delays
2199  *
2200  * When the CPU rail voltage is in the low-voltage range, use the
2201  * extended clock propagation delays set by
2202  * tegra114_clock_tune_cpu_trimmers_init().  The intention is to
2203  * maintain the input clock duty cycle that the FCPU subsystem
2204  * expects.  No return value.
2205  */
2206 void tegra114_clock_tune_cpu_trimmers_low(void)
2207 {
2208         u32 select = 0;
2209
2210         /*
2211          * Use software-specified rise->rise & fall->fall clock
2212          * propagation delays (from
2213          * tegra114_clock_tune_cpu_trimmers_init()
2214          */
2215         select |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
2216                    CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
2217                    CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
2218         writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
2219
2220         tegra114_car_barrier();
2221 }
2222 EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_low);
2223
2224 /**
2225  * tegra114_clock_tune_cpu_trimmers_init - set up and enable clk prop delays
2226  *
2227  * Program extended clock propagation delays into the FCPU clock
2228  * shaper and enable them.  XXX Define the purpose - peak current
2229  * reduction?  No return value.
2230  */
2231 /* XXX Initial voltage rail state assumption issues? */
2232 void tegra114_clock_tune_cpu_trimmers_init(void)
2233 {
2234         u32 dr = 0, r = 0;
2235
2236         /* Increment the rise->rise clock delay by four steps */
2237         r |= (CPU_FINETRIM_R_FCPU_1_MASK | CPU_FINETRIM_R_FCPU_2_MASK |
2238               CPU_FINETRIM_R_FCPU_3_MASK | CPU_FINETRIM_R_FCPU_4_MASK |
2239               CPU_FINETRIM_R_FCPU_5_MASK | CPU_FINETRIM_R_FCPU_6_MASK);
2240         writel_relaxed(r, clk_base + CPU_FINETRIM_R);
2241
2242         /*
2243          * Use the rise->rise clock propagation delay specified in the
2244          * r field
2245          */
2246         dr |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
2247                CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
2248                CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
2249         writel_relaxed(dr, clk_base + CPU_FINETRIM_DR);
2250
2251         tegra114_clock_tune_cpu_trimmers_low();
2252 }
2253 EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_init);
2254
2255 /**
2256  * tegra114_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
2257  *
2258  * Assert the reset line of the DFLL's DVCO.  No return value.
2259  */
2260 void tegra114_clock_assert_dfll_dvco_reset(void)
2261 {
2262         u32 v;
2263
2264         v = readl_relaxed(clk_base + RST_DFLL_DVCO);
2265         v |= (1 << DVFS_DFLL_RESET_SHIFT);
2266         writel_relaxed(v, clk_base + RST_DFLL_DVCO);
2267         tegra114_car_barrier();
2268 }
2269 EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset);
2270
2271 /**
2272  * tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
2273  *
2274  * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
2275  * operate.  No return value.
2276  */
2277 void tegra114_clock_deassert_dfll_dvco_reset(void)
2278 {
2279         u32 v;
2280
2281         v = readl_relaxed(clk_base + RST_DFLL_DVCO);
2282         v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
2283         writel_relaxed(v, clk_base + RST_DFLL_DVCO);
2284         tegra114_car_barrier();
2285 }
2286 EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset);
2287
2288 static void __init tegra114_clock_init(struct device_node *np)
2289 {
2290         struct device_node *node;
2291         int i;
2292
2293         clk_base = of_iomap(np, 0);
2294         if (!clk_base) {
2295                 pr_err("ioremap tegra114 CAR failed\n");
2296                 return;
2297         }
2298
2299         node = of_find_matching_node(NULL, pmc_match);
2300         if (!node) {
2301                 pr_err("Failed to find pmc node\n");
2302                 WARN_ON(1);
2303                 return;
2304         }
2305
2306         pmc_base = of_iomap(node, 0);
2307         if (!pmc_base) {
2308                 pr_err("Can't map pmc registers\n");
2309                 WARN_ON(1);
2310                 return;
2311         }
2312
2313         if (tegra114_osc_clk_init(clk_base) < 0)
2314                 return;
2315
2316         tegra114_fixed_clk_init(clk_base);
2317         tegra114_pll_init(clk_base, pmc_base);
2318         tegra114_periph_clk_init(clk_base);
2319         tegra114_audio_clk_init(clk_base);
2320         tegra114_pmc_clk_init(pmc_base);
2321         tegra114_super_clk_init(clk_base);
2322
2323         for (i = 0; i < ARRAY_SIZE(clks); i++) {
2324                 if (IS_ERR(clks[i])) {
2325                         pr_err
2326                             ("Tegra114 clk %d: register failed with %ld\n",
2327                              i, PTR_ERR(clks[i]));
2328                 }
2329                 if (!clks[i])
2330                         clks[i] = ERR_PTR(-EINVAL);
2331         }
2332
2333         clk_data.clks = clks;
2334         clk_data.clk_num = ARRAY_SIZE(clks);
2335         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
2336
2337         tegra_clk_apply_init_table = tegra114_clock_apply_init_table;
2338
2339         tegra_cpu_car_ops = &tegra114_cpu_car_ops;
2340 }
2341 CLK_OF_DECLARE(tegra114, "nvidia,tegra114-car", tegra114_clock_init);