1 // SPDX-License-Identifier: GPL-2.0
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
7 #include <clk-uclass.h>
14 #include <asm/arch-rockchip/clock.h>
15 #include <asm/arch-rockchip/cru_rk322x.h>
16 #include <asm/arch-rockchip/hardware.h>
18 #include <dt-bindings/clock/rk3228-cru.h>
19 #include <linux/delay.h>
20 #include <linux/log2.h>
21 #include <linux/stringify.h>
24 VCO_MAX_HZ = 3200U * 1000000,
25 VCO_MIN_HZ = 800 * 1000000,
26 OUTPUT_MAX_HZ = 3200U * 1000000,
27 OUTPUT_MIN_HZ = 24 * 1000000,
30 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
32 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
34 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
35 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
36 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \
37 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \
38 #hz "Hz cannot be hit with PLL "\
39 "divisors on line " __stringify(__LINE__));
42 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
43 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
45 static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id,
46 const struct pll_div *div)
48 int pll_id = rk_pll_id(clk_id);
49 struct rk322x_pll *pll = &cru->pll[pll_id];
51 /* All PLLs have same VCO and output frequency range restrictions. */
52 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
53 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
55 debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n",
56 pll, div->fbdiv, div->refdiv, div->postdiv1,
57 div->postdiv2, vco_hz, output_hz);
58 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
59 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
61 /* use integer mode */
62 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
64 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);
66 rk_clrsetreg(&pll->con0,
67 PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
68 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
69 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
70 (div->postdiv2 << PLL_POSTDIV2_SHIFT |
71 div->refdiv << PLL_REFDIV_SHIFT));
74 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);
76 /* waiting for pll lock */
77 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
83 static void rkclk_init(struct rk322x_cru *cru)
89 /* pll enter slow-mode */
90 rk_clrsetreg(&cru->cru_mode_con,
91 GPLL_MODE_MASK | APLL_MODE_MASK,
92 GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
93 APLL_MODE_SLOW << APLL_MODE_SHIFT);
96 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
97 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
100 * select apll as cpu/core clock pll source and
101 * set up dependent divisors for PERI and ACLK clocks.
102 * core hz : apll = 1:1
104 aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
105 assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
107 pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
108 assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
110 rk_clrsetreg(&cru->cru_clksel_con[0],
111 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
112 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
113 0 << CORE_DIV_CON_SHIFT);
115 rk_clrsetreg(&cru->cru_clksel_con[1],
116 CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
117 aclk_div << CORE_ACLK_DIV_SHIFT |
118 pclk_div << CORE_PERI_DIV_SHIFT);
121 * select gpll as pd_bus bus clock source and
122 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
124 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
125 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
127 pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
128 assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7);
130 hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
131 assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3);
133 rk_clrsetreg(&cru->cru_clksel_con[0],
134 BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
135 BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
136 aclk_div << BUS_ACLK_DIV_SHIFT);
138 rk_clrsetreg(&cru->cru_clksel_con[1],
139 BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
140 pclk_div << BUS_PCLK_DIV_SHIFT |
141 hclk_div << BUS_HCLK_DIV_SHIFT);
144 * select gpll as pd_peri bus clock source and
145 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
147 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
148 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
150 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
151 assert((1 << hclk_div) * PERI_HCLK_HZ ==
152 PERI_ACLK_HZ && (hclk_div < 0x4));
154 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
155 assert((1 << pclk_div) * PERI_PCLK_HZ ==
156 PERI_ACLK_HZ && pclk_div < 0x8);
158 rk_clrsetreg(&cru->cru_clksel_con[10],
159 PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
160 PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
161 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
162 pclk_div << PERI_PCLK_DIV_SHIFT |
163 hclk_div << PERI_HCLK_DIV_SHIFT |
164 aclk_div << PERI_ACLK_DIV_SHIFT);
166 /* PLL enter normal-mode */
167 rk_clrsetreg(&cru->cru_mode_con,
168 GPLL_MODE_MASK | APLL_MODE_MASK,
169 GPLL_MODE_NORM << GPLL_MODE_SHIFT |
170 APLL_MODE_NORM << APLL_MODE_SHIFT);
173 /* Get pll rate by id */
174 static uint32_t rkclk_pll_get_rate(struct rk322x_cru *cru,
175 enum rk_clk_id clk_id)
177 uint32_t refdiv, fbdiv, postdiv1, postdiv2;
179 int pll_id = rk_pll_id(clk_id);
180 struct rk322x_pll *pll = &cru->pll[pll_id];
181 static u8 clk_shift[CLK_COUNT] = {
182 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
183 GPLL_MODE_SHIFT, 0xff
185 static u32 clk_mask[CLK_COUNT] = {
186 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff,
192 con = readl(&cru->cru_mode_con);
193 shift = clk_shift[clk_id];
194 mask = clk_mask[clk_id];
196 switch ((con & mask) >> shift) {
202 con = readl(&pll->con0);
203 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
204 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
205 con = readl(&pll->con1);
206 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
207 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
208 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
214 static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,
224 case SCLK_EMMC_SAMPLE:
225 con = readl(&cru->cru_clksel_con[11]);
226 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
227 con = readl(&cru->cru_clksel_con[12]);
228 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
232 con = readl(&cru->cru_clksel_con[11]);
233 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
234 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
240 src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
241 return DIV_TO_RATE(src_rate, div) / 2;
244 static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq)
249 * The gmac clock can be derived either from an external clock
250 * or can be generated from internally by a divider from SCLK_MAC.
252 if (readl(&cru->cru_clksel_con[5]) & BIT(5)) {
253 /* An external clock will always generate the right rate... */
256 u32 con = readl(&cru->cru_clksel_con[5]);
260 if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_MASK)
263 /* CPLL is not set */
266 div = DIV_ROUND_UP(pll_rate, freq) - 1;
268 rk_clrsetreg(&cru->cru_clksel_con[5], CLK_MAC_DIV_MASK,
269 div << CLK_MAC_DIV_SHIFT);
271 debug("Unsupported div for gmac:%d\n", div);
273 return DIV_TO_RATE(pll_rate, div);
279 static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
280 int periph, uint freq)
285 debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
287 /* mmc clock defaulg div 2 internal, need provide double in cru */
288 src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
290 if (src_clk_div > 128) {
291 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
292 assert(src_clk_div - 1 < 128);
301 case SCLK_EMMC_SAMPLE:
302 rk_clrsetreg(&cru->cru_clksel_con[11],
304 mux << EMMC_PLL_SHIFT);
305 rk_clrsetreg(&cru->cru_clksel_con[12],
307 (src_clk_div - 1) << EMMC_DIV_SHIFT);
311 rk_clrsetreg(&cru->cru_clksel_con[11],
312 MMC0_PLL_MASK | MMC0_DIV_MASK,
313 mux << MMC0_PLL_SHIFT |
314 (src_clk_div - 1) << MMC0_DIV_SHIFT);
320 return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
323 static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate)
325 struct pll_div dpll_cfg;
327 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
330 dpll_cfg = (struct pll_div)
331 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
334 dpll_cfg = (struct pll_div)
335 {.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1};
338 dpll_cfg = (struct pll_div)
339 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
343 /* pll enter slow-mode */
344 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
345 DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
346 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg);
347 /* PLL enter normal-mode */
348 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
349 DPLL_MODE_NORM << DPLL_MODE_SHIFT);
353 static ulong rk322x_clk_get_rate(struct clk *clk)
355 struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
356 ulong rate, gclk_rate;
358 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
361 rate = rkclk_pll_get_rate(priv->cru, clk->id);
367 rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
376 static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate)
378 struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
379 ulong new_rate, gclk_rate;
381 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
387 new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
391 new_rate = rk322x_ddr_set_clk(priv->cru, rate);
394 new_rate = rk322x_mac_set_clk(priv->cru, rate);
405 static int rk322x_gmac_set_parent(struct clk *clk, struct clk *parent)
407 struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
408 struct rk322x_cru *cru = priv->cru;
411 * If the requested parent is in the same clock-controller and the id
412 * is SCLK_MAC_SRC ("sclk_gmac_src"), switch to the internal clock.
414 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_SRC)) {
415 debug("%s: switching RGMII to SCLK_MAC_SRC\n", __func__);
416 rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), 0);
421 * If the requested parent is in the same clock-controller and the id
422 * is SCLK_MAC_EXTCLK (sclk_mac_extclk), switch to the external clock.
424 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_EXTCLK)) {
425 debug("%s: switching RGMII to SCLK_MAC_EXTCLK\n", __func__);
426 rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), BIT(5));
433 static int rk322x_gmac_extclk_set_parent(struct clk *clk, struct clk *parent)
435 struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
436 const char *clock_output_name;
437 struct rk322x_cru *cru = priv->cru;
440 ret = dev_read_string_index(parent->dev, "clock-output-names",
441 parent->id, &clock_output_name);
445 if (!strcmp(clock_output_name, "ext_gmac")) {
446 debug("%s: switching gmac extclk to ext_gmac\n", __func__);
447 rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), 0);
449 } else if (!strcmp(clock_output_name, "phy_50m_out")) {
450 debug("%s: switching gmac extclk to phy_50m_out\n", __func__);
451 rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), BIT(10));
458 static int rk322x_clk_set_parent(struct clk *clk, struct clk *parent)
462 return rk322x_gmac_set_parent(clk, parent);
463 case SCLK_MAC_EXTCLK:
464 return rk322x_gmac_extclk_set_parent(clk, parent);
467 debug("%s: unsupported clk %ld\n", __func__, clk->id);
471 static struct clk_ops rk322x_clk_ops = {
472 .get_rate = rk322x_clk_get_rate,
473 .set_rate = rk322x_clk_set_rate,
474 .set_parent = rk322x_clk_set_parent,
477 static int rk322x_clk_ofdata_to_platdata(struct udevice *dev)
479 struct rk322x_clk_priv *priv = dev_get_priv(dev);
481 priv->cru = dev_read_addr_ptr(dev);
486 static int rk322x_clk_probe(struct udevice *dev)
488 struct rk322x_clk_priv *priv = dev_get_priv(dev);
490 rkclk_init(priv->cru);
495 static int rk322x_clk_bind(struct udevice *dev)
498 struct udevice *sys_child;
499 struct sysreset_reg *priv;
501 /* The reset driver does not have a device node, so bind it here */
502 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
505 debug("Warning: No sysreset driver: ret=%d\n", ret);
507 priv = malloc(sizeof(struct sysreset_reg));
508 priv->glb_srst_fst_value = offsetof(struct rk322x_cru,
509 cru_glb_srst_fst_value);
510 priv->glb_srst_snd_value = offsetof(struct rk322x_cru,
511 cru_glb_srst_snd_value);
512 sys_child->priv = priv;
515 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
516 ret = offsetof(struct rk322x_cru, cru_softrst_con[0]);
517 ret = rockchip_reset_bind(dev, ret, 9);
519 debug("Warning: software reset driver bind faile\n");
525 static const struct udevice_id rk322x_clk_ids[] = {
526 { .compatible = "rockchip,rk3228-cru" },
530 U_BOOT_DRIVER(rockchip_rk322x_cru) = {
531 .name = "clk_rk322x",
533 .of_match = rk322x_clk_ids,
534 .priv_auto_alloc_size = sizeof(struct rk322x_clk_priv),
535 .ofdata_to_platdata = rk322x_clk_ofdata_to_platdata,
536 .ops = &rk322x_clk_ops,
537 .bind = rk322x_clk_bind,
538 .probe = rk322x_clk_probe,