1 // SPDX-License-Identifier: GPL-2.0
3 * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
7 #include <clk-uclass.h>
12 #include <asm/arch-rockchip/clock.h>
13 #include <asm/arch-rockchip/hardware.h>
16 static struct rockchip_pll_rate_table rockchip_auto_table;
18 #define PLL_MODE_MASK 0x3
19 #define PLL_RK3328_MODE_MASK 0x1
21 #define RK3036_PLLCON0_FBDIV_MASK 0xfff
22 #define RK3036_PLLCON0_FBDIV_SHIFT 0
23 #define RK3036_PLLCON0_POSTDIV1_MASK 0x7 << 12
24 #define RK3036_PLLCON0_POSTDIV1_SHIFT 12
25 #define RK3036_PLLCON1_REFDIV_MASK 0x3f
26 #define RK3036_PLLCON1_REFDIV_SHIFT 0
27 #define RK3036_PLLCON1_POSTDIV2_MASK 0x7 << 6
28 #define RK3036_PLLCON1_POSTDIV2_SHIFT 6
29 #define RK3036_PLLCON1_DSMPD_MASK 0x1 << 12
30 #define RK3036_PLLCON1_DSMPD_SHIFT 12
31 #define RK3036_PLLCON2_FRAC_MASK 0xffffff
32 #define RK3036_PLLCON2_FRAC_SHIFT 0
33 #define RK3036_PLLCON1_PWRDOWN_SHIT 13
38 OSC_HZ = 24 * 1000000,
39 VCO_MAX_HZ = 3200U * 1000000,
40 VCO_MIN_HZ = 800 * 1000000,
41 OUTPUT_MAX_HZ = 3200U * 1000000,
42 OUTPUT_MIN_HZ = 24 * 1000000,
45 #define MIN_FOUTVCO_FREQ (800 * MHZ)
46 #define MAX_FOUTVCO_FREQ (2000 * MHZ)
64 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
65 * Formulas also embedded within the Fractional PLL Verilog model:
66 * If DSMPD = 1 (DSM is disabled, "integer mode")
67 * FOUTVCO = FREF / REFDIV * FBDIV
68 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
70 * FOUTVCO = Fractional PLL non-divided output frequency
71 * FOUTPOSTDIV = Fractional PLL divided output frequency
72 * (output of second post divider)
73 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
74 * REFDIV = Fractional PLL input reference clock divider
75 * FBDIV = Integer value programmed into feedback divide
79 static int rockchip_pll_clk_set_postdiv(ulong fout_hz,
86 if (fout_hz < MIN_FOUTVCO_FREQ) {
87 for (*postdiv1 = 1; *postdiv1 <= 7; (*postdiv1)++) {
88 for (*postdiv2 = 1; *postdiv2 <= 7; (*postdiv2)++) {
89 freq = fout_hz * (*postdiv1) * (*postdiv2);
90 if (freq >= MIN_FOUTVCO_FREQ &&
91 freq <= MAX_FOUTVCO_FREQ) {
97 printf("Can't FIND postdiv1/2 to make fout=%lu in 800~2000M.\n",
106 static struct rockchip_pll_rate_table *
107 rockchip_pll_clk_set_by_auto(ulong fin_hz,
110 struct rockchip_pll_rate_table *rate_table = &rockchip_auto_table;
111 /* FIXME set postdiv1/2 always 1*/
112 u32 foutvco = fout_hz;
113 ulong fin_64, frac_64;
114 u32 f_frac, postdiv1, postdiv2;
117 if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz)
120 rockchip_pll_clk_set_postdiv(fout_hz, &postdiv1, &postdiv2, &foutvco);
121 rate_table->postdiv1 = postdiv1;
122 rate_table->postdiv2 = postdiv2;
123 rate_table->dsmpd = 1;
125 if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) {
128 clk_gcd = gcd(fin_hz, foutvco);
129 rate_table->refdiv = fin_hz / clk_gcd;
130 rate_table->fbdiv = foutvco / clk_gcd;
132 rate_table->frac = 0;
134 debug("fin = %ld, fout = %ld, clk_gcd = %ld,\n",
135 fin_hz, fout_hz, clk_gcd);
136 debug("refdiv= %d,fbdiv= %d,postdiv1= %d,postdiv2= %d\n",
138 rate_table->fbdiv, rate_table->postdiv1,
139 rate_table->postdiv2);
141 debug("frac div,fin_hz = %ld,fout_hz = %ld\n",
143 debug("frac get postdiv1 = %d, postdiv2 = %d, foutvco = %d\n",
144 rate_table->postdiv1, rate_table->postdiv2, foutvco);
145 clk_gcd = gcd(fin_hz / MHZ, foutvco / MHZ);
146 rate_table->refdiv = fin_hz / MHZ / clk_gcd;
147 rate_table->fbdiv = foutvco / MHZ / clk_gcd;
148 debug("frac get refdiv = %d, fbdiv = %d\n",
149 rate_table->refdiv, rate_table->fbdiv);
151 rate_table->frac = 0;
153 f_frac = (foutvco % MHZ);
155 fin_64 = fin_64 / rate_table->refdiv;
156 frac_64 = f_frac << 24;
157 frac_64 = frac_64 / fin_64;
158 rate_table->frac = frac_64;
159 if (rate_table->frac > 0)
160 rate_table->dsmpd = 0;
161 debug("frac = %x\n", rate_table->frac);
166 static const struct rockchip_pll_rate_table *
167 rockchip_get_pll_settings(struct rockchip_pll_clock *pll, ulong rate)
169 struct rockchip_pll_rate_table *rate_table = pll->rate_table;
171 while (rate_table->rate) {
172 if (rate_table->rate == rate)
176 if (rate_table->rate != rate)
177 return rockchip_pll_clk_set_by_auto(24 * MHZ, rate);
182 static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll,
183 void __iomem *base, ulong pll_id,
186 const struct rockchip_pll_rate_table *rate;
188 rate = rockchip_get_pll_settings(pll, drate);
190 printf("%s unsupport rate\n", __func__);
194 debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d\n",
195 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv);
196 debug("%s: rate settings for %lu postdiv2: %d, dsmpd: %d, frac: %d\n",
197 __func__, rate->rate, rate->postdiv2, rate->dsmpd, rate->frac);
200 * When power on or changing PLL setting,
201 * we must force PLL into slow mode to ensure output stable clock.
203 rk_clrsetreg(base + pll->mode_offset,
204 pll->mode_mask << pll->mode_shift,
205 RKCLK_PLL_MODE_SLOW << pll->mode_shift);
208 rk_setreg(base + pll->con_offset + 0x4,
209 1 << RK3036_PLLCON1_PWRDOWN_SHIT);
211 rk_clrsetreg(base + pll->con_offset,
212 (RK3036_PLLCON0_POSTDIV1_MASK |
213 RK3036_PLLCON0_FBDIV_MASK),
214 (rate->postdiv1 << RK3036_PLLCON0_POSTDIV1_SHIFT) |
216 rk_clrsetreg(base + pll->con_offset + 0x4,
217 (RK3036_PLLCON1_POSTDIV2_MASK |
218 RK3036_PLLCON1_REFDIV_MASK),
219 (rate->postdiv2 << RK3036_PLLCON1_POSTDIV2_SHIFT |
220 rate->refdiv << RK3036_PLLCON1_REFDIV_SHIFT));
222 rk_clrsetreg(base + pll->con_offset + 0x4,
223 RK3036_PLLCON1_DSMPD_MASK,
224 rate->dsmpd << RK3036_PLLCON1_DSMPD_SHIFT);
225 writel((readl(base + pll->con_offset + 0x8) &
226 (~RK3036_PLLCON2_FRAC_MASK)) |
227 (rate->frac << RK3036_PLLCON2_FRAC_SHIFT),
228 base + pll->con_offset + 0x8);
232 rk_clrreg(base + pll->con_offset + 0x4,
233 1 << RK3036_PLLCON1_PWRDOWN_SHIT);
235 /* waiting for pll lock */
236 while (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift)))
239 rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift,
240 RKCLK_PLL_MODE_NORMAL << pll->mode_shift);
241 debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n",
242 pll, readl(base + pll->con_offset),
243 readl(base + pll->con_offset + 0x4),
244 readl(base + pll->con_offset + 0x8),
245 readl(base + pll->mode_offset));
250 static ulong rk3036_pll_get_rate(struct rockchip_pll_clock *pll,
251 void __iomem *base, ulong pll_id)
253 u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac;
254 u32 con = 0, shift, mask;
257 con = readl(base + pll->mode_offset);
258 shift = pll->mode_shift;
259 mask = pll->mode_mask << shift;
261 switch ((con & mask) >> shift) {
262 case RKCLK_PLL_MODE_SLOW:
264 case RKCLK_PLL_MODE_NORMAL:
266 con = readl(base + pll->con_offset);
267 postdiv1 = (con & RK3036_PLLCON0_POSTDIV1_MASK) >>
268 RK3036_PLLCON0_POSTDIV1_SHIFT;
269 fbdiv = (con & RK3036_PLLCON0_FBDIV_MASK) >>
270 RK3036_PLLCON0_FBDIV_SHIFT;
271 con = readl(base + pll->con_offset + 0x4);
272 postdiv2 = (con & RK3036_PLLCON1_POSTDIV2_MASK) >>
273 RK3036_PLLCON1_POSTDIV2_SHIFT;
274 refdiv = (con & RK3036_PLLCON1_REFDIV_MASK) >>
275 RK3036_PLLCON1_REFDIV_SHIFT;
276 dsmpd = (con & RK3036_PLLCON1_DSMPD_MASK) >>
277 RK3036_PLLCON1_DSMPD_SHIFT;
278 con = readl(base + pll->con_offset + 0x8);
279 frac = (con & RK3036_PLLCON2_FRAC_MASK) >>
280 RK3036_PLLCON2_FRAC_SHIFT;
281 rate = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
283 u64 frac_rate = OSC_HZ * (u64)frac;
285 do_div(frac_rate, refdiv);
287 do_div(frac_rate, postdiv1);
288 do_div(frac_rate, postdiv1);
292 case RKCLK_PLL_MODE_DEEP:
298 ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll,
306 pll->mode_mask = PLL_MODE_MASK;
307 rate = rk3036_pll_get_rate(pll, base, pll_id);
310 pll->mode_mask = PLL_RK3328_MODE_MASK;
311 rate = rk3036_pll_get_rate(pll, base, pll_id);
314 printf("%s: Unknown pll type for pll clk %ld\n",
320 int rockchip_pll_set_rate(struct rockchip_pll_clock *pll,
321 void __iomem *base, ulong pll_id,
326 if (rockchip_pll_get_rate(pll, base, pll_id) == drate)
331 pll->mode_mask = PLL_MODE_MASK;
332 ret = rk3036_pll_set_rate(pll, base, pll_id, drate);
335 pll->mode_mask = PLL_RK3328_MODE_MASK;
336 ret = rk3036_pll_set_rate(pll, base, pll_id, drate);
339 printf("%s: Unknown pll type for pll clk %ld\n",
345 const struct rockchip_cpu_rate_table *
346 rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table,
349 struct rockchip_cpu_rate_table *ps = cpu_table;
352 if (ps->rate == rate)
356 if (ps->rate != rate)