1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2017-2019 NXP.
5 * Peng Fan <peng.fan@nxp.com>
11 #include <clk-uclass.h>
12 #include <dm/device.h>
13 #include <dm/devres.h>
14 #include <linux/clk-provider.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/iopoll.h>
23 #define UBOOT_DM_CLK_IMX_PLL1443X "imx_clk_pll1443x"
24 #define UBOOT_DM_CLK_IMX_PLL1416X "imx_clk_pll1416x"
28 #define LOCK_STATUS BIT(31)
29 #define LOCK_SEL_MASK BIT(29)
30 #define CLKE_MASK BIT(11)
31 #define RST_MASK BIT(9)
32 #define BYPASS_MASK BIT(4)
34 #define MDIV_MASK GENMASK(21, 12)
36 #define PDIV_MASK GENMASK(9, 4)
38 #define SDIV_MASK GENMASK(2, 0)
40 #define KDIV_MASK GENMASK(15, 0)
42 #define LOCK_TIMEOUT_US 10000
47 enum imx_pll14xx_type type;
48 const struct imx_pll14xx_rate_table *rate_table;
52 #define to_clk_pll14xx(_clk) container_of(_clk, struct clk_pll14xx, clk)
54 static const struct imx_pll14xx_rate_table *imx_get_pll_settings(
55 struct clk_pll14xx *pll, unsigned long rate)
57 const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
60 for (i = 0; i < pll->rate_count; i++)
61 if (rate == rate_table[i].rate)
62 return &rate_table[i];
67 static unsigned long clk_pll1416x_recalc_rate(struct clk *clk)
69 struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
70 u64 fvco = clk_get_parent_rate(clk);
71 u32 mdiv, pdiv, sdiv, pll_div;
73 pll_div = readl(pll->base + 4);
74 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
75 pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
76 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT;
79 do_div(fvco, pdiv << sdiv);
84 static unsigned long clk_pll1443x_recalc_rate(struct clk *clk)
86 struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
87 u64 fvco = clk_get_parent_rate(clk);
88 u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1;
91 pll_div_ctl0 = readl(pll->base + 4);
92 pll_div_ctl1 = readl(pll->base + 8);
93 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
94 pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
95 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT;
96 kdiv = pll_div_ctl1 & KDIV_MASK;
98 /* fvco = (m * 65536 + k) * Fin / (p * 65536) */
99 fvco *= (mdiv * 65536 + kdiv);
102 do_div(fvco, pdiv << sdiv);
107 static inline bool clk_pll1416x_mp_change(const struct imx_pll14xx_rate_table *rate,
110 u32 old_mdiv, old_pdiv;
112 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
113 old_pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
115 return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;
118 static inline bool clk_pll1443x_mpk_change(const struct imx_pll14xx_rate_table *rate,
119 u32 pll_div_ctl0, u32 pll_div_ctl1)
121 u32 old_mdiv, old_pdiv, old_kdiv;
123 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
124 old_pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
125 old_kdiv = (pll_div_ctl1 & KDIV_MASK) >> KDIV_SHIFT;
127 return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
128 rate->kdiv != old_kdiv;
131 static inline bool clk_pll1443x_mp_change(const struct imx_pll14xx_rate_table *rate,
132 u32 pll_div_ctl0, u32 pll_div_ctl1)
134 u32 old_mdiv, old_pdiv, old_kdiv;
136 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
137 old_pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
138 old_kdiv = (pll_div_ctl1 & KDIV_MASK) >> KDIV_SHIFT;
140 return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
141 rate->kdiv != old_kdiv;
144 static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)
148 return readl_poll_timeout(pll->base, val, val & LOCK_TIMEOUT_US,
152 static ulong clk_pll1416x_set_rate(struct clk *clk, unsigned long drate)
154 struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
155 const struct imx_pll14xx_rate_table *rate;
159 rate = imx_get_pll_settings(pll, drate);
161 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
166 tmp = readl(pll->base + 4);
168 if (!clk_pll1416x_mp_change(rate, tmp)) {
169 tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
170 tmp |= rate->sdiv << SDIV_SHIFT;
171 writel(tmp, pll->base + 4);
173 return clk_pll1416x_recalc_rate(clk);
176 /* Bypass clock and set lock to pll output lock */
177 tmp = readl(pll->base);
178 tmp |= LOCK_SEL_MASK;
179 writel(tmp, pll->base);
183 writel(tmp, pll->base);
187 writel(tmp, pll->base);
190 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
191 (rate->sdiv << SDIV_SHIFT);
192 writel(div_val, pll->base + 0x4);
195 * According to SPEC, t3 - t2 need to be greater than
196 * 1us and 1/FREF, respectively.
197 * FREF is FIN / Prediv, the prediv is [1, 63], so choose
204 writel(tmp, pll->base);
207 ret = clk_pll14xx_wait_lock(pll);
213 writel(tmp, pll->base);
215 return clk_pll1416x_recalc_rate(clk);
218 static ulong clk_pll1443x_set_rate(struct clk *clk, unsigned long drate)
220 struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
221 const struct imx_pll14xx_rate_table *rate;
225 rate = imx_get_pll_settings(pll, drate);
227 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
232 tmp = readl(pll->base + 4);
233 div_val = readl(pll->base + 8);
235 if (!clk_pll1443x_mpk_change(rate, tmp, div_val)) {
236 tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
237 tmp |= rate->sdiv << SDIV_SHIFT;
238 writel(tmp, pll->base + 4);
240 return clk_pll1443x_recalc_rate(clk);
243 tmp = readl(pll->base);
247 writel(tmp, pll->base);
251 writel(tmp, pll->base);
253 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
254 (rate->sdiv << SDIV_SHIFT);
255 writel(div_val, pll->base + 0x4);
256 writel(rate->kdiv << KDIV_SHIFT, pll->base + 0x8);
259 * According to SPEC, t3 - t2 need to be greater than
260 * 1us and 1/FREF, respectively.
261 * FREF is FIN / Prediv, the prediv is [1, 63], so choose
268 writel(tmp, pll->base);
271 ret = clk_pll14xx_wait_lock(pll);
277 writel(tmp, pll->base);
279 return clk_pll1443x_recalc_rate(clk);
282 static int clk_pll14xx_prepare(struct clk *clk)
284 struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
288 * RESETB = 1 from 0, PLL starts its normal
289 * operation after lock time
291 val = readl(pll->base + GNRL_CTL);
293 writel(val, pll->base + GNRL_CTL);
295 return clk_pll14xx_wait_lock(pll);
298 static int clk_pll14xx_unprepare(struct clk *clk)
300 struct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));
304 * Set RST to 0, power down mode is enabled and
305 * every digital block is reset
307 val = readl(pll->base + GNRL_CTL);
309 writel(val, pll->base + GNRL_CTL);
314 static const struct clk_ops clk_pll1416x_ops = {
315 .enable = clk_pll14xx_prepare,
316 .disable = clk_pll14xx_unprepare,
317 .set_rate = clk_pll1416x_set_rate,
318 .get_rate = clk_pll1416x_recalc_rate,
321 static const struct clk_ops clk_pll1443x_ops = {
322 .enable = clk_pll14xx_prepare,
323 .disable = clk_pll14xx_unprepare,
324 .set_rate = clk_pll1443x_set_rate,
325 .get_rate = clk_pll1443x_recalc_rate,
328 struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
330 const struct imx_pll14xx_clk *pll_clk)
332 struct clk_pll14xx *pll;
337 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
339 return ERR_PTR(-ENOMEM);
341 switch (pll_clk->type) {
343 type_name = UBOOT_DM_CLK_IMX_PLL1416X;
346 type_name = UBOOT_DM_CLK_IMX_PLL1443X;
349 pr_err("%s: Unknown pll type for pll clk %s\n",
351 return ERR_PTR(-EINVAL);
355 pll->type = pll_clk->type;
356 pll->rate_table = pll_clk->rate_table;
357 pll->rate_count = pll_clk->rate_count;
361 ret = clk_register(clk, type_name, name, parent_name);
363 pr_err("%s: failed to register pll %s %d\n",
364 __func__, name, ret);
372 U_BOOT_DRIVER(clk_pll1443x) = {
373 .name = UBOOT_DM_CLK_IMX_PLL1443X,
375 .ops = &clk_pll1443x_ops,
376 .flags = DM_FLAG_PRE_RELOC,
379 U_BOOT_DRIVER(clk_pll1416x) = {
380 .name = UBOOT_DM_CLK_IMX_PLL1416X,
382 .ops = &clk_pll1416x_ops,
383 .flags = DM_FLAG_PRE_RELOC,