drivers/clk/clk-vt8500.c

   1 /*
   2  * Clock implementation for VIA/Wondermedia SoC's
   3  * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15
  16 #include <linux/io.h>
  17 #include <linux/of.h>
  18 #include <linux/slab.h>
  19 #include <linux/bitops.h>
  20 #include <linux/clkdev.h>
  21 #include <linux/clk-provider.h>
  22
  23 /* All clocks share the same lock as none can be changed concurrently */
  24 static DEFINE_SPINLOCK(_lock);
  25
  26 struct clk_device {
  27         struct clk_hw   hw;
  28         void __iomem    *div_reg;
  29         unsigned int    div_mask;
  30         void __iomem    *en_reg;
  31         int             en_bit;
  32         spinlock_t      *lock;
  33 };
  34
  35 /*
  36  * Add new PLL_TYPE_x definitions here as required. Use the first known model
  37  * to support the new type as the name.
  38  * Add case statements to vtwm_pll_recalc_rate(), vtwm_pll_round_round() and
  39  * vtwm_pll_set_rate() to handle the new PLL_TYPE_x
  40  */
  41
  42 #define PLL_TYPE_VT8500         0
  43 #define PLL_TYPE_WM8650         1
  44
  45 struct clk_pll {
  46         struct clk_hw   hw;
  47         void __iomem    *reg;
  48         spinlock_t      *lock;
  49         int             type;
  50 };
  51
  52 static void __iomem *pmc_base;
  53
  54 #define to_clk_device(_hw) container_of(_hw, struct clk_device, hw)
  55
  56 #define VT8500_PMC_BUSY_MASK            0x18
  57
  58 static void vt8500_pmc_wait_busy(void)
  59 {
  60         while (readl(pmc_base) & VT8500_PMC_BUSY_MASK)
  61                 cpu_relax();
  62 }
  63
  64 static int vt8500_dclk_enable(struct clk_hw *hw)
  65 {
  66         struct clk_device *cdev = to_clk_device(hw);
  67         u32 en_val;
  68         unsigned long flags = 0;
  69
  70         spin_lock_irqsave(cdev->lock, flags);
  71
  72         en_val = readl(cdev->en_reg);
  73         en_val |= BIT(cdev->en_bit);
  74         writel(en_val, cdev->en_reg);
  75
  76         spin_unlock_irqrestore(cdev->lock, flags);
  77         return 0;
  78 }
  79
  80 static void vt8500_dclk_disable(struct clk_hw *hw)
  81 {
  82         struct clk_device *cdev = to_clk_device(hw);
  83         u32 en_val;
  84         unsigned long flags = 0;
  85
  86         spin_lock_irqsave(cdev->lock, flags);
  87
  88         en_val = readl(cdev->en_reg);
  89         en_val &= ~BIT(cdev->en_bit);
  90         writel(en_val, cdev->en_reg);
  91
  92         spin_unlock_irqrestore(cdev->lock, flags);
  93 }
  94
  95 static int vt8500_dclk_is_enabled(struct clk_hw *hw)
  96 {
  97         struct clk_device *cdev = to_clk_device(hw);
  98         u32 en_val = (readl(cdev->en_reg) & BIT(cdev->en_bit));
  99
 100         return en_val ? 1 : 0;
 101 }
 102
 103 static unsigned long vt8500_dclk_recalc_rate(struct clk_hw *hw,
 104                                 unsigned long parent_rate)
 105 {
 106         struct clk_device *cdev = to_clk_device(hw);
 107         u32 div = readl(cdev->div_reg) & cdev->div_mask;
 108
 109         /* Special case for SDMMC devices */
 110         if ((cdev->div_mask == 0x3F) && (div & BIT(5)))
 111                 div = 64 * (div & 0x1f);
 112
 113         /* div == 0 is actually the highest divisor */
 114         if (div == 0)
 115                 div = (cdev->div_mask + 1);
 116
 117         return parent_rate / div;
 118 }
 119
 120 static long vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
 121                                 unsigned long *prate)
 122 {
 123         struct clk_device *cdev = to_clk_device(hw);
 124         u32 divisor = *prate / rate;
 125
 126         /*
 127          * If this is a request for SDMMC we have to adjust the divisor
 128          * when >31 to use the fixed predivisor
 129          */
 130         if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
 131                 divisor = 64 * ((divisor / 64) + 1);
 132         }
 133
 134         return *prate / divisor;
 135 }
 136
 137 static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
 138                                 unsigned long parent_rate)
 139 {
 140         struct clk_device *cdev = to_clk_device(hw);
 141         u32 divisor = parent_rate / rate;
 142         unsigned long flags = 0;
 143
 144         if (divisor == cdev->div_mask + 1)
 145                 divisor = 0;
 146
 147         /* SDMMC mask may need to be corrected before testing if its valid */
 148         if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
 149                 /*
 150                  * Bit 5 is a fixed /64 predivisor. If the requested divisor
 151                  * is >31 then correct for the fixed divisor being required.
 152                  */
 153                 divisor = 0x20 + (divisor / 64);
 154         }
 155
 156         if (divisor > cdev->div_mask) {
 157                 pr_err("%s: invalid divisor for clock\n", __func__);
 158                 return -EINVAL;
 159         }
 160
 161         spin_lock_irqsave(cdev->lock, flags);
 162
 163         vt8500_pmc_wait_busy();
 164         writel(divisor, cdev->div_reg);
 165         vt8500_pmc_wait_busy();
 166
 167         spin_lock_irqsave(cdev->lock, flags);
 168
 169         return 0;
 170 }
 171
 172
 173 static const struct clk_ops vt8500_gated_clk_ops = {
 174         .enable = vt8500_dclk_enable,
 175         .disable = vt8500_dclk_disable,
 176         .is_enabled = vt8500_dclk_is_enabled,
 177 };
 178
 179 static const struct clk_ops vt8500_divisor_clk_ops = {
 180         .round_rate = vt8500_dclk_round_rate,
 181         .set_rate = vt8500_dclk_set_rate,
 182         .recalc_rate = vt8500_dclk_recalc_rate,
 183 };
 184
 185 static const struct clk_ops vt8500_gated_divisor_clk_ops = {
 186         .enable = vt8500_dclk_enable,
 187         .disable = vt8500_dclk_disable,
 188         .is_enabled = vt8500_dclk_is_enabled,
 189         .round_rate = vt8500_dclk_round_rate,
 190         .set_rate = vt8500_dclk_set_rate,
 191         .recalc_rate = vt8500_dclk_recalc_rate,
 192 };
 193
 194 #define CLK_INIT_GATED                  BIT(0)
 195 #define CLK_INIT_DIVISOR                BIT(1)
 196 #define CLK_INIT_GATED_DIVISOR          (CLK_INIT_DIVISOR | CLK_INIT_GATED)
 197
 198 static __init void vtwm_device_clk_init(struct device_node *node)
 199 {
 200         u32 en_reg, div_reg;
 201         struct clk *clk;
 202         struct clk_device *dev_clk;
 203         const char *clk_name = node->name;
 204         const char *parent_name;
 205         struct clk_init_data init;
 206         int rc;
 207         int clk_init_flags = 0;
 208
 209         dev_clk = kzalloc(sizeof(*dev_clk), GFP_KERNEL);
 210         if (WARN_ON(!dev_clk))
 211                 return;
 212
 213         dev_clk->lock = &_lock;
 214
 215         rc = of_property_read_u32(node, "enable-reg", &en_reg);
 216         if (!rc) {
 217                 dev_clk->en_reg = pmc_base + en_reg;
 218                 rc = of_property_read_u32(node, "enable-bit", &dev_clk->en_bit);
 219                 if (rc) {
 220                         pr_err("%s: enable-bit property required for gated clock\n",
 221                                                                 __func__);
 222                         return;
 223                 }
 224                 clk_init_flags |= CLK_INIT_GATED;
 225         }
 226
 227         rc = of_property_read_u32(node, "divisor-reg", &div_reg);
 228         if (!rc) {
 229                 dev_clk->div_reg = pmc_base + div_reg;
 230                 /*
 231                  * use 0x1f as the default mask since it covers
 232                  * almost all the clocks and reduces dts properties
 233                  */
 234                 dev_clk->div_mask = 0x1f;
 235
 236                 of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask);
 237                 clk_init_flags |= CLK_INIT_DIVISOR;
 238         }
 239
 240         of_property_read_string(node, "clock-output-names", &clk_name);
 241
 242         switch (clk_init_flags) {
 243         case CLK_INIT_GATED:
 244                 init.ops = &vt8500_gated_clk_ops;
 245                 break;
 246         case CLK_INIT_DIVISOR:
 247                 init.ops = &vt8500_divisor_clk_ops;
 248                 break;
 249         case CLK_INIT_GATED_DIVISOR:
 250                 init.ops = &vt8500_gated_divisor_clk_ops;
 251                 break;
 252         default:
 253                 pr_err("%s: Invalid clock description in device tree\n",
 254                                                                 __func__);
 255                 kfree(dev_clk);
 256                 return;
 257         }
 258
 259         init.name = clk_name;
 260         init.flags = 0;
 261         parent_name = of_clk_get_parent_name(node, 0);
 262         init.parent_names = &parent_name;
 263         init.num_parents = 1;
 264
 265         dev_clk->hw.init = &init;
 266
 267         clk = clk_register(NULL, &dev_clk->hw);
 268         if (WARN_ON(IS_ERR(clk))) {
 269                 kfree(dev_clk);
 270                 return;
 271         }
 272         rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
 273         clk_register_clkdev(clk, clk_name, NULL);
 274 }
 275
 276
 277 /* PLL clock related functions */
 278
 279 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
 280
 281 /* Helper macros for PLL_VT8500 */
 282 #define VT8500_PLL_MUL(x)       ((x & 0x1F) << 1)
 283 #define VT8500_PLL_DIV(x)       ((x & 0x100) ? 1 : 2)
 284
 285 #define VT8500_BITS_TO_FREQ(r, m, d)                                    \
 286                                 ((r / d) * m)
 287
 288 #define VT8500_BITS_TO_VAL(m, d)                                        \
 289                                 ((d == 2 ? 0 : 0x100) | ((m >> 1) & 0x1F))
 290
 291 /* Helper macros for PLL_WM8650 */
 292 #define WM8650_PLL_MUL(x)       (x & 0x3FF)
 293 #define WM8650_PLL_DIV(x)       (((x >> 10) & 7) * (1 << ((x >> 13) & 3)))
 294
 295 #define WM8650_BITS_TO_FREQ(r, m, d1, d2)                               \
 296                                 (r * m / (d1 * (1 << d2)))
 297
 298 #define WM8650_BITS_TO_VAL(m, d1, d2)                                   \
 299                                 ((d2 << 13) | (d1 << 10) | (m & 0x3FF))
 300
 301
 302 static void vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate,
 303                                 u32 *multiplier, u32 *prediv)
 304 {
 305         unsigned long tclk;
 306
 307         /* sanity check */
 308         if ((rate < parent_rate * 4) || (rate > parent_rate * 62)) {
 309                 pr_err("%s: requested rate out of range\n", __func__);
 310                 *multiplier = 0;
 311                 *prediv = 1;
 312                 return;
 313         }
 314         if (rate <= parent_rate * 31)
 315                 /* use the prediv to double the resolution */
 316                 *prediv = 2;
 317         else
 318                 *prediv = 1;
 319
 320         *multiplier = rate / (parent_rate / *prediv);
 321         tclk = (parent_rate / *prediv) * *multiplier;
 322
 323         if (tclk != rate)
 324                 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__,
 325                                                                 rate, tclk);
 326 }
 327
 328 static void wm8650_find_pll_bits(unsigned long rate, unsigned long parent_rate,
 329                                 u32 *multiplier, u32 *divisor1, u32 *divisor2)
 330 {
 331         u32 mul, div1, div2;
 332         u32 best_mul, best_div1, best_div2;
 333         unsigned long tclk, rate_err, best_err;
 334
 335         best_err = (unsigned long)-1;
 336
 337         /* Find the closest match (lower or equal to requested) */
 338         for (div1 = 5; div1 >= 3; div1--)
 339                 for (div2 = 3; div2 >= 0; div2--)
 340                         for (mul = 3; mul <= 1023; mul++) {
 341                                 tclk = parent_rate * mul / (div1 * (1 << div2));
 342                                 if (tclk > rate)
 343                                         continue;
 344                                 /* error will always be +ve */
 345                                 rate_err = rate - tclk;
 346                                 if (rate_err == 0) {
 347                                         *multiplier = mul;
 348                                         *divisor1 = div1;
 349                                         *divisor2 = div2;
 350                                         return;
 351                                 }
 352
 353                                 if (rate_err < best_err) {
 354                                         best_err = rate_err;
 355                                         best_mul = mul;
 356                                         best_div1 = div1;
 357                                         best_div2 = div2;
 358                                 }
 359                         }
 360
 361         /* if we got here, it wasn't an exact match */
 362         pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
 363                                                         rate - best_err);
 364         *multiplier = mul;
 365         *divisor1 = div1;
 366         *divisor2 = div2;
 367 }
 368
 369 static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 370                                 unsigned long parent_rate)
 371 {
 372         struct clk_pll *pll = to_clk_pll(hw);
 373         u32 mul, div1, div2;
 374         u32 pll_val;
 375         unsigned long flags = 0;
 376
 377         /* sanity check */
 378
 379         switch (pll->type) {
 380         case PLL_TYPE_VT8500:
 381                 vt8500_find_pll_bits(rate, parent_rate, &mul, &div1);
 382                 pll_val = VT8500_BITS_TO_VAL(mul, div1);
 383                 break;
 384         case PLL_TYPE_WM8650:
 385                 wm8650_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
 386                 pll_val = WM8650_BITS_TO_VAL(mul, div1, div2);
 387                 break;
 388         default:
 389                 pr_err("%s: invalid pll type\n", __func__);
 390                 return 0;
 391         }
 392
 393         spin_lock_irqsave(pll->lock, flags);
 394
 395         vt8500_pmc_wait_busy();
 396         writel(pll_val, pll->reg);
 397         vt8500_pmc_wait_busy();
 398
 399         spin_unlock_irqrestore(pll->lock, flags);
 400
 401         return 0;
 402 }
 403
 404 static long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 405                                 unsigned long *prate)
 406 {
 407         struct clk_pll *pll = to_clk_pll(hw);
 408         u32 mul, div1, div2;
 409         long round_rate;
 410
 411         switch (pll->type) {
 412         case PLL_TYPE_VT8500:
 413                 vt8500_find_pll_bits(rate, *prate, &mul, &div1);
 414                 round_rate = VT8500_BITS_TO_FREQ(*prate, mul, div1);
 415                 break;
 416         case PLL_TYPE_WM8650:
 417                 wm8650_find_pll_bits(rate, *prate, &mul, &div1, &div2);
 418                 round_rate = WM8650_BITS_TO_FREQ(*prate, mul, div1, div2);
 419                 break;
 420         default:
 421                 round_rate = 0;
 422         }
 423
 424         return round_rate;
 425 }
 426
 427 static unsigned long vtwm_pll_recalc_rate(struct clk_hw *hw,
 428                                 unsigned long parent_rate)
 429 {
 430         struct clk_pll *pll = to_clk_pll(hw);
 431         u32 pll_val = readl(pll->reg);
 432         unsigned long pll_freq;
 433
 434         switch (pll->type) {
 435         case PLL_TYPE_VT8500:
 436                 pll_freq = parent_rate * VT8500_PLL_MUL(pll_val);
 437                 pll_freq /= VT8500_PLL_DIV(pll_val);
 438                 break;
 439         case PLL_TYPE_WM8650:
 440                 pll_freq = parent_rate * WM8650_PLL_MUL(pll_val);
 441                 pll_freq /= WM8650_PLL_DIV(pll_val);
 442                 break;
 443         default:
 444                 pll_freq = 0;
 445         }
 446
 447         return pll_freq;
 448 }
 449
 450 const struct clk_ops vtwm_pll_ops = {
 451         .round_rate = vtwm_pll_round_rate,
 452         .set_rate = vtwm_pll_set_rate,
 453         .recalc_rate = vtwm_pll_recalc_rate,
 454 };
 455
 456 static __init void vtwm_pll_clk_init(struct device_node *node, int pll_type)
 457 {
 458         u32 reg;
 459         struct clk *clk;
 460         struct clk_pll *pll_clk;
 461         const char *clk_name = node->name;
 462         const char *parent_name;
 463         struct clk_init_data init;
 464         int rc;
 465
 466         rc = of_property_read_u32(node, "reg", &reg);
 467         if (WARN_ON(rc))
 468                 return;
 469
 470         pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
 471         if (WARN_ON(!pll_clk))
 472                 return;
 473
 474         pll_clk->reg = pmc_base + reg;
 475         pll_clk->lock = &_lock;
 476         pll_clk->type = pll_type;
 477
 478         of_property_read_string(node, "clock-output-names", &clk_name);
 479
 480         init.name = clk_name;
 481         init.ops = &vtwm_pll_ops;
 482         init.flags = 0;
 483         parent_name = of_clk_get_parent_name(node, 0);
 484         init.parent_names = &parent_name;
 485         init.num_parents = 1;
 486
 487         pll_clk->hw.init = &init;
 488
 489         clk = clk_register(NULL, &pll_clk->hw);
 490         if (WARN_ON(IS_ERR(clk))) {
 491                 kfree(pll_clk);
 492                 return;
 493         }
 494         rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
 495         clk_register_clkdev(clk, clk_name, NULL);
 496 }
 497
 498
 499 /* Wrappers for initialization functions */
 500
 501 static void __init vt8500_pll_init(struct device_node *node)
 502 {
 503         vtwm_pll_clk_init(node, PLL_TYPE_VT8500);
 504 }
 505
 506 static void __init wm8650_pll_init(struct device_node *node)
 507 {
 508         vtwm_pll_clk_init(node, PLL_TYPE_WM8650);
 509 }
 510
 511 static const __initconst struct of_device_id clk_match[] = {
 512         { .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
 513         { .compatible = "via,vt8500-pll-clock", .data = vt8500_pll_init, },
 514         { .compatible = "wm,wm8650-pll-clock", .data = wm8650_pll_init, },
 515         { .compatible = "via,vt8500-device-clock",
 516                                         .data = vtwm_device_clk_init, },
 517         { /* sentinel */ }
 518 };
 519
 520 void __init vtwm_clk_init(void __iomem *base)
 521 {
 522         if (!base)
 523                 return;
 524
 525         pmc_base = base;
 526
 527         of_clk_init(clk_match);
 528 }