2 * drivers/char/watchdog/pnx4008_wdt.c
4 * Watchdog driver for PNX4008 board
6 * Authors: Dmitry Chigirev <source@mvista.com>,
7 * Vitaly Wool <vitalywool@gmail.com>
8 * Based on sa1100 driver,
9 * Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
11 * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
12 * the terms of the GNU General Public License version 2. This program
13 * is licensed "as is" without any warranty of any kind, whether express
17 #include <linux/config.h>
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/types.h>
21 #include <linux/kernel.h>
23 #include <linux/miscdevice.h>
24 #include <linux/watchdog.h>
25 #include <linux/init.h>
26 #include <linux/bitops.h>
27 #include <linux/ioport.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
32 #include <asm/hardware.h>
33 #include <asm/uaccess.h>
36 #define MODULE_NAME "PNX4008-WDT: "
38 /* WatchDog Timer - Chapter 23 Page 207 */
40 #define DEFAULT_HEARTBEAT 19
41 #define MAX_HEARTBEAT 60
43 /* Watchdog timer register set definition */
44 #define WDTIM_INT(p) ((p) + 0x0)
45 #define WDTIM_CTRL(p) ((p) + 0x4)
46 #define WDTIM_COUNTER(p) ((p) + 0x8)
47 #define WDTIM_MCTRL(p) ((p) + 0xC)
48 #define WDTIM_MATCH0(p) ((p) + 0x10)
49 #define WDTIM_EMR(p) ((p) + 0x14)
50 #define WDTIM_PULSE(p) ((p) + 0x18)
51 #define WDTIM_RES(p) ((p) + 0x1C)
53 /* WDTIM_INT bit definitions */
56 /* WDTIM_CTRL bit definitions */
58 #define RESET_COUNT (1<<1)
59 #define DEBUG_EN (1<<2)
61 /* WDTIM_MCTRL bit definitions */
64 #define RESET_COUNT0 (1<<2)
65 #define STOP_COUNT0 (1<<2)
68 #define RESFRC1 (1<<5)
69 #define RESFRC2 (1<<6)
71 /* WDTIM_EMR bit definitions */
73 #define MATCH_OUTPUT_HIGH (2<<4) /*a MATCH_CTRL setting */
75 /* WDTIM_RES bit definitions */
76 #define WDOG_RESET 1 /* read only */
78 #define WDOG_COUNTER_RATE 13000000 /*the counter clock is 13 MHz fixed */
80 #ifdef CONFIG_WATCHDOG_NOWAYOUT
81 static int nowayout = 1;
83 static int nowayout = 0;
85 static int heartbeat = DEFAULT_HEARTBEAT;
87 static unsigned long wdt_status;
89 #define WDT_OK_TO_CLOSE 1
90 #define WDT_REGION_INITED 2
91 #define WDT_DEVICE_INITED 3
93 static unsigned long boot_status;
95 static struct resource *wdt_mem;
96 static void __iomem *wdt_base;
99 static void wdt_enable(void)
102 clk_set_rate(wdt_clk, 1);
104 /* stop counter, initiate counter reset */
105 __raw_writel(RESET_COUNT, WDTIM_CTRL(wdt_base));
106 /*wait for reset to complete. 100% guarantee event */
107 while (__raw_readl(WDTIM_COUNTER(wdt_base)));
108 /* internal and external reset, stop after that */
109 __raw_writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0,
110 WDTIM_MCTRL(wdt_base));
111 /* configure match output */
112 __raw_writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base));
113 /* clear interrupt, just in case */
114 __raw_writel(MATCH_INT, WDTIM_INT(wdt_base));
115 /* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */
116 __raw_writel(0xFFFF, WDTIM_PULSE(wdt_base));
117 __raw_writel(heartbeat * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base));
118 /*enable counter, stop when debugger active */
119 __raw_writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base));
122 static void wdt_disable(void)
124 __raw_writel(0, WDTIM_CTRL(wdt_base)); /*stop counter */
126 clk_set_rate(wdt_clk, 0);
129 static int pnx4008_wdt_open(struct inode *inode, struct file *file)
131 if (test_and_set_bit(WDT_IN_USE, &wdt_status))
134 clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
138 return nonseekable_open(inode, file);
142 pnx4008_wdt_write(struct file *file, const char *data, size_t len,
145 /* Can't seek (pwrite) on this device */
146 if (ppos != &file->f_pos)
153 clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
155 for (i = 0; i != len; i++) {
158 if (get_user(c, data + i))
161 set_bit(WDT_OK_TO_CLOSE, &wdt_status);
170 static struct watchdog_info ident = {
171 .options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE |
172 WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
173 .identity = "PNX4008 Watchdog",
177 pnx4008_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
180 int ret = -ENOIOCTLCMD;
184 case WDIOC_GETSUPPORT:
185 ret = copy_to_user((struct watchdog_info *)arg, &ident,
186 sizeof(ident)) ? -EFAULT : 0;
189 case WDIOC_GETSTATUS:
190 ret = put_user(0, (int *)arg);
193 case WDIOC_GETBOOTSTATUS:
194 ret = put_user(boot_status, (int *)arg);
197 case WDIOC_SETTIMEOUT:
198 ret = get_user(time, (int *)arg);
202 if (time <= 0 || time > MAX_HEARTBEAT) {
211 case WDIOC_GETTIMEOUT:
212 ret = put_user(heartbeat, (int *)arg);
215 case WDIOC_KEEPALIVE:
223 static int pnx4008_wdt_release(struct inode *inode, struct file *file)
225 if (!test_bit(WDT_OK_TO_CLOSE, &wdt_status))
226 printk(KERN_WARNING "WATCHDOG: Device closed unexpectdly\n");
229 clear_bit(WDT_IN_USE, &wdt_status);
230 clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
235 static struct file_operations pnx4008_wdt_fops = {
236 .owner = THIS_MODULE,
238 .write = pnx4008_wdt_write,
239 .ioctl = pnx4008_wdt_ioctl,
240 .open = pnx4008_wdt_open,
241 .release = pnx4008_wdt_release,
244 static struct miscdevice pnx4008_wdt_miscdev = {
245 .minor = WATCHDOG_MINOR,
247 .fops = &pnx4008_wdt_fops,
250 static int pnx4008_wdt_probe(struct platform_device *pdev)
253 struct resource *res;
255 if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
256 heartbeat = DEFAULT_HEARTBEAT;
258 printk(KERN_INFO MODULE_NAME
259 "PNX4008 Watchdog Timer: heartbeat %d sec\n", heartbeat);
261 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
263 printk(KERN_INFO MODULE_NAME
264 "failed to get memory region resouce\n");
268 size = res->end - res->start + 1;
269 wdt_mem = request_mem_region(res->start, size, pdev->name);
271 if (wdt_mem == NULL) {
272 printk(KERN_INFO MODULE_NAME "failed to get memory region\n");
275 wdt_base = (void __iomem *)IO_ADDRESS(res->start);
277 wdt_clk = clk_get(&pdev->dev, "wdt_ck");
279 release_resource(wdt_mem);
283 clk_set_rate(wdt_clk, 1);
285 ret = misc_register(&pnx4008_wdt_miscdev);
287 printk(KERN_ERR MODULE_NAME "cannot register misc device\n");
288 release_resource(wdt_mem);
290 clk_set_rate(wdt_clk, 0);
292 boot_status = (__raw_readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ?
294 wdt_disable(); /*disable for now */
295 set_bit(WDT_DEVICE_INITED, &wdt_status);
302 static int pnx4008_wdt_remove(struct platform_device *pdev)
305 release_resource(wdt_mem);
310 clk_set_rate(wdt_clk, 0);
314 misc_deregister(&pnx4008_wdt_miscdev);
318 static struct platform_driver platform_wdt_driver = {
322 .probe = pnx4008_wdt_probe,
323 .remove = pnx4008_wdt_remove,
326 static int __init pnx4008_wdt_init(void)
328 return platform_driver_register(&platform_wdt_driver);
331 static void __exit pnx4008_wdt_exit(void)
333 return platform_driver_unregister(&platform_wdt_driver);
336 module_init(pnx4008_wdt_init);
337 module_exit(pnx4008_wdt_exit);
339 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
340 MODULE_DESCRIPTION("PNX4008 Watchdog Driver");
342 module_param(heartbeat, int, 0);
343 MODULE_PARM_DESC(heartbeat,
344 "Watchdog heartbeat period in seconds from 1 to "
345 __MODULE_STRING(MAX_HEARTBEAT) ", default "
346 __MODULE_STRING(DEFAULT_HEARTBEAT));
348 module_param(nowayout, int, 0);
349 MODULE_PARM_DESC(nowayout,
350 "Set to 1 to keep watchdog running after device release");
352 MODULE_LICENSE("GPL");
353 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);