drivers/char/agp/intel-gtt.c

   1 /*
   2  * Intel GTT (Graphics Translation Table) routines
   3  *
   4  * Caveat: This driver implements the linux agp interface, but this is far from
   5  * a agp driver! GTT support ended up here for purely historical reasons: The
   6  * old userspace intel graphics drivers needed an interface to map memory into
   7  * the GTT. And the drm provides a default interface for graphic devices sitting
   8  * on an agp port. So it made sense to fake the GTT support as an agp port to
   9  * avoid having to create a new api.
  10  *
  11  * With gem this does not make much sense anymore, just needlessly complicates
  12  * the code. But as long as the old graphics stack is still support, it's stuck
  13  * here.
  14  *
  15  * /fairy-tale-mode off
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/pci.h>
  20 #include <linux/init.h>
  21 #include <linux/kernel.h>
  22 #include <linux/pagemap.h>
  23 #include <linux/agp_backend.h>
  24 #include <asm/smp.h>
  25 #include "agp.h"
  26 #include "intel-agp.h"
  27 #include <linux/intel-gtt.h>
  28 #include <drm/intel-gtt.h>
  29
  30 /*
  31  * If we have Intel graphics, we're not going to have anything other than
  32  * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
  33  * on the Intel IOMMU support (CONFIG_DMAR).
  34  * Only newer chipsets need to bother with this, of course.
  35  */
  36 #ifdef CONFIG_DMAR
  37 #define USE_PCI_DMA_API 1
  38 #else
  39 #define USE_PCI_DMA_API 0
  40 #endif
  41
  42 /* Max amount of stolen space, anything above will be returned to Linux */
  43 int intel_max_stolen = 32 * 1024 * 1024;
  44 EXPORT_SYMBOL(intel_max_stolen);
  45
  46 static const struct aper_size_info_fixed intel_i810_sizes[] =
  47 {
  48         {64, 16384, 4},
  49         /* The 32M mode still requires a 64k gatt */
  50         {32, 8192, 4}
  51 };
  52
  53 #define AGP_DCACHE_MEMORY       1
  54 #define AGP_PHYS_MEMORY         2
  55 #define INTEL_AGP_CACHED_MEMORY 3
  56
  57 static struct gatt_mask intel_i810_masks[] =
  58 {
  59         {.mask = I810_PTE_VALID, .type = 0},
  60         {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
  61         {.mask = I810_PTE_VALID, .type = 0},
  62         {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
  63          .type = INTEL_AGP_CACHED_MEMORY}
  64 };
  65
  66 #define INTEL_AGP_UNCACHED_MEMORY              0
  67 #define INTEL_AGP_CACHED_MEMORY_LLC            1
  68 #define INTEL_AGP_CACHED_MEMORY_LLC_GFDT       2
  69 #define INTEL_AGP_CACHED_MEMORY_LLC_MLC        3
  70 #define INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT   4
  71
  72 static struct gatt_mask intel_gen6_masks[] =
  73 {
  74         {.mask = I810_PTE_VALID | GEN6_PTE_UNCACHED,
  75          .type = INTEL_AGP_UNCACHED_MEMORY },
  76         {.mask = I810_PTE_VALID | GEN6_PTE_LLC,
  77          .type = INTEL_AGP_CACHED_MEMORY_LLC },
  78         {.mask = I810_PTE_VALID | GEN6_PTE_LLC | GEN6_PTE_GFDT,
  79          .type = INTEL_AGP_CACHED_MEMORY_LLC_GFDT },
  80         {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC,
  81          .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC },
  82         {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC | GEN6_PTE_GFDT,
  83          .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT },
  84 };
  85
  86 struct intel_gtt_driver {
  87         unsigned int gen : 8;
  88         unsigned int is_g33 : 1;
  89         unsigned int is_pineview : 1;
  90         unsigned int is_ironlake : 1;
  91         /* Chipset specific GTT setup */
  92         int (*setup)(void);
  93         void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
  94         /* Flags is a more or less chipset specific opaque value.
  95          * For chipsets that need to support old ums (non-gem) code, this
  96          * needs to be identical to the various supported agp memory types! */
  97         bool (*check_flags)(unsigned int flags);
  98 };
  99
 100 static struct _intel_private {
 101         struct intel_gtt base;
 102         const struct intel_gtt_driver *driver;
 103         struct pci_dev *pcidev; /* device one */
 104         struct pci_dev *bridge_dev;
 105         u8 __iomem *registers;
 106         phys_addr_t gtt_bus_addr;
 107         phys_addr_t gma_bus_addr;
 108         phys_addr_t pte_bus_addr;
 109         u32 __iomem *gtt;               /* I915G */
 110         int num_dcache_entries;
 111         union {
 112                 void __iomem *i9xx_flush_page;
 113                 void *i8xx_flush_page;
 114         };
 115         struct page *i8xx_page;
 116         struct resource ifp_resource;
 117         int resource_valid;
 118         struct page *scratch_page;
 119         dma_addr_t scratch_page_dma;
 120 } intel_private;
 121
 122 #define INTEL_GTT_GEN   intel_private.driver->gen
 123 #define IS_G33          intel_private.driver->is_g33
 124 #define IS_PINEVIEW     intel_private.driver->is_pineview
 125 #define IS_IRONLAKE     intel_private.driver->is_ironlake
 126
 127 static void intel_agp_free_sglist(struct agp_memory *mem)
 128 {
 129         struct sg_table st;
 130
 131         st.sgl = mem->sg_list;
 132         st.orig_nents = st.nents = mem->page_count;
 133
 134         sg_free_table(&st);
 135
 136         mem->sg_list = NULL;
 137         mem->num_sg = 0;
 138 }
 139
 140 static int intel_agp_map_memory(struct agp_memory *mem)
 141 {
 142         struct sg_table st;
 143         struct scatterlist *sg;
 144         int i;
 145
 146         if (mem->sg_list)
 147                 return 0; /* already mapped (for e.g. resume */
 148
 149         DBG("try mapping %lu pages\n", (unsigned long)mem->page_count);
 150
 151         if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL))
 152                 goto err;
 153
 154         mem->sg_list = sg = st.sgl;
 155
 156         for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg))
 157                 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0);
 158
 159         mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list,
 160                                  mem->page_count, PCI_DMA_BIDIRECTIONAL);
 161         if (unlikely(!mem->num_sg))
 162                 goto err;
 163
 164         return 0;
 165
 166 err:
 167         sg_free_table(&st);
 168         return -ENOMEM;
 169 }
 170
 171 static void intel_agp_unmap_memory(struct agp_memory *mem)
 172 {
 173         DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
 174
 175         pci_unmap_sg(intel_private.pcidev, mem->sg_list,
 176                      mem->page_count, PCI_DMA_BIDIRECTIONAL);
 177         intel_agp_free_sglist(mem);
 178 }
 179
 180 #if USE_PCI_DMA_API
 181 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
 182                                         off_t pg_start, int mask_type)
 183 {
 184         struct scatterlist *sg;
 185         int i, j;
 186
 187         j = pg_start;
 188
 189         WARN_ON(!mem->num_sg);
 190
 191         if (mem->num_sg == mem->page_count) {
 192                 for_each_sg(mem->sg_list, sg, mem->page_count, i) {
 193                         writel(agp_bridge->driver->mask_memory(agp_bridge,
 194                                         sg_dma_address(sg), mask_type),
 195                                         intel_private.gtt+j);
 196                         j++;
 197                 }
 198         } else {
 199                 /* sg may merge pages, but we have to separate
 200                  * per-page addr for GTT */
 201                 unsigned int len, m;
 202
 203                 for_each_sg(mem->sg_list, sg, mem->num_sg, i) {
 204                         len = sg_dma_len(sg) / PAGE_SIZE;
 205                         for (m = 0; m < len; m++) {
 206                                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 207                                                                        sg_dma_address(sg) + m * PAGE_SIZE,
 208                                                                        mask_type),
 209                                        intel_private.gtt+j);
 210                                 j++;
 211                         }
 212                 }
 213         }
 214         readl(intel_private.gtt+j-1);
 215 }
 216
 217 #else
 218
 219 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
 220                                         off_t pg_start, int mask_type)
 221 {
 222         int i, j;
 223
 224         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 225                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 226                                 page_to_phys(mem->pages[i]), mask_type),
 227                        intel_private.gtt+j);
 228         }
 229
 230         readl(intel_private.gtt+j-1);
 231 }
 232
 233 #endif
 234
 235 static int intel_i810_fetch_size(void)
 236 {
 237         u32 smram_miscc;
 238         struct aper_size_info_fixed *values;
 239
 240         pci_read_config_dword(intel_private.bridge_dev,
 241                               I810_SMRAM_MISCC, &smram_miscc);
 242         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 243
 244         if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
 245                 dev_warn(&intel_private.bridge_dev->dev, "i810 is disabled\n");
 246                 return 0;
 247         }
 248         if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
 249                 agp_bridge->current_size = (void *) (values + 1);
 250                 agp_bridge->aperture_size_idx = 1;
 251                 return values[1].size;
 252         } else {
 253                 agp_bridge->current_size = (void *) (values);
 254                 agp_bridge->aperture_size_idx = 0;
 255                 return values[0].size;
 256         }
 257
 258         return 0;
 259 }
 260
 261 static int intel_i810_configure(void)
 262 {
 263         struct aper_size_info_fixed *current_size;
 264         u32 temp;
 265         int i;
 266
 267         current_size = A_SIZE_FIX(agp_bridge->current_size);
 268
 269         if (!intel_private.registers) {
 270                 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 271                 temp &= 0xfff80000;
 272
 273                 intel_private.registers = ioremap(temp, 128 * 4096);
 274                 if (!intel_private.registers) {
 275                         dev_err(&intel_private.pcidev->dev,
 276                                 "can't remap memory\n");
 277                         return -ENOMEM;
 278                 }
 279         }
 280
 281         if ((readl(intel_private.registers+I810_DRAM_CTL)
 282                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 283                 /* This will need to be dynamically assigned */
 284                 dev_info(&intel_private.pcidev->dev,
 285                          "detected 4MB dedicated video ram\n");
 286                 intel_private.num_dcache_entries = 1024;
 287         }
 288         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 289         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 290         writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 291         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 292
 293         if (agp_bridge->driver->needs_scratch_page) {
 294                 for (i = 0; i < current_size->num_entries; i++) {
 295                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 296                 }
 297                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
 298         }
 299         global_cache_flush();
 300         return 0;
 301 }
 302
 303 static void intel_i810_cleanup(void)
 304 {
 305         writel(0, intel_private.registers+I810_PGETBL_CTL);
 306         readl(intel_private.registers); /* PCI Posting. */
 307         iounmap(intel_private.registers);
 308 }
 309
 310 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 311 {
 312         return;
 313 }
 314
 315 /* Exists to support ARGB cursors */
 316 static struct page *i8xx_alloc_pages(void)
 317 {
 318         struct page *page;
 319
 320         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
 321         if (page == NULL)
 322                 return NULL;
 323
 324         if (set_pages_uc(page, 4) < 0) {
 325                 set_pages_wb(page, 4);
 326                 __free_pages(page, 2);
 327                 return NULL;
 328         }
 329         get_page(page);
 330         atomic_inc(&agp_bridge->current_memory_agp);
 331         return page;
 332 }
 333
 334 static void i8xx_destroy_pages(struct page *page)
 335 {
 336         if (page == NULL)
 337                 return;
 338
 339         set_pages_wb(page, 4);
 340         put_page(page);
 341         __free_pages(page, 2);
 342         atomic_dec(&agp_bridge->current_memory_agp);
 343 }
 344
 345 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
 346                                         int type)
 347 {
 348         if (type < AGP_USER_TYPES)
 349                 return type;
 350         else if (type == AGP_USER_CACHED_MEMORY)
 351                 return INTEL_AGP_CACHED_MEMORY;
 352         else
 353                 return 0;
 354 }
 355
 356 static int intel_gen6_type_to_mask_type(struct agp_bridge_data *bridge,
 357                                         int type)
 358 {
 359         unsigned int type_mask = type & ~AGP_USER_CACHED_MEMORY_GFDT;
 360         unsigned int gfdt = type & AGP_USER_CACHED_MEMORY_GFDT;
 361
 362         if (type_mask == AGP_USER_UNCACHED_MEMORY)
 363                 return INTEL_AGP_UNCACHED_MEMORY;
 364         else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC)
 365                 return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT :
 366                               INTEL_AGP_CACHED_MEMORY_LLC_MLC;
 367         else /* set 'normal'/'cached' to LLC by default */
 368                 return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_GFDT :
 369                               INTEL_AGP_CACHED_MEMORY_LLC;
 370 }
 371
 372
 373 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
 374                                 int type)
 375 {
 376         int i, j, num_entries;
 377         void *temp;
 378         int ret = -EINVAL;
 379         int mask_type;
 380
 381         if (mem->page_count == 0)
 382                 goto out;
 383
 384         temp = agp_bridge->current_size;
 385         num_entries = A_SIZE_FIX(temp)->num_entries;
 386
 387         if ((pg_start + mem->page_count) > num_entries)
 388                 goto out_err;
 389
 390
 391         for (j = pg_start; j < (pg_start + mem->page_count); j++) {
 392                 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
 393                         ret = -EBUSY;
 394                         goto out_err;
 395                 }
 396         }
 397
 398         if (type != mem->type)
 399                 goto out_err;
 400
 401         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 402
 403         switch (mask_type) {
 404         case AGP_DCACHE_MEMORY:
 405                 if (!mem->is_flushed)
 406                         global_cache_flush();
 407                 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 408                         writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
 409                                intel_private.registers+I810_PTE_BASE+(i*4));
 410                 }
 411                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 412                 break;
 413         case AGP_PHYS_MEMORY:
 414         case AGP_NORMAL_MEMORY:
 415                 if (!mem->is_flushed)
 416                         global_cache_flush();
 417                 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 418                         writel(agp_bridge->driver->mask_memory(agp_bridge,
 419                                         page_to_phys(mem->pages[i]), mask_type),
 420                                intel_private.registers+I810_PTE_BASE+(j*4));
 421                 }
 422                 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 423                 break;
 424         default:
 425                 goto out_err;
 426         }
 427
 428 out:
 429         ret = 0;
 430 out_err:
 431         mem->is_flushed = true;
 432         return ret;
 433 }
 434
 435 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
 436                                 int type)
 437 {
 438         int i;
 439
 440         if (mem->page_count == 0)
 441                 return 0;
 442
 443         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 444                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 445         }
 446         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 447
 448         return 0;
 449 }
 450
 451 /*
 452  * The i810/i830 requires a physical address to program its mouse
 453  * pointer into hardware.
 454  * However the Xserver still writes to it through the agp aperture.
 455  */
 456 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
 457 {
 458         struct agp_memory *new;
 459         struct page *page;
 460
 461         switch (pg_count) {
 462         case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
 463                 break;
 464         case 4:
 465                 /* kludge to get 4 physical pages for ARGB cursor */
 466                 page = i8xx_alloc_pages();
 467                 break;
 468         default:
 469                 return NULL;
 470         }
 471
 472         if (page == NULL)
 473                 return NULL;
 474
 475         new = agp_create_memory(pg_count);
 476         if (new == NULL)
 477                 return NULL;
 478
 479         new->pages[0] = page;
 480         if (pg_count == 4) {
 481                 /* kludge to get 4 physical pages for ARGB cursor */
 482                 new->pages[1] = new->pages[0] + 1;
 483                 new->pages[2] = new->pages[1] + 1;
 484                 new->pages[3] = new->pages[2] + 1;
 485         }
 486         new->page_count = pg_count;
 487         new->num_scratch_pages = pg_count;
 488         new->type = AGP_PHYS_MEMORY;
 489         new->physical = page_to_phys(new->pages[0]);
 490         return new;
 491 }
 492
 493 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
 494 {
 495         struct agp_memory *new;
 496
 497         if (type == AGP_DCACHE_MEMORY) {
 498                 if (pg_count != intel_private.num_dcache_entries)
 499                         return NULL;
 500
 501                 new = agp_create_memory(1);
 502                 if (new == NULL)
 503                         return NULL;
 504
 505                 new->type = AGP_DCACHE_MEMORY;
 506                 new->page_count = pg_count;
 507                 new->num_scratch_pages = 0;
 508                 agp_free_page_array(new);
 509                 return new;
 510         }
 511         if (type == AGP_PHYS_MEMORY)
 512                 return alloc_agpphysmem_i8xx(pg_count, type);
 513         return NULL;
 514 }
 515
 516 static void intel_i810_free_by_type(struct agp_memory *curr)
 517 {
 518         agp_free_key(curr->key);
 519         if (curr->type == AGP_PHYS_MEMORY) {
 520                 if (curr->page_count == 4)
 521                         i8xx_destroy_pages(curr->pages[0]);
 522                 else {
 523                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 524                                                              AGP_PAGE_DESTROY_UNMAP);
 525                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 526                                                              AGP_PAGE_DESTROY_FREE);
 527                 }
 528                 agp_free_page_array(curr);
 529         }
 530         kfree(curr);
 531 }
 532
 533 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
 534                                             dma_addr_t addr, int type)
 535 {
 536         /* Type checking must be done elsewhere */
 537         return addr | bridge->driver->masks[type].mask;
 538 }
 539
 540 static int intel_gtt_setup_scratch_page(void)
 541 {
 542         struct page *page;
 543         dma_addr_t dma_addr;
 544
 545         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
 546         if (page == NULL)
 547                 return -ENOMEM;
 548         get_page(page);
 549         set_pages_uc(page, 1);
 550
 551         if (USE_PCI_DMA_API && INTEL_GTT_GEN > 2) {
 552                 dma_addr = pci_map_page(intel_private.pcidev, page, 0,
 553                                     PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 554                 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr))
 555                         return -EINVAL;
 556
 557                 intel_private.scratch_page_dma = dma_addr;
 558         } else
 559                 intel_private.scratch_page_dma = page_to_phys(page);
 560
 561         intel_private.scratch_page = page;
 562
 563         return 0;
 564 }
 565
 566 static const struct aper_size_info_fixed const intel_fake_agp_sizes[] = {
 567         {128, 32768, 5},
 568         /* The 64M mode still requires a 128k gatt */
 569         {64, 16384, 5},
 570         {256, 65536, 6},
 571         {512, 131072, 7},
 572 };
 573
 574 static unsigned int intel_gtt_stolen_entries(void)
 575 {
 576         u16 gmch_ctrl;
 577         u8 rdct;
 578         int local = 0;
 579         static const int ddt[4] = { 0, 16, 32, 64 };
 580         unsigned int overhead_entries, stolen_entries;
 581         unsigned int stolen_size = 0;
 582
 583         pci_read_config_word(intel_private.bridge_dev,
 584                              I830_GMCH_CTRL, &gmch_ctrl);
 585
 586         if (INTEL_GTT_GEN > 4 || IS_PINEVIEW)
 587                 overhead_entries = 0;
 588         else
 589                 overhead_entries = intel_private.base.gtt_mappable_entries
 590                         / 1024;
 591
 592         overhead_entries += 1; /* BIOS popup */
 593
 594         if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
 595             intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
 596                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 597                 case I830_GMCH_GMS_STOLEN_512:
 598                         stolen_size = KB(512);
 599                         break;
 600                 case I830_GMCH_GMS_STOLEN_1024:
 601                         stolen_size = MB(1);
 602                         break;
 603                 case I830_GMCH_GMS_STOLEN_8192:
 604                         stolen_size = MB(8);
 605                         break;
 606                 case I830_GMCH_GMS_LOCAL:
 607                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
 608                         stolen_size = (I830_RDRAM_ND(rdct) + 1) *
 609                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
 610                         local = 1;
 611                         break;
 612                 default:
 613                         stolen_size = 0;
 614                         break;
 615                 }
 616         } else if (INTEL_GTT_GEN == 6) {
 617                 /*
 618                  * SandyBridge has new memory control reg at 0x50.w
 619                  */
 620                 u16 snb_gmch_ctl;
 621                 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 622                 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) {
 623                 case SNB_GMCH_GMS_STOLEN_32M:
 624                         stolen_size = MB(32);
 625                         break;
 626                 case SNB_GMCH_GMS_STOLEN_64M:
 627                         stolen_size = MB(64);
 628                         break;
 629                 case SNB_GMCH_GMS_STOLEN_96M:
 630                         stolen_size = MB(96);
 631                         break;
 632                 case SNB_GMCH_GMS_STOLEN_128M:
 633                         stolen_size = MB(128);
 634                         break;
 635                 case SNB_GMCH_GMS_STOLEN_160M:
 636                         stolen_size = MB(160);
 637                         break;
 638                 case SNB_GMCH_GMS_STOLEN_192M:
 639                         stolen_size = MB(192);
 640                         break;
 641                 case SNB_GMCH_GMS_STOLEN_224M:
 642                         stolen_size = MB(224);
 643                         break;
 644                 case SNB_GMCH_GMS_STOLEN_256M:
 645                         stolen_size = MB(256);
 646                         break;
 647                 case SNB_GMCH_GMS_STOLEN_288M:
 648                         stolen_size = MB(288);
 649                         break;
 650                 case SNB_GMCH_GMS_STOLEN_320M:
 651                         stolen_size = MB(320);
 652                         break;
 653                 case SNB_GMCH_GMS_STOLEN_352M:
 654                         stolen_size = MB(352);
 655                         break;
 656                 case SNB_GMCH_GMS_STOLEN_384M:
 657                         stolen_size = MB(384);
 658                         break;
 659                 case SNB_GMCH_GMS_STOLEN_416M:
 660                         stolen_size = MB(416);
 661                         break;
 662                 case SNB_GMCH_GMS_STOLEN_448M:
 663                         stolen_size = MB(448);
 664                         break;
 665                 case SNB_GMCH_GMS_STOLEN_480M:
 666                         stolen_size = MB(480);
 667                         break;
 668                 case SNB_GMCH_GMS_STOLEN_512M:
 669                         stolen_size = MB(512);
 670                         break;
 671                 }
 672         } else {
 673                 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
 674                 case I855_GMCH_GMS_STOLEN_1M:
 675                         stolen_size = MB(1);
 676                         break;
 677                 case I855_GMCH_GMS_STOLEN_4M:
 678                         stolen_size = MB(4);
 679                         break;
 680                 case I855_GMCH_GMS_STOLEN_8M:
 681                         stolen_size = MB(8);
 682                         break;
 683                 case I855_GMCH_GMS_STOLEN_16M:
 684                         stolen_size = MB(16);
 685                         break;
 686                 case I855_GMCH_GMS_STOLEN_32M:
 687                         stolen_size = MB(32);
 688                         break;
 689                 case I915_GMCH_GMS_STOLEN_48M:
 690                         stolen_size = MB(48);
 691                         break;
 692                 case I915_GMCH_GMS_STOLEN_64M:
 693                         stolen_size = MB(64);
 694                         break;
 695                 case G33_GMCH_GMS_STOLEN_128M:
 696                         stolen_size = MB(128);
 697                         break;
 698                 case G33_GMCH_GMS_STOLEN_256M:
 699                         stolen_size = MB(256);
 700                         break;
 701                 case INTEL_GMCH_GMS_STOLEN_96M:
 702                         stolen_size = MB(96);
 703                         break;
 704                 case INTEL_GMCH_GMS_STOLEN_160M:
 705                         stolen_size = MB(160);
 706                         break;
 707                 case INTEL_GMCH_GMS_STOLEN_224M:
 708                         stolen_size = MB(224);
 709                         break;
 710                 case INTEL_GMCH_GMS_STOLEN_352M:
 711                         stolen_size = MB(352);
 712                         break;
 713                 default:
 714                         stolen_size = 0;
 715                         break;
 716                 }
 717         }
 718
 719         if (!local && stolen_size > intel_max_stolen) {
 720                 dev_info(&intel_private.bridge_dev->dev,
 721                          "detected %dK stolen memory, trimming to %dK\n",
 722                          stolen_size / KB(1), intel_max_stolen / KB(1));
 723                 stolen_size = intel_max_stolen;
 724         } else if (stolen_size > 0) {
 725                 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
 726                        stolen_size / KB(1), local ? "local" : "stolen");
 727         } else {
 728                 dev_info(&intel_private.bridge_dev->dev,
 729                        "no pre-allocated video memory detected\n");
 730                 stolen_size = 0;
 731         }
 732
 733         stolen_entries = stolen_size/KB(4) - overhead_entries;
 734
 735         return stolen_entries;
 736 }
 737
 738 static unsigned int intel_gtt_total_entries(void)
 739 {
 740         int size;
 741
 742         if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) {
 743                 u32 pgetbl_ctl;
 744                 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 745
 746                 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
 747                 case I965_PGETBL_SIZE_128KB:
 748                         size = KB(128);
 749                         break;
 750                 case I965_PGETBL_SIZE_256KB:
 751                         size = KB(256);
 752                         break;
 753                 case I965_PGETBL_SIZE_512KB:
 754                         size = KB(512);
 755                         break;
 756                 case I965_PGETBL_SIZE_1MB:
 757                         size = KB(1024);
 758                         break;
 759                 case I965_PGETBL_SIZE_2MB:
 760                         size = KB(2048);
 761                         break;
 762                 case I965_PGETBL_SIZE_1_5MB:
 763                         size = KB(1024 + 512);
 764                         break;
 765                 default:
 766                         dev_info(&intel_private.pcidev->dev,
 767                                  "unknown page table size, assuming 512KB\n");
 768                         size = KB(512);
 769                 }
 770
 771                 return size/4;
 772         } else if (INTEL_GTT_GEN == 6) {
 773                 u16 snb_gmch_ctl;
 774
 775                 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 776                 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
 777                 default:
 778                 case SNB_GTT_SIZE_0M:
 779                         printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
 780                         size = MB(0);
 781                         break;
 782                 case SNB_GTT_SIZE_1M:
 783                         size = MB(1);
 784                         break;
 785                 case SNB_GTT_SIZE_2M:
 786                         size = MB(2);
 787                         break;
 788                 }
 789                 return size/4;
 790         } else {
 791                 /* On previous hardware, the GTT size was just what was
 792                  * required to map the aperture.
 793                  */
 794                 return intel_private.base.gtt_mappable_entries;
 795         }
 796 }
 797
 798 static unsigned int intel_gtt_mappable_entries(void)
 799 {
 800         unsigned int aperture_size;
 801
 802         if (INTEL_GTT_GEN == 2) {
 803                 u16 gmch_ctrl;
 804
 805                 pci_read_config_word(intel_private.bridge_dev,
 806                                      I830_GMCH_CTRL, &gmch_ctrl);
 807
 808                 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
 809                         aperture_size = MB(64);
 810                 else
 811                         aperture_size = MB(128);
 812         } else {
 813                 /* 9xx supports large sizes, just look at the length */
 814                 aperture_size = pci_resource_len(intel_private.pcidev, 2);
 815         }
 816
 817         return aperture_size >> PAGE_SHIFT;
 818 }
 819
 820 static void intel_gtt_teardown_scratch_page(void)
 821 {
 822         set_pages_wb(intel_private.scratch_page, 1);
 823         pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma,
 824                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 825         put_page(intel_private.scratch_page);
 826         __free_page(intel_private.scratch_page);
 827 }
 828
 829 static void intel_gtt_cleanup(void)
 830 {
 831         if (intel_private.i9xx_flush_page)
 832                 iounmap(intel_private.i9xx_flush_page);
 833         if (intel_private.resource_valid)
 834                 release_resource(&intel_private.ifp_resource);
 835         intel_private.ifp_resource.start = 0;
 836         intel_private.resource_valid = 0;
 837         iounmap(intel_private.gtt);
 838         iounmap(intel_private.registers);
 839
 840         intel_gtt_teardown_scratch_page();
 841 }
 842
 843 static int intel_gtt_init(void)
 844 {
 845         u32 gtt_map_size;
 846         int ret;
 847
 848         ret = intel_private.driver->setup();
 849         if (ret != 0)
 850                 return ret;
 851
 852         intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries();
 853         intel_private.base.gtt_total_entries = intel_gtt_total_entries();
 854
 855         gtt_map_size = intel_private.base.gtt_total_entries * 4;
 856
 857         intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
 858                                     gtt_map_size);
 859         if (!intel_private.gtt) {
 860                 iounmap(intel_private.registers);
 861                 return -ENOMEM;
 862         }
 863
 864         global_cache_flush();   /* FIXME: ? */
 865
 866         /* we have to call this as early as possible after the MMIO base address is known */
 867         intel_private.base.gtt_stolen_entries = intel_gtt_stolen_entries();
 868         if (intel_private.base.gtt_stolen_entries == 0) {
 869                 iounmap(intel_private.registers);
 870                 iounmap(intel_private.gtt);
 871                 return -ENOMEM;
 872         }
 873
 874         ret = intel_gtt_setup_scratch_page();
 875         if (ret != 0) {
 876                 intel_gtt_cleanup();
 877                 return ret;
 878         }
 879
 880         return 0;
 881 }
 882
 883 static int intel_fake_agp_fetch_size(void)
 884 {
 885         int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
 886         unsigned int aper_size;
 887         int i;
 888
 889         aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT)
 890                     / MB(1);
 891
 892         for (i = 0; i < num_sizes; i++) {
 893                 if (aper_size == intel_fake_agp_sizes[i].size) {
 894                         agp_bridge->current_size =
 895                                 (void *) (intel_fake_agp_sizes + i);
 896                         return aper_size;
 897                 }
 898         }
 899
 900         return 0;
 901 }
 902
 903 static void intel_i830_fini_flush(void)
 904 {
 905         kunmap(intel_private.i8xx_page);
 906         intel_private.i8xx_flush_page = NULL;
 907         unmap_page_from_agp(intel_private.i8xx_page);
 908
 909         __free_page(intel_private.i8xx_page);
 910         intel_private.i8xx_page = NULL;
 911 }
 912
 913 static void intel_i830_setup_flush(void)
 914 {
 915         /* return if we've already set the flush mechanism up */
 916         if (intel_private.i8xx_page)
 917                 return;
 918
 919         intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
 920         if (!intel_private.i8xx_page)
 921                 return;
 922
 923         intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
 924         if (!intel_private.i8xx_flush_page)
 925                 intel_i830_fini_flush();
 926 }
 927
 928 /* The chipset_flush interface needs to get data that has already been
 929  * flushed out of the CPU all the way out to main memory, because the GPU
 930  * doesn't snoop those buffers.
 931  *
 932  * The 8xx series doesn't have the same lovely interface for flushing the
 933  * chipset write buffers that the later chips do. According to the 865
 934  * specs, it's 64 octwords, or 1KB.  So, to get those previous things in
 935  * that buffer out, we just fill 1KB and clflush it out, on the assumption
 936  * that it'll push whatever was in there out.  It appears to work.
 937  */
 938 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
 939 {
 940         unsigned int *pg = intel_private.i8xx_flush_page;
 941
 942         memset(pg, 0, 1024);
 943
 944         if (cpu_has_clflush)
 945                 clflush_cache_range(pg, 1024);
 946         else if (wbinvd_on_all_cpus() != 0)
 947                 printk(KERN_ERR "Timed out waiting for cache flush.\n");
 948 }
 949
 950 static void i830_write_entry(dma_addr_t addr, unsigned int entry,
 951                              unsigned int flags)
 952 {
 953         u32 pte_flags = I810_PTE_VALID;
 954
 955         switch (flags) {
 956         case AGP_DCACHE_MEMORY:
 957                 pte_flags |= I810_PTE_LOCAL;
 958                 break;
 959         case AGP_USER_CACHED_MEMORY:
 960                 pte_flags |= I830_PTE_SYSTEM_CACHED;
 961                 break;
 962         }
 963
 964         writel(addr | pte_flags, intel_private.gtt + entry);
 965 }
 966
 967 static void intel_enable_gtt(void)
 968 {
 969         u32 gma_addr;
 970         u16 gmch_ctrl;
 971
 972         if (INTEL_GTT_GEN == 2)
 973                 pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
 974                                       &gma_addr);
 975         else
 976                 pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
 977                                       &gma_addr);
 978
 979         intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
 980
 981         pci_read_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, &gmch_ctrl);
 982         gmch_ctrl |= I830_GMCH_ENABLED;
 983         pci_write_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, gmch_ctrl);
 984
 985         writel(intel_private.pte_bus_addr|I810_PGETBL_ENABLED,
 986                intel_private.registers+I810_PGETBL_CTL);
 987         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 988 }
 989
 990 static int i830_setup(void)
 991 {
 992         u32 reg_addr;
 993
 994         pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
 995         reg_addr &= 0xfff80000;
 996
 997         intel_private.registers = ioremap(reg_addr, KB(64));
 998         if (!intel_private.registers)
 999                 return -ENOMEM;
1000
1001         intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
1002         intel_private.pte_bus_addr =
1003                 readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1004
1005         intel_i830_setup_flush();
1006
1007         return 0;
1008 }
1009
1010 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
1011 {
1012         agp_bridge->gatt_table_real = NULL;
1013         agp_bridge->gatt_table = NULL;
1014         agp_bridge->gatt_bus_addr = 0;
1015
1016         return 0;
1017 }
1018
1019 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
1020 {
1021         return 0;
1022 }
1023
1024 static int intel_fake_agp_configure(void)
1025 {
1026         int i;
1027
1028         intel_enable_gtt();
1029
1030         agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
1031
1032         for (i = intel_private.base.gtt_stolen_entries;
1033                         i < intel_private.base.gtt_total_entries; i++) {
1034                 intel_private.driver->write_entry(intel_private.scratch_page_dma,
1035                                                   i, 0);
1036         }
1037         readl(intel_private.gtt+i-1);   /* PCI Posting. */
1038
1039         global_cache_flush();
1040
1041         return 0;
1042 }
1043
1044 static bool i830_check_flags(unsigned int flags)
1045 {
1046         switch (flags) {
1047         case 0:
1048         case AGP_PHYS_MEMORY:
1049         case AGP_USER_CACHED_MEMORY:
1050         case AGP_USER_MEMORY:
1051                 return true;
1052         }
1053
1054         return false;
1055 }
1056
1057 static void intel_gtt_insert_sg_entries(struct scatterlist *sg_list,
1058                                         unsigned int sg_len,
1059                                         unsigned int pg_start,
1060                                         unsigned int flags)
1061 {
1062         struct scatterlist *sg;
1063         unsigned int len, m;
1064         int i, j;
1065
1066         j = pg_start;
1067
1068         /* sg may merge pages, but we have to separate
1069          * per-page addr for GTT */
1070         for_each_sg(sg_list, sg, sg_len, i) {
1071                 len = sg_dma_len(sg) >> PAGE_SHIFT;
1072                 for (m = 0; m < len; m++) {
1073                         dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
1074                         intel_private.driver->write_entry(addr,
1075                                                           j, flags);
1076                         j++;
1077                 }
1078         }
1079         readl(intel_private.gtt+j-1);
1080 }
1081
1082 static int intel_fake_agp_insert_entries(struct agp_memory *mem,
1083                                          off_t pg_start, int type)
1084 {
1085         int i, j;
1086         int ret = -EINVAL;
1087
1088         if (mem->page_count == 0)
1089                 goto out;
1090
1091         if (pg_start < intel_private.base.gtt_stolen_entries) {
1092                 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1093                            "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
1094                            pg_start, intel_private.base.gtt_stolen_entries);
1095
1096                 dev_info(&intel_private.pcidev->dev,
1097                          "trying to insert into local/stolen memory\n");
1098                 goto out_err;
1099         }
1100
1101         if ((pg_start + mem->page_count) > intel_private.base.gtt_total_entries)
1102                 goto out_err;
1103
1104         if (type != mem->type)
1105                 goto out_err;
1106
1107         if (!intel_private.driver->check_flags(type))
1108                 goto out_err;
1109
1110         if (!mem->is_flushed)
1111                 global_cache_flush();
1112
1113         if (USE_PCI_DMA_API && INTEL_GTT_GEN > 2) {
1114                 ret = intel_agp_map_memory(mem);
1115                 if (ret != 0)
1116                         return ret;
1117
1118                 intel_gtt_insert_sg_entries(mem->sg_list, mem->num_sg,
1119                                             pg_start, type);
1120         } else {
1121                 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1122                         dma_addr_t addr = page_to_phys(mem->pages[i]);
1123                         intel_private.driver->write_entry(addr,
1124                                                           j, type);
1125                 }
1126                 readl(intel_private.gtt+j-1);
1127         }
1128
1129 out:
1130         ret = 0;
1131 out_err:
1132         mem->is_flushed = true;
1133         return ret;
1134 }
1135
1136 static int intel_fake_agp_remove_entries(struct agp_memory *mem,
1137                                          off_t pg_start, int type)
1138 {
1139         int i;
1140
1141         if (mem->page_count == 0)
1142                 return 0;
1143
1144         if (pg_start < intel_private.base.gtt_stolen_entries) {
1145                 dev_info(&intel_private.pcidev->dev,
1146                          "trying to disable local/stolen memory\n");
1147                 return -EINVAL;
1148         }
1149
1150         if (USE_PCI_DMA_API && INTEL_GTT_GEN > 2)
1151                 intel_agp_unmap_memory(mem);
1152
1153         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1154                 intel_private.driver->write_entry(intel_private.scratch_page_dma,
1155                                                   i, 0);
1156         }
1157         readl(intel_private.gtt+i-1);
1158
1159         return 0;
1160 }
1161
1162 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
1163                                                        int type)
1164 {
1165         if (type == AGP_PHYS_MEMORY)
1166                 return alloc_agpphysmem_i8xx(pg_count, type);
1167         /* always return NULL for other allocation types for now */
1168         return NULL;
1169 }
1170
1171 static int intel_alloc_chipset_flush_resource(void)
1172 {
1173         int ret;
1174         ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1175                                      PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1176                                      pcibios_align_resource, intel_private.bridge_dev);
1177
1178         return ret;
1179 }
1180
1181 static void intel_i915_setup_chipset_flush(void)
1182 {
1183         int ret;
1184         u32 temp;
1185
1186         pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1187         if (!(temp & 0x1)) {
1188                 intel_alloc_chipset_flush_resource();
1189                 intel_private.resource_valid = 1;
1190                 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1191         } else {
1192                 temp &= ~1;
1193
1194                 intel_private.resource_valid = 1;
1195                 intel_private.ifp_resource.start = temp;
1196                 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1197                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1198                 /* some BIOSes reserve this area in a pnp some don't */
1199                 if (ret)
1200                         intel_private.resource_valid = 0;
1201         }
1202 }
1203
1204 static void intel_i965_g33_setup_chipset_flush(void)
1205 {
1206         u32 temp_hi, temp_lo;
1207         int ret;
1208
1209         pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1210         pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1211
1212         if (!(temp_lo & 0x1)) {
1213
1214                 intel_alloc_chipset_flush_resource();
1215
1216                 intel_private.resource_valid = 1;
1217                 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1218                         upper_32_bits(intel_private.ifp_resource.start));
1219                 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1220         } else {
1221                 u64 l64;
1222
1223                 temp_lo &= ~0x1;
1224                 l64 = ((u64)temp_hi << 32) | temp_lo;
1225
1226                 intel_private.resource_valid = 1;
1227                 intel_private.ifp_resource.start = l64;
1228                 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1229                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1230                 /* some BIOSes reserve this area in a pnp some don't */
1231                 if (ret)
1232                         intel_private.resource_valid = 0;
1233         }
1234 }
1235
1236 static void intel_i9xx_setup_flush(void)
1237 {
1238         /* return if already configured */
1239         if (intel_private.ifp_resource.start)
1240                 return;
1241
1242         if (INTEL_GTT_GEN == 6)
1243                 return;
1244
1245         /* setup a resource for this object */
1246         intel_private.ifp_resource.name = "Intel Flush Page";
1247         intel_private.ifp_resource.flags = IORESOURCE_MEM;
1248
1249         /* Setup chipset flush for 915 */
1250         if (IS_G33 || INTEL_GTT_GEN >= 4) {
1251                 intel_i965_g33_setup_chipset_flush();
1252         } else {
1253                 intel_i915_setup_chipset_flush();
1254         }
1255
1256         if (intel_private.ifp_resource.start)
1257                 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1258         if (!intel_private.i9xx_flush_page)
1259                 dev_err(&intel_private.pcidev->dev,
1260                         "can't ioremap flush page - no chipset flushing\n");
1261 }
1262
1263 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1264 {
1265         if (intel_private.i9xx_flush_page)
1266                 writel(1, intel_private.i9xx_flush_page);
1267 }
1268
1269 static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1270                                      int type)
1271 {
1272         int num_entries;
1273         void *temp;
1274         int ret = -EINVAL;
1275         int mask_type;
1276
1277         if (mem->page_count == 0)
1278                 goto out;
1279
1280         temp = agp_bridge->current_size;
1281         num_entries = A_SIZE_FIX(temp)->num_entries;
1282
1283         if (pg_start < intel_private.base.gtt_stolen_entries) {
1284                 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1285                            "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
1286                            pg_start, intel_private.base.gtt_stolen_entries);
1287
1288                 dev_info(&intel_private.pcidev->dev,
1289                          "trying to insert into local/stolen memory\n");
1290                 goto out_err;
1291         }
1292
1293         if ((pg_start + mem->page_count) > num_entries)
1294                 goto out_err;
1295
1296         /* The i915 can't check the GTT for entries since it's read only;
1297          * depend on the caller to make the correct offset decisions.
1298          */
1299
1300         if (type != mem->type)
1301                 goto out_err;
1302
1303         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1304
1305         if (INTEL_GTT_GEN != 6 && mask_type != 0 &&
1306             mask_type != AGP_PHYS_MEMORY &&
1307             mask_type != INTEL_AGP_CACHED_MEMORY)
1308                 goto out_err;
1309
1310         if (!mem->is_flushed)
1311                 global_cache_flush();
1312
1313         intel_agp_insert_sg_entries(mem, pg_start, mask_type);
1314
1315  out:
1316         ret = 0;
1317  out_err:
1318         mem->is_flushed = true;
1319         return ret;
1320 }
1321
1322 static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1323                                      int type)
1324 {
1325         int i;
1326
1327         if (mem->page_count == 0)
1328                 return 0;
1329
1330         if (pg_start < intel_private.base.gtt_stolen_entries) {
1331                 dev_info(&intel_private.pcidev->dev,
1332                          "trying to disable local/stolen memory\n");
1333                 return -EINVAL;
1334         }
1335
1336         for (i = pg_start; i < (mem->page_count + pg_start); i++)
1337                 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1338
1339         readl(intel_private.gtt+i-1);
1340
1341         return 0;
1342 }
1343
1344 static void i965_write_entry(dma_addr_t addr, unsigned int entry,
1345                              unsigned int flags)
1346 {
1347         /* Shift high bits down */
1348         addr |= (addr >> 28) & 0xf0;
1349         writel(addr | I810_PTE_VALID, intel_private.gtt + entry);
1350 }
1351
1352 static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
1353                              unsigned int flags)
1354 {
1355         unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
1356         unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
1357         u32 pte_flags;
1358
1359         if (type_mask == AGP_USER_UNCACHED_MEMORY)
1360                 pte_flags = GEN6_PTE_UNCACHED;
1361         else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
1362                 pte_flags = GEN6_PTE_LLC;
1363                 if (gfdt)
1364                         pte_flags |= GEN6_PTE_GFDT;
1365         } else { /* set 'normal'/'cached' to LLC by default */
1366                 pte_flags = GEN6_PTE_LLC_MLC;
1367                 if (gfdt)
1368                         pte_flags |= GEN6_PTE_GFDT;
1369         }
1370
1371         /* gen6 has bit11-4 for physical addr bit39-32 */
1372         addr |= (addr >> 28) & 0xff0;
1373         writel(addr | pte_flags, intel_private.gtt + entry);
1374 }
1375
1376 static int i9xx_setup(void)
1377 {
1378         u32 reg_addr;
1379
1380         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
1381
1382         reg_addr &= 0xfff80000;
1383
1384         intel_private.registers = ioremap(reg_addr, 128 * 4096);
1385         if (!intel_private.registers)
1386                 return -ENOMEM;
1387
1388         if (INTEL_GTT_GEN == 3) {
1389                 u32 gtt_addr;
1390
1391                 pci_read_config_dword(intel_private.pcidev,
1392                                       I915_PTEADDR, &gtt_addr);
1393                 intel_private.gtt_bus_addr = gtt_addr;
1394         } else {
1395                 u32 gtt_offset;
1396
1397                 switch (INTEL_GTT_GEN) {
1398                 case 5:
1399                 case 6:
1400                         gtt_offset = MB(2);
1401                         break;
1402                 case 4:
1403                 default:
1404                         gtt_offset =  KB(512);
1405                         break;
1406                 }
1407                 intel_private.gtt_bus_addr = reg_addr + gtt_offset;
1408         }
1409
1410         intel_private.pte_bus_addr =
1411                 readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1412
1413         intel_i9xx_setup_flush();
1414
1415         return 0;
1416 }
1417
1418 /*
1419  * The i965 supports 36-bit physical addresses, but to keep
1420  * the format of the GTT the same, the bits that don't fit
1421  * in a 32-bit word are shifted down to bits 4..7.
1422  *
1423  * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1424  * is always zero on 32-bit architectures, so no need to make
1425  * this conditional.
1426  */
1427 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1428                                             dma_addr_t addr, int type)
1429 {
1430         /* Shift high bits down */
1431         addr |= (addr >> 28) & 0xf0;
1432
1433         /* Type checking must be done elsewhere */
1434         return addr | bridge->driver->masks[type].mask;
1435 }
1436
1437 static unsigned long intel_gen6_mask_memory(struct agp_bridge_data *bridge,
1438                                             dma_addr_t addr, int type)
1439 {
1440         /* gen6 has bit11-4 for physical addr bit39-32 */
1441         addr |= (addr >> 28) & 0xff0;
1442
1443         /* Type checking must be done elsewhere */
1444         return addr | bridge->driver->masks[type].mask;
1445 }
1446
1447 static const struct agp_bridge_driver intel_810_driver = {
1448         .owner                  = THIS_MODULE,
1449         .aperture_sizes         = intel_i810_sizes,
1450         .size_type              = FIXED_APER_SIZE,
1451         .num_aperture_sizes     = 2,
1452         .needs_scratch_page     = true,
1453         .configure              = intel_i810_configure,
1454         .fetch_size             = intel_i810_fetch_size,
1455         .cleanup                = intel_i810_cleanup,
1456         .mask_memory            = intel_i810_mask_memory,
1457         .masks                  = intel_i810_masks,
1458         .agp_enable             = intel_fake_agp_enable,
1459         .cache_flush            = global_cache_flush,
1460         .create_gatt_table      = agp_generic_create_gatt_table,
1461         .free_gatt_table        = agp_generic_free_gatt_table,
1462         .insert_memory          = intel_i810_insert_entries,
1463         .remove_memory          = intel_i810_remove_entries,
1464         .alloc_by_type          = intel_i810_alloc_by_type,
1465         .free_by_type           = intel_i810_free_by_type,
1466         .agp_alloc_page         = agp_generic_alloc_page,
1467         .agp_alloc_pages        = agp_generic_alloc_pages,
1468         .agp_destroy_page       = agp_generic_destroy_page,
1469         .agp_destroy_pages      = agp_generic_destroy_pages,
1470         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1471 };
1472
1473 static const struct agp_bridge_driver intel_830_driver = {
1474         .owner                  = THIS_MODULE,
1475         .size_type              = FIXED_APER_SIZE,
1476         .aperture_sizes         = intel_fake_agp_sizes,
1477         .num_aperture_sizes     = ARRAY_SIZE(intel_fake_agp_sizes),
1478         .configure              = intel_fake_agp_configure,
1479         .fetch_size             = intel_fake_agp_fetch_size,
1480         .cleanup                = intel_gtt_cleanup,
1481         .mask_memory            = intel_i810_mask_memory,
1482         .masks                  = intel_i810_masks,
1483         .agp_enable             = intel_fake_agp_enable,
1484         .cache_flush            = global_cache_flush,
1485         .create_gatt_table      = intel_fake_agp_create_gatt_table,
1486         .free_gatt_table        = intel_fake_agp_free_gatt_table,
1487         .insert_memory          = intel_fake_agp_insert_entries,
1488         .remove_memory          = intel_fake_agp_remove_entries,
1489         .alloc_by_type          = intel_fake_agp_alloc_by_type,
1490         .free_by_type           = intel_i810_free_by_type,
1491         .agp_alloc_page         = agp_generic_alloc_page,
1492         .agp_alloc_pages        = agp_generic_alloc_pages,
1493         .agp_destroy_page       = agp_generic_destroy_page,
1494         .agp_destroy_pages      = agp_generic_destroy_pages,
1495         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1496         .chipset_flush          = intel_i830_chipset_flush,
1497 };
1498
1499 static const struct agp_bridge_driver intel_915_driver = {
1500         .owner                  = THIS_MODULE,
1501         .size_type              = FIXED_APER_SIZE,
1502         .aperture_sizes         = intel_fake_agp_sizes,
1503         .num_aperture_sizes     = ARRAY_SIZE(intel_fake_agp_sizes),
1504         .configure              = intel_fake_agp_configure,
1505         .fetch_size             = intel_fake_agp_fetch_size,
1506         .cleanup                = intel_gtt_cleanup,
1507         .mask_memory            = intel_i810_mask_memory,
1508         .masks                  = intel_i810_masks,
1509         .agp_enable             = intel_fake_agp_enable,
1510         .cache_flush            = global_cache_flush,
1511         .create_gatt_table      = intel_fake_agp_create_gatt_table,
1512         .free_gatt_table        = intel_fake_agp_free_gatt_table,
1513         .insert_memory          = intel_fake_agp_insert_entries,
1514         .remove_memory          = intel_fake_agp_remove_entries,
1515         .alloc_by_type          = intel_fake_agp_alloc_by_type,
1516         .free_by_type           = intel_i810_free_by_type,
1517         .agp_alloc_page         = agp_generic_alloc_page,
1518         .agp_alloc_pages        = agp_generic_alloc_pages,
1519         .agp_destroy_page       = agp_generic_destroy_page,
1520         .agp_destroy_pages      = agp_generic_destroy_pages,
1521         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1522         .chipset_flush          = intel_i915_chipset_flush,
1523 };
1524
1525 static const struct agp_bridge_driver intel_i965_driver = {
1526         .owner                  = THIS_MODULE,
1527         .size_type              = FIXED_APER_SIZE,
1528         .aperture_sizes         = intel_fake_agp_sizes,
1529         .num_aperture_sizes     = ARRAY_SIZE(intel_fake_agp_sizes),
1530         .configure              = intel_fake_agp_configure,
1531         .fetch_size             = intel_fake_agp_fetch_size,
1532         .cleanup                = intel_gtt_cleanup,
1533         .mask_memory            = intel_i965_mask_memory,
1534         .masks                  = intel_i810_masks,
1535         .agp_enable             = intel_fake_agp_enable,
1536         .cache_flush            = global_cache_flush,
1537         .create_gatt_table      = intel_fake_agp_create_gatt_table,
1538         .free_gatt_table        = intel_fake_agp_free_gatt_table,
1539         .insert_memory          = intel_fake_agp_insert_entries,
1540         .remove_memory          = intel_fake_agp_remove_entries,
1541         .alloc_by_type          = intel_fake_agp_alloc_by_type,
1542         .free_by_type           = intel_i810_free_by_type,
1543         .agp_alloc_page         = agp_generic_alloc_page,
1544         .agp_alloc_pages        = agp_generic_alloc_pages,
1545         .agp_destroy_page       = agp_generic_destroy_page,
1546         .agp_destroy_pages      = agp_generic_destroy_pages,
1547         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1548         .chipset_flush          = intel_i915_chipset_flush,
1549 };
1550
1551 static const struct agp_bridge_driver intel_gen6_driver = {
1552         .owner                  = THIS_MODULE,
1553         .size_type              = FIXED_APER_SIZE,
1554         .aperture_sizes         = intel_fake_agp_sizes,
1555         .num_aperture_sizes     = ARRAY_SIZE(intel_fake_agp_sizes),
1556         .configure              = intel_fake_agp_configure,
1557         .fetch_size             = intel_fake_agp_fetch_size,
1558         .cleanup                = intel_gtt_cleanup,
1559         .mask_memory            = intel_gen6_mask_memory,
1560         .masks                  = intel_gen6_masks,
1561         .agp_enable             = intel_fake_agp_enable,
1562         .cache_flush            = global_cache_flush,
1563         .create_gatt_table      = intel_fake_agp_create_gatt_table,
1564         .free_gatt_table        = intel_fake_agp_free_gatt_table,
1565         .insert_memory          = intel_i915_insert_entries,
1566         .remove_memory          = intel_i915_remove_entries,
1567         .alloc_by_type          = intel_fake_agp_alloc_by_type,
1568         .free_by_type           = intel_i810_free_by_type,
1569         .agp_alloc_page         = agp_generic_alloc_page,
1570         .agp_alloc_pages        = agp_generic_alloc_pages,
1571         .agp_destroy_page       = agp_generic_destroy_page,
1572         .agp_destroy_pages      = agp_generic_destroy_pages,
1573         .agp_type_to_mask_type  = intel_gen6_type_to_mask_type,
1574         .chipset_flush          = intel_i915_chipset_flush,
1575 #if USE_PCI_DMA_API
1576         .agp_map_memory         = intel_agp_map_memory,
1577         .agp_unmap_memory       = intel_agp_unmap_memory,
1578 #endif
1579 };
1580
1581 static const struct agp_bridge_driver intel_g33_driver = {
1582         .owner                  = THIS_MODULE,
1583         .size_type              = FIXED_APER_SIZE,
1584         .aperture_sizes         = intel_fake_agp_sizes,
1585         .num_aperture_sizes     = ARRAY_SIZE(intel_fake_agp_sizes),
1586         .configure              = intel_fake_agp_configure,
1587         .fetch_size             = intel_fake_agp_fetch_size,
1588         .cleanup                = intel_gtt_cleanup,
1589         .mask_memory            = intel_i965_mask_memory,
1590         .masks                  = intel_i810_masks,
1591         .agp_enable             = intel_fake_agp_enable,
1592         .cache_flush            = global_cache_flush,
1593         .create_gatt_table      = intel_fake_agp_create_gatt_table,
1594         .free_gatt_table        = intel_fake_agp_free_gatt_table,
1595         .insert_memory          = intel_fake_agp_insert_entries,
1596         .remove_memory          = intel_fake_agp_remove_entries,
1597         .alloc_by_type          = intel_fake_agp_alloc_by_type,
1598         .free_by_type           = intel_i810_free_by_type,
1599         .agp_alloc_page         = agp_generic_alloc_page,
1600         .agp_alloc_pages        = agp_generic_alloc_pages,
1601         .agp_destroy_page       = agp_generic_destroy_page,
1602         .agp_destroy_pages      = agp_generic_destroy_pages,
1603         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1604         .chipset_flush          = intel_i915_chipset_flush,
1605 };
1606
1607 static const struct intel_gtt_driver i8xx_gtt_driver = {
1608         .gen = 2,
1609         .setup = i830_setup,
1610         .write_entry = i830_write_entry,
1611         .check_flags = i830_check_flags,
1612 };
1613 static const struct intel_gtt_driver i915_gtt_driver = {
1614         .gen = 3,
1615         .setup = i9xx_setup,
1616         /* i945 is the last gpu to need phys mem (for overlay and cursors). */
1617         .write_entry = i830_write_entry,
1618         .check_flags = i830_check_flags,
1619 };
1620 static const struct intel_gtt_driver g33_gtt_driver = {
1621         .gen = 3,
1622         .is_g33 = 1,
1623         .setup = i9xx_setup,
1624         .write_entry = i965_write_entry,
1625         .check_flags = i830_check_flags,
1626 };
1627 static const struct intel_gtt_driver pineview_gtt_driver = {
1628         .gen = 3,
1629         .is_pineview = 1, .is_g33 = 1,
1630         .setup = i9xx_setup,
1631         .write_entry = i965_write_entry,
1632         .check_flags = i830_check_flags,
1633 };
1634 static const struct intel_gtt_driver i965_gtt_driver = {
1635         .gen = 4,
1636         .setup = i9xx_setup,
1637         .write_entry = i965_write_entry,
1638         .check_flags = i830_check_flags,
1639 };
1640 static const struct intel_gtt_driver g4x_gtt_driver = {
1641         .gen = 5,
1642         .setup = i9xx_setup,
1643         .write_entry = i965_write_entry,
1644         .check_flags = i830_check_flags,
1645 };
1646 static const struct intel_gtt_driver ironlake_gtt_driver = {
1647         .gen = 5,
1648         .is_ironlake = 1,
1649         .setup = i9xx_setup,
1650         .write_entry = i965_write_entry,
1651         .check_flags = i830_check_flags,
1652 };
1653 static const struct intel_gtt_driver sandybridge_gtt_driver = {
1654         .gen = 6,
1655         .setup = i9xx_setup,
1656         .write_entry = gen6_write_entry,
1657 };
1658
1659 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
1660  * driver and gmch_driver must be non-null, and find_gmch will determine
1661  * which one should be used if a gmch_chip_id is present.
1662  */
1663 static const struct intel_gtt_driver_description {
1664         unsigned int gmch_chip_id;
1665         char *name;
1666         const struct agp_bridge_driver *gmch_driver;
1667         const struct intel_gtt_driver *gtt_driver;
1668 } intel_gtt_chipsets[] = {
1669         { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", &intel_810_driver , NULL},
1670         { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", &intel_810_driver , NULL},
1671         { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", &intel_810_driver , NULL},
1672         { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", &intel_810_driver , NULL},
1673         { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1674                 &intel_830_driver , &i8xx_gtt_driver},
1675         { PCI_DEVICE_ID_INTEL_82845G_IG, "830M",
1676                 &intel_830_driver , &i8xx_gtt_driver},
1677         { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1678                 &intel_830_driver , &i8xx_gtt_driver},
1679         { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1680                 &intel_830_driver , &i8xx_gtt_driver},
1681         { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1682                 &intel_830_driver , &i8xx_gtt_driver},
1683         { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1684                 &intel_915_driver , &i915_gtt_driver },
1685         { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1686                 &intel_915_driver , &i915_gtt_driver },
1687         { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1688                 &intel_915_driver , &i915_gtt_driver },
1689         { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1690                 &intel_915_driver , &i915_gtt_driver },
1691         { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1692                 &intel_915_driver , &i915_gtt_driver },
1693         { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1694                 &intel_915_driver , &i915_gtt_driver },
1695         { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1696                 &intel_i965_driver , &i965_gtt_driver },
1697         { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1698                 &intel_i965_driver , &i965_gtt_driver },
1699         { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1700                 &intel_i965_driver , &i965_gtt_driver },
1701         { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1702                 &intel_i965_driver , &i965_gtt_driver },
1703         { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1704                 &intel_i965_driver , &i965_gtt_driver },
1705         { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1706                 &intel_i965_driver , &i965_gtt_driver },
1707         { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1708                 &intel_g33_driver , &g33_gtt_driver },
1709         { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1710                 &intel_g33_driver , &g33_gtt_driver },
1711         { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1712                 &intel_g33_driver , &g33_gtt_driver },
1713         { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1714                 &intel_g33_driver , &pineview_gtt_driver },
1715         { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1716                 &intel_g33_driver , &pineview_gtt_driver },
1717         { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1718                 &intel_i965_driver , &g4x_gtt_driver },
1719         { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1720                 &intel_i965_driver , &g4x_gtt_driver },
1721         { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1722                 &intel_i965_driver , &g4x_gtt_driver },
1723         { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1724                 &intel_i965_driver , &g4x_gtt_driver },
1725         { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1726                 &intel_i965_driver , &g4x_gtt_driver },
1727         { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
1728                 &intel_i965_driver , &g4x_gtt_driver },
1729         { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1730                 &intel_i965_driver , &g4x_gtt_driver },
1731         { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1732             "HD Graphics", &intel_i965_driver , &ironlake_gtt_driver },
1733         { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1734             "HD Graphics", &intel_i965_driver , &ironlake_gtt_driver },
1735         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
1736             "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1737         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
1738             "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1739         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
1740             "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1741         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
1742             "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1743         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
1744             "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1745         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
1746             "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1747         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
1748             "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1749         { 0, NULL, NULL }
1750 };
1751
1752 static int find_gmch(u16 device)
1753 {
1754         struct pci_dev *gmch_device;
1755
1756         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1757         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1758                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1759                                              device, gmch_device);
1760         }
1761
1762         if (!gmch_device)
1763                 return 0;
1764
1765         intel_private.pcidev = gmch_device;
1766         return 1;
1767 }
1768
1769 int intel_gmch_probe(struct pci_dev *pdev,
1770                                       struct agp_bridge_data *bridge)
1771 {
1772         int i, mask;
1773         bridge->driver = NULL;
1774
1775         for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1776                 if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1777                         bridge->driver =
1778                                 intel_gtt_chipsets[i].gmch_driver;
1779                         intel_private.driver =
1780                                 intel_gtt_chipsets[i].gtt_driver;
1781                         break;
1782                 }
1783         }
1784
1785         if (!bridge->driver)
1786                 return 0;
1787
1788         bridge->dev_private_data = &intel_private;
1789         bridge->dev = pdev;
1790
1791         intel_private.bridge_dev = pci_dev_get(pdev);
1792
1793         dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1794
1795         if (bridge->driver->mask_memory == intel_gen6_mask_memory)
1796                 mask = 40;
1797         else if (bridge->driver->mask_memory == intel_i965_mask_memory)
1798                 mask = 36;
1799         else
1800                 mask = 32;
1801
1802         if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1803                 dev_err(&intel_private.pcidev->dev,
1804                         "set gfx device dma mask %d-bit failed!\n", mask);
1805         else
1806                 pci_set_consistent_dma_mask(intel_private.pcidev,
1807                                             DMA_BIT_MASK(mask));
1808
1809         if (bridge->driver == &intel_810_driver)
1810                 return 1;
1811
1812         if (intel_gtt_init() != 0)
1813                 return 0;
1814
1815         return 1;
1816 }
1817 EXPORT_SYMBOL(intel_gmch_probe);
1818
1819 struct intel_gtt *intel_gtt_get(void)
1820 {
1821         return &intel_private.base;
1822 }
1823 EXPORT_SYMBOL(intel_gtt_get);
1824
1825 void intel_gmch_remove(struct pci_dev *pdev)
1826 {
1827         if (intel_private.pcidev)
1828                 pci_dev_put(intel_private.pcidev);
1829         if (intel_private.bridge_dev)
1830                 pci_dev_put(intel_private.bridge_dev);
1831 }
1832 EXPORT_SYMBOL(intel_gmch_remove);
1833
1834 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1835 MODULE_LICENSE("GPL and additional rights");