drivers/char/agp/intel-gtt.c

   1 /*
   2  * Intel GTT (Graphics Translation Table) routines
   3  *
   4  * Caveat: This driver implements the linux agp interface, but this is far from
   5  * a agp driver! GTT support ended up here for purely historical reasons: The
   6  * old userspace intel graphics drivers needed an interface to map memory into
   7  * the GTT. And the drm provides a default interface for graphic devices sitting
   8  * on an agp port. So it made sense to fake the GTT support as an agp port to
   9  * avoid having to create a new api.
  10  *
  11  * With gem this does not make much sense anymore, just needlessly complicates
  12  * the code. But as long as the old graphics stack is still support, it's stuck
  13  * here.
  14  *
  15  * /fairy-tale-mode off
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/pci.h>
  20 #include <linux/init.h>
  21 #include <linux/kernel.h>
  22 #include <linux/pagemap.h>
  23 #include <linux/agp_backend.h>
  24 #include <asm/smp.h>
  25 #include "agp.h"
  26 #include "intel-agp.h"
  27 #include <linux/intel-gtt.h>
  28 #include <drm/intel-gtt.h>
  29
  30 /*
  31  * If we have Intel graphics, we're not going to have anything other than
  32  * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
  33  * on the Intel IOMMU support (CONFIG_DMAR).
  34  * Only newer chipsets need to bother with this, of course.
  35  */
  36 #ifdef CONFIG_DMAR
  37 #define USE_PCI_DMA_API 1
  38 #endif
  39
  40 /* Max amount of stolen space, anything above will be returned to Linux */
  41 int intel_max_stolen = 32 * 1024 * 1024;
  42 EXPORT_SYMBOL(intel_max_stolen);
  43
  44 static const struct aper_size_info_fixed intel_i810_sizes[] =
  45 {
  46         {64, 16384, 4},
  47         /* The 32M mode still requires a 64k gatt */
  48         {32, 8192, 4}
  49 };
  50
  51 #define AGP_DCACHE_MEMORY       1
  52 #define AGP_PHYS_MEMORY         2
  53 #define INTEL_AGP_CACHED_MEMORY 3
  54
  55 static struct gatt_mask intel_i810_masks[] =
  56 {
  57         {.mask = I810_PTE_VALID, .type = 0},
  58         {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
  59         {.mask = I810_PTE_VALID, .type = 0},
  60         {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
  61          .type = INTEL_AGP_CACHED_MEMORY}
  62 };
  63
  64 #define INTEL_AGP_UNCACHED_MEMORY              0
  65 #define INTEL_AGP_CACHED_MEMORY_LLC            1
  66 #define INTEL_AGP_CACHED_MEMORY_LLC_GFDT       2
  67 #define INTEL_AGP_CACHED_MEMORY_LLC_MLC        3
  68 #define INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT   4
  69
  70 static struct gatt_mask intel_gen6_masks[] =
  71 {
  72         {.mask = I810_PTE_VALID | GEN6_PTE_UNCACHED,
  73          .type = INTEL_AGP_UNCACHED_MEMORY },
  74         {.mask = I810_PTE_VALID | GEN6_PTE_LLC,
  75          .type = INTEL_AGP_CACHED_MEMORY_LLC },
  76         {.mask = I810_PTE_VALID | GEN6_PTE_LLC | GEN6_PTE_GFDT,
  77          .type = INTEL_AGP_CACHED_MEMORY_LLC_GFDT },
  78         {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC,
  79          .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC },
  80         {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC | GEN6_PTE_GFDT,
  81          .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT },
  82 };
  83
  84 struct intel_gtt_driver {
  85         unsigned int gen : 8;
  86         unsigned int is_g33 : 1;
  87         unsigned int is_pineview : 1;
  88         unsigned int is_ironlake : 1;
  89 };
  90
  91 static struct _intel_private {
  92         struct intel_gtt base;
  93         const struct intel_gtt_driver *driver;
  94         struct pci_dev *pcidev; /* device one */
  95         struct pci_dev *bridge_dev;
  96         u8 __iomem *registers;
  97         u32 __iomem *gtt;               /* I915G */
  98         int num_dcache_entries;
  99         union {
 100                 void __iomem *i9xx_flush_page;
 101                 void *i8xx_flush_page;
 102         };
 103         struct page *i8xx_page;
 104         struct resource ifp_resource;
 105         int resource_valid;
 106 } intel_private;
 107
 108 #define INTEL_GTT_GEN   intel_private.driver->gen
 109 #define IS_G33          intel_private.driver->is_g33
 110 #define IS_PINEVIEW     intel_private.driver->is_pineview
 111 #define IS_IRONLAKE     intel_private.driver->is_ironlake
 112
 113 #ifdef USE_PCI_DMA_API
 114 static int intel_agp_map_page(struct page *page, dma_addr_t *ret)
 115 {
 116         *ret = pci_map_page(intel_private.pcidev, page, 0,
 117                             PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 118         if (pci_dma_mapping_error(intel_private.pcidev, *ret))
 119                 return -EINVAL;
 120         return 0;
 121 }
 122
 123 static void intel_agp_unmap_page(struct page *page, dma_addr_t dma)
 124 {
 125         pci_unmap_page(intel_private.pcidev, dma,
 126                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 127 }
 128
 129 static void intel_agp_free_sglist(struct agp_memory *mem)
 130 {
 131         struct sg_table st;
 132
 133         st.sgl = mem->sg_list;
 134         st.orig_nents = st.nents = mem->page_count;
 135
 136         sg_free_table(&st);
 137
 138         mem->sg_list = NULL;
 139         mem->num_sg = 0;
 140 }
 141
 142 static int intel_agp_map_memory(struct agp_memory *mem)
 143 {
 144         struct sg_table st;
 145         struct scatterlist *sg;
 146         int i;
 147
 148         DBG("try mapping %lu pages\n", (unsigned long)mem->page_count);
 149
 150         if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL))
 151                 goto err;
 152
 153         mem->sg_list = sg = st.sgl;
 154
 155         for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg))
 156                 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0);
 157
 158         mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list,
 159                                  mem->page_count, PCI_DMA_BIDIRECTIONAL);
 160         if (unlikely(!mem->num_sg))
 161                 goto err;
 162
 163         return 0;
 164
 165 err:
 166         sg_free_table(&st);
 167         return -ENOMEM;
 168 }
 169
 170 static void intel_agp_unmap_memory(struct agp_memory *mem)
 171 {
 172         DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
 173
 174         pci_unmap_sg(intel_private.pcidev, mem->sg_list,
 175                      mem->page_count, PCI_DMA_BIDIRECTIONAL);
 176         intel_agp_free_sglist(mem);
 177 }
 178
 179 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
 180                                         off_t pg_start, int mask_type)
 181 {
 182         struct scatterlist *sg;
 183         int i, j;
 184
 185         j = pg_start;
 186
 187         WARN_ON(!mem->num_sg);
 188
 189         if (mem->num_sg == mem->page_count) {
 190                 for_each_sg(mem->sg_list, sg, mem->page_count, i) {
 191                         writel(agp_bridge->driver->mask_memory(agp_bridge,
 192                                         sg_dma_address(sg), mask_type),
 193                                         intel_private.gtt+j);
 194                         j++;
 195                 }
 196         } else {
 197                 /* sg may merge pages, but we have to separate
 198                  * per-page addr for GTT */
 199                 unsigned int len, m;
 200
 201                 for_each_sg(mem->sg_list, sg, mem->num_sg, i) {
 202                         len = sg_dma_len(sg) / PAGE_SIZE;
 203                         for (m = 0; m < len; m++) {
 204                                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 205                                                                        sg_dma_address(sg) + m * PAGE_SIZE,
 206                                                                        mask_type),
 207                                        intel_private.gtt+j);
 208                                 j++;
 209                         }
 210                 }
 211         }
 212         readl(intel_private.gtt+j-1);
 213 }
 214
 215 #else
 216
 217 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
 218                                         off_t pg_start, int mask_type)
 219 {
 220         int i, j;
 221
 222         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 223                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 224                                 page_to_phys(mem->pages[i]), mask_type),
 225                        intel_private.gtt+j);
 226         }
 227
 228         readl(intel_private.gtt+j-1);
 229 }
 230
 231 #endif
 232
 233 static int intel_i810_fetch_size(void)
 234 {
 235         u32 smram_miscc;
 236         struct aper_size_info_fixed *values;
 237
 238         pci_read_config_dword(intel_private.bridge_dev,
 239                               I810_SMRAM_MISCC, &smram_miscc);
 240         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 241
 242         if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
 243                 dev_warn(&intel_private.bridge_dev->dev, "i810 is disabled\n");
 244                 return 0;
 245         }
 246         if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
 247                 agp_bridge->current_size = (void *) (values + 1);
 248                 agp_bridge->aperture_size_idx = 1;
 249                 return values[1].size;
 250         } else {
 251                 agp_bridge->current_size = (void *) (values);
 252                 agp_bridge->aperture_size_idx = 0;
 253                 return values[0].size;
 254         }
 255
 256         return 0;
 257 }
 258
 259 static int intel_i810_configure(void)
 260 {
 261         struct aper_size_info_fixed *current_size;
 262         u32 temp;
 263         int i;
 264
 265         current_size = A_SIZE_FIX(agp_bridge->current_size);
 266
 267         if (!intel_private.registers) {
 268                 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 269                 temp &= 0xfff80000;
 270
 271                 intel_private.registers = ioremap(temp, 128 * 4096);
 272                 if (!intel_private.registers) {
 273                         dev_err(&intel_private.pcidev->dev,
 274                                 "can't remap memory\n");
 275                         return -ENOMEM;
 276                 }
 277         }
 278
 279         if ((readl(intel_private.registers+I810_DRAM_CTL)
 280                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 281                 /* This will need to be dynamically assigned */
 282                 dev_info(&intel_private.pcidev->dev,
 283                          "detected 4MB dedicated video ram\n");
 284                 intel_private.num_dcache_entries = 1024;
 285         }
 286         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 287         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 288         writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 289         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 290
 291         if (agp_bridge->driver->needs_scratch_page) {
 292                 for (i = 0; i < current_size->num_entries; i++) {
 293                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 294                 }
 295                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
 296         }
 297         global_cache_flush();
 298         return 0;
 299 }
 300
 301 static void intel_i810_cleanup(void)
 302 {
 303         writel(0, intel_private.registers+I810_PGETBL_CTL);
 304         readl(intel_private.registers); /* PCI Posting. */
 305         iounmap(intel_private.registers);
 306 }
 307
 308 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 309 {
 310         return;
 311 }
 312
 313 /* Exists to support ARGB cursors */
 314 static struct page *i8xx_alloc_pages(void)
 315 {
 316         struct page *page;
 317
 318         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
 319         if (page == NULL)
 320                 return NULL;
 321
 322         if (set_pages_uc(page, 4) < 0) {
 323                 set_pages_wb(page, 4);
 324                 __free_pages(page, 2);
 325                 return NULL;
 326         }
 327         get_page(page);
 328         atomic_inc(&agp_bridge->current_memory_agp);
 329         return page;
 330 }
 331
 332 static void i8xx_destroy_pages(struct page *page)
 333 {
 334         if (page == NULL)
 335                 return;
 336
 337         set_pages_wb(page, 4);
 338         put_page(page);
 339         __free_pages(page, 2);
 340         atomic_dec(&agp_bridge->current_memory_agp);
 341 }
 342
 343 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
 344                                         int type)
 345 {
 346         if (type < AGP_USER_TYPES)
 347                 return type;
 348         else if (type == AGP_USER_CACHED_MEMORY)
 349                 return INTEL_AGP_CACHED_MEMORY;
 350         else
 351                 return 0;
 352 }
 353
 354 static int intel_gen6_type_to_mask_type(struct agp_bridge_data *bridge,
 355                                         int type)
 356 {
 357         unsigned int type_mask = type & ~AGP_USER_CACHED_MEMORY_GFDT;
 358         unsigned int gfdt = type & AGP_USER_CACHED_MEMORY_GFDT;
 359
 360         if (type_mask == AGP_USER_UNCACHED_MEMORY)
 361                 return INTEL_AGP_UNCACHED_MEMORY;
 362         else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC)
 363                 return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT :
 364                               INTEL_AGP_CACHED_MEMORY_LLC_MLC;
 365         else /* set 'normal'/'cached' to LLC by default */
 366                 return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_GFDT :
 367                               INTEL_AGP_CACHED_MEMORY_LLC;
 368 }
 369
 370
 371 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
 372                                 int type)
 373 {
 374         int i, j, num_entries;
 375         void *temp;
 376         int ret = -EINVAL;
 377         int mask_type;
 378
 379         if (mem->page_count == 0)
 380                 goto out;
 381
 382         temp = agp_bridge->current_size;
 383         num_entries = A_SIZE_FIX(temp)->num_entries;
 384
 385         if ((pg_start + mem->page_count) > num_entries)
 386                 goto out_err;
 387
 388
 389         for (j = pg_start; j < (pg_start + mem->page_count); j++) {
 390                 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
 391                         ret = -EBUSY;
 392                         goto out_err;
 393                 }
 394         }
 395
 396         if (type != mem->type)
 397                 goto out_err;
 398
 399         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 400
 401         switch (mask_type) {
 402         case AGP_DCACHE_MEMORY:
 403                 if (!mem->is_flushed)
 404                         global_cache_flush();
 405                 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 406                         writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
 407                                intel_private.registers+I810_PTE_BASE+(i*4));
 408                 }
 409                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 410                 break;
 411         case AGP_PHYS_MEMORY:
 412         case AGP_NORMAL_MEMORY:
 413                 if (!mem->is_flushed)
 414                         global_cache_flush();
 415                 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 416                         writel(agp_bridge->driver->mask_memory(agp_bridge,
 417                                         page_to_phys(mem->pages[i]), mask_type),
 418                                intel_private.registers+I810_PTE_BASE+(j*4));
 419                 }
 420                 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 421                 break;
 422         default:
 423                 goto out_err;
 424         }
 425
 426 out:
 427         ret = 0;
 428 out_err:
 429         mem->is_flushed = true;
 430         return ret;
 431 }
 432
 433 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
 434                                 int type)
 435 {
 436         int i;
 437
 438         if (mem->page_count == 0)
 439                 return 0;
 440
 441         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 442                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 443         }
 444         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 445
 446         return 0;
 447 }
 448
 449 /*
 450  * The i810/i830 requires a physical address to program its mouse
 451  * pointer into hardware.
 452  * However the Xserver still writes to it through the agp aperture.
 453  */
 454 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
 455 {
 456         struct agp_memory *new;
 457         struct page *page;
 458
 459         switch (pg_count) {
 460         case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
 461                 break;
 462         case 4:
 463                 /* kludge to get 4 physical pages for ARGB cursor */
 464                 page = i8xx_alloc_pages();
 465                 break;
 466         default:
 467                 return NULL;
 468         }
 469
 470         if (page == NULL)
 471                 return NULL;
 472
 473         new = agp_create_memory(pg_count);
 474         if (new == NULL)
 475                 return NULL;
 476
 477         new->pages[0] = page;
 478         if (pg_count == 4) {
 479                 /* kludge to get 4 physical pages for ARGB cursor */
 480                 new->pages[1] = new->pages[0] + 1;
 481                 new->pages[2] = new->pages[1] + 1;
 482                 new->pages[3] = new->pages[2] + 1;
 483         }
 484         new->page_count = pg_count;
 485         new->num_scratch_pages = pg_count;
 486         new->type = AGP_PHYS_MEMORY;
 487         new->physical = page_to_phys(new->pages[0]);
 488         return new;
 489 }
 490
 491 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
 492 {
 493         struct agp_memory *new;
 494
 495         if (type == AGP_DCACHE_MEMORY) {
 496                 if (pg_count != intel_private.num_dcache_entries)
 497                         return NULL;
 498
 499                 new = agp_create_memory(1);
 500                 if (new == NULL)
 501                         return NULL;
 502
 503                 new->type = AGP_DCACHE_MEMORY;
 504                 new->page_count = pg_count;
 505                 new->num_scratch_pages = 0;
 506                 agp_free_page_array(new);
 507                 return new;
 508         }
 509         if (type == AGP_PHYS_MEMORY)
 510                 return alloc_agpphysmem_i8xx(pg_count, type);
 511         return NULL;
 512 }
 513
 514 static void intel_i810_free_by_type(struct agp_memory *curr)
 515 {
 516         agp_free_key(curr->key);
 517         if (curr->type == AGP_PHYS_MEMORY) {
 518                 if (curr->page_count == 4)
 519                         i8xx_destroy_pages(curr->pages[0]);
 520                 else {
 521                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 522                                                              AGP_PAGE_DESTROY_UNMAP);
 523                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 524                                                              AGP_PAGE_DESTROY_FREE);
 525                 }
 526                 agp_free_page_array(curr);
 527         }
 528         kfree(curr);
 529 }
 530
 531 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
 532                                             dma_addr_t addr, int type)
 533 {
 534         /* Type checking must be done elsewhere */
 535         return addr | bridge->driver->masks[type].mask;
 536 }
 537
 538 static struct aper_size_info_fixed intel_fake_agp_sizes[] =
 539 {
 540         {128, 32768, 5},
 541         /* The 64M mode still requires a 128k gatt */
 542         {64, 16384, 5},
 543         {256, 65536, 6},
 544         {512, 131072, 7},
 545 };
 546
 547 static unsigned int intel_gtt_stolen_entries(void)
 548 {
 549         u16 gmch_ctrl;
 550         u8 rdct;
 551         int local = 0;
 552         static const int ddt[4] = { 0, 16, 32, 64 };
 553         unsigned int overhead_entries, stolen_entries;
 554         unsigned int stolen_size = 0;
 555
 556         pci_read_config_word(intel_private.bridge_dev,
 557                              I830_GMCH_CTRL, &gmch_ctrl);
 558
 559         if (INTEL_GTT_GEN > 4 || IS_PINEVIEW)
 560                 overhead_entries = 0;
 561         else
 562                 overhead_entries = intel_private.base.gtt_mappable_entries
 563                         / 1024;
 564
 565         overhead_entries += 1; /* BIOS popup */
 566
 567         if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
 568             intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
 569                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 570                 case I830_GMCH_GMS_STOLEN_512:
 571                         stolen_size = KB(512);
 572                         break;
 573                 case I830_GMCH_GMS_STOLEN_1024:
 574                         stolen_size = MB(1);
 575                         break;
 576                 case I830_GMCH_GMS_STOLEN_8192:
 577                         stolen_size = MB(8);
 578                         break;
 579                 case I830_GMCH_GMS_LOCAL:
 580                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
 581                         stolen_size = (I830_RDRAM_ND(rdct) + 1) *
 582                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
 583                         local = 1;
 584                         break;
 585                 default:
 586                         stolen_size = 0;
 587                         break;
 588                 }
 589         } else if (INTEL_GTT_GEN == 6) {
 590                 /*
 591                  * SandyBridge has new memory control reg at 0x50.w
 592                  */
 593                 u16 snb_gmch_ctl;
 594                 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 595                 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) {
 596                 case SNB_GMCH_GMS_STOLEN_32M:
 597                         stolen_size = MB(32);
 598                         break;
 599                 case SNB_GMCH_GMS_STOLEN_64M:
 600                         stolen_size = MB(64);
 601                         break;
 602                 case SNB_GMCH_GMS_STOLEN_96M:
 603                         stolen_size = MB(96);
 604                         break;
 605                 case SNB_GMCH_GMS_STOLEN_128M:
 606                         stolen_size = MB(128);
 607                         break;
 608                 case SNB_GMCH_GMS_STOLEN_160M:
 609                         stolen_size = MB(160);
 610                         break;
 611                 case SNB_GMCH_GMS_STOLEN_192M:
 612                         stolen_size = MB(192);
 613                         break;
 614                 case SNB_GMCH_GMS_STOLEN_224M:
 615                         stolen_size = MB(224);
 616                         break;
 617                 case SNB_GMCH_GMS_STOLEN_256M:
 618                         stolen_size = MB(256);
 619                         break;
 620                 case SNB_GMCH_GMS_STOLEN_288M:
 621                         stolen_size = MB(288);
 622                         break;
 623                 case SNB_GMCH_GMS_STOLEN_320M:
 624                         stolen_size = MB(320);
 625                         break;
 626                 case SNB_GMCH_GMS_STOLEN_352M:
 627                         stolen_size = MB(352);
 628                         break;
 629                 case SNB_GMCH_GMS_STOLEN_384M:
 630                         stolen_size = MB(384);
 631                         break;
 632                 case SNB_GMCH_GMS_STOLEN_416M:
 633                         stolen_size = MB(416);
 634                         break;
 635                 case SNB_GMCH_GMS_STOLEN_448M:
 636                         stolen_size = MB(448);
 637                         break;
 638                 case SNB_GMCH_GMS_STOLEN_480M:
 639                         stolen_size = MB(480);
 640                         break;
 641                 case SNB_GMCH_GMS_STOLEN_512M:
 642                         stolen_size = MB(512);
 643                         break;
 644                 }
 645         } else {
 646                 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
 647                 case I855_GMCH_GMS_STOLEN_1M:
 648                         stolen_size = MB(1);
 649                         break;
 650                 case I855_GMCH_GMS_STOLEN_4M:
 651                         stolen_size = MB(4);
 652                         break;
 653                 case I855_GMCH_GMS_STOLEN_8M:
 654                         stolen_size = MB(8);
 655                         break;
 656                 case I855_GMCH_GMS_STOLEN_16M:
 657                         stolen_size = MB(16);
 658                         break;
 659                 case I855_GMCH_GMS_STOLEN_32M:
 660                         stolen_size = MB(32);
 661                         break;
 662                 case I915_GMCH_GMS_STOLEN_48M:
 663                         stolen_size = MB(48);
 664                         break;
 665                 case I915_GMCH_GMS_STOLEN_64M:
 666                         stolen_size = MB(64);
 667                         break;
 668                 case G33_GMCH_GMS_STOLEN_128M:
 669                         stolen_size = MB(128);
 670                         break;
 671                 case G33_GMCH_GMS_STOLEN_256M:
 672                         stolen_size = MB(256);
 673                         break;
 674                 case INTEL_GMCH_GMS_STOLEN_96M:
 675                         stolen_size = MB(96);
 676                         break;
 677                 case INTEL_GMCH_GMS_STOLEN_160M:
 678                         stolen_size = MB(160);
 679                         break;
 680                 case INTEL_GMCH_GMS_STOLEN_224M:
 681                         stolen_size = MB(224);
 682                         break;
 683                 case INTEL_GMCH_GMS_STOLEN_352M:
 684                         stolen_size = MB(352);
 685                         break;
 686                 default:
 687                         stolen_size = 0;
 688                         break;
 689                 }
 690         }
 691
 692         if (!local && stolen_size > intel_max_stolen) {
 693                 dev_info(&intel_private.bridge_dev->dev,
 694                          "detected %dK stolen memory, trimming to %dK\n",
 695                          stolen_size / KB(1), intel_max_stolen / KB(1));
 696                 stolen_size = intel_max_stolen;
 697         } else if (stolen_size > 0) {
 698                 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
 699                        stolen_size / KB(1), local ? "local" : "stolen");
 700         } else {
 701                 dev_info(&intel_private.bridge_dev->dev,
 702                        "no pre-allocated video memory detected\n");
 703                 stolen_size = 0;
 704         }
 705
 706         stolen_entries = stolen_size/KB(4) - overhead_entries;
 707
 708         return stolen_entries;
 709 }
 710
 711 static unsigned int intel_gtt_total_entries(void)
 712 {
 713         int size;
 714
 715         if (IS_G33 || INTEL_GTT_GEN >= 4) {
 716                 u32 pgetbl_ctl;
 717                 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 718
 719                 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
 720                 case I965_PGETBL_SIZE_128KB:
 721                         size = KB(128);
 722                         break;
 723                 case I965_PGETBL_SIZE_256KB:
 724                         size = KB(256);
 725                         break;
 726                 case I965_PGETBL_SIZE_512KB:
 727                         size = KB(512);
 728                         break;
 729                 case I965_PGETBL_SIZE_1MB:
 730                         size = KB(1024);
 731                         break;
 732                 case I965_PGETBL_SIZE_2MB:
 733                         size = KB(2048);
 734                         break;
 735                 case I965_PGETBL_SIZE_1_5MB:
 736                         size = KB(1024 + 512);
 737                         break;
 738                 default:
 739                         dev_info(&intel_private.pcidev->dev,
 740                                  "unknown page table size, assuming 512KB\n");
 741                         size = KB(512);
 742                 }
 743
 744                 return size/4;
 745         } else {
 746                 /* On previous hardware, the GTT size was just what was
 747                  * required to map the aperture.
 748                  */
 749                 return intel_private.base.gtt_mappable_entries;
 750         }
 751 }
 752
 753 static unsigned int intel_gtt_mappable_entries(void)
 754 {
 755         unsigned int aperture_size;
 756         u16 gmch_ctrl;
 757
 758         aperture_size = 1024 * 1024;
 759
 760         pci_read_config_word(intel_private.bridge_dev,
 761                              I830_GMCH_CTRL, &gmch_ctrl);
 762
 763         switch (intel_private.pcidev->device) {
 764         case PCI_DEVICE_ID_INTEL_82830_CGC:
 765         case PCI_DEVICE_ID_INTEL_82845G_IG:
 766         case PCI_DEVICE_ID_INTEL_82855GM_IG:
 767         case PCI_DEVICE_ID_INTEL_82865_IG:
 768                 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
 769                         aperture_size *= 64;
 770                 else
 771                         aperture_size *= 128;
 772                 break;
 773         default:
 774                 /* 9xx supports large sizes, just look at the length */
 775                 aperture_size = pci_resource_len(intel_private.pcidev, 2);
 776                 break;
 777         }
 778
 779         return aperture_size >> PAGE_SHIFT;
 780 }
 781
 782 static int intel_gtt_init(void)
 783 {
 784         /* we have to call this as early as possible after the MMIO base address is known */
 785         intel_private.base.gtt_stolen_entries = intel_gtt_stolen_entries();
 786         if (intel_private.base.gtt_stolen_entries == 0) {
 787                 iounmap(intel_private.registers);
 788                 return -ENOMEM;
 789         }
 790
 791         return 0;
 792 }
 793
 794 static int intel_fake_agp_fetch_size(void)
 795 {
 796         unsigned int aper_size;
 797         int i;
 798         int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
 799
 800         aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT)
 801                     / MB(1);
 802
 803         for (i = 0; i < num_sizes; i++) {
 804                 if (aper_size == intel_fake_agp_sizes[i].size) {
 805                         agp_bridge->current_size = intel_fake_agp_sizes + i;
 806                         return aper_size;
 807                 }
 808         }
 809
 810         return 0;
 811 }
 812
 813 static void intel_i830_fini_flush(void)
 814 {
 815         kunmap(intel_private.i8xx_page);
 816         intel_private.i8xx_flush_page = NULL;
 817         unmap_page_from_agp(intel_private.i8xx_page);
 818
 819         __free_page(intel_private.i8xx_page);
 820         intel_private.i8xx_page = NULL;
 821 }
 822
 823 static void intel_i830_setup_flush(void)
 824 {
 825         /* return if we've already set the flush mechanism up */
 826         if (intel_private.i8xx_page)
 827                 return;
 828
 829         intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
 830         if (!intel_private.i8xx_page)
 831                 return;
 832
 833         intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
 834         if (!intel_private.i8xx_flush_page)
 835                 intel_i830_fini_flush();
 836 }
 837
 838 /* The chipset_flush interface needs to get data that has already been
 839  * flushed out of the CPU all the way out to main memory, because the GPU
 840  * doesn't snoop those buffers.
 841  *
 842  * The 8xx series doesn't have the same lovely interface for flushing the
 843  * chipset write buffers that the later chips do. According to the 865
 844  * specs, it's 64 octwords, or 1KB.  So, to get those previous things in
 845  * that buffer out, we just fill 1KB and clflush it out, on the assumption
 846  * that it'll push whatever was in there out.  It appears to work.
 847  */
 848 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
 849 {
 850         unsigned int *pg = intel_private.i8xx_flush_page;
 851
 852         memset(pg, 0, 1024);
 853
 854         if (cpu_has_clflush)
 855                 clflush_cache_range(pg, 1024);
 856         else if (wbinvd_on_all_cpus() != 0)
 857                 printk(KERN_ERR "Timed out waiting for cache flush.\n");
 858 }
 859
 860 /* The intel i830 automatically initializes the agp aperture during POST.
 861  * Use the memory already set aside for in the GTT.
 862  */
 863 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
 864 {
 865         int page_order, ret;
 866         struct aper_size_info_fixed *size;
 867         int num_entries;
 868         u32 temp;
 869
 870         size = agp_bridge->current_size;
 871         page_order = size->page_order;
 872         num_entries = size->num_entries;
 873         agp_bridge->gatt_table_real = NULL;
 874
 875         pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 876         temp &= 0xfff80000;
 877
 878         intel_private.registers = ioremap(temp, 128 * 4096);
 879         if (!intel_private.registers)
 880                 return -ENOMEM;
 881
 882         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
 883         global_cache_flush();   /* FIXME: ?? */
 884
 885         ret = intel_gtt_init();
 886         if (ret != 0)
 887                 return ret;
 888
 889         agp_bridge->gatt_table = NULL;
 890
 891         agp_bridge->gatt_bus_addr = temp;
 892
 893         return 0;
 894 }
 895
 896 /* Return the gatt table to a sane state. Use the top of stolen
 897  * memory for the GTT.
 898  */
 899 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
 900 {
 901         return 0;
 902 }
 903
 904 static int intel_i830_configure(void)
 905 {
 906         struct aper_size_info_fixed *current_size;
 907         u32 temp;
 908         u16 gmch_ctrl;
 909         int i;
 910
 911         current_size = A_SIZE_FIX(agp_bridge->current_size);
 912
 913         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 914         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 915
 916         pci_read_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, &gmch_ctrl);
 917         gmch_ctrl |= I830_GMCH_ENABLED;
 918         pci_write_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, gmch_ctrl);
 919
 920         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 921         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 922
 923         if (agp_bridge->driver->needs_scratch_page) {
 924                 for (i = intel_private.base.gtt_stolen_entries; i < current_size->num_entries; i++) {
 925                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 926                 }
 927                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */
 928         }
 929
 930         global_cache_flush();
 931
 932         intel_i830_setup_flush();
 933         return 0;
 934 }
 935
 936 static void intel_i830_cleanup(void)
 937 {
 938         iounmap(intel_private.registers);
 939 }
 940
 941 static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
 942                                      int type)
 943 {
 944         int i, j, num_entries;
 945         void *temp;
 946         int ret = -EINVAL;
 947         int mask_type;
 948
 949         if (mem->page_count == 0)
 950                 goto out;
 951
 952         temp = agp_bridge->current_size;
 953         num_entries = A_SIZE_FIX(temp)->num_entries;
 954
 955         if (pg_start < intel_private.base.gtt_stolen_entries) {
 956                 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
 957                            "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
 958                            pg_start, intel_private.base.gtt_stolen_entries);
 959
 960                 dev_info(&intel_private.pcidev->dev,
 961                          "trying to insert into local/stolen memory\n");
 962                 goto out_err;
 963         }
 964
 965         if ((pg_start + mem->page_count) > num_entries)
 966                 goto out_err;
 967
 968         /* The i830 can't check the GTT for entries since its read only,
 969          * depend on the caller to make the correct offset decisions.
 970          */
 971
 972         if (type != mem->type)
 973                 goto out_err;
 974
 975         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 976
 977         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
 978             mask_type != INTEL_AGP_CACHED_MEMORY)
 979                 goto out_err;
 980
 981         if (!mem->is_flushed)
 982                 global_cache_flush();
 983
 984         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 985                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 986                                 page_to_phys(mem->pages[i]), mask_type),
 987                        intel_private.registers+I810_PTE_BASE+(j*4));
 988         }
 989         readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 990
 991 out:
 992         ret = 0;
 993 out_err:
 994         mem->is_flushed = true;
 995         return ret;
 996 }
 997
 998 static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
 999                                      int type)
1000 {
1001         int i;
1002
1003         if (mem->page_count == 0)
1004                 return 0;
1005
1006         if (pg_start < intel_private.base.gtt_stolen_entries) {
1007                 dev_info(&intel_private.pcidev->dev,
1008                          "trying to disable local/stolen memory\n");
1009                 return -EINVAL;
1010         }
1011
1012         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1013                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
1014         }
1015         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
1016
1017         return 0;
1018 }
1019
1020 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
1021                                                        int type)
1022 {
1023         if (type == AGP_PHYS_MEMORY)
1024                 return alloc_agpphysmem_i8xx(pg_count, type);
1025         /* always return NULL for other allocation types for now */
1026         return NULL;
1027 }
1028
1029 static int intel_alloc_chipset_flush_resource(void)
1030 {
1031         int ret;
1032         ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1033                                      PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1034                                      pcibios_align_resource, intel_private.bridge_dev);
1035
1036         return ret;
1037 }
1038
1039 static void intel_i915_setup_chipset_flush(void)
1040 {
1041         int ret;
1042         u32 temp;
1043
1044         pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1045         if (!(temp & 0x1)) {
1046                 intel_alloc_chipset_flush_resource();
1047                 intel_private.resource_valid = 1;
1048                 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1049         } else {
1050                 temp &= ~1;
1051
1052                 intel_private.resource_valid = 1;
1053                 intel_private.ifp_resource.start = temp;
1054                 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1055                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1056                 /* some BIOSes reserve this area in a pnp some don't */
1057                 if (ret)
1058                         intel_private.resource_valid = 0;
1059         }
1060 }
1061
1062 static void intel_i965_g33_setup_chipset_flush(void)
1063 {
1064         u32 temp_hi, temp_lo;
1065         int ret;
1066
1067         pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1068         pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1069
1070         if (!(temp_lo & 0x1)) {
1071
1072                 intel_alloc_chipset_flush_resource();
1073
1074                 intel_private.resource_valid = 1;
1075                 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1076                         upper_32_bits(intel_private.ifp_resource.start));
1077                 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1078         } else {
1079                 u64 l64;
1080
1081                 temp_lo &= ~0x1;
1082                 l64 = ((u64)temp_hi << 32) | temp_lo;
1083
1084                 intel_private.resource_valid = 1;
1085                 intel_private.ifp_resource.start = l64;
1086                 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1087                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1088                 /* some BIOSes reserve this area in a pnp some don't */
1089                 if (ret)
1090                         intel_private.resource_valid = 0;
1091         }
1092 }
1093
1094 static void intel_i9xx_setup_flush(void)
1095 {
1096         /* return if already configured */
1097         if (intel_private.ifp_resource.start)
1098                 return;
1099
1100         if (INTEL_GTT_GEN == 6)
1101                 return;
1102
1103         /* setup a resource for this object */
1104         intel_private.ifp_resource.name = "Intel Flush Page";
1105         intel_private.ifp_resource.flags = IORESOURCE_MEM;
1106
1107         /* Setup chipset flush for 915 */
1108         if (IS_G33 || INTEL_GTT_GEN >= 4) {
1109                 intel_i965_g33_setup_chipset_flush();
1110         } else {
1111                 intel_i915_setup_chipset_flush();
1112         }
1113
1114         if (intel_private.ifp_resource.start)
1115                 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1116         if (!intel_private.i9xx_flush_page)
1117                 dev_err(&intel_private.pcidev->dev,
1118                         "can't ioremap flush page - no chipset flushing\n");
1119 }
1120
1121 static int intel_i9xx_configure(void)
1122 {
1123         struct aper_size_info_fixed *current_size;
1124         u32 temp;
1125         u16 gmch_ctrl;
1126         int i;
1127
1128         current_size = A_SIZE_FIX(agp_bridge->current_size);
1129
1130         pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
1131
1132         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1133
1134         pci_read_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, &gmch_ctrl);
1135         gmch_ctrl |= I830_GMCH_ENABLED;
1136         pci_write_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, gmch_ctrl);
1137
1138         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
1139         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1140
1141         if (agp_bridge->driver->needs_scratch_page) {
1142                 for (i = intel_private.base.gtt_stolen_entries; i <
1143                                 intel_private.base.gtt_total_entries; i++) {
1144                         writel(agp_bridge->scratch_page, intel_private.gtt+i);
1145                 }
1146                 readl(intel_private.gtt+i-1);   /* PCI Posting. */
1147         }
1148
1149         global_cache_flush();
1150
1151         intel_i9xx_setup_flush();
1152
1153         return 0;
1154 }
1155
1156 static void intel_i915_cleanup(void)
1157 {
1158         if (intel_private.i9xx_flush_page)
1159                 iounmap(intel_private.i9xx_flush_page);
1160         if (intel_private.resource_valid)
1161                 release_resource(&intel_private.ifp_resource);
1162         intel_private.ifp_resource.start = 0;
1163         intel_private.resource_valid = 0;
1164         iounmap(intel_private.gtt);
1165         iounmap(intel_private.registers);
1166 }
1167
1168 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1169 {
1170         if (intel_private.i9xx_flush_page)
1171                 writel(1, intel_private.i9xx_flush_page);
1172 }
1173
1174 static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1175                                      int type)
1176 {
1177         int num_entries;
1178         void *temp;
1179         int ret = -EINVAL;
1180         int mask_type;
1181
1182         if (mem->page_count == 0)
1183                 goto out;
1184
1185         temp = agp_bridge->current_size;
1186         num_entries = A_SIZE_FIX(temp)->num_entries;
1187
1188         if (pg_start < intel_private.base.gtt_stolen_entries) {
1189                 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1190                            "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
1191                            pg_start, intel_private.base.gtt_stolen_entries);
1192
1193                 dev_info(&intel_private.pcidev->dev,
1194                          "trying to insert into local/stolen memory\n");
1195                 goto out_err;
1196         }
1197
1198         if ((pg_start + mem->page_count) > num_entries)
1199                 goto out_err;
1200
1201         /* The i915 can't check the GTT for entries since it's read only;
1202          * depend on the caller to make the correct offset decisions.
1203          */
1204
1205         if (type != mem->type)
1206                 goto out_err;
1207
1208         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1209
1210         if (INTEL_GTT_GEN != 6 && mask_type != 0 &&
1211             mask_type != AGP_PHYS_MEMORY &&
1212             mask_type != INTEL_AGP_CACHED_MEMORY)
1213                 goto out_err;
1214
1215         if (!mem->is_flushed)
1216                 global_cache_flush();
1217
1218         intel_agp_insert_sg_entries(mem, pg_start, mask_type);
1219
1220  out:
1221         ret = 0;
1222  out_err:
1223         mem->is_flushed = true;
1224         return ret;
1225 }
1226
1227 static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1228                                      int type)
1229 {
1230         int i;
1231
1232         if (mem->page_count == 0)
1233                 return 0;
1234
1235         if (pg_start < intel_private.base.gtt_stolen_entries) {
1236                 dev_info(&intel_private.pcidev->dev,
1237                          "trying to disable local/stolen memory\n");
1238                 return -EINVAL;
1239         }
1240
1241         for (i = pg_start; i < (mem->page_count + pg_start); i++)
1242                 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1243
1244         readl(intel_private.gtt+i-1);
1245
1246         return 0;
1247 }
1248
1249 /* The intel i915 automatically initializes the agp aperture during POST.
1250  * Use the memory already set aside for in the GTT.
1251  */
1252 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1253 {
1254         int page_order, ret;
1255         struct aper_size_info_fixed *size;
1256         int num_entries;
1257         u32 temp, temp2;
1258         int gtt_map_size;
1259
1260         size = agp_bridge->current_size;
1261         page_order = size->page_order;
1262         num_entries = size->num_entries;
1263         agp_bridge->gatt_table_real = NULL;
1264
1265         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1266         pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
1267
1268         temp &= 0xfff80000;
1269
1270         intel_private.registers = ioremap(temp, 128 * 4096);
1271         if (!intel_private.registers)
1272                 return -ENOMEM;
1273
1274         intel_private.base.gtt_total_entries = intel_gtt_total_entries();
1275         gtt_map_size = intel_private.base.gtt_total_entries * 4;
1276
1277         intel_private.gtt = ioremap(temp2, gtt_map_size);
1278         if (!intel_private.gtt) {
1279                 iounmap(intel_private.registers);
1280                 return -ENOMEM;
1281         }
1282
1283         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1284         global_cache_flush();   /* FIXME: ? */
1285
1286         ret = intel_gtt_init();
1287         if (ret != 0) {
1288                 iounmap(intel_private.gtt);
1289                 return ret;
1290         }
1291
1292         agp_bridge->gatt_table = NULL;
1293
1294         agp_bridge->gatt_bus_addr = temp;
1295
1296         return 0;
1297 }
1298
1299 /*
1300  * The i965 supports 36-bit physical addresses, but to keep
1301  * the format of the GTT the same, the bits that don't fit
1302  * in a 32-bit word are shifted down to bits 4..7.
1303  *
1304  * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1305  * is always zero on 32-bit architectures, so no need to make
1306  * this conditional.
1307  */
1308 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1309                                             dma_addr_t addr, int type)
1310 {
1311         /* Shift high bits down */
1312         addr |= (addr >> 28) & 0xf0;
1313
1314         /* Type checking must be done elsewhere */
1315         return addr | bridge->driver->masks[type].mask;
1316 }
1317
1318 static unsigned long intel_gen6_mask_memory(struct agp_bridge_data *bridge,
1319                                             dma_addr_t addr, int type)
1320 {
1321         /* gen6 has bit11-4 for physical addr bit39-32 */
1322         addr |= (addr >> 28) & 0xff0;
1323
1324         /* Type checking must be done elsewhere */
1325         return addr | bridge->driver->masks[type].mask;
1326 }
1327
1328 static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1329 {
1330         u16 snb_gmch_ctl;
1331
1332         switch (intel_private.bridge_dev->device) {
1333         case PCI_DEVICE_ID_INTEL_GM45_HB:
1334         case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB:
1335         case PCI_DEVICE_ID_INTEL_Q45_HB:
1336         case PCI_DEVICE_ID_INTEL_G45_HB:
1337         case PCI_DEVICE_ID_INTEL_G41_HB:
1338         case PCI_DEVICE_ID_INTEL_B43_HB:
1339         case PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB:
1340         case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB:
1341         case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB:
1342         case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB:
1343                 *gtt_offset = *gtt_size = MB(2);
1344                 break;
1345         case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB:
1346         case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB:
1347         case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB:
1348                 *gtt_offset = MB(2);
1349
1350                 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1351                 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
1352                 default:
1353                 case SNB_GTT_SIZE_0M:
1354                         printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
1355                         *gtt_size = MB(0);
1356                         break;
1357                 case SNB_GTT_SIZE_1M:
1358                         *gtt_size = MB(1);
1359                         break;
1360                 case SNB_GTT_SIZE_2M:
1361                         *gtt_size = MB(2);
1362                         break;
1363                 }
1364                 break;
1365         default:
1366                 *gtt_offset = *gtt_size = KB(512);
1367         }
1368 }
1369
1370 /* The intel i965 automatically initializes the agp aperture during POST.
1371  * Use the memory already set aside for in the GTT.
1372  */
1373 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1374 {
1375         int page_order, ret;
1376         struct aper_size_info_fixed *size;
1377         int num_entries;
1378         u32 temp;
1379         int gtt_offset, gtt_size;
1380
1381         size = agp_bridge->current_size;
1382         page_order = size->page_order;
1383         num_entries = size->num_entries;
1384         agp_bridge->gatt_table_real = NULL;
1385
1386         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1387
1388         temp &= 0xfff00000;
1389
1390         intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
1391
1392         intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1393
1394         if (!intel_private.gtt)
1395                 return -ENOMEM;
1396
1397         intel_private.base.gtt_total_entries = gtt_size / 4;
1398
1399         intel_private.registers = ioremap(temp, 128 * 4096);
1400         if (!intel_private.registers) {
1401                 iounmap(intel_private.gtt);
1402                 return -ENOMEM;
1403         }
1404
1405         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1406         global_cache_flush();   /* FIXME: ? */
1407
1408         ret = intel_gtt_init();
1409         if (ret != 0) {
1410                 iounmap(intel_private.gtt);
1411                 return ret;
1412         }
1413
1414         agp_bridge->gatt_table = NULL;
1415
1416         agp_bridge->gatt_bus_addr = temp;
1417
1418         return 0;
1419 }
1420
1421 static const struct agp_bridge_driver intel_810_driver = {
1422         .owner                  = THIS_MODULE,
1423         .aperture_sizes         = intel_i810_sizes,
1424         .size_type              = FIXED_APER_SIZE,
1425         .num_aperture_sizes     = 2,
1426         .needs_scratch_page     = true,
1427         .configure              = intel_i810_configure,
1428         .fetch_size             = intel_i810_fetch_size,
1429         .cleanup                = intel_i810_cleanup,
1430         .mask_memory            = intel_i810_mask_memory,
1431         .masks                  = intel_i810_masks,
1432         .agp_enable             = intel_fake_agp_enable,
1433         .cache_flush            = global_cache_flush,
1434         .create_gatt_table      = agp_generic_create_gatt_table,
1435         .free_gatt_table        = agp_generic_free_gatt_table,
1436         .insert_memory          = intel_i810_insert_entries,
1437         .remove_memory          = intel_i810_remove_entries,
1438         .alloc_by_type          = intel_i810_alloc_by_type,
1439         .free_by_type           = intel_i810_free_by_type,
1440         .agp_alloc_page         = agp_generic_alloc_page,
1441         .agp_alloc_pages        = agp_generic_alloc_pages,
1442         .agp_destroy_page       = agp_generic_destroy_page,
1443         .agp_destroy_pages      = agp_generic_destroy_pages,
1444         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1445 };
1446
1447 static const struct agp_bridge_driver intel_830_driver = {
1448         .owner                  = THIS_MODULE,
1449         .aperture_sizes         = intel_fake_agp_sizes,
1450         .size_type              = FIXED_APER_SIZE,
1451         .num_aperture_sizes     = 4,
1452         .needs_scratch_page     = true,
1453         .configure              = intel_i830_configure,
1454         .fetch_size             = intel_fake_agp_fetch_size,
1455         .cleanup                = intel_i830_cleanup,
1456         .mask_memory            = intel_i810_mask_memory,
1457         .masks                  = intel_i810_masks,
1458         .agp_enable             = intel_fake_agp_enable,
1459         .cache_flush            = global_cache_flush,
1460         .create_gatt_table      = intel_i830_create_gatt_table,
1461         .free_gatt_table        = intel_fake_agp_free_gatt_table,
1462         .insert_memory          = intel_i830_insert_entries,
1463         .remove_memory          = intel_i830_remove_entries,
1464         .alloc_by_type          = intel_fake_agp_alloc_by_type,
1465         .free_by_type           = intel_i810_free_by_type,
1466         .agp_alloc_page         = agp_generic_alloc_page,
1467         .agp_alloc_pages        = agp_generic_alloc_pages,
1468         .agp_destroy_page       = agp_generic_destroy_page,
1469         .agp_destroy_pages      = agp_generic_destroy_pages,
1470         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1471         .chipset_flush          = intel_i830_chipset_flush,
1472 };
1473
1474 static const struct agp_bridge_driver intel_915_driver = {
1475         .owner                  = THIS_MODULE,
1476         .aperture_sizes         = intel_fake_agp_sizes,
1477         .size_type              = FIXED_APER_SIZE,
1478         .num_aperture_sizes     = 4,
1479         .needs_scratch_page     = true,
1480         .configure              = intel_i9xx_configure,
1481         .fetch_size             = intel_fake_agp_fetch_size,
1482         .cleanup                = intel_i915_cleanup,
1483         .mask_memory            = intel_i810_mask_memory,
1484         .masks                  = intel_i810_masks,
1485         .agp_enable             = intel_fake_agp_enable,
1486         .cache_flush            = global_cache_flush,
1487         .create_gatt_table      = intel_i915_create_gatt_table,
1488         .free_gatt_table        = intel_fake_agp_free_gatt_table,
1489         .insert_memory          = intel_i915_insert_entries,
1490         .remove_memory          = intel_i915_remove_entries,
1491         .alloc_by_type          = intel_fake_agp_alloc_by_type,
1492         .free_by_type           = intel_i810_free_by_type,
1493         .agp_alloc_page         = agp_generic_alloc_page,
1494         .agp_alloc_pages        = agp_generic_alloc_pages,
1495         .agp_destroy_page       = agp_generic_destroy_page,
1496         .agp_destroy_pages      = agp_generic_destroy_pages,
1497         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1498         .chipset_flush          = intel_i915_chipset_flush,
1499 #ifdef USE_PCI_DMA_API
1500         .agp_map_page           = intel_agp_map_page,
1501         .agp_unmap_page         = intel_agp_unmap_page,
1502         .agp_map_memory         = intel_agp_map_memory,
1503         .agp_unmap_memory       = intel_agp_unmap_memory,
1504 #endif
1505 };
1506
1507 static const struct agp_bridge_driver intel_i965_driver = {
1508         .owner                  = THIS_MODULE,
1509         .aperture_sizes         = intel_fake_agp_sizes,
1510         .size_type              = FIXED_APER_SIZE,
1511         .num_aperture_sizes     = 4,
1512         .needs_scratch_page     = true,
1513         .configure              = intel_i9xx_configure,
1514         .fetch_size             = intel_fake_agp_fetch_size,
1515         .cleanup                = intel_i915_cleanup,
1516         .mask_memory            = intel_i965_mask_memory,
1517         .masks                  = intel_i810_masks,
1518         .agp_enable             = intel_fake_agp_enable,
1519         .cache_flush            = global_cache_flush,
1520         .create_gatt_table      = intel_i965_create_gatt_table,
1521         .free_gatt_table        = intel_fake_agp_free_gatt_table,
1522         .insert_memory          = intel_i915_insert_entries,
1523         .remove_memory          = intel_i915_remove_entries,
1524         .alloc_by_type          = intel_fake_agp_alloc_by_type,
1525         .free_by_type           = intel_i810_free_by_type,
1526         .agp_alloc_page         = agp_generic_alloc_page,
1527         .agp_alloc_pages        = agp_generic_alloc_pages,
1528         .agp_destroy_page       = agp_generic_destroy_page,
1529         .agp_destroy_pages      = agp_generic_destroy_pages,
1530         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1531         .chipset_flush          = intel_i915_chipset_flush,
1532 #ifdef USE_PCI_DMA_API
1533         .agp_map_page           = intel_agp_map_page,
1534         .agp_unmap_page         = intel_agp_unmap_page,
1535         .agp_map_memory         = intel_agp_map_memory,
1536         .agp_unmap_memory       = intel_agp_unmap_memory,
1537 #endif
1538 };
1539
1540 static const struct agp_bridge_driver intel_gen6_driver = {
1541         .owner                  = THIS_MODULE,
1542         .aperture_sizes         = intel_fake_agp_sizes,
1543         .size_type              = FIXED_APER_SIZE,
1544         .num_aperture_sizes     = 4,
1545         .needs_scratch_page     = true,
1546         .configure              = intel_i9xx_configure,
1547         .fetch_size             = intel_fake_agp_fetch_size,
1548         .cleanup                = intel_i915_cleanup,
1549         .mask_memory            = intel_gen6_mask_memory,
1550         .masks                  = intel_gen6_masks,
1551         .agp_enable             = intel_fake_agp_enable,
1552         .cache_flush            = global_cache_flush,
1553         .create_gatt_table      = intel_i965_create_gatt_table,
1554         .free_gatt_table        = intel_fake_agp_free_gatt_table,
1555         .insert_memory          = intel_i915_insert_entries,
1556         .remove_memory          = intel_i915_remove_entries,
1557         .alloc_by_type          = intel_fake_agp_alloc_by_type,
1558         .free_by_type           = intel_i810_free_by_type,
1559         .agp_alloc_page         = agp_generic_alloc_page,
1560         .agp_alloc_pages        = agp_generic_alloc_pages,
1561         .agp_destroy_page       = agp_generic_destroy_page,
1562         .agp_destroy_pages      = agp_generic_destroy_pages,
1563         .agp_type_to_mask_type  = intel_gen6_type_to_mask_type,
1564         .chipset_flush          = intel_i915_chipset_flush,
1565 #ifdef USE_PCI_DMA_API
1566         .agp_map_page           = intel_agp_map_page,
1567         .agp_unmap_page         = intel_agp_unmap_page,
1568         .agp_map_memory         = intel_agp_map_memory,
1569         .agp_unmap_memory       = intel_agp_unmap_memory,
1570 #endif
1571 };
1572
1573 static const struct agp_bridge_driver intel_g33_driver = {
1574         .owner                  = THIS_MODULE,
1575         .aperture_sizes         = intel_fake_agp_sizes,
1576         .size_type              = FIXED_APER_SIZE,
1577         .num_aperture_sizes     = 4,
1578         .needs_scratch_page     = true,
1579         .configure              = intel_i9xx_configure,
1580         .fetch_size             = intel_fake_agp_fetch_size,
1581         .cleanup                = intel_i915_cleanup,
1582         .mask_memory            = intel_i965_mask_memory,
1583         .masks                  = intel_i810_masks,
1584         .agp_enable             = intel_fake_agp_enable,
1585         .cache_flush            = global_cache_flush,
1586         .create_gatt_table      = intel_i915_create_gatt_table,
1587         .free_gatt_table        = intel_fake_agp_free_gatt_table,
1588         .insert_memory          = intel_i915_insert_entries,
1589         .remove_memory          = intel_i915_remove_entries,
1590         .alloc_by_type          = intel_fake_agp_alloc_by_type,
1591         .free_by_type           = intel_i810_free_by_type,
1592         .agp_alloc_page         = agp_generic_alloc_page,
1593         .agp_alloc_pages        = agp_generic_alloc_pages,
1594         .agp_destroy_page       = agp_generic_destroy_page,
1595         .agp_destroy_pages      = agp_generic_destroy_pages,
1596         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1597         .chipset_flush          = intel_i915_chipset_flush,
1598 #ifdef USE_PCI_DMA_API
1599         .agp_map_page           = intel_agp_map_page,
1600         .agp_unmap_page         = intel_agp_unmap_page,
1601         .agp_map_memory         = intel_agp_map_memory,
1602         .agp_unmap_memory       = intel_agp_unmap_memory,
1603 #endif
1604 };
1605
1606 static const struct intel_gtt_driver i8xx_gtt_driver = {
1607         .gen = 2,
1608 };
1609 static const struct intel_gtt_driver i915_gtt_driver = {
1610         .gen = 3,
1611 };
1612 static const struct intel_gtt_driver g33_gtt_driver = {
1613         .gen = 3,
1614         .is_g33 = 1,
1615 };
1616 static const struct intel_gtt_driver pineview_gtt_driver = {
1617         .gen = 3,
1618         .is_pineview = 1, .is_g33 = 1,
1619 };
1620 static const struct intel_gtt_driver i965_gtt_driver = {
1621         .gen = 4,
1622 };
1623 static const struct intel_gtt_driver g4x_gtt_driver = {
1624         .gen = 5,
1625 };
1626 static const struct intel_gtt_driver ironlake_gtt_driver = {
1627         .gen = 5,
1628         .is_ironlake = 1,
1629 };
1630 static const struct intel_gtt_driver sandybridge_gtt_driver = {
1631         .gen = 6,
1632 };
1633
1634 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
1635  * driver and gmch_driver must be non-null, and find_gmch will determine
1636  * which one should be used if a gmch_chip_id is present.
1637  */
1638 static const struct intel_gtt_driver_description {
1639         unsigned int gmch_chip_id;
1640         char *name;
1641         const struct agp_bridge_driver *gmch_driver;
1642         const struct intel_gtt_driver *gtt_driver;
1643 } intel_gtt_chipsets[] = {
1644         { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", &intel_810_driver , NULL},
1645         { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", &intel_810_driver , NULL},
1646         { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", &intel_810_driver , NULL},
1647         { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", &intel_810_driver , NULL},
1648         { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1649                 &intel_830_driver , &i8xx_gtt_driver},
1650         { PCI_DEVICE_ID_INTEL_82845G_IG, "830M",
1651                 &intel_830_driver , &i8xx_gtt_driver},
1652         { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1653                 &intel_830_driver , &i8xx_gtt_driver},
1654         { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1655                 &intel_830_driver , &i8xx_gtt_driver},
1656         { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1657                 &intel_830_driver , &i8xx_gtt_driver},
1658         { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1659                 &intel_915_driver , &i915_gtt_driver },
1660         { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1661                 &intel_915_driver , &i915_gtt_driver },
1662         { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1663                 &intel_915_driver , &i915_gtt_driver },
1664         { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1665                 &intel_915_driver , &i915_gtt_driver },
1666         { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1667                 &intel_915_driver , &i915_gtt_driver },
1668         { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1669                 &intel_915_driver , &i915_gtt_driver },
1670         { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1671                 &intel_i965_driver , &i965_gtt_driver },
1672         { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1673                 &intel_i965_driver , &i965_gtt_driver },
1674         { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1675                 &intel_i965_driver , &i965_gtt_driver },
1676         { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1677                 &intel_i965_driver , &i965_gtt_driver },
1678         { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1679                 &intel_i965_driver , &i965_gtt_driver },
1680         { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1681                 &intel_i965_driver , &i965_gtt_driver },
1682         { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1683                 &intel_g33_driver , &g33_gtt_driver },
1684         { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1685                 &intel_g33_driver , &g33_gtt_driver },
1686         { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1687                 &intel_g33_driver , &g33_gtt_driver },
1688         { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1689                 &intel_g33_driver , &pineview_gtt_driver },
1690         { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1691                 &intel_g33_driver , &pineview_gtt_driver },
1692         { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1693                 &intel_i965_driver , &g4x_gtt_driver },
1694         { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1695                 &intel_i965_driver , &g4x_gtt_driver },
1696         { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1697                 &intel_i965_driver , &g4x_gtt_driver },
1698         { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1699                 &intel_i965_driver , &g4x_gtt_driver },
1700         { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1701                 &intel_i965_driver , &g4x_gtt_driver },
1702         { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1703                 &intel_i965_driver , &g4x_gtt_driver },
1704         { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1705             "HD Graphics", &intel_i965_driver , &ironlake_gtt_driver },
1706         { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1707             "HD Graphics", &intel_i965_driver , &ironlake_gtt_driver },
1708         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
1709             "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1710         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
1711             "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1712         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
1713             "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1714         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
1715             "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1716         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
1717             "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1718         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
1719             "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1720         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
1721             "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1722         { 0, NULL, NULL }
1723 };
1724
1725 static int find_gmch(u16 device)
1726 {
1727         struct pci_dev *gmch_device;
1728
1729         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1730         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1731                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1732                                              device, gmch_device);
1733         }
1734
1735         if (!gmch_device)
1736                 return 0;
1737
1738         intel_private.pcidev = gmch_device;
1739         return 1;
1740 }
1741
1742 int intel_gmch_probe(struct pci_dev *pdev,
1743                                       struct agp_bridge_data *bridge)
1744 {
1745         int i, mask;
1746         bridge->driver = NULL;
1747
1748         for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1749                 if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1750                         bridge->driver =
1751                                 intel_gtt_chipsets[i].gmch_driver;
1752                         intel_private.driver =
1753                                 intel_gtt_chipsets[i].gtt_driver;
1754                         break;
1755                 }
1756         }
1757
1758         if (!bridge->driver)
1759                 return 0;
1760
1761         bridge->dev_private_data = &intel_private;
1762         bridge->dev = pdev;
1763
1764         intel_private.bridge_dev = pci_dev_get(pdev);
1765
1766         dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1767
1768         if (bridge->driver->mask_memory == intel_gen6_mask_memory)
1769                 mask = 40;
1770         else if (bridge->driver->mask_memory == intel_i965_mask_memory)
1771                 mask = 36;
1772         else
1773                 mask = 32;
1774
1775         if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1776                 dev_err(&intel_private.pcidev->dev,
1777                         "set gfx device dma mask %d-bit failed!\n", mask);
1778         else
1779                 pci_set_consistent_dma_mask(intel_private.pcidev,
1780                                             DMA_BIT_MASK(mask));
1781
1782         if (bridge->driver == &intel_810_driver)
1783                 return 1;
1784
1785         intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries();
1786
1787         return 1;
1788 }
1789 EXPORT_SYMBOL(intel_gmch_probe);
1790
1791 void intel_gmch_remove(struct pci_dev *pdev)
1792 {
1793         if (intel_private.pcidev)
1794                 pci_dev_put(intel_private.pcidev);
1795         if (intel_private.bridge_dev)
1796                 pci_dev_put(intel_private.bridge_dev);
1797 }
1798 EXPORT_SYMBOL(intel_gmch_remove);
1799
1800 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1801 MODULE_LICENSE("GPL and additional rights");