drivers/char/agp/intel-agp.c

   1 /*
   2  * Intel AGPGART routines.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/init.h>
   8 #include <linux/kernel.h>
   9 #include <linux/pagemap.h>
  10 #include <linux/agp_backend.h>
  11 #include "agp.h"
  12
  13 /*
  14  * If we have Intel graphics, we're not going to have anything other than
  15  * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
  16  * on the Intel IOMMU support (CONFIG_DMAR).
  17  * Only newer chipsets need to bother with this, of course.
  18  */
  19 #ifdef CONFIG_DMAR
  20 #define USE_PCI_DMA_API 1
  21 #endif
  22
  23 #define PCI_DEVICE_ID_INTEL_E7221_HB    0x2588
  24 #define PCI_DEVICE_ID_INTEL_E7221_IG    0x258a
  25 #define PCI_DEVICE_ID_INTEL_82946GZ_HB      0x2970
  26 #define PCI_DEVICE_ID_INTEL_82946GZ_IG      0x2972
  27 #define PCI_DEVICE_ID_INTEL_82G35_HB     0x2980
  28 #define PCI_DEVICE_ID_INTEL_82G35_IG     0x2982
  29 #define PCI_DEVICE_ID_INTEL_82965Q_HB       0x2990
  30 #define PCI_DEVICE_ID_INTEL_82965Q_IG       0x2992
  31 #define PCI_DEVICE_ID_INTEL_82965G_HB       0x29A0
  32 #define PCI_DEVICE_ID_INTEL_82965G_IG       0x29A2
  33 #define PCI_DEVICE_ID_INTEL_82965GM_HB      0x2A00
  34 #define PCI_DEVICE_ID_INTEL_82965GM_IG      0x2A02
  35 #define PCI_DEVICE_ID_INTEL_82965GME_HB     0x2A10
  36 #define PCI_DEVICE_ID_INTEL_82965GME_IG     0x2A12
  37 #define PCI_DEVICE_ID_INTEL_82945GME_HB     0x27AC
  38 #define PCI_DEVICE_ID_INTEL_82945GME_IG     0x27AE
  39 #define PCI_DEVICE_ID_INTEL_IGDGM_HB        0xA010
  40 #define PCI_DEVICE_ID_INTEL_IGDGM_IG        0xA011
  41 #define PCI_DEVICE_ID_INTEL_IGDG_HB         0xA000
  42 #define PCI_DEVICE_ID_INTEL_IGDG_IG         0xA001
  43 #define PCI_DEVICE_ID_INTEL_G33_HB          0x29C0
  44 #define PCI_DEVICE_ID_INTEL_G33_IG          0x29C2
  45 #define PCI_DEVICE_ID_INTEL_Q35_HB          0x29B0
  46 #define PCI_DEVICE_ID_INTEL_Q35_IG          0x29B2
  47 #define PCI_DEVICE_ID_INTEL_Q33_HB          0x29D0
  48 #define PCI_DEVICE_ID_INTEL_Q33_IG          0x29D2
  49 #define PCI_DEVICE_ID_INTEL_B43_HB          0x2E40
  50 #define PCI_DEVICE_ID_INTEL_B43_IG          0x2E42
  51 #define PCI_DEVICE_ID_INTEL_GM45_HB         0x2A40
  52 #define PCI_DEVICE_ID_INTEL_GM45_IG         0x2A42
  53 #define PCI_DEVICE_ID_INTEL_IGD_E_HB        0x2E00
  54 #define PCI_DEVICE_ID_INTEL_IGD_E_IG        0x2E02
  55 #define PCI_DEVICE_ID_INTEL_Q45_HB          0x2E10
  56 #define PCI_DEVICE_ID_INTEL_Q45_IG          0x2E12
  57 #define PCI_DEVICE_ID_INTEL_G45_HB          0x2E20
  58 #define PCI_DEVICE_ID_INTEL_G45_IG          0x2E22
  59 #define PCI_DEVICE_ID_INTEL_G41_HB          0x2E30
  60 #define PCI_DEVICE_ID_INTEL_G41_IG          0x2E32
  61 #define PCI_DEVICE_ID_INTEL_IGDNG_D_HB      0x0040
  62 #define PCI_DEVICE_ID_INTEL_IGDNG_D_IG      0x0042
  63 #define PCI_DEVICE_ID_INTEL_IGDNG_M_HB      0x0044
  64 #define PCI_DEVICE_ID_INTEL_IGDNG_MA_HB     0x0062
  65 #define PCI_DEVICE_ID_INTEL_IGDNG_M_IG      0x0046
  66
  67 /* cover 915 and 945 variants */
  68 #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
  69                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \
  70                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \
  71                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \
  72                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \
  73                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB)
  74
  75 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
  76                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \
  77                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
  78                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
  79                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
  80                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
  81
  82 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
  83                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
  84                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \
  85                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \
  86                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB)
  87
  88 #define IS_IGD (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \
  89                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB)
  90
  91 #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \
  92                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
  93                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
  94                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \
  95                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \
  96                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \
  97                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_D_HB || \
  98                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_M_HB || \
  99                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_MA_HB)
 100
 101 extern int agp_memory_reserved;
 102
 103
 104 /* Intel 815 register */
 105 #define INTEL_815_APCONT        0x51
 106 #define INTEL_815_ATTBASE_MASK  ~0x1FFFFFFF
 107
 108 /* Intel i820 registers */
 109 #define INTEL_I820_RDCR         0x51
 110 #define INTEL_I820_ERRSTS       0xc8
 111
 112 /* Intel i840 registers */
 113 #define INTEL_I840_MCHCFG       0x50
 114 #define INTEL_I840_ERRSTS       0xc8
 115
 116 /* Intel i850 registers */
 117 #define INTEL_I850_MCHCFG       0x50
 118 #define INTEL_I850_ERRSTS       0xc8
 119
 120 /* intel 915G registers */
 121 #define I915_GMADDR     0x18
 122 #define I915_MMADDR     0x10
 123 #define I915_PTEADDR    0x1C
 124 #define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
 125 #define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
 126 #define G33_GMCH_GMS_STOLEN_128M        (0x8 << 4)
 127 #define G33_GMCH_GMS_STOLEN_256M        (0x9 << 4)
 128 #define INTEL_GMCH_GMS_STOLEN_96M       (0xa << 4)
 129 #define INTEL_GMCH_GMS_STOLEN_160M      (0xb << 4)
 130 #define INTEL_GMCH_GMS_STOLEN_224M      (0xc << 4)
 131 #define INTEL_GMCH_GMS_STOLEN_352M      (0xd << 4)
 132
 133 #define I915_IFPADDR    0x60
 134
 135 /* Intel 965G registers */
 136 #define I965_MSAC 0x62
 137 #define I965_IFPADDR    0x70
 138
 139 /* Intel 7505 registers */
 140 #define INTEL_I7505_APSIZE      0x74
 141 #define INTEL_I7505_NCAPID      0x60
 142 #define INTEL_I7505_NISTAT      0x6c
 143 #define INTEL_I7505_ATTBASE     0x78
 144 #define INTEL_I7505_ERRSTS      0x42
 145 #define INTEL_I7505_AGPCTRL     0x70
 146 #define INTEL_I7505_MCHCFG      0x50
 147
 148 static const struct aper_size_info_fixed intel_i810_sizes[] =
 149 {
 150         {64, 16384, 4},
 151         /* The 32M mode still requires a 64k gatt */
 152         {32, 8192, 4}
 153 };
 154
 155 #define AGP_DCACHE_MEMORY       1
 156 #define AGP_PHYS_MEMORY         2
 157 #define INTEL_AGP_CACHED_MEMORY 3
 158
 159 static struct gatt_mask intel_i810_masks[] =
 160 {
 161         {.mask = I810_PTE_VALID, .type = 0},
 162         {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
 163         {.mask = I810_PTE_VALID, .type = 0},
 164         {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
 165          .type = INTEL_AGP_CACHED_MEMORY}
 166 };
 167
 168 static struct _intel_private {
 169         struct pci_dev *pcidev; /* device one */
 170         u8 __iomem *registers;
 171         u32 __iomem *gtt;               /* I915G */
 172         int num_dcache_entries;
 173         /* gtt_entries is the number of gtt entries that are already mapped
 174          * to stolen memory.  Stolen memory is larger than the memory mapped
 175          * through gtt_entries, as it includes some reserved space for the BIOS
 176          * popup and for the GTT.
 177          */
 178         int gtt_entries;                        /* i830+ */
 179         union {
 180                 void __iomem *i9xx_flush_page;
 181                 void *i8xx_flush_page;
 182         };
 183         struct page *i8xx_page;
 184         struct resource ifp_resource;
 185         int resource_valid;
 186 } intel_private;
 187
 188 #ifdef USE_PCI_DMA_API
 189 static int intel_agp_map_page(struct page *page, dma_addr_t *ret)
 190 {
 191         *ret = pci_map_page(intel_private.pcidev, page, 0,
 192                             PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 193         if (pci_dma_mapping_error(intel_private.pcidev, *ret))
 194                 return -EINVAL;
 195         return 0;
 196 }
 197
 198 static void intel_agp_unmap_page(struct page *page, dma_addr_t dma)
 199 {
 200         pci_unmap_page(intel_private.pcidev, dma,
 201                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 202 }
 203
 204 static void intel_agp_free_sglist(struct agp_memory *mem)
 205 {
 206         struct sg_table st;
 207
 208         st.sgl = mem->sg_list;
 209         st.orig_nents = st.nents = mem->page_count;
 210
 211         sg_free_table(&st);
 212
 213         mem->sg_list = NULL;
 214         mem->num_sg = 0;
 215 }
 216
 217 static int intel_agp_map_memory(struct agp_memory *mem)
 218 {
 219         struct sg_table st;
 220         struct scatterlist *sg;
 221         int i;
 222
 223         DBG("try mapping %lu pages\n", (unsigned long)mem->page_count);
 224
 225         if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL))
 226                 return -ENOMEM;
 227
 228         mem->sg_list = sg = st.sgl;
 229
 230         for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg))
 231                 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0);
 232
 233         mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list,
 234                                  mem->page_count, PCI_DMA_BIDIRECTIONAL);
 235         if (unlikely(!mem->num_sg)) {
 236                 intel_agp_free_sglist(mem);
 237                 return -ENOMEM;
 238         }
 239         return 0;
 240 }
 241
 242 static void intel_agp_unmap_memory(struct agp_memory *mem)
 243 {
 244         DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
 245
 246         pci_unmap_sg(intel_private.pcidev, mem->sg_list,
 247                      mem->page_count, PCI_DMA_BIDIRECTIONAL);
 248         intel_agp_free_sglist(mem);
 249 }
 250
 251 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
 252                                         off_t pg_start, int mask_type)
 253 {
 254         struct scatterlist *sg;
 255         int i, j;
 256
 257         j = pg_start;
 258
 259         WARN_ON(!mem->num_sg);
 260
 261         if (mem->num_sg == mem->page_count) {
 262                 for_each_sg(mem->sg_list, sg, mem->page_count, i) {
 263                         writel(agp_bridge->driver->mask_memory(agp_bridge,
 264                                         sg_dma_address(sg), mask_type),
 265                                         intel_private.gtt+j);
 266                         j++;
 267                 }
 268         } else {
 269                 /* sg may merge pages, but we have to seperate
 270                  * per-page addr for GTT */
 271                 unsigned int len, m;
 272
 273                 for_each_sg(mem->sg_list, sg, mem->num_sg, i) {
 274                         len = sg_dma_len(sg) / PAGE_SIZE;
 275                         for (m = 0; m < len; m++) {
 276                                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 277                                                                        sg_dma_address(sg) + m * PAGE_SIZE,
 278                                                                        mask_type),
 279                                        intel_private.gtt+j);
 280                                 j++;
 281                         }
 282                 }
 283         }
 284         readl(intel_private.gtt+j-1);
 285 }
 286
 287 #else
 288
 289 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
 290                                         off_t pg_start, int mask_type)
 291 {
 292         int i, j;
 293
 294         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 295                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 296                                 page_to_phys(mem->pages[i]), mask_type),
 297                        intel_private.gtt+j);
 298         }
 299
 300         readl(intel_private.gtt+j-1);
 301 }
 302
 303 #endif
 304
 305 static int intel_i810_fetch_size(void)
 306 {
 307         u32 smram_miscc;
 308         struct aper_size_info_fixed *values;
 309
 310         pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
 311         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 312
 313         if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
 314                 dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n");
 315                 return 0;
 316         }
 317         if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
 318                 agp_bridge->previous_size =
 319                         agp_bridge->current_size = (void *) (values + 1);
 320                 agp_bridge->aperture_size_idx = 1;
 321                 return values[1].size;
 322         } else {
 323                 agp_bridge->previous_size =
 324                         agp_bridge->current_size = (void *) (values);
 325                 agp_bridge->aperture_size_idx = 0;
 326                 return values[0].size;
 327         }
 328
 329         return 0;
 330 }
 331
 332 static int intel_i810_configure(void)
 333 {
 334         struct aper_size_info_fixed *current_size;
 335         u32 temp;
 336         int i;
 337
 338         current_size = A_SIZE_FIX(agp_bridge->current_size);
 339
 340         if (!intel_private.registers) {
 341                 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 342                 temp &= 0xfff80000;
 343
 344                 intel_private.registers = ioremap(temp, 128 * 4096);
 345                 if (!intel_private.registers) {
 346                         dev_err(&intel_private.pcidev->dev,
 347                                 "can't remap memory\n");
 348                         return -ENOMEM;
 349                 }
 350         }
 351
 352         if ((readl(intel_private.registers+I810_DRAM_CTL)
 353                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 354                 /* This will need to be dynamically assigned */
 355                 dev_info(&intel_private.pcidev->dev,
 356                          "detected 4MB dedicated video ram\n");
 357                 intel_private.num_dcache_entries = 1024;
 358         }
 359         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 360         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 361         writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 362         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 363
 364         if (agp_bridge->driver->needs_scratch_page) {
 365                 for (i = 0; i < current_size->num_entries; i++) {
 366                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 367                 }
 368                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
 369         }
 370         global_cache_flush();
 371         return 0;
 372 }
 373
 374 static void intel_i810_cleanup(void)
 375 {
 376         writel(0, intel_private.registers+I810_PGETBL_CTL);
 377         readl(intel_private.registers); /* PCI Posting. */
 378         iounmap(intel_private.registers);
 379 }
 380
 381 static void intel_i810_tlbflush(struct agp_memory *mem)
 382 {
 383         return;
 384 }
 385
 386 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 387 {
 388         return;
 389 }
 390
 391 /* Exists to support ARGB cursors */
 392 static struct page *i8xx_alloc_pages(void)
 393 {
 394         struct page *page;
 395
 396         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
 397         if (page == NULL)
 398                 return NULL;
 399
 400         if (set_pages_uc(page, 4) < 0) {
 401                 set_pages_wb(page, 4);
 402                 __free_pages(page, 2);
 403                 return NULL;
 404         }
 405         get_page(page);
 406         atomic_inc(&agp_bridge->current_memory_agp);
 407         return page;
 408 }
 409
 410 static void i8xx_destroy_pages(struct page *page)
 411 {
 412         if (page == NULL)
 413                 return;
 414
 415         set_pages_wb(page, 4);
 416         put_page(page);
 417         __free_pages(page, 2);
 418         atomic_dec(&agp_bridge->current_memory_agp);
 419 }
 420
 421 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
 422                                         int type)
 423 {
 424         if (type < AGP_USER_TYPES)
 425                 return type;
 426         else if (type == AGP_USER_CACHED_MEMORY)
 427                 return INTEL_AGP_CACHED_MEMORY;
 428         else
 429                 return 0;
 430 }
 431
 432 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
 433                                 int type)
 434 {
 435         int i, j, num_entries;
 436         void *temp;
 437         int ret = -EINVAL;
 438         int mask_type;
 439
 440         if (mem->page_count == 0)
 441                 goto out;
 442
 443         temp = agp_bridge->current_size;
 444         num_entries = A_SIZE_FIX(temp)->num_entries;
 445
 446         if ((pg_start + mem->page_count) > num_entries)
 447                 goto out_err;
 448
 449
 450         for (j = pg_start; j < (pg_start + mem->page_count); j++) {
 451                 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
 452                         ret = -EBUSY;
 453                         goto out_err;
 454                 }
 455         }
 456
 457         if (type != mem->type)
 458                 goto out_err;
 459
 460         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 461
 462         switch (mask_type) {
 463         case AGP_DCACHE_MEMORY:
 464                 if (!mem->is_flushed)
 465                         global_cache_flush();
 466                 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 467                         writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
 468                                intel_private.registers+I810_PTE_BASE+(i*4));
 469                 }
 470                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 471                 break;
 472         case AGP_PHYS_MEMORY:
 473         case AGP_NORMAL_MEMORY:
 474                 if (!mem->is_flushed)
 475                         global_cache_flush();
 476                 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 477                         writel(agp_bridge->driver->mask_memory(agp_bridge,
 478                                         page_to_phys(mem->pages[i]), mask_type),
 479                                intel_private.registers+I810_PTE_BASE+(j*4));
 480                 }
 481                 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 482                 break;
 483         default:
 484                 goto out_err;
 485         }
 486
 487         agp_bridge->driver->tlb_flush(mem);
 488 out:
 489         ret = 0;
 490 out_err:
 491         mem->is_flushed = true;
 492         return ret;
 493 }
 494
 495 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
 496                                 int type)
 497 {
 498         int i;
 499
 500         if (mem->page_count == 0)
 501                 return 0;
 502
 503         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 504                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 505         }
 506         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 507
 508         agp_bridge->driver->tlb_flush(mem);
 509         return 0;
 510 }
 511
 512 /*
 513  * The i810/i830 requires a physical address to program its mouse
 514  * pointer into hardware.
 515  * However the Xserver still writes to it through the agp aperture.
 516  */
 517 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
 518 {
 519         struct agp_memory *new;
 520         struct page *page;
 521
 522         switch (pg_count) {
 523         case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
 524                 break;
 525         case 4:
 526                 /* kludge to get 4 physical pages for ARGB cursor */
 527                 page = i8xx_alloc_pages();
 528                 break;
 529         default:
 530                 return NULL;
 531         }
 532
 533         if (page == NULL)
 534                 return NULL;
 535
 536         new = agp_create_memory(pg_count);
 537         if (new == NULL)
 538                 return NULL;
 539
 540         new->pages[0] = page;
 541         if (pg_count == 4) {
 542                 /* kludge to get 4 physical pages for ARGB cursor */
 543                 new->pages[1] = new->pages[0] + 1;
 544                 new->pages[2] = new->pages[1] + 1;
 545                 new->pages[3] = new->pages[2] + 1;
 546         }
 547         new->page_count = pg_count;
 548         new->num_scratch_pages = pg_count;
 549         new->type = AGP_PHYS_MEMORY;
 550         new->physical = page_to_phys(new->pages[0]);
 551         return new;
 552 }
 553
 554 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
 555 {
 556         struct agp_memory *new;
 557
 558         if (type == AGP_DCACHE_MEMORY) {
 559                 if (pg_count != intel_private.num_dcache_entries)
 560                         return NULL;
 561
 562                 new = agp_create_memory(1);
 563                 if (new == NULL)
 564                         return NULL;
 565
 566                 new->type = AGP_DCACHE_MEMORY;
 567                 new->page_count = pg_count;
 568                 new->num_scratch_pages = 0;
 569                 agp_free_page_array(new);
 570                 return new;
 571         }
 572         if (type == AGP_PHYS_MEMORY)
 573                 return alloc_agpphysmem_i8xx(pg_count, type);
 574         return NULL;
 575 }
 576
 577 static void intel_i810_free_by_type(struct agp_memory *curr)
 578 {
 579         agp_free_key(curr->key);
 580         if (curr->type == AGP_PHYS_MEMORY) {
 581                 if (curr->page_count == 4)
 582                         i8xx_destroy_pages(curr->pages[0]);
 583                 else {
 584                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 585                                                              AGP_PAGE_DESTROY_UNMAP);
 586                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 587                                                              AGP_PAGE_DESTROY_FREE);
 588                 }
 589                 agp_free_page_array(curr);
 590         }
 591         kfree(curr);
 592 }
 593
 594 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
 595                                             dma_addr_t addr, int type)
 596 {
 597         /* Type checking must be done elsewhere */
 598         return addr | bridge->driver->masks[type].mask;
 599 }
 600
 601 static struct aper_size_info_fixed intel_i830_sizes[] =
 602 {
 603         {128, 32768, 5},
 604         /* The 64M mode still requires a 128k gatt */
 605         {64, 16384, 5},
 606         {256, 65536, 6},
 607         {512, 131072, 7},
 608 };
 609
 610 static void intel_i830_init_gtt_entries(void)
 611 {
 612         u16 gmch_ctrl;
 613         int gtt_entries;
 614         u8 rdct;
 615         int local = 0;
 616         static const int ddt[4] = { 0, 16, 32, 64 };
 617         int size; /* reserved space (in kb) at the top of stolen memory */
 618
 619         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 620
 621         if (IS_I965) {
 622                 u32 pgetbl_ctl;
 623                 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 624
 625                 /* The 965 has a field telling us the size of the GTT,
 626                  * which may be larger than what is necessary to map the
 627                  * aperture.
 628                  */
 629                 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
 630                 case I965_PGETBL_SIZE_128KB:
 631                         size = 128;
 632                         break;
 633                 case I965_PGETBL_SIZE_256KB:
 634                         size = 256;
 635                         break;
 636                 case I965_PGETBL_SIZE_512KB:
 637                         size = 512;
 638                         break;
 639                 case I965_PGETBL_SIZE_1MB:
 640                         size = 1024;
 641                         break;
 642                 case I965_PGETBL_SIZE_2MB:
 643                         size = 2048;
 644                         break;
 645                 case I965_PGETBL_SIZE_1_5MB:
 646                         size = 1024 + 512;
 647                         break;
 648                 default:
 649                         dev_info(&intel_private.pcidev->dev,
 650                                  "unknown page table size, assuming 512KB\n");
 651                         size = 512;
 652                 }
 653                 size += 4; /* add in BIOS popup space */
 654         } else if (IS_G33 && !IS_IGD) {
 655         /* G33's GTT size defined in gmch_ctrl */
 656                 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
 657                 case G33_PGETBL_SIZE_1M:
 658                         size = 1024;
 659                         break;
 660                 case G33_PGETBL_SIZE_2M:
 661                         size = 2048;
 662                         break;
 663                 default:
 664                         dev_info(&agp_bridge->dev->dev,
 665                                  "unknown page table size 0x%x, assuming 512KB\n",
 666                                 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
 667                         size = 512;
 668                 }
 669                 size += 4;
 670         } else if (IS_G4X || IS_IGD) {
 671                 /* On 4 series hardware, GTT stolen is separate from graphics
 672                  * stolen, ignore it in stolen gtt entries counting.  However,
 673                  * 4KB of the stolen memory doesn't get mapped to the GTT.
 674                  */
 675                 size = 4;
 676         } else {
 677                 /* On previous hardware, the GTT size was just what was
 678                  * required to map the aperture.
 679                  */
 680                 size = agp_bridge->driver->fetch_size() + 4;
 681         }
 682
 683         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
 684             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
 685                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 686                 case I830_GMCH_GMS_STOLEN_512:
 687                         gtt_entries = KB(512) - KB(size);
 688                         break;
 689                 case I830_GMCH_GMS_STOLEN_1024:
 690                         gtt_entries = MB(1) - KB(size);
 691                         break;
 692                 case I830_GMCH_GMS_STOLEN_8192:
 693                         gtt_entries = MB(8) - KB(size);
 694                         break;
 695                 case I830_GMCH_GMS_LOCAL:
 696                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
 697                         gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
 698                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
 699                         local = 1;
 700                         break;
 701                 default:
 702                         gtt_entries = 0;
 703                         break;
 704                 }
 705         } else {
 706                 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
 707                 case I855_GMCH_GMS_STOLEN_1M:
 708                         gtt_entries = MB(1) - KB(size);
 709                         break;
 710                 case I855_GMCH_GMS_STOLEN_4M:
 711                         gtt_entries = MB(4) - KB(size);
 712                         break;
 713                 case I855_GMCH_GMS_STOLEN_8M:
 714                         gtt_entries = MB(8) - KB(size);
 715                         break;
 716                 case I855_GMCH_GMS_STOLEN_16M:
 717                         gtt_entries = MB(16) - KB(size);
 718                         break;
 719                 case I855_GMCH_GMS_STOLEN_32M:
 720                         gtt_entries = MB(32) - KB(size);
 721                         break;
 722                 case I915_GMCH_GMS_STOLEN_48M:
 723                         /* Check it's really I915G */
 724                         if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
 725                                 gtt_entries = MB(48) - KB(size);
 726                         else
 727                                 gtt_entries = 0;
 728                         break;
 729                 case I915_GMCH_GMS_STOLEN_64M:
 730                         /* Check it's really I915G */
 731                         if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
 732                                 gtt_entries = MB(64) - KB(size);
 733                         else
 734                                 gtt_entries = 0;
 735                         break;
 736                 case G33_GMCH_GMS_STOLEN_128M:
 737                         if (IS_G33 || IS_I965 || IS_G4X)
 738                                 gtt_entries = MB(128) - KB(size);
 739                         else
 740                                 gtt_entries = 0;
 741                         break;
 742                 case G33_GMCH_GMS_STOLEN_256M:
 743                         if (IS_G33 || IS_I965 || IS_G4X)
 744                                 gtt_entries = MB(256) - KB(size);
 745                         else
 746                                 gtt_entries = 0;
 747                         break;
 748                 case INTEL_GMCH_GMS_STOLEN_96M:
 749                         if (IS_I965 || IS_G4X)
 750                                 gtt_entries = MB(96) - KB(size);
 751                         else
 752                                 gtt_entries = 0;
 753                         break;
 754                 case INTEL_GMCH_GMS_STOLEN_160M:
 755                         if (IS_I965 || IS_G4X)
 756                                 gtt_entries = MB(160) - KB(size);
 757                         else
 758                                 gtt_entries = 0;
 759                         break;
 760                 case INTEL_GMCH_GMS_STOLEN_224M:
 761                         if (IS_I965 || IS_G4X)
 762                                 gtt_entries = MB(224) - KB(size);
 763                         else
 764                                 gtt_entries = 0;
 765                         break;
 766                 case INTEL_GMCH_GMS_STOLEN_352M:
 767                         if (IS_I965 || IS_G4X)
 768                                 gtt_entries = MB(352) - KB(size);
 769                         else
 770                                 gtt_entries = 0;
 771                         break;
 772                 default:
 773                         gtt_entries = 0;
 774                         break;
 775                 }
 776         }
 777         if (gtt_entries > 0) {
 778                 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n",
 779                        gtt_entries / KB(1), local ? "local" : "stolen");
 780                 gtt_entries /= KB(4);
 781         } else {
 782                 dev_info(&agp_bridge->dev->dev,
 783                        "no pre-allocated video memory detected\n");
 784                 gtt_entries = 0;
 785         }
 786
 787         intel_private.gtt_entries = gtt_entries;
 788 }
 789
 790 static void intel_i830_fini_flush(void)
 791 {
 792         kunmap(intel_private.i8xx_page);
 793         intel_private.i8xx_flush_page = NULL;
 794         unmap_page_from_agp(intel_private.i8xx_page);
 795
 796         __free_page(intel_private.i8xx_page);
 797         intel_private.i8xx_page = NULL;
 798 }
 799
 800 static void intel_i830_setup_flush(void)
 801 {
 802         /* return if we've already set the flush mechanism up */
 803         if (intel_private.i8xx_page)
 804                 return;
 805
 806         intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
 807         if (!intel_private.i8xx_page)
 808                 return;
 809
 810         intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
 811         if (!intel_private.i8xx_flush_page)
 812                 intel_i830_fini_flush();
 813 }
 814
 815 static void
 816 do_wbinvd(void *null)
 817 {
 818         wbinvd();
 819 }
 820
 821 /* The chipset_flush interface needs to get data that has already been
 822  * flushed out of the CPU all the way out to main memory, because the GPU
 823  * doesn't snoop those buffers.
 824  *
 825  * The 8xx series doesn't have the same lovely interface for flushing the
 826  * chipset write buffers that the later chips do. According to the 865
 827  * specs, it's 64 octwords, or 1KB.  So, to get those previous things in
 828  * that buffer out, we just fill 1KB and clflush it out, on the assumption
 829  * that it'll push whatever was in there out.  It appears to work.
 830  */
 831 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
 832 {
 833         unsigned int *pg = intel_private.i8xx_flush_page;
 834
 835         memset(pg, 0, 1024);
 836
 837         if (cpu_has_clflush) {
 838                 clflush_cache_range(pg, 1024);
 839         } else {
 840                 if (on_each_cpu(do_wbinvd, NULL, 1) != 0)
 841                         printk(KERN_ERR "Timed out waiting for cache flush.\n");
 842         }
 843 }
 844
 845 /* The intel i830 automatically initializes the agp aperture during POST.
 846  * Use the memory already set aside for in the GTT.
 847  */
 848 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
 849 {
 850         int page_order;
 851         struct aper_size_info_fixed *size;
 852         int num_entries;
 853         u32 temp;
 854
 855         size = agp_bridge->current_size;
 856         page_order = size->page_order;
 857         num_entries = size->num_entries;
 858         agp_bridge->gatt_table_real = NULL;
 859
 860         pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 861         temp &= 0xfff80000;
 862
 863         intel_private.registers = ioremap(temp, 128 * 4096);
 864         if (!intel_private.registers)
 865                 return -ENOMEM;
 866
 867         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
 868         global_cache_flush();   /* FIXME: ?? */
 869
 870         /* we have to call this as early as possible after the MMIO base address is known */
 871         intel_i830_init_gtt_entries();
 872
 873         agp_bridge->gatt_table = NULL;
 874
 875         agp_bridge->gatt_bus_addr = temp;
 876
 877         return 0;
 878 }
 879
 880 /* Return the gatt table to a sane state. Use the top of stolen
 881  * memory for the GTT.
 882  */
 883 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
 884 {
 885         return 0;
 886 }
 887
 888 static int intel_i830_fetch_size(void)
 889 {
 890         u16 gmch_ctrl;
 891         struct aper_size_info_fixed *values;
 892
 893         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 894
 895         if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
 896             agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
 897                 /* 855GM/852GM/865G has 128MB aperture size */
 898                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 899                 agp_bridge->aperture_size_idx = 0;
 900                 return values[0].size;
 901         }
 902
 903         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 904
 905         if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
 906                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 907                 agp_bridge->aperture_size_idx = 0;
 908                 return values[0].size;
 909         } else {
 910                 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
 911                 agp_bridge->aperture_size_idx = 1;
 912                 return values[1].size;
 913         }
 914
 915         return 0;
 916 }
 917
 918 static int intel_i830_configure(void)
 919 {
 920         struct aper_size_info_fixed *current_size;
 921         u32 temp;
 922         u16 gmch_ctrl;
 923         int i;
 924
 925         current_size = A_SIZE_FIX(agp_bridge->current_size);
 926
 927         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 928         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 929
 930         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 931         gmch_ctrl |= I830_GMCH_ENABLED;
 932         pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
 933
 934         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 935         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 936
 937         if (agp_bridge->driver->needs_scratch_page) {
 938                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
 939                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 940                 }
 941                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */
 942         }
 943
 944         global_cache_flush();
 945
 946         intel_i830_setup_flush();
 947         return 0;
 948 }
 949
 950 static void intel_i830_cleanup(void)
 951 {
 952         iounmap(intel_private.registers);
 953 }
 954
 955 static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
 956                                      int type)
 957 {
 958         int i, j, num_entries;
 959         void *temp;
 960         int ret = -EINVAL;
 961         int mask_type;
 962
 963         if (mem->page_count == 0)
 964                 goto out;
 965
 966         temp = agp_bridge->current_size;
 967         num_entries = A_SIZE_FIX(temp)->num_entries;
 968
 969         if (pg_start < intel_private.gtt_entries) {
 970                 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
 971                            "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
 972                            pg_start, intel_private.gtt_entries);
 973
 974                 dev_info(&intel_private.pcidev->dev,
 975                          "trying to insert into local/stolen memory\n");
 976                 goto out_err;
 977         }
 978
 979         if ((pg_start + mem->page_count) > num_entries)
 980                 goto out_err;
 981
 982         /* The i830 can't check the GTT for entries since its read only,
 983          * depend on the caller to make the correct offset decisions.
 984          */
 985
 986         if (type != mem->type)
 987                 goto out_err;
 988
 989         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 990
 991         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
 992             mask_type != INTEL_AGP_CACHED_MEMORY)
 993                 goto out_err;
 994
 995         if (!mem->is_flushed)
 996                 global_cache_flush();
 997
 998         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 999                 writel(agp_bridge->driver->mask_memory(agp_bridge,
1000                                 page_to_phys(mem->pages[i]), mask_type),
1001                        intel_private.registers+I810_PTE_BASE+(j*4));
1002         }
1003         readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
1004         agp_bridge->driver->tlb_flush(mem);
1005
1006 out:
1007         ret = 0;
1008 out_err:
1009         mem->is_flushed = true;
1010         return ret;
1011 }
1012
1013 static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
1014                                      int type)
1015 {
1016         int i;
1017
1018         if (mem->page_count == 0)
1019                 return 0;
1020
1021         if (pg_start < intel_private.gtt_entries) {
1022                 dev_info(&intel_private.pcidev->dev,
1023                          "trying to disable local/stolen memory\n");
1024                 return -EINVAL;
1025         }
1026
1027         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1028                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
1029         }
1030         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
1031
1032         agp_bridge->driver->tlb_flush(mem);
1033         return 0;
1034 }
1035
1036 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type)
1037 {
1038         if (type == AGP_PHYS_MEMORY)
1039                 return alloc_agpphysmem_i8xx(pg_count, type);
1040         /* always return NULL for other allocation types for now */
1041         return NULL;
1042 }
1043
1044 static int intel_alloc_chipset_flush_resource(void)
1045 {
1046         int ret;
1047         ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1048                                      PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1049                                      pcibios_align_resource, agp_bridge->dev);
1050
1051         return ret;
1052 }
1053
1054 static void intel_i915_setup_chipset_flush(void)
1055 {
1056         int ret;
1057         u32 temp;
1058
1059         pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
1060         if (!(temp & 0x1)) {
1061                 intel_alloc_chipset_flush_resource();
1062                 intel_private.resource_valid = 1;
1063                 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1064         } else {
1065                 temp &= ~1;
1066
1067                 intel_private.resource_valid = 1;
1068                 intel_private.ifp_resource.start = temp;
1069                 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1070                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1071                 /* some BIOSes reserve this area in a pnp some don't */
1072                 if (ret)
1073                         intel_private.resource_valid = 0;
1074         }
1075 }
1076
1077 static void intel_i965_g33_setup_chipset_flush(void)
1078 {
1079         u32 temp_hi, temp_lo;
1080         int ret;
1081
1082         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
1083         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
1084
1085         if (!(temp_lo & 0x1)) {
1086
1087                 intel_alloc_chipset_flush_resource();
1088
1089                 intel_private.resource_valid = 1;
1090                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
1091                         upper_32_bits(intel_private.ifp_resource.start));
1092                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1093         } else {
1094                 u64 l64;
1095
1096                 temp_lo &= ~0x1;
1097                 l64 = ((u64)temp_hi << 32) | temp_lo;
1098
1099                 intel_private.resource_valid = 1;
1100                 intel_private.ifp_resource.start = l64;
1101                 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1102                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1103                 /* some BIOSes reserve this area in a pnp some don't */
1104                 if (ret)
1105                         intel_private.resource_valid = 0;
1106         }
1107 }
1108
1109 static void intel_i9xx_setup_flush(void)
1110 {
1111         /* return if already configured */
1112         if (intel_private.ifp_resource.start)
1113                 return;
1114
1115         /* setup a resource for this object */
1116         intel_private.ifp_resource.name = "Intel Flush Page";
1117         intel_private.ifp_resource.flags = IORESOURCE_MEM;
1118
1119         /* Setup chipset flush for 915 */
1120         if (IS_I965 || IS_G33 || IS_G4X) {
1121                 intel_i965_g33_setup_chipset_flush();
1122         } else {
1123                 intel_i915_setup_chipset_flush();
1124         }
1125
1126         if (intel_private.ifp_resource.start) {
1127                 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1128                 if (!intel_private.i9xx_flush_page)
1129                         dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing");
1130         }
1131 }
1132
1133 static int intel_i915_configure(void)
1134 {
1135         struct aper_size_info_fixed *current_size;
1136         u32 temp;
1137         u16 gmch_ctrl;
1138         int i;
1139
1140         current_size = A_SIZE_FIX(agp_bridge->current_size);
1141
1142         pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
1143
1144         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1145
1146         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
1147         gmch_ctrl |= I830_GMCH_ENABLED;
1148         pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
1149
1150         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
1151         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1152
1153         if (agp_bridge->driver->needs_scratch_page) {
1154                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
1155                         writel(agp_bridge->scratch_page, intel_private.gtt+i);
1156                 }
1157                 readl(intel_private.gtt+i-1);   /* PCI Posting. */
1158         }
1159
1160         global_cache_flush();
1161
1162         intel_i9xx_setup_flush();
1163
1164 #ifdef USE_PCI_DMA_API
1165         if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(36)))
1166                 dev_err(&intel_private.pcidev->dev,
1167                         "set gfx device dma mask 36bit failed!\n");
1168 #endif
1169
1170         return 0;
1171 }
1172
1173 static void intel_i915_cleanup(void)
1174 {
1175         if (intel_private.i9xx_flush_page)
1176                 iounmap(intel_private.i9xx_flush_page);
1177         if (intel_private.resource_valid)
1178                 release_resource(&intel_private.ifp_resource);
1179         intel_private.ifp_resource.start = 0;
1180         intel_private.resource_valid = 0;
1181         iounmap(intel_private.gtt);
1182         iounmap(intel_private.registers);
1183 }
1184
1185 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1186 {
1187         if (intel_private.i9xx_flush_page)
1188                 writel(1, intel_private.i9xx_flush_page);
1189 }
1190
1191 static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1192                                      int type)
1193 {
1194         int num_entries;
1195         void *temp;
1196         int ret = -EINVAL;
1197         int mask_type;
1198
1199         if (mem->page_count == 0)
1200                 goto out;
1201
1202         temp = agp_bridge->current_size;
1203         num_entries = A_SIZE_FIX(temp)->num_entries;
1204
1205         if (pg_start < intel_private.gtt_entries) {
1206                 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1207                            "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
1208                            pg_start, intel_private.gtt_entries);
1209
1210                 dev_info(&intel_private.pcidev->dev,
1211                          "trying to insert into local/stolen memory\n");
1212                 goto out_err;
1213         }
1214
1215         if ((pg_start + mem->page_count) > num_entries)
1216                 goto out_err;
1217
1218         /* The i915 can't check the GTT for entries since it's read only;
1219          * depend on the caller to make the correct offset decisions.
1220          */
1221
1222         if (type != mem->type)
1223                 goto out_err;
1224
1225         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1226
1227         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1228             mask_type != INTEL_AGP_CACHED_MEMORY)
1229                 goto out_err;
1230
1231         if (!mem->is_flushed)
1232                 global_cache_flush();
1233
1234         intel_agp_insert_sg_entries(mem, pg_start, mask_type);
1235         agp_bridge->driver->tlb_flush(mem);
1236
1237  out:
1238         ret = 0;
1239  out_err:
1240         mem->is_flushed = true;
1241         return ret;
1242 }
1243
1244 static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1245                                      int type)
1246 {
1247         int i;
1248
1249         if (mem->page_count == 0)
1250                 return 0;
1251
1252         if (pg_start < intel_private.gtt_entries) {
1253                 dev_info(&intel_private.pcidev->dev,
1254                          "trying to disable local/stolen memory\n");
1255                 return -EINVAL;
1256         }
1257
1258         for (i = pg_start; i < (mem->page_count + pg_start); i++)
1259                 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1260
1261         readl(intel_private.gtt+i-1);
1262
1263         agp_bridge->driver->tlb_flush(mem);
1264         return 0;
1265 }
1266
1267 /* Return the aperture size by just checking the resource length.  The effect
1268  * described in the spec of the MSAC registers is just changing of the
1269  * resource size.
1270  */
1271 static int intel_i9xx_fetch_size(void)
1272 {
1273         int num_sizes = ARRAY_SIZE(intel_i830_sizes);
1274         int aper_size; /* size in megabytes */
1275         int i;
1276
1277         aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1278
1279         for (i = 0; i < num_sizes; i++) {
1280                 if (aper_size == intel_i830_sizes[i].size) {
1281                         agp_bridge->current_size = intel_i830_sizes + i;
1282                         agp_bridge->previous_size = agp_bridge->current_size;
1283                         return aper_size;
1284                 }
1285         }
1286
1287         return 0;
1288 }
1289
1290 /* The intel i915 automatically initializes the agp aperture during POST.
1291  * Use the memory already set aside for in the GTT.
1292  */
1293 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1294 {
1295         int page_order;
1296         struct aper_size_info_fixed *size;
1297         int num_entries;
1298         u32 temp, temp2;
1299         int gtt_map_size = 256 * 1024;
1300
1301         size = agp_bridge->current_size;
1302         page_order = size->page_order;
1303         num_entries = size->num_entries;
1304         agp_bridge->gatt_table_real = NULL;
1305
1306         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1307         pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
1308
1309         if (IS_G33)
1310             gtt_map_size = 1024 * 1024; /* 1M on G33 */
1311         intel_private.gtt = ioremap(temp2, gtt_map_size);
1312         if (!intel_private.gtt)
1313                 return -ENOMEM;
1314
1315         temp &= 0xfff80000;
1316
1317         intel_private.registers = ioremap(temp, 128 * 4096);
1318         if (!intel_private.registers) {
1319                 iounmap(intel_private.gtt);
1320                 return -ENOMEM;
1321         }
1322
1323         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1324         global_cache_flush();   /* FIXME: ? */
1325
1326         /* we have to call this as early as possible after the MMIO base address is known */
1327         intel_i830_init_gtt_entries();
1328
1329         agp_bridge->gatt_table = NULL;
1330
1331         agp_bridge->gatt_bus_addr = temp;
1332
1333         return 0;
1334 }
1335
1336 /*
1337  * The i965 supports 36-bit physical addresses, but to keep
1338  * the format of the GTT the same, the bits that don't fit
1339  * in a 32-bit word are shifted down to bits 4..7.
1340  *
1341  * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1342  * is always zero on 32-bit architectures, so no need to make
1343  * this conditional.
1344  */
1345 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1346                                             dma_addr_t addr, int type)
1347 {
1348         /* Shift high bits down */
1349         addr |= (addr >> 28) & 0xf0;
1350
1351         /* Type checking must be done elsewhere */
1352         return addr | bridge->driver->masks[type].mask;
1353 }
1354
1355 static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1356 {
1357         switch (agp_bridge->dev->device) {
1358         case PCI_DEVICE_ID_INTEL_GM45_HB:
1359         case PCI_DEVICE_ID_INTEL_IGD_E_HB:
1360         case PCI_DEVICE_ID_INTEL_Q45_HB:
1361         case PCI_DEVICE_ID_INTEL_G45_HB:
1362         case PCI_DEVICE_ID_INTEL_G41_HB:
1363         case PCI_DEVICE_ID_INTEL_B43_HB:
1364         case PCI_DEVICE_ID_INTEL_IGDNG_D_HB:
1365         case PCI_DEVICE_ID_INTEL_IGDNG_M_HB:
1366         case PCI_DEVICE_ID_INTEL_IGDNG_MA_HB:
1367                 *gtt_offset = *gtt_size = MB(2);
1368                 break;
1369         default:
1370                 *gtt_offset = *gtt_size = KB(512);
1371         }
1372 }
1373
1374 /* The intel i965 automatically initializes the agp aperture during POST.
1375  * Use the memory already set aside for in the GTT.
1376  */
1377 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1378 {
1379         int page_order;
1380         struct aper_size_info_fixed *size;
1381         int num_entries;
1382         u32 temp;
1383         int gtt_offset, gtt_size;
1384
1385         size = agp_bridge->current_size;
1386         page_order = size->page_order;
1387         num_entries = size->num_entries;
1388         agp_bridge->gatt_table_real = NULL;
1389
1390         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1391
1392         temp &= 0xfff00000;
1393
1394         intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
1395
1396         intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1397
1398         if (!intel_private.gtt)
1399                 return -ENOMEM;
1400
1401         intel_private.registers = ioremap(temp, 128 * 4096);
1402         if (!intel_private.registers) {
1403                 iounmap(intel_private.gtt);
1404                 return -ENOMEM;
1405         }
1406
1407         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1408         global_cache_flush();   /* FIXME: ? */
1409
1410         /* we have to call this as early as possible after the MMIO base address is known */
1411         intel_i830_init_gtt_entries();
1412
1413         agp_bridge->gatt_table = NULL;
1414
1415         agp_bridge->gatt_bus_addr = temp;
1416
1417         return 0;
1418 }
1419
1420
1421 static int intel_fetch_size(void)
1422 {
1423         int i;
1424         u16 temp;
1425         struct aper_size_info_16 *values;
1426
1427         pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1428         values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1429
1430         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1431                 if (temp == values[i].size_value) {
1432                         agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1433                         agp_bridge->aperture_size_idx = i;
1434                         return values[i].size;
1435                 }
1436         }
1437
1438         return 0;
1439 }
1440
1441 static int __intel_8xx_fetch_size(u8 temp)
1442 {
1443         int i;
1444         struct aper_size_info_8 *values;
1445
1446         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1447
1448         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1449                 if (temp == values[i].size_value) {
1450                         agp_bridge->previous_size =
1451                                 agp_bridge->current_size = (void *) (values + i);
1452                         agp_bridge->aperture_size_idx = i;
1453                         return values[i].size;
1454                 }
1455         }
1456         return 0;
1457 }
1458
1459 static int intel_8xx_fetch_size(void)
1460 {
1461         u8 temp;
1462
1463         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1464         return __intel_8xx_fetch_size(temp);
1465 }
1466
1467 static int intel_815_fetch_size(void)
1468 {
1469         u8 temp;
1470
1471         /* Intel 815 chipsets have a _weird_ APSIZE register with only
1472          * one non-reserved bit, so mask the others out ... */
1473         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1474         temp &= (1 << 3);
1475
1476         return __intel_8xx_fetch_size(temp);
1477 }
1478
1479 static void intel_tlbflush(struct agp_memory *mem)
1480 {
1481         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1482         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1483 }
1484
1485
1486 static void intel_8xx_tlbflush(struct agp_memory *mem)
1487 {
1488         u32 temp;
1489         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1490         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1491         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1492         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1493 }
1494
1495
1496 static void intel_cleanup(void)
1497 {
1498         u16 temp;
1499         struct aper_size_info_16 *previous_size;
1500
1501         previous_size = A_SIZE_16(agp_bridge->previous_size);
1502         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1503         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1504         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1505 }
1506
1507
1508 static void intel_8xx_cleanup(void)
1509 {
1510         u16 temp;
1511         struct aper_size_info_8 *previous_size;
1512
1513         previous_size = A_SIZE_8(agp_bridge->previous_size);
1514         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1515         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1516         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1517 }
1518
1519
1520 static int intel_configure(void)
1521 {
1522         u32 temp;
1523         u16 temp2;
1524         struct aper_size_info_16 *current_size;
1525
1526         current_size = A_SIZE_16(agp_bridge->current_size);
1527
1528         /* aperture size */
1529         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1530
1531         /* address to map to */
1532         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1533         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1534
1535         /* attbase - aperture base */
1536         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1537
1538         /* agpctrl */
1539         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1540
1541         /* paccfg/nbxcfg */
1542         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1543         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1544                         (temp2 & ~(1 << 10)) | (1 << 9));
1545         /* clear any possible error conditions */
1546         pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1547         return 0;
1548 }
1549
1550 static int intel_815_configure(void)
1551 {
1552         u32 temp, addr;
1553         u8 temp2;
1554         struct aper_size_info_8 *current_size;
1555
1556         /* attbase - aperture base */
1557         /* the Intel 815 chipset spec. says that bits 29-31 in the
1558         * ATTBASE register are reserved -> try not to write them */
1559         if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1560                 dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high");
1561                 return -EINVAL;
1562         }
1563
1564         current_size = A_SIZE_8(agp_bridge->current_size);
1565
1566         /* aperture size */
1567         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1568                         current_size->size_value);
1569
1570         /* address to map to */
1571         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1572         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1573
1574         pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1575         addr &= INTEL_815_ATTBASE_MASK;
1576         addr |= agp_bridge->gatt_bus_addr;
1577         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1578
1579         /* agpctrl */
1580         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1581
1582         /* apcont */
1583         pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1584         pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1585
1586         /* clear any possible error conditions */
1587         /* Oddness : this chipset seems to have no ERRSTS register ! */
1588         return 0;
1589 }
1590
1591 static void intel_820_tlbflush(struct agp_memory *mem)
1592 {
1593         return;
1594 }
1595
1596 static void intel_820_cleanup(void)
1597 {
1598         u8 temp;
1599         struct aper_size_info_8 *previous_size;
1600
1601         previous_size = A_SIZE_8(agp_bridge->previous_size);
1602         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1603         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1604                         temp & ~(1 << 1));
1605         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1606                         previous_size->size_value);
1607 }
1608
1609
1610 static int intel_820_configure(void)
1611 {
1612         u32 temp;
1613         u8 temp2;
1614         struct aper_size_info_8 *current_size;
1615
1616         current_size = A_SIZE_8(agp_bridge->current_size);
1617
1618         /* aperture size */
1619         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1620
1621         /* address to map to */
1622         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1623         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1624
1625         /* attbase - aperture base */
1626         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1627
1628         /* agpctrl */
1629         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1630
1631         /* global enable aperture access */
1632         /* This flag is not accessed through MCHCFG register as in */
1633         /* i850 chipset. */
1634         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1635         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1636         /* clear any possible AGP-related error conditions */
1637         pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1638         return 0;
1639 }
1640
1641 static int intel_840_configure(void)
1642 {
1643         u32 temp;
1644         u16 temp2;
1645         struct aper_size_info_8 *current_size;
1646
1647         current_size = A_SIZE_8(agp_bridge->current_size);
1648
1649         /* aperture size */
1650         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1651
1652         /* address to map to */
1653         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1654         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1655
1656         /* attbase - aperture base */
1657         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1658
1659         /* agpctrl */
1660         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1661
1662         /* mcgcfg */
1663         pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1664         pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1665         /* clear any possible error conditions */
1666         pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1667         return 0;
1668 }
1669
1670 static int intel_845_configure(void)
1671 {
1672         u32 temp;
1673         u8 temp2;
1674         struct aper_size_info_8 *current_size;
1675
1676         current_size = A_SIZE_8(agp_bridge->current_size);
1677
1678         /* aperture size */
1679         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1680
1681         if (agp_bridge->apbase_config != 0) {
1682                 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1683                                        agp_bridge->apbase_config);
1684         } else {
1685                 /* address to map to */
1686                 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1687                 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1688                 agp_bridge->apbase_config = temp;
1689         }
1690
1691         /* attbase - aperture base */
1692         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1693
1694         /* agpctrl */
1695         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1696
1697         /* agpm */
1698         pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1699         pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1700         /* clear any possible error conditions */
1701         pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1702
1703         intel_i830_setup_flush();
1704         return 0;
1705 }
1706
1707 static int intel_850_configure(void)
1708 {
1709         u32 temp;
1710         u16 temp2;
1711         struct aper_size_info_8 *current_size;
1712
1713         current_size = A_SIZE_8(agp_bridge->current_size);
1714
1715         /* aperture size */
1716         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1717
1718         /* address to map to */
1719         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1720         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1721
1722         /* attbase - aperture base */
1723         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1724
1725         /* agpctrl */
1726         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1727
1728         /* mcgcfg */
1729         pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1730         pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1731         /* clear any possible AGP-related error conditions */
1732         pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1733         return 0;
1734 }
1735
1736 static int intel_860_configure(void)
1737 {
1738         u32 temp;
1739         u16 temp2;
1740         struct aper_size_info_8 *current_size;
1741
1742         current_size = A_SIZE_8(agp_bridge->current_size);
1743
1744         /* aperture size */
1745         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1746
1747         /* address to map to */
1748         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1749         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1750
1751         /* attbase - aperture base */
1752         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1753
1754         /* agpctrl */
1755         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1756
1757         /* mcgcfg */
1758         pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1759         pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1760         /* clear any possible AGP-related error conditions */
1761         pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1762         return 0;
1763 }
1764
1765 static int intel_830mp_configure(void)
1766 {
1767         u32 temp;
1768         u16 temp2;
1769         struct aper_size_info_8 *current_size;
1770
1771         current_size = A_SIZE_8(agp_bridge->current_size);
1772
1773         /* aperture size */
1774         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1775
1776         /* address to map to */
1777         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1778         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1779
1780         /* attbase - aperture base */
1781         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1782
1783         /* agpctrl */
1784         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1785
1786         /* gmch */
1787         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1788         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1789         /* clear any possible AGP-related error conditions */
1790         pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1791         return 0;
1792 }
1793
1794 static int intel_7505_configure(void)
1795 {
1796         u32 temp;
1797         u16 temp2;
1798         struct aper_size_info_8 *current_size;
1799
1800         current_size = A_SIZE_8(agp_bridge->current_size);
1801
1802         /* aperture size */
1803         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1804
1805         /* address to map to */
1806         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1807         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1808
1809         /* attbase - aperture base */
1810         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1811
1812         /* agpctrl */
1813         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1814
1815         /* mchcfg */
1816         pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1817         pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1818
1819         return 0;
1820 }
1821
1822 /* Setup function */
1823 static const struct gatt_mask intel_generic_masks[] =
1824 {
1825         {.mask = 0x00000017, .type = 0}
1826 };
1827
1828 static const struct aper_size_info_8 intel_815_sizes[2] =
1829 {
1830         {64, 16384, 4, 0},
1831         {32, 8192, 3, 8},
1832 };
1833
1834 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1835 {
1836         {256, 65536, 6, 0},
1837         {128, 32768, 5, 32},
1838         {64, 16384, 4, 48},
1839         {32, 8192, 3, 56},
1840         {16, 4096, 2, 60},
1841         {8, 2048, 1, 62},
1842         {4, 1024, 0, 63}
1843 };
1844
1845 static const struct aper_size_info_16 intel_generic_sizes[7] =
1846 {
1847         {256, 65536, 6, 0},
1848         {128, 32768, 5, 32},
1849         {64, 16384, 4, 48},
1850         {32, 8192, 3, 56},
1851         {16, 4096, 2, 60},
1852         {8, 2048, 1, 62},
1853         {4, 1024, 0, 63}
1854 };
1855
1856 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1857 {
1858         {256, 65536, 6, 0},
1859         {128, 32768, 5, 32},
1860         {64, 16384, 4, 48},
1861         {32, 8192, 3, 56}
1862 };
1863
1864 static const struct agp_bridge_driver intel_generic_driver = {
1865         .owner                  = THIS_MODULE,
1866         .aperture_sizes         = intel_generic_sizes,
1867         .size_type              = U16_APER_SIZE,
1868         .num_aperture_sizes     = 7,
1869         .configure              = intel_configure,
1870         .fetch_size             = intel_fetch_size,
1871         .cleanup                = intel_cleanup,
1872         .tlb_flush              = intel_tlbflush,
1873         .mask_memory            = agp_generic_mask_memory,
1874         .masks                  = intel_generic_masks,
1875         .agp_enable             = agp_generic_enable,
1876         .cache_flush            = global_cache_flush,
1877         .create_gatt_table      = agp_generic_create_gatt_table,
1878         .free_gatt_table        = agp_generic_free_gatt_table,
1879         .insert_memory          = agp_generic_insert_memory,
1880         .remove_memory          = agp_generic_remove_memory,
1881         .alloc_by_type          = agp_generic_alloc_by_type,
1882         .free_by_type           = agp_generic_free_by_type,
1883         .agp_alloc_page         = agp_generic_alloc_page,
1884         .agp_alloc_pages        = agp_generic_alloc_pages,
1885         .agp_destroy_page       = agp_generic_destroy_page,
1886         .agp_destroy_pages      = agp_generic_destroy_pages,
1887         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1888 };
1889
1890 static const struct agp_bridge_driver intel_810_driver = {
1891         .owner                  = THIS_MODULE,
1892         .aperture_sizes         = intel_i810_sizes,
1893         .size_type              = FIXED_APER_SIZE,
1894         .num_aperture_sizes     = 2,
1895         .needs_scratch_page     = true,
1896         .configure              = intel_i810_configure,
1897         .fetch_size             = intel_i810_fetch_size,
1898         .cleanup                = intel_i810_cleanup,
1899         .tlb_flush              = intel_i810_tlbflush,
1900         .mask_memory            = intel_i810_mask_memory,
1901         .masks                  = intel_i810_masks,
1902         .agp_enable             = intel_i810_agp_enable,
1903         .cache_flush            = global_cache_flush,
1904         .create_gatt_table      = agp_generic_create_gatt_table,
1905         .free_gatt_table        = agp_generic_free_gatt_table,
1906         .insert_memory          = intel_i810_insert_entries,
1907         .remove_memory          = intel_i810_remove_entries,
1908         .alloc_by_type          = intel_i810_alloc_by_type,
1909         .free_by_type           = intel_i810_free_by_type,
1910         .agp_alloc_page         = agp_generic_alloc_page,
1911         .agp_alloc_pages        = agp_generic_alloc_pages,
1912         .agp_destroy_page       = agp_generic_destroy_page,
1913         .agp_destroy_pages      = agp_generic_destroy_pages,
1914         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1915 };
1916
1917 static const struct agp_bridge_driver intel_815_driver = {
1918         .owner                  = THIS_MODULE,
1919         .aperture_sizes         = intel_815_sizes,
1920         .size_type              = U8_APER_SIZE,
1921         .num_aperture_sizes     = 2,
1922         .configure              = intel_815_configure,
1923         .fetch_size             = intel_815_fetch_size,
1924         .cleanup                = intel_8xx_cleanup,
1925         .tlb_flush              = intel_8xx_tlbflush,
1926         .mask_memory            = agp_generic_mask_memory,
1927         .masks                  = intel_generic_masks,
1928         .agp_enable             = agp_generic_enable,
1929         .cache_flush            = global_cache_flush,
1930         .create_gatt_table      = agp_generic_create_gatt_table,
1931         .free_gatt_table        = agp_generic_free_gatt_table,
1932         .insert_memory          = agp_generic_insert_memory,
1933         .remove_memory          = agp_generic_remove_memory,
1934         .alloc_by_type          = agp_generic_alloc_by_type,
1935         .free_by_type           = agp_generic_free_by_type,
1936         .agp_alloc_page         = agp_generic_alloc_page,
1937         .agp_alloc_pages        = agp_generic_alloc_pages,
1938         .agp_destroy_page       = agp_generic_destroy_page,
1939         .agp_destroy_pages      = agp_generic_destroy_pages,
1940         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1941 };
1942
1943 static const struct agp_bridge_driver intel_830_driver = {
1944         .owner                  = THIS_MODULE,
1945         .aperture_sizes         = intel_i830_sizes,
1946         .size_type              = FIXED_APER_SIZE,
1947         .num_aperture_sizes     = 4,
1948         .needs_scratch_page     = true,
1949         .configure              = intel_i830_configure,
1950         .fetch_size             = intel_i830_fetch_size,
1951         .cleanup                = intel_i830_cleanup,
1952         .tlb_flush              = intel_i810_tlbflush,
1953         .mask_memory            = intel_i810_mask_memory,
1954         .masks                  = intel_i810_masks,
1955         .agp_enable             = intel_i810_agp_enable,
1956         .cache_flush            = global_cache_flush,
1957         .create_gatt_table      = intel_i830_create_gatt_table,
1958         .free_gatt_table        = intel_i830_free_gatt_table,
1959         .insert_memory          = intel_i830_insert_entries,
1960         .remove_memory          = intel_i830_remove_entries,
1961         .alloc_by_type          = intel_i830_alloc_by_type,
1962         .free_by_type           = intel_i810_free_by_type,
1963         .agp_alloc_page         = agp_generic_alloc_page,
1964         .agp_alloc_pages        = agp_generic_alloc_pages,
1965         .agp_destroy_page       = agp_generic_destroy_page,
1966         .agp_destroy_pages      = agp_generic_destroy_pages,
1967         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1968         .chipset_flush          = intel_i830_chipset_flush,
1969 };
1970
1971 static const struct agp_bridge_driver intel_820_driver = {
1972         .owner                  = THIS_MODULE,
1973         .aperture_sizes         = intel_8xx_sizes,
1974         .size_type              = U8_APER_SIZE,
1975         .num_aperture_sizes     = 7,
1976         .configure              = intel_820_configure,
1977         .fetch_size             = intel_8xx_fetch_size,
1978         .cleanup                = intel_820_cleanup,
1979         .tlb_flush              = intel_820_tlbflush,
1980         .mask_memory            = agp_generic_mask_memory,
1981         .masks                  = intel_generic_masks,
1982         .agp_enable             = agp_generic_enable,
1983         .cache_flush            = global_cache_flush,
1984         .create_gatt_table      = agp_generic_create_gatt_table,
1985         .free_gatt_table        = agp_generic_free_gatt_table,
1986         .insert_memory          = agp_generic_insert_memory,
1987         .remove_memory          = agp_generic_remove_memory,
1988         .alloc_by_type          = agp_generic_alloc_by_type,
1989         .free_by_type           = agp_generic_free_by_type,
1990         .agp_alloc_page         = agp_generic_alloc_page,
1991         .agp_alloc_pages        = agp_generic_alloc_pages,
1992         .agp_destroy_page       = agp_generic_destroy_page,
1993         .agp_destroy_pages      = agp_generic_destroy_pages,
1994         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1995 };
1996
1997 static const struct agp_bridge_driver intel_830mp_driver = {
1998         .owner                  = THIS_MODULE,
1999         .aperture_sizes         = intel_830mp_sizes,
2000         .size_type              = U8_APER_SIZE,
2001         .num_aperture_sizes     = 4,
2002         .configure              = intel_830mp_configure,
2003         .fetch_size             = intel_8xx_fetch_size,
2004         .cleanup                = intel_8xx_cleanup,
2005         .tlb_flush              = intel_8xx_tlbflush,
2006         .mask_memory            = agp_generic_mask_memory,
2007         .masks                  = intel_generic_masks,
2008         .agp_enable             = agp_generic_enable,
2009         .cache_flush            = global_cache_flush,
2010         .create_gatt_table      = agp_generic_create_gatt_table,
2011         .free_gatt_table        = agp_generic_free_gatt_table,
2012         .insert_memory          = agp_generic_insert_memory,
2013         .remove_memory          = agp_generic_remove_memory,
2014         .alloc_by_type          = agp_generic_alloc_by_type,
2015         .free_by_type           = agp_generic_free_by_type,
2016         .agp_alloc_page         = agp_generic_alloc_page,
2017         .agp_alloc_pages        = agp_generic_alloc_pages,
2018         .agp_destroy_page       = agp_generic_destroy_page,
2019         .agp_destroy_pages      = agp_generic_destroy_pages,
2020         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2021 };
2022
2023 static const struct agp_bridge_driver intel_840_driver = {
2024         .owner                  = THIS_MODULE,
2025         .aperture_sizes         = intel_8xx_sizes,
2026         .size_type              = U8_APER_SIZE,
2027         .num_aperture_sizes     = 7,
2028         .configure              = intel_840_configure,
2029         .fetch_size             = intel_8xx_fetch_size,
2030         .cleanup                = intel_8xx_cleanup,
2031         .tlb_flush              = intel_8xx_tlbflush,
2032         .mask_memory            = agp_generic_mask_memory,
2033         .masks                  = intel_generic_masks,
2034         .agp_enable             = agp_generic_enable,
2035         .cache_flush            = global_cache_flush,
2036         .create_gatt_table      = agp_generic_create_gatt_table,
2037         .free_gatt_table        = agp_generic_free_gatt_table,
2038         .insert_memory          = agp_generic_insert_memory,
2039         .remove_memory          = agp_generic_remove_memory,
2040         .alloc_by_type          = agp_generic_alloc_by_type,
2041         .free_by_type           = agp_generic_free_by_type,
2042         .agp_alloc_page         = agp_generic_alloc_page,
2043         .agp_alloc_pages        = agp_generic_alloc_pages,
2044         .agp_destroy_page       = agp_generic_destroy_page,
2045         .agp_destroy_pages      = agp_generic_destroy_pages,
2046         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2047 };
2048
2049 static const struct agp_bridge_driver intel_845_driver = {
2050         .owner                  = THIS_MODULE,
2051         .aperture_sizes         = intel_8xx_sizes,
2052         .size_type              = U8_APER_SIZE,
2053         .num_aperture_sizes     = 7,
2054         .configure              = intel_845_configure,
2055         .fetch_size             = intel_8xx_fetch_size,
2056         .cleanup                = intel_8xx_cleanup,
2057         .tlb_flush              = intel_8xx_tlbflush,
2058         .mask_memory            = agp_generic_mask_memory,
2059         .masks                  = intel_generic_masks,
2060         .agp_enable             = agp_generic_enable,
2061         .cache_flush            = global_cache_flush,
2062         .create_gatt_table      = agp_generic_create_gatt_table,
2063         .free_gatt_table        = agp_generic_free_gatt_table,
2064         .insert_memory          = agp_generic_insert_memory,
2065         .remove_memory          = agp_generic_remove_memory,
2066         .alloc_by_type          = agp_generic_alloc_by_type,
2067         .free_by_type           = agp_generic_free_by_type,
2068         .agp_alloc_page         = agp_generic_alloc_page,
2069         .agp_alloc_pages        = agp_generic_alloc_pages,
2070         .agp_destroy_page       = agp_generic_destroy_page,
2071         .agp_destroy_pages      = agp_generic_destroy_pages,
2072         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2073         .chipset_flush          = intel_i830_chipset_flush,
2074 };
2075
2076 static const struct agp_bridge_driver intel_850_driver = {
2077         .owner                  = THIS_MODULE,
2078         .aperture_sizes         = intel_8xx_sizes,
2079         .size_type              = U8_APER_SIZE,
2080         .num_aperture_sizes     = 7,
2081         .configure              = intel_850_configure,
2082         .fetch_size             = intel_8xx_fetch_size,
2083         .cleanup                = intel_8xx_cleanup,
2084         .tlb_flush              = intel_8xx_tlbflush,
2085         .mask_memory            = agp_generic_mask_memory,
2086         .masks                  = intel_generic_masks,
2087         .agp_enable             = agp_generic_enable,
2088         .cache_flush            = global_cache_flush,
2089         .create_gatt_table      = agp_generic_create_gatt_table,
2090         .free_gatt_table        = agp_generic_free_gatt_table,
2091         .insert_memory          = agp_generic_insert_memory,
2092         .remove_memory          = agp_generic_remove_memory,
2093         .alloc_by_type          = agp_generic_alloc_by_type,
2094         .free_by_type           = agp_generic_free_by_type,
2095         .agp_alloc_page         = agp_generic_alloc_page,
2096         .agp_alloc_pages        = agp_generic_alloc_pages,
2097         .agp_destroy_page       = agp_generic_destroy_page,
2098         .agp_destroy_pages      = agp_generic_destroy_pages,
2099         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2100 };
2101
2102 static const struct agp_bridge_driver intel_860_driver = {
2103         .owner                  = THIS_MODULE,
2104         .aperture_sizes         = intel_8xx_sizes,
2105         .size_type              = U8_APER_SIZE,
2106         .num_aperture_sizes     = 7,
2107         .configure              = intel_860_configure,
2108         .fetch_size             = intel_8xx_fetch_size,
2109         .cleanup                = intel_8xx_cleanup,
2110         .tlb_flush              = intel_8xx_tlbflush,
2111         .mask_memory            = agp_generic_mask_memory,
2112         .masks                  = intel_generic_masks,
2113         .agp_enable             = agp_generic_enable,
2114         .cache_flush            = global_cache_flush,
2115         .create_gatt_table      = agp_generic_create_gatt_table,
2116         .free_gatt_table        = agp_generic_free_gatt_table,
2117         .insert_memory          = agp_generic_insert_memory,
2118         .remove_memory          = agp_generic_remove_memory,
2119         .alloc_by_type          = agp_generic_alloc_by_type,
2120         .free_by_type           = agp_generic_free_by_type,
2121         .agp_alloc_page         = agp_generic_alloc_page,
2122         .agp_alloc_pages        = agp_generic_alloc_pages,
2123         .agp_destroy_page       = agp_generic_destroy_page,
2124         .agp_destroy_pages      = agp_generic_destroy_pages,
2125         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2126 };
2127
2128 static const struct agp_bridge_driver intel_915_driver = {
2129         .owner                  = THIS_MODULE,
2130         .aperture_sizes         = intel_i830_sizes,
2131         .size_type              = FIXED_APER_SIZE,
2132         .num_aperture_sizes     = 4,
2133         .needs_scratch_page     = true,
2134         .configure              = intel_i915_configure,
2135         .fetch_size             = intel_i9xx_fetch_size,
2136         .cleanup                = intel_i915_cleanup,
2137         .tlb_flush              = intel_i810_tlbflush,
2138         .mask_memory            = intel_i810_mask_memory,
2139         .masks                  = intel_i810_masks,
2140         .agp_enable             = intel_i810_agp_enable,
2141         .cache_flush            = global_cache_flush,
2142         .create_gatt_table      = intel_i915_create_gatt_table,
2143         .free_gatt_table        = intel_i830_free_gatt_table,
2144         .insert_memory          = intel_i915_insert_entries,
2145         .remove_memory          = intel_i915_remove_entries,
2146         .alloc_by_type          = intel_i830_alloc_by_type,
2147         .free_by_type           = intel_i810_free_by_type,
2148         .agp_alloc_page         = agp_generic_alloc_page,
2149         .agp_alloc_pages        = agp_generic_alloc_pages,
2150         .agp_destroy_page       = agp_generic_destroy_page,
2151         .agp_destroy_pages      = agp_generic_destroy_pages,
2152         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
2153         .chipset_flush          = intel_i915_chipset_flush,
2154 #ifdef USE_PCI_DMA_API
2155         .agp_map_page           = intel_agp_map_page,
2156         .agp_unmap_page         = intel_agp_unmap_page,
2157         .agp_map_memory         = intel_agp_map_memory,
2158         .agp_unmap_memory       = intel_agp_unmap_memory,
2159 #endif
2160 };
2161
2162 static const struct agp_bridge_driver intel_i965_driver = {
2163         .owner                  = THIS_MODULE,
2164         .aperture_sizes         = intel_i830_sizes,
2165         .size_type              = FIXED_APER_SIZE,
2166         .num_aperture_sizes     = 4,
2167         .needs_scratch_page     = true,
2168         .configure              = intel_i915_configure,
2169         .fetch_size             = intel_i9xx_fetch_size,
2170         .cleanup                = intel_i915_cleanup,
2171         .tlb_flush              = intel_i810_tlbflush,
2172         .mask_memory            = intel_i965_mask_memory,
2173         .masks                  = intel_i810_masks,
2174         .agp_enable             = intel_i810_agp_enable,
2175         .cache_flush            = global_cache_flush,
2176         .create_gatt_table      = intel_i965_create_gatt_table,
2177         .free_gatt_table        = intel_i830_free_gatt_table,
2178         .insert_memory          = intel_i915_insert_entries,
2179         .remove_memory          = intel_i915_remove_entries,
2180         .alloc_by_type          = intel_i830_alloc_by_type,
2181         .free_by_type           = intel_i810_free_by_type,
2182         .agp_alloc_page         = agp_generic_alloc_page,
2183         .agp_alloc_pages        = agp_generic_alloc_pages,
2184         .agp_destroy_page       = agp_generic_destroy_page,
2185         .agp_destroy_pages      = agp_generic_destroy_pages,
2186         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
2187         .chipset_flush          = intel_i915_chipset_flush,
2188 #ifdef USE_PCI_DMA_API
2189         .agp_map_page           = intel_agp_map_page,
2190         .agp_unmap_page         = intel_agp_unmap_page,
2191         .agp_map_memory         = intel_agp_map_memory,
2192         .agp_unmap_memory       = intel_agp_unmap_memory,
2193 #endif
2194 };
2195
2196 static const struct agp_bridge_driver intel_7505_driver = {
2197         .owner                  = THIS_MODULE,
2198         .aperture_sizes         = intel_8xx_sizes,
2199         .size_type              = U8_APER_SIZE,
2200         .num_aperture_sizes     = 7,
2201         .configure              = intel_7505_configure,
2202         .fetch_size             = intel_8xx_fetch_size,
2203         .cleanup                = intel_8xx_cleanup,
2204         .tlb_flush              = intel_8xx_tlbflush,
2205         .mask_memory            = agp_generic_mask_memory,
2206         .masks                  = intel_generic_masks,
2207         .agp_enable             = agp_generic_enable,
2208         .cache_flush            = global_cache_flush,
2209         .create_gatt_table      = agp_generic_create_gatt_table,
2210         .free_gatt_table        = agp_generic_free_gatt_table,
2211         .insert_memory          = agp_generic_insert_memory,
2212         .remove_memory          = agp_generic_remove_memory,
2213         .alloc_by_type          = agp_generic_alloc_by_type,
2214         .free_by_type           = agp_generic_free_by_type,
2215         .agp_alloc_page         = agp_generic_alloc_page,
2216         .agp_alloc_pages        = agp_generic_alloc_pages,
2217         .agp_destroy_page       = agp_generic_destroy_page,
2218         .agp_destroy_pages      = agp_generic_destroy_pages,
2219         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2220 };
2221
2222 static const struct agp_bridge_driver intel_g33_driver = {
2223         .owner                  = THIS_MODULE,
2224         .aperture_sizes         = intel_i830_sizes,
2225         .size_type              = FIXED_APER_SIZE,
2226         .num_aperture_sizes     = 4,
2227         .needs_scratch_page     = true,
2228         .configure              = intel_i915_configure,
2229         .fetch_size             = intel_i9xx_fetch_size,
2230         .cleanup                = intel_i915_cleanup,
2231         .tlb_flush              = intel_i810_tlbflush,
2232         .mask_memory            = intel_i965_mask_memory,
2233         .masks                  = intel_i810_masks,
2234         .agp_enable             = intel_i810_agp_enable,
2235         .cache_flush            = global_cache_flush,
2236         .create_gatt_table      = intel_i915_create_gatt_table,
2237         .free_gatt_table        = intel_i830_free_gatt_table,
2238         .insert_memory          = intel_i915_insert_entries,
2239         .remove_memory          = intel_i915_remove_entries,
2240         .alloc_by_type          = intel_i830_alloc_by_type,
2241         .free_by_type           = intel_i810_free_by_type,
2242         .agp_alloc_page         = agp_generic_alloc_page,
2243         .agp_alloc_pages        = agp_generic_alloc_pages,
2244         .agp_destroy_page       = agp_generic_destroy_page,
2245         .agp_destroy_pages      = agp_generic_destroy_pages,
2246         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
2247         .chipset_flush          = intel_i915_chipset_flush,
2248 #ifdef USE_PCI_DMA_API
2249         .agp_map_page           = intel_agp_map_page,
2250         .agp_unmap_page         = intel_agp_unmap_page,
2251         .agp_map_memory         = intel_agp_map_memory,
2252         .agp_unmap_memory       = intel_agp_unmap_memory,
2253 #endif
2254 };
2255
2256 static int find_gmch(u16 device)
2257 {
2258         struct pci_dev *gmch_device;
2259
2260         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
2261         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
2262                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
2263                                              device, gmch_device);
2264         }
2265
2266         if (!gmch_device)
2267                 return 0;
2268
2269         intel_private.pcidev = gmch_device;
2270         return 1;
2271 }
2272
2273 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
2274  * driver and gmch_driver must be non-null, and find_gmch will determine
2275  * which one should be used if a gmch_chip_id is present.
2276  */
2277 static const struct intel_driver_description {
2278         unsigned int chip_id;
2279         unsigned int gmch_chip_id;
2280         unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
2281         char *name;
2282         const struct agp_bridge_driver *driver;
2283         const struct agp_bridge_driver *gmch_driver;
2284 } intel_agp_chipsets[] = {
2285         { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
2286         { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
2287         { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
2288         { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
2289                 NULL, &intel_810_driver },
2290         { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
2291                 NULL, &intel_810_driver },
2292         { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
2293                 NULL, &intel_810_driver },
2294         { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
2295                 &intel_815_driver, &intel_810_driver },
2296         { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
2297         { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
2298         { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
2299                 &intel_830mp_driver, &intel_830_driver },
2300         { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
2301         { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
2302         { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
2303                 &intel_845_driver, &intel_830_driver },
2304         { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
2305         { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, 0, "854",
2306                 &intel_845_driver, &intel_830_driver },
2307         { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
2308         { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
2309                 &intel_845_driver, &intel_830_driver },
2310         { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
2311         { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
2312                 &intel_845_driver, &intel_830_driver },
2313         { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
2314         { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
2315                 NULL, &intel_915_driver },
2316         { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
2317                 NULL, &intel_915_driver },
2318         { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
2319                 NULL, &intel_915_driver },
2320         { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
2321                 NULL, &intel_915_driver },
2322         { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
2323                 NULL, &intel_915_driver },
2324         { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
2325                 NULL, &intel_915_driver },
2326         { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
2327                 NULL, &intel_i965_driver },
2328         { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35",
2329                 NULL, &intel_i965_driver },
2330         { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
2331                 NULL, &intel_i965_driver },
2332         { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
2333                 NULL, &intel_i965_driver },
2334         { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
2335                 NULL, &intel_i965_driver },
2336         { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
2337                 NULL, &intel_i965_driver },
2338         { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
2339         { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
2340         { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
2341                 NULL, &intel_g33_driver },
2342         { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
2343                 NULL, &intel_g33_driver },
2344         { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
2345                 NULL, &intel_g33_driver },
2346         { PCI_DEVICE_ID_INTEL_IGDGM_HB, PCI_DEVICE_ID_INTEL_IGDGM_IG, 0, "IGD",
2347                 NULL, &intel_g33_driver },
2348         { PCI_DEVICE_ID_INTEL_IGDG_HB, PCI_DEVICE_ID_INTEL_IGDG_IG, 0, "IGD",
2349                 NULL, &intel_g33_driver },
2350         { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0,
2351             "Mobile Intel® GM45 Express", NULL, &intel_i965_driver },
2352         { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0,
2353             "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
2354         { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
2355             "Q45/Q43", NULL, &intel_i965_driver },
2356         { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
2357             "G45/G43", NULL, &intel_i965_driver },
2358         { PCI_DEVICE_ID_INTEL_B43_HB, PCI_DEVICE_ID_INTEL_B43_IG, 0,
2359             "B43", NULL, &intel_i965_driver },
2360         { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0,
2361             "G41", NULL, &intel_i965_driver },
2362         { PCI_DEVICE_ID_INTEL_IGDNG_D_HB, PCI_DEVICE_ID_INTEL_IGDNG_D_IG, 0,
2363             "IGDNG/D", NULL, &intel_i965_driver },
2364         { PCI_DEVICE_ID_INTEL_IGDNG_M_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,
2365             "IGDNG/M", NULL, &intel_i965_driver },
2366         { PCI_DEVICE_ID_INTEL_IGDNG_MA_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,
2367             "IGDNG/MA", NULL, &intel_i965_driver },
2368         { 0, 0, 0, NULL, NULL, NULL }
2369 };
2370
2371 static int __devinit agp_intel_probe(struct pci_dev *pdev,
2372                                      const struct pci_device_id *ent)
2373 {
2374         struct agp_bridge_data *bridge;
2375         u8 cap_ptr = 0;
2376         struct resource *r;
2377         int i;
2378
2379         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2380
2381         bridge = agp_alloc_bridge();
2382         if (!bridge)
2383                 return -ENOMEM;
2384
2385         for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
2386                 /* In case that multiple models of gfx chip may
2387                    stand on same host bridge type, this can be
2388                    sure we detect the right IGD. */
2389                 if (pdev->device == intel_agp_chipsets[i].chip_id) {
2390                         if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
2391                                 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
2392                                 bridge->driver =
2393                                         intel_agp_chipsets[i].gmch_driver;
2394                                 break;
2395                         } else if (intel_agp_chipsets[i].multi_gmch_chip) {
2396                                 continue;
2397                         } else {
2398                                 bridge->driver = intel_agp_chipsets[i].driver;
2399                                 break;
2400                         }
2401                 }
2402         }
2403
2404         if (intel_agp_chipsets[i].name == NULL) {
2405                 if (cap_ptr)
2406                         dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n",
2407                                  pdev->vendor, pdev->device);
2408                 agp_put_bridge(bridge);
2409                 return -ENODEV;
2410         }
2411
2412         if (bridge->driver == NULL) {
2413                 /* bridge has no AGP and no IGD detected */
2414                 if (cap_ptr)
2415                         dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n",
2416                                  intel_agp_chipsets[i].gmch_chip_id);
2417                 agp_put_bridge(bridge);
2418                 return -ENODEV;
2419         }
2420
2421         bridge->dev = pdev;
2422         bridge->capndx = cap_ptr;
2423         bridge->dev_private_data = &intel_private;
2424
2425         dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
2426
2427         /*
2428         * The following fixes the case where the BIOS has "forgotten" to
2429         * provide an address range for the GART.
2430         * 20030610 - hamish@zot.org
2431         */
2432         r = &pdev->resource[0];
2433         if (!r->start && r->end) {
2434                 if (pci_assign_resource(pdev, 0)) {
2435                         dev_err(&pdev->dev, "can't assign resource 0\n");
2436                         agp_put_bridge(bridge);
2437                         return -ENODEV;
2438                 }
2439         }
2440
2441         /*
2442         * If the device has not been properly setup, the following will catch
2443         * the problem and should stop the system from crashing.
2444         * 20030610 - hamish@zot.org
2445         */
2446         if (pci_enable_device(pdev)) {
2447                 dev_err(&pdev->dev, "can't enable PCI device\n");
2448                 agp_put_bridge(bridge);
2449                 return -ENODEV;
2450         }
2451
2452         /* Fill in the mode register */
2453         if (cap_ptr) {
2454                 pci_read_config_dword(pdev,
2455                                 bridge->capndx+PCI_AGP_STATUS,
2456                                 &bridge->mode);
2457         }
2458
2459         pci_set_drvdata(pdev, bridge);
2460         return agp_add_bridge(bridge);
2461 }
2462
2463 static void __devexit agp_intel_remove(struct pci_dev *pdev)
2464 {
2465         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2466
2467         agp_remove_bridge(bridge);
2468
2469         if (intel_private.pcidev)
2470                 pci_dev_put(intel_private.pcidev);
2471
2472         agp_put_bridge(bridge);
2473 }
2474
2475 #ifdef CONFIG_PM
2476 static int agp_intel_resume(struct pci_dev *pdev)
2477 {
2478         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2479         int ret_val;
2480
2481         if (bridge->driver == &intel_generic_driver)
2482                 intel_configure();
2483         else if (bridge->driver == &intel_850_driver)
2484                 intel_850_configure();
2485         else if (bridge->driver == &intel_845_driver)
2486                 intel_845_configure();
2487         else if (bridge->driver == &intel_830mp_driver)
2488                 intel_830mp_configure();
2489         else if (bridge->driver == &intel_915_driver)
2490                 intel_i915_configure();
2491         else if (bridge->driver == &intel_830_driver)
2492                 intel_i830_configure();
2493         else if (bridge->driver == &intel_810_driver)
2494                 intel_i810_configure();
2495         else if (bridge->driver == &intel_i965_driver)
2496                 intel_i915_configure();
2497
2498         ret_val = agp_rebind_memory();
2499         if (ret_val != 0)
2500                 return ret_val;
2501
2502         return 0;
2503 }
2504 #endif
2505
2506 static struct pci_device_id agp_intel_pci_table[] = {
2507 #define ID(x)                                           \
2508         {                                               \
2509         .class          = (PCI_CLASS_BRIDGE_HOST << 8), \
2510         .class_mask     = ~0,                           \
2511         .vendor         = PCI_VENDOR_ID_INTEL,          \
2512         .device         = x,                            \
2513         .subvendor      = PCI_ANY_ID,                   \
2514         .subdevice      = PCI_ANY_ID,                   \
2515         }
2516         ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2517         ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2518         ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2519         ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2520         ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2521         ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2522         ID(PCI_DEVICE_ID_INTEL_82815_MC),
2523         ID(PCI_DEVICE_ID_INTEL_82820_HB),
2524         ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2525         ID(PCI_DEVICE_ID_INTEL_82830_HB),
2526         ID(PCI_DEVICE_ID_INTEL_82840_HB),
2527         ID(PCI_DEVICE_ID_INTEL_82845_HB),
2528         ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2529         ID(PCI_DEVICE_ID_INTEL_82850_HB),
2530         ID(PCI_DEVICE_ID_INTEL_82854_HB),
2531         ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2532         ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2533         ID(PCI_DEVICE_ID_INTEL_82860_HB),
2534         ID(PCI_DEVICE_ID_INTEL_82865_HB),
2535         ID(PCI_DEVICE_ID_INTEL_82875_HB),
2536         ID(PCI_DEVICE_ID_INTEL_7505_0),
2537         ID(PCI_DEVICE_ID_INTEL_7205_0),
2538         ID(PCI_DEVICE_ID_INTEL_E7221_HB),
2539         ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2540         ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2541         ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2542         ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2543         ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2544         ID(PCI_DEVICE_ID_INTEL_IGDGM_HB),
2545         ID(PCI_DEVICE_ID_INTEL_IGDG_HB),
2546         ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2547         ID(PCI_DEVICE_ID_INTEL_82G35_HB),
2548         ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2549         ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2550         ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2551         ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2552         ID(PCI_DEVICE_ID_INTEL_G33_HB),
2553         ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2554         ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2555         ID(PCI_DEVICE_ID_INTEL_GM45_HB),
2556         ID(PCI_DEVICE_ID_INTEL_IGD_E_HB),
2557         ID(PCI_DEVICE_ID_INTEL_Q45_HB),
2558         ID(PCI_DEVICE_ID_INTEL_G45_HB),
2559         ID(PCI_DEVICE_ID_INTEL_G41_HB),
2560         ID(PCI_DEVICE_ID_INTEL_B43_HB),
2561         ID(PCI_DEVICE_ID_INTEL_IGDNG_D_HB),
2562         ID(PCI_DEVICE_ID_INTEL_IGDNG_M_HB),
2563         ID(PCI_DEVICE_ID_INTEL_IGDNG_MA_HB),
2564         { }
2565 };
2566
2567 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2568
2569 static struct pci_driver agp_intel_pci_driver = {
2570         .name           = "agpgart-intel",
2571         .id_table       = agp_intel_pci_table,
2572         .probe          = agp_intel_probe,
2573         .remove         = __devexit_p(agp_intel_remove),
2574 #ifdef CONFIG_PM
2575         .resume         = agp_intel_resume,
2576 #endif
2577 };
2578
2579 static int __init agp_intel_init(void)
2580 {
2581         if (agp_off)
2582                 return -EINVAL;
2583         return pci_register_driver(&agp_intel_pci_driver);
2584 }
2585
2586 static void __exit agp_intel_cleanup(void)
2587 {
2588         pci_unregister_driver(&agp_intel_pci_driver);
2589 }
2590
2591 module_init(agp_intel_init);
2592 module_exit(agp_intel_cleanup);
2593
2594 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
2595 MODULE_LICENSE("GPL and additional rights");