drivers/char/agp/intel-agp.c

   1 /*
   2  * Intel AGPGART routines.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/init.h>
   8 #include <linux/kernel.h>
   9 #include <linux/pagemap.h>
  10 #include <linux/agp_backend.h>
  11 #include "agp.h"
  12
  13 #define PCI_DEVICE_ID_INTEL_82946GZ_HB      0x2970
  14 #define PCI_DEVICE_ID_INTEL_82946GZ_IG      0x2972
  15 #define PCI_DEVICE_ID_INTEL_82965G_1_HB     0x2980
  16 #define PCI_DEVICE_ID_INTEL_82965G_1_IG     0x2982
  17 #define PCI_DEVICE_ID_INTEL_82965Q_HB       0x2990
  18 #define PCI_DEVICE_ID_INTEL_82965Q_IG       0x2992
  19 #define PCI_DEVICE_ID_INTEL_82965G_HB       0x29A0
  20 #define PCI_DEVICE_ID_INTEL_82965G_IG       0x29A2
  21 #define PCI_DEVICE_ID_INTEL_82965GM_HB      0x2A00
  22 #define PCI_DEVICE_ID_INTEL_82965GM_IG      0x2A02
  23 #define PCI_DEVICE_ID_INTEL_82965GME_IG     0x2A12
  24
  25 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
  26                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \
  27                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
  28                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
  29                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB)
  30
  31
  32 extern int agp_memory_reserved;
  33
  34
  35 /* Intel 815 register */
  36 #define INTEL_815_APCONT        0x51
  37 #define INTEL_815_ATTBASE_MASK  ~0x1FFFFFFF
  38
  39 /* Intel i820 registers */
  40 #define INTEL_I820_RDCR         0x51
  41 #define INTEL_I820_ERRSTS       0xc8
  42
  43 /* Intel i840 registers */
  44 #define INTEL_I840_MCHCFG       0x50
  45 #define INTEL_I840_ERRSTS       0xc8
  46
  47 /* Intel i850 registers */
  48 #define INTEL_I850_MCHCFG       0x50
  49 #define INTEL_I850_ERRSTS       0xc8
  50
  51 /* intel 915G registers */
  52 #define I915_GMADDR     0x18
  53 #define I915_MMADDR     0x10
  54 #define I915_PTEADDR    0x1C
  55 #define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
  56 #define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
  57
  58 /* Intel 965G registers */
  59 #define I965_MSAC 0x62
  60
  61 /* Intel 7505 registers */
  62 #define INTEL_I7505_APSIZE      0x74
  63 #define INTEL_I7505_NCAPID      0x60
  64 #define INTEL_I7505_NISTAT      0x6c
  65 #define INTEL_I7505_ATTBASE     0x78
  66 #define INTEL_I7505_ERRSTS      0x42
  67 #define INTEL_I7505_AGPCTRL     0x70
  68 #define INTEL_I7505_MCHCFG      0x50
  69
  70 static const struct aper_size_info_fixed intel_i810_sizes[] =
  71 {
  72         {64, 16384, 4},
  73         /* The 32M mode still requires a 64k gatt */
  74         {32, 8192, 4}
  75 };
  76
  77 #define AGP_DCACHE_MEMORY       1
  78 #define AGP_PHYS_MEMORY         2
  79 #define INTEL_AGP_CACHED_MEMORY 3
  80
  81 static struct gatt_mask intel_i810_masks[] =
  82 {
  83         {.mask = I810_PTE_VALID, .type = 0},
  84         {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
  85         {.mask = I810_PTE_VALID, .type = 0},
  86         {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
  87          .type = INTEL_AGP_CACHED_MEMORY}
  88 };
  89
  90 static struct _intel_private {
  91         struct pci_dev *pcidev; /* device one */
  92         u8 __iomem *registers;
  93         u32 __iomem *gtt;               /* I915G */
  94         int num_dcache_entries;
  95         /* gtt_entries is the number of gtt entries that are already mapped
  96          * to stolen memory.  Stolen memory is larger than the memory mapped
  97          * through gtt_entries, as it includes some reserved space for the BIOS
  98          * popup and for the GTT.
  99          */
 100         int gtt_entries;                        /* i830+ */
 101 } intel_private;
 102
 103 static int intel_i810_fetch_size(void)
 104 {
 105         u32 smram_miscc;
 106         struct aper_size_info_fixed *values;
 107
 108         pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
 109         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 110
 111         if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
 112                 printk(KERN_WARNING PFX "i810 is disabled\n");
 113                 return 0;
 114         }
 115         if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
 116                 agp_bridge->previous_size =
 117                         agp_bridge->current_size = (void *) (values + 1);
 118                 agp_bridge->aperture_size_idx = 1;
 119                 return values[1].size;
 120         } else {
 121                 agp_bridge->previous_size =
 122                         agp_bridge->current_size = (void *) (values);
 123                 agp_bridge->aperture_size_idx = 0;
 124                 return values[0].size;
 125         }
 126
 127         return 0;
 128 }
 129
 130 static int intel_i810_configure(void)
 131 {
 132         struct aper_size_info_fixed *current_size;
 133         u32 temp;
 134         int i;
 135
 136         current_size = A_SIZE_FIX(agp_bridge->current_size);
 137
 138         if (!intel_private.registers) {
 139                 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 140                 temp &= 0xfff80000;
 141
 142                 intel_private.registers = ioremap(temp, 128 * 4096);
 143                 if (!intel_private.registers) {
 144                         printk(KERN_ERR PFX "Unable to remap memory.\n");
 145                         return -ENOMEM;
 146                 }
 147         }
 148
 149         if ((readl(intel_private.registers+I810_DRAM_CTL)
 150                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 151                 /* This will need to be dynamically assigned */
 152                 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n");
 153                 intel_private.num_dcache_entries = 1024;
 154         }
 155         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 156         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 157         writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 158         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 159
 160         if (agp_bridge->driver->needs_scratch_page) {
 161                 for (i = 0; i < current_size->num_entries; i++) {
 162                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 163                         readl(intel_private.registers+I810_PTE_BASE+(i*4));     /* PCI posting. */
 164                 }
 165         }
 166         global_cache_flush();
 167         return 0;
 168 }
 169
 170 static void intel_i810_cleanup(void)
 171 {
 172         writel(0, intel_private.registers+I810_PGETBL_CTL);
 173         readl(intel_private.registers); /* PCI Posting. */
 174         iounmap(intel_private.registers);
 175 }
 176
 177 static void intel_i810_tlbflush(struct agp_memory *mem)
 178 {
 179         return;
 180 }
 181
 182 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 183 {
 184         return;
 185 }
 186
 187 /* Exists to support ARGB cursors */
 188 static void *i8xx_alloc_pages(void)
 189 {
 190         struct page * page;
 191
 192         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
 193         if (page == NULL)
 194                 return NULL;
 195
 196         if (change_page_attr(page, 4, PAGE_KERNEL_NOCACHE) < 0) {
 197                 change_page_attr(page, 4, PAGE_KERNEL);
 198                 global_flush_tlb();
 199                 __free_pages(page, 2);
 200                 return NULL;
 201         }
 202         global_flush_tlb();
 203         get_page(page);
 204         SetPageLocked(page);
 205         atomic_inc(&agp_bridge->current_memory_agp);
 206         return page_address(page);
 207 }
 208
 209 static void i8xx_destroy_pages(void *addr)
 210 {
 211         struct page *page;
 212
 213         if (addr == NULL)
 214                 return;
 215
 216         page = virt_to_page(addr);
 217         change_page_attr(page, 4, PAGE_KERNEL);
 218         global_flush_tlb();
 219         put_page(page);
 220         unlock_page(page);
 221         __free_pages(page, 2);
 222         atomic_dec(&agp_bridge->current_memory_agp);
 223 }
 224
 225 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
 226                                         int type)
 227 {
 228         if (type < AGP_USER_TYPES)
 229                 return type;
 230         else if (type == AGP_USER_CACHED_MEMORY)
 231                 return INTEL_AGP_CACHED_MEMORY;
 232         else
 233                 return 0;
 234 }
 235
 236 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
 237                                 int type)
 238 {
 239         int i, j, num_entries;
 240         void *temp;
 241         int ret = -EINVAL;
 242         int mask_type;
 243
 244         if (mem->page_count == 0)
 245                 goto out;
 246
 247         temp = agp_bridge->current_size;
 248         num_entries = A_SIZE_FIX(temp)->num_entries;
 249
 250         if ((pg_start + mem->page_count) > num_entries)
 251                 goto out_err;
 252
 253
 254         for (j = pg_start; j < (pg_start + mem->page_count); j++) {
 255                 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
 256                         ret = -EBUSY;
 257                         goto out_err;
 258                 }
 259         }
 260
 261         if (type != mem->type)
 262                 goto out_err;
 263
 264         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 265
 266         switch (mask_type) {
 267         case AGP_DCACHE_MEMORY:
 268                 if (!mem->is_flushed)
 269                         global_cache_flush();
 270                 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 271                         writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
 272                                intel_private.registers+I810_PTE_BASE+(i*4));
 273                 }
 274                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 275                 break;
 276         case AGP_PHYS_MEMORY:
 277         case AGP_NORMAL_MEMORY:
 278                 if (!mem->is_flushed)
 279                         global_cache_flush();
 280                 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 281                         writel(agp_bridge->driver->mask_memory(agp_bridge,
 282                                                                mem->memory[i],
 283                                                                mask_type),
 284                                intel_private.registers+I810_PTE_BASE+(j*4));
 285                 }
 286                 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 287                 break;
 288         default:
 289                 goto out_err;
 290         }
 291
 292         agp_bridge->driver->tlb_flush(mem);
 293 out:
 294         ret = 0;
 295 out_err:
 296         mem->is_flushed = 1;
 297         return ret;
 298 }
 299
 300 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
 301                                 int type)
 302 {
 303         int i;
 304
 305         if (mem->page_count == 0)
 306                 return 0;
 307
 308         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 309                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 310         }
 311         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 312
 313         agp_bridge->driver->tlb_flush(mem);
 314         return 0;
 315 }
 316
 317 /*
 318  * The i810/i830 requires a physical address to program its mouse
 319  * pointer into hardware.
 320  * However the Xserver still writes to it through the agp aperture.
 321  */
 322 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
 323 {
 324         struct agp_memory *new;
 325         void *addr;
 326
 327         switch (pg_count) {
 328         case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
 329                 global_flush_tlb();
 330                 break;
 331         case 4:
 332                 /* kludge to get 4 physical pages for ARGB cursor */
 333                 addr = i8xx_alloc_pages();
 334                 break;
 335         default:
 336                 return NULL;
 337         }
 338
 339         if (addr == NULL)
 340                 return NULL;
 341
 342         new = agp_create_memory(pg_count);
 343         if (new == NULL)
 344                 return NULL;
 345
 346         new->memory[0] = virt_to_gart(addr);
 347         if (pg_count == 4) {
 348                 /* kludge to get 4 physical pages for ARGB cursor */
 349                 new->memory[1] = new->memory[0] + PAGE_SIZE;
 350                 new->memory[2] = new->memory[1] + PAGE_SIZE;
 351                 new->memory[3] = new->memory[2] + PAGE_SIZE;
 352         }
 353         new->page_count = pg_count;
 354         new->num_scratch_pages = pg_count;
 355         new->type = AGP_PHYS_MEMORY;
 356         new->physical = new->memory[0];
 357         return new;
 358 }
 359
 360 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
 361 {
 362         struct agp_memory *new;
 363
 364         if (type == AGP_DCACHE_MEMORY) {
 365                 if (pg_count != intel_private.num_dcache_entries)
 366                         return NULL;
 367
 368                 new = agp_create_memory(1);
 369                 if (new == NULL)
 370                         return NULL;
 371
 372                 new->type = AGP_DCACHE_MEMORY;
 373                 new->page_count = pg_count;
 374                 new->num_scratch_pages = 0;
 375                 agp_free_page_array(new);
 376                 return new;
 377         }
 378         if (type == AGP_PHYS_MEMORY)
 379                 return alloc_agpphysmem_i8xx(pg_count, type);
 380         return NULL;
 381 }
 382
 383 static void intel_i810_free_by_type(struct agp_memory *curr)
 384 {
 385         agp_free_key(curr->key);
 386         if (curr->type == AGP_PHYS_MEMORY) {
 387                 if (curr->page_count == 4)
 388                         i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
 389                 else {
 390                         agp_bridge->driver->agp_destroy_page(
 391                                  gart_to_virt(curr->memory[0]));
 392                         global_flush_tlb();
 393                 }
 394                 agp_free_page_array(curr);
 395         }
 396         kfree(curr);
 397 }
 398
 399 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
 400         unsigned long addr, int type)
 401 {
 402         /* Type checking must be done elsewhere */
 403         return addr | bridge->driver->masks[type].mask;
 404 }
 405
 406 static struct aper_size_info_fixed intel_i830_sizes[] =
 407 {
 408         {128, 32768, 5},
 409         /* The 64M mode still requires a 128k gatt */
 410         {64, 16384, 5},
 411         {256, 65536, 6},
 412         {512, 131072, 7},
 413 };
 414
 415 static void intel_i830_init_gtt_entries(void)
 416 {
 417         u16 gmch_ctrl;
 418         int gtt_entries;
 419         u8 rdct;
 420         int local = 0;
 421         static const int ddt[4] = { 0, 16, 32, 64 };
 422         int size; /* reserved space (in kb) at the top of stolen memory */
 423
 424         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
 425
 426         if (IS_I965) {
 427                 u32 pgetbl_ctl;
 428                 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 429
 430                 /* The 965 has a field telling us the size of the GTT,
 431                  * which may be larger than what is necessary to map the
 432                  * aperture.
 433                  */
 434                 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
 435                 case I965_PGETBL_SIZE_128KB:
 436                         size = 128;
 437                         break;
 438                 case I965_PGETBL_SIZE_256KB:
 439                         size = 256;
 440                         break;
 441                 case I965_PGETBL_SIZE_512KB:
 442                         size = 512;
 443                         break;
 444                 default:
 445                         printk(KERN_INFO PFX "Unknown page table size, "
 446                                "assuming 512KB\n");
 447                         size = 512;
 448                 }
 449                 size += 4; /* add in BIOS popup space */
 450         } else {
 451                 /* On previous hardware, the GTT size was just what was
 452                  * required to map the aperture.
 453                  */
 454                 size = agp_bridge->driver->fetch_size() + 4;
 455         }
 456
 457         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
 458             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
 459                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 460                 case I830_GMCH_GMS_STOLEN_512:
 461                         gtt_entries = KB(512) - KB(size);
 462                         break;
 463                 case I830_GMCH_GMS_STOLEN_1024:
 464                         gtt_entries = MB(1) - KB(size);
 465                         break;
 466                 case I830_GMCH_GMS_STOLEN_8192:
 467                         gtt_entries = MB(8) - KB(size);
 468                         break;
 469                 case I830_GMCH_GMS_LOCAL:
 470                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
 471                         gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
 472                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
 473                         local = 1;
 474                         break;
 475                 default:
 476                         gtt_entries = 0;
 477                         break;
 478                 }
 479         } else {
 480                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 481                 case I855_GMCH_GMS_STOLEN_1M:
 482                         gtt_entries = MB(1) - KB(size);
 483                         break;
 484                 case I855_GMCH_GMS_STOLEN_4M:
 485                         gtt_entries = MB(4) - KB(size);
 486                         break;
 487                 case I855_GMCH_GMS_STOLEN_8M:
 488                         gtt_entries = MB(8) - KB(size);
 489                         break;
 490                 case I855_GMCH_GMS_STOLEN_16M:
 491                         gtt_entries = MB(16) - KB(size);
 492                         break;
 493                 case I855_GMCH_GMS_STOLEN_32M:
 494                         gtt_entries = MB(32) - KB(size);
 495                         break;
 496                 case I915_GMCH_GMS_STOLEN_48M:
 497                         /* Check it's really I915G */
 498                         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
 499                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
 500                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
 501                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || IS_I965 )
 502                                 gtt_entries = MB(48) - KB(size);
 503                         else
 504                                 gtt_entries = 0;
 505                         break;
 506                 case I915_GMCH_GMS_STOLEN_64M:
 507                         /* Check it's really I915G */
 508                         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
 509                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
 510                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
 511                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || IS_I965)
 512                                 gtt_entries = MB(64) - KB(size);
 513                         else
 514                                 gtt_entries = 0;
 515                 default:
 516                         gtt_entries = 0;
 517                         break;
 518                 }
 519         }
 520         if (gtt_entries > 0)
 521                 printk(KERN_INFO PFX "Detected %dK %s memory.\n",
 522                        gtt_entries / KB(1), local ? "local" : "stolen");
 523         else
 524                 printk(KERN_INFO PFX
 525                        "No pre-allocated video memory detected.\n");
 526         gtt_entries /= KB(4);
 527
 528         intel_private.gtt_entries = gtt_entries;
 529 }
 530
 531 /* The intel i830 automatically initializes the agp aperture during POST.
 532  * Use the memory already set aside for in the GTT.
 533  */
 534 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
 535 {
 536         int page_order;
 537         struct aper_size_info_fixed *size;
 538         int num_entries;
 539         u32 temp;
 540
 541         size = agp_bridge->current_size;
 542         page_order = size->page_order;
 543         num_entries = size->num_entries;
 544         agp_bridge->gatt_table_real = NULL;
 545
 546         pci_read_config_dword(intel_private.pcidev,I810_MMADDR,&temp);
 547         temp &= 0xfff80000;
 548
 549         intel_private.registers = ioremap(temp,128 * 4096);
 550         if (!intel_private.registers)
 551                 return -ENOMEM;
 552
 553         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
 554         global_cache_flush();   /* FIXME: ?? */
 555
 556         /* we have to call this as early as possible after the MMIO base address is known */
 557         intel_i830_init_gtt_entries();
 558
 559         agp_bridge->gatt_table = NULL;
 560
 561         agp_bridge->gatt_bus_addr = temp;
 562
 563         return 0;
 564 }
 565
 566 /* Return the gatt table to a sane state. Use the top of stolen
 567  * memory for the GTT.
 568  */
 569 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
 570 {
 571         return 0;
 572 }
 573
 574 static int intel_i830_fetch_size(void)
 575 {
 576         u16 gmch_ctrl;
 577         struct aper_size_info_fixed *values;
 578
 579         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 580
 581         if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
 582             agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
 583                 /* 855GM/852GM/865G has 128MB aperture size */
 584                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 585                 agp_bridge->aperture_size_idx = 0;
 586                 return values[0].size;
 587         }
 588
 589         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
 590
 591         if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
 592                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 593                 agp_bridge->aperture_size_idx = 0;
 594                 return values[0].size;
 595         } else {
 596                 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
 597                 agp_bridge->aperture_size_idx = 1;
 598                 return values[1].size;
 599         }
 600
 601         return 0;
 602 }
 603
 604 static int intel_i830_configure(void)
 605 {
 606         struct aper_size_info_fixed *current_size;
 607         u32 temp;
 608         u16 gmch_ctrl;
 609         int i;
 610
 611         current_size = A_SIZE_FIX(agp_bridge->current_size);
 612
 613         pci_read_config_dword(intel_private.pcidev,I810_GMADDR,&temp);
 614         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 615
 616         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
 617         gmch_ctrl |= I830_GMCH_ENABLED;
 618         pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
 619
 620         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 621         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 622
 623         if (agp_bridge->driver->needs_scratch_page) {
 624                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
 625                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 626                         readl(intel_private.registers+I810_PTE_BASE+(i*4));     /* PCI Posting. */
 627                 }
 628         }
 629
 630         global_cache_flush();
 631         return 0;
 632 }
 633
 634 static void intel_i830_cleanup(void)
 635 {
 636         iounmap(intel_private.registers);
 637 }
 638
 639 static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type)
 640 {
 641         int i,j,num_entries;
 642         void *temp;
 643         int ret = -EINVAL;
 644         int mask_type;
 645
 646         if (mem->page_count == 0)
 647                 goto out;
 648
 649         temp = agp_bridge->current_size;
 650         num_entries = A_SIZE_FIX(temp)->num_entries;
 651
 652         if (pg_start < intel_private.gtt_entries) {
 653                 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
 654                                 pg_start,intel_private.gtt_entries);
 655
 656                 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
 657                 goto out_err;
 658         }
 659
 660         if ((pg_start + mem->page_count) > num_entries)
 661                 goto out_err;
 662
 663         /* The i830 can't check the GTT for entries since its read only,
 664          * depend on the caller to make the correct offset decisions.
 665          */
 666
 667         if (type != mem->type)
 668                 goto out_err;
 669
 670         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 671
 672         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
 673             mask_type != INTEL_AGP_CACHED_MEMORY)
 674                 goto out_err;
 675
 676         if (!mem->is_flushed)
 677                 global_cache_flush();
 678
 679         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 680                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 681                                                        mem->memory[i], mask_type),
 682                        intel_private.registers+I810_PTE_BASE+(j*4));
 683         }
 684         readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 685         agp_bridge->driver->tlb_flush(mem);
 686
 687 out:
 688         ret = 0;
 689 out_err:
 690         mem->is_flushed = 1;
 691         return ret;
 692 }
 693
 694 static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start,
 695                                 int type)
 696 {
 697         int i;
 698
 699         if (mem->page_count == 0)
 700                 return 0;
 701
 702         if (pg_start < intel_private.gtt_entries) {
 703                 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
 704                 return -EINVAL;
 705         }
 706
 707         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 708                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 709         }
 710         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 711
 712         agp_bridge->driver->tlb_flush(mem);
 713         return 0;
 714 }
 715
 716 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type)
 717 {
 718         if (type == AGP_PHYS_MEMORY)
 719                 return alloc_agpphysmem_i8xx(pg_count, type);
 720         /* always return NULL for other allocation types for now */
 721         return NULL;
 722 }
 723
 724 static int intel_i915_configure(void)
 725 {
 726         struct aper_size_info_fixed *current_size;
 727         u32 temp;
 728         u16 gmch_ctrl;
 729         int i;
 730
 731         current_size = A_SIZE_FIX(agp_bridge->current_size);
 732
 733         pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
 734
 735         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 736
 737         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
 738         gmch_ctrl |= I830_GMCH_ENABLED;
 739         pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
 740
 741         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 742         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 743
 744         if (agp_bridge->driver->needs_scratch_page) {
 745                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
 746                         writel(agp_bridge->scratch_page, intel_private.gtt+i);
 747                         readl(intel_private.gtt+i);     /* PCI Posting. */
 748                 }
 749         }
 750
 751         global_cache_flush();
 752         return 0;
 753 }
 754
 755 static void intel_i915_cleanup(void)
 756 {
 757         iounmap(intel_private.gtt);
 758         iounmap(intel_private.registers);
 759 }
 760
 761 static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start,
 762                                 int type)
 763 {
 764         int i,j,num_entries;
 765         void *temp;
 766         int ret = -EINVAL;
 767         int mask_type;
 768
 769         if (mem->page_count == 0)
 770                 goto out;
 771
 772         temp = agp_bridge->current_size;
 773         num_entries = A_SIZE_FIX(temp)->num_entries;
 774
 775         if (pg_start < intel_private.gtt_entries) {
 776                 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
 777                                 pg_start,intel_private.gtt_entries);
 778
 779                 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
 780                 goto out_err;
 781         }
 782
 783         if ((pg_start + mem->page_count) > num_entries)
 784                 goto out_err;
 785
 786         /* The i915 can't check the GTT for entries since its read only,
 787          * depend on the caller to make the correct offset decisions.
 788          */
 789
 790         if (type != mem->type)
 791                 goto out_err;
 792
 793         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 794
 795         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
 796             mask_type != INTEL_AGP_CACHED_MEMORY)
 797                 goto out_err;
 798
 799         if (!mem->is_flushed)
 800                 global_cache_flush();
 801
 802         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 803                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 804                         mem->memory[i], mask_type), intel_private.gtt+j);
 805         }
 806
 807         readl(intel_private.gtt+j-1);
 808         agp_bridge->driver->tlb_flush(mem);
 809
 810  out:
 811         ret = 0;
 812  out_err:
 813         mem->is_flushed = 1;
 814         return ret;
 815 }
 816
 817 static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start,
 818                                 int type)
 819 {
 820         int i;
 821
 822         if (mem->page_count == 0)
 823                 return 0;
 824
 825         if (pg_start < intel_private.gtt_entries) {
 826                 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
 827                 return -EINVAL;
 828         }
 829
 830         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 831                 writel(agp_bridge->scratch_page, intel_private.gtt+i);
 832         }
 833         readl(intel_private.gtt+i-1);
 834
 835         agp_bridge->driver->tlb_flush(mem);
 836         return 0;
 837 }
 838
 839 /* Return the aperture size by just checking the resource length.  The effect
 840  * described in the spec of the MSAC registers is just changing of the
 841  * resource size.
 842  */
 843 static int intel_i9xx_fetch_size(void)
 844 {
 845         int num_sizes = ARRAY_SIZE(intel_i830_sizes);
 846         int aper_size; /* size in megabytes */
 847         int i;
 848
 849         aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
 850
 851         for (i = 0; i < num_sizes; i++) {
 852                 if (aper_size == intel_i830_sizes[i].size) {
 853                         agp_bridge->current_size = intel_i830_sizes + i;
 854                         agp_bridge->previous_size = agp_bridge->current_size;
 855                         return aper_size;
 856                 }
 857         }
 858
 859         return 0;
 860 }
 861
 862 /* The intel i915 automatically initializes the agp aperture during POST.
 863  * Use the memory already set aside for in the GTT.
 864  */
 865 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
 866 {
 867         int page_order;
 868         struct aper_size_info_fixed *size;
 869         int num_entries;
 870         u32 temp, temp2;
 871
 872         size = agp_bridge->current_size;
 873         page_order = size->page_order;
 874         num_entries = size->num_entries;
 875         agp_bridge->gatt_table_real = NULL;
 876
 877         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
 878         pci_read_config_dword(intel_private.pcidev, I915_PTEADDR,&temp2);
 879
 880         intel_private.gtt = ioremap(temp2, 256 * 1024);
 881         if (!intel_private.gtt)
 882                 return -ENOMEM;
 883
 884         temp &= 0xfff80000;
 885
 886         intel_private.registers = ioremap(temp,128 * 4096);
 887         if (!intel_private.registers)
 888                 return -ENOMEM;
 889
 890         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
 891         global_cache_flush();   /* FIXME: ? */
 892
 893         /* we have to call this as early as possible after the MMIO base address is known */
 894         intel_i830_init_gtt_entries();
 895
 896         agp_bridge->gatt_table = NULL;
 897
 898         agp_bridge->gatt_bus_addr = temp;
 899
 900         return 0;
 901 }
 902
 903 /*
 904  * The i965 supports 36-bit physical addresses, but to keep
 905  * the format of the GTT the same, the bits that don't fit
 906  * in a 32-bit word are shifted down to bits 4..7.
 907  *
 908  * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
 909  * is always zero on 32-bit architectures, so no need to make
 910  * this conditional.
 911  */
 912 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
 913         unsigned long addr, int type)
 914 {
 915         /* Shift high bits down */
 916         addr |= (addr >> 28) & 0xf0;
 917
 918         /* Type checking must be done elsewhere */
 919         return addr | bridge->driver->masks[type].mask;
 920 }
 921
 922 /* The intel i965 automatically initializes the agp aperture during POST.
 923  * Use the memory already set aside for in the GTT.
 924  */
 925 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
 926 {
 927        int page_order;
 928        struct aper_size_info_fixed *size;
 929        int num_entries;
 930        u32 temp;
 931
 932        size = agp_bridge->current_size;
 933        page_order = size->page_order;
 934        num_entries = size->num_entries;
 935        agp_bridge->gatt_table_real = NULL;
 936
 937        pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
 938
 939        temp &= 0xfff00000;
 940        intel_private.gtt = ioremap((temp + (512 * 1024)) , 512 * 1024);
 941
 942        if (!intel_private.gtt)
 943                return -ENOMEM;
 944
 945
 946        intel_private.registers = ioremap(temp,128 * 4096);
 947        if (!intel_private.registers)
 948                return -ENOMEM;
 949
 950        temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
 951        global_cache_flush();   /* FIXME: ? */
 952
 953        /* we have to call this as early as possible after the MMIO base address is known */
 954        intel_i830_init_gtt_entries();
 955
 956        agp_bridge->gatt_table = NULL;
 957
 958        agp_bridge->gatt_bus_addr = temp;
 959
 960        return 0;
 961 }
 962
 963
 964 static int intel_fetch_size(void)
 965 {
 966         int i;
 967         u16 temp;
 968         struct aper_size_info_16 *values;
 969
 970         pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
 971         values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
 972
 973         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
 974                 if (temp == values[i].size_value) {
 975                         agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
 976                         agp_bridge->aperture_size_idx = i;
 977                         return values[i].size;
 978                 }
 979         }
 980
 981         return 0;
 982 }
 983
 984 static int __intel_8xx_fetch_size(u8 temp)
 985 {
 986         int i;
 987         struct aper_size_info_8 *values;
 988
 989         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
 990
 991         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
 992                 if (temp == values[i].size_value) {
 993                         agp_bridge->previous_size =
 994                                 agp_bridge->current_size = (void *) (values + i);
 995                         agp_bridge->aperture_size_idx = i;
 996                         return values[i].size;
 997                 }
 998         }
 999         return 0;
1000 }
1001
1002 static int intel_8xx_fetch_size(void)
1003 {
1004         u8 temp;
1005
1006         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1007         return __intel_8xx_fetch_size(temp);
1008 }
1009
1010 static int intel_815_fetch_size(void)
1011 {
1012         u8 temp;
1013
1014         /* Intel 815 chipsets have a _weird_ APSIZE register with only
1015          * one non-reserved bit, so mask the others out ... */
1016         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1017         temp &= (1 << 3);
1018
1019         return __intel_8xx_fetch_size(temp);
1020 }
1021
1022 static void intel_tlbflush(struct agp_memory *mem)
1023 {
1024         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1025         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1026 }
1027
1028
1029 static void intel_8xx_tlbflush(struct agp_memory *mem)
1030 {
1031         u32 temp;
1032         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1033         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1034         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1035         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1036 }
1037
1038
1039 static void intel_cleanup(void)
1040 {
1041         u16 temp;
1042         struct aper_size_info_16 *previous_size;
1043
1044         previous_size = A_SIZE_16(agp_bridge->previous_size);
1045         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1046         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1047         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1048 }
1049
1050
1051 static void intel_8xx_cleanup(void)
1052 {
1053         u16 temp;
1054         struct aper_size_info_8 *previous_size;
1055
1056         previous_size = A_SIZE_8(agp_bridge->previous_size);
1057         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1058         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1059         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1060 }
1061
1062
1063 static int intel_configure(void)
1064 {
1065         u32 temp;
1066         u16 temp2;
1067         struct aper_size_info_16 *current_size;
1068
1069         current_size = A_SIZE_16(agp_bridge->current_size);
1070
1071         /* aperture size */
1072         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1073
1074         /* address to map to */
1075         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1076         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1077
1078         /* attbase - aperture base */
1079         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1080
1081         /* agpctrl */
1082         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1083
1084         /* paccfg/nbxcfg */
1085         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1086         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1087                         (temp2 & ~(1 << 10)) | (1 << 9));
1088         /* clear any possible error conditions */
1089         pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1090         return 0;
1091 }
1092
1093 static int intel_815_configure(void)
1094 {
1095         u32 temp, addr;
1096         u8 temp2;
1097         struct aper_size_info_8 *current_size;
1098
1099         /* attbase - aperture base */
1100         /* the Intel 815 chipset spec. says that bits 29-31 in the
1101         * ATTBASE register are reserved -> try not to write them */
1102         if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1103                 printk (KERN_EMERG PFX "gatt bus addr too high");
1104                 return -EINVAL;
1105         }
1106
1107         current_size = A_SIZE_8(agp_bridge->current_size);
1108
1109         /* aperture size */
1110         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1111                         current_size->size_value);
1112
1113         /* address to map to */
1114         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1115         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1116
1117         pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1118         addr &= INTEL_815_ATTBASE_MASK;
1119         addr |= agp_bridge->gatt_bus_addr;
1120         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1121
1122         /* agpctrl */
1123         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1124
1125         /* apcont */
1126         pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1127         pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1128
1129         /* clear any possible error conditions */
1130         /* Oddness : this chipset seems to have no ERRSTS register ! */
1131         return 0;
1132 }
1133
1134 static void intel_820_tlbflush(struct agp_memory *mem)
1135 {
1136         return;
1137 }
1138
1139 static void intel_820_cleanup(void)
1140 {
1141         u8 temp;
1142         struct aper_size_info_8 *previous_size;
1143
1144         previous_size = A_SIZE_8(agp_bridge->previous_size);
1145         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1146         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1147                         temp & ~(1 << 1));
1148         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1149                         previous_size->size_value);
1150 }
1151
1152
1153 static int intel_820_configure(void)
1154 {
1155         u32 temp;
1156         u8 temp2;
1157         struct aper_size_info_8 *current_size;
1158
1159         current_size = A_SIZE_8(agp_bridge->current_size);
1160
1161         /* aperture size */
1162         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1163
1164         /* address to map to */
1165         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1166         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1167
1168         /* attbase - aperture base */
1169         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1170
1171         /* agpctrl */
1172         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1173
1174         /* global enable aperture access */
1175         /* This flag is not accessed through MCHCFG register as in */
1176         /* i850 chipset. */
1177         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1178         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1179         /* clear any possible AGP-related error conditions */
1180         pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1181         return 0;
1182 }
1183
1184 static int intel_840_configure(void)
1185 {
1186         u32 temp;
1187         u16 temp2;
1188         struct aper_size_info_8 *current_size;
1189
1190         current_size = A_SIZE_8(agp_bridge->current_size);
1191
1192         /* aperture size */
1193         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1194
1195         /* address to map to */
1196         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1197         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1198
1199         /* attbase - aperture base */
1200         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1201
1202         /* agpctrl */
1203         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1204
1205         /* mcgcfg */
1206         pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1207         pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1208         /* clear any possible error conditions */
1209         pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1210         return 0;
1211 }
1212
1213 static int intel_845_configure(void)
1214 {
1215         u32 temp;
1216         u8 temp2;
1217         struct aper_size_info_8 *current_size;
1218
1219         current_size = A_SIZE_8(agp_bridge->current_size);
1220
1221         /* aperture size */
1222         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1223
1224         if (agp_bridge->apbase_config != 0) {
1225                 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1226                                        agp_bridge->apbase_config);
1227         } else {
1228                 /* address to map to */
1229                 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1230                 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1231                 agp_bridge->apbase_config = temp;
1232         }
1233
1234         /* attbase - aperture base */
1235         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1236
1237         /* agpctrl */
1238         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1239
1240         /* agpm */
1241         pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1242         pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1243         /* clear any possible error conditions */
1244         pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1245         return 0;
1246 }
1247
1248 static int intel_850_configure(void)
1249 {
1250         u32 temp;
1251         u16 temp2;
1252         struct aper_size_info_8 *current_size;
1253
1254         current_size = A_SIZE_8(agp_bridge->current_size);
1255
1256         /* aperture size */
1257         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1258
1259         /* address to map to */
1260         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1261         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1262
1263         /* attbase - aperture base */
1264         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1265
1266         /* agpctrl */
1267         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1268
1269         /* mcgcfg */
1270         pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1271         pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1272         /* clear any possible AGP-related error conditions */
1273         pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1274         return 0;
1275 }
1276
1277 static int intel_860_configure(void)
1278 {
1279         u32 temp;
1280         u16 temp2;
1281         struct aper_size_info_8 *current_size;
1282
1283         current_size = A_SIZE_8(agp_bridge->current_size);
1284
1285         /* aperture size */
1286         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1287
1288         /* address to map to */
1289         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1290         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1291
1292         /* attbase - aperture base */
1293         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1294
1295         /* agpctrl */
1296         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1297
1298         /* mcgcfg */
1299         pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1300         pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1301         /* clear any possible AGP-related error conditions */
1302         pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1303         return 0;
1304 }
1305
1306 static int intel_830mp_configure(void)
1307 {
1308         u32 temp;
1309         u16 temp2;
1310         struct aper_size_info_8 *current_size;
1311
1312         current_size = A_SIZE_8(agp_bridge->current_size);
1313
1314         /* aperture size */
1315         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1316
1317         /* address to map to */
1318         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1319         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1320
1321         /* attbase - aperture base */
1322         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1323
1324         /* agpctrl */
1325         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1326
1327         /* gmch */
1328         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1329         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1330         /* clear any possible AGP-related error conditions */
1331         pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1332         return 0;
1333 }
1334
1335 static int intel_7505_configure(void)
1336 {
1337         u32 temp;
1338         u16 temp2;
1339         struct aper_size_info_8 *current_size;
1340
1341         current_size = A_SIZE_8(agp_bridge->current_size);
1342
1343         /* aperture size */
1344         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1345
1346         /* address to map to */
1347         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1348         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1349
1350         /* attbase - aperture base */
1351         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1352
1353         /* agpctrl */
1354         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1355
1356         /* mchcfg */
1357         pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1358         pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1359
1360         return 0;
1361 }
1362
1363 /* Setup function */
1364 static const struct gatt_mask intel_generic_masks[] =
1365 {
1366         {.mask = 0x00000017, .type = 0}
1367 };
1368
1369 static const struct aper_size_info_8 intel_815_sizes[2] =
1370 {
1371         {64, 16384, 4, 0},
1372         {32, 8192, 3, 8},
1373 };
1374
1375 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1376 {
1377         {256, 65536, 6, 0},
1378         {128, 32768, 5, 32},
1379         {64, 16384, 4, 48},
1380         {32, 8192, 3, 56},
1381         {16, 4096, 2, 60},
1382         {8, 2048, 1, 62},
1383         {4, 1024, 0, 63}
1384 };
1385
1386 static const struct aper_size_info_16 intel_generic_sizes[7] =
1387 {
1388         {256, 65536, 6, 0},
1389         {128, 32768, 5, 32},
1390         {64, 16384, 4, 48},
1391         {32, 8192, 3, 56},
1392         {16, 4096, 2, 60},
1393         {8, 2048, 1, 62},
1394         {4, 1024, 0, 63}
1395 };
1396
1397 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1398 {
1399         {256, 65536, 6, 0},
1400         {128, 32768, 5, 32},
1401         {64, 16384, 4, 48},
1402         {32, 8192, 3, 56}
1403 };
1404
1405 static const struct agp_bridge_driver intel_generic_driver = {
1406         .owner                  = THIS_MODULE,
1407         .aperture_sizes         = intel_generic_sizes,
1408         .size_type              = U16_APER_SIZE,
1409         .num_aperture_sizes     = 7,
1410         .configure              = intel_configure,
1411         .fetch_size             = intel_fetch_size,
1412         .cleanup                = intel_cleanup,
1413         .tlb_flush              = intel_tlbflush,
1414         .mask_memory            = agp_generic_mask_memory,
1415         .masks                  = intel_generic_masks,
1416         .agp_enable             = agp_generic_enable,
1417         .cache_flush            = global_cache_flush,
1418         .create_gatt_table      = agp_generic_create_gatt_table,
1419         .free_gatt_table        = agp_generic_free_gatt_table,
1420         .insert_memory          = agp_generic_insert_memory,
1421         .remove_memory          = agp_generic_remove_memory,
1422         .alloc_by_type          = agp_generic_alloc_by_type,
1423         .free_by_type           = agp_generic_free_by_type,
1424         .agp_alloc_page         = agp_generic_alloc_page,
1425         .agp_destroy_page       = agp_generic_destroy_page,
1426         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1427 };
1428
1429 static const struct agp_bridge_driver intel_810_driver = {
1430         .owner                  = THIS_MODULE,
1431         .aperture_sizes         = intel_i810_sizes,
1432         .size_type              = FIXED_APER_SIZE,
1433         .num_aperture_sizes     = 2,
1434         .needs_scratch_page     = TRUE,
1435         .configure              = intel_i810_configure,
1436         .fetch_size             = intel_i810_fetch_size,
1437         .cleanup                = intel_i810_cleanup,
1438         .tlb_flush              = intel_i810_tlbflush,
1439         .mask_memory            = intel_i810_mask_memory,
1440         .masks                  = intel_i810_masks,
1441         .agp_enable             = intel_i810_agp_enable,
1442         .cache_flush            = global_cache_flush,
1443         .create_gatt_table      = agp_generic_create_gatt_table,
1444         .free_gatt_table        = agp_generic_free_gatt_table,
1445         .insert_memory          = intel_i810_insert_entries,
1446         .remove_memory          = intel_i810_remove_entries,
1447         .alloc_by_type          = intel_i810_alloc_by_type,
1448         .free_by_type           = intel_i810_free_by_type,
1449         .agp_alloc_page         = agp_generic_alloc_page,
1450         .agp_destroy_page       = agp_generic_destroy_page,
1451         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1452 };
1453
1454 static const struct agp_bridge_driver intel_815_driver = {
1455         .owner                  = THIS_MODULE,
1456         .aperture_sizes         = intel_815_sizes,
1457         .size_type              = U8_APER_SIZE,
1458         .num_aperture_sizes     = 2,
1459         .configure              = intel_815_configure,
1460         .fetch_size             = intel_815_fetch_size,
1461         .cleanup                = intel_8xx_cleanup,
1462         .tlb_flush              = intel_8xx_tlbflush,
1463         .mask_memory            = agp_generic_mask_memory,
1464         .masks                  = intel_generic_masks,
1465         .agp_enable             = agp_generic_enable,
1466         .cache_flush            = global_cache_flush,
1467         .create_gatt_table      = agp_generic_create_gatt_table,
1468         .free_gatt_table        = agp_generic_free_gatt_table,
1469         .insert_memory          = agp_generic_insert_memory,
1470         .remove_memory          = agp_generic_remove_memory,
1471         .alloc_by_type          = agp_generic_alloc_by_type,
1472         .free_by_type           = agp_generic_free_by_type,
1473         .agp_alloc_page         = agp_generic_alloc_page,
1474         .agp_destroy_page       = agp_generic_destroy_page,
1475         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1476 };
1477
1478 static const struct agp_bridge_driver intel_830_driver = {
1479         .owner                  = THIS_MODULE,
1480         .aperture_sizes         = intel_i830_sizes,
1481         .size_type              = FIXED_APER_SIZE,
1482         .num_aperture_sizes     = 4,
1483         .needs_scratch_page     = TRUE,
1484         .configure              = intel_i830_configure,
1485         .fetch_size             = intel_i830_fetch_size,
1486         .cleanup                = intel_i830_cleanup,
1487         .tlb_flush              = intel_i810_tlbflush,
1488         .mask_memory            = intel_i810_mask_memory,
1489         .masks                  = intel_i810_masks,
1490         .agp_enable             = intel_i810_agp_enable,
1491         .cache_flush            = global_cache_flush,
1492         .create_gatt_table      = intel_i830_create_gatt_table,
1493         .free_gatt_table        = intel_i830_free_gatt_table,
1494         .insert_memory          = intel_i830_insert_entries,
1495         .remove_memory          = intel_i830_remove_entries,
1496         .alloc_by_type          = intel_i830_alloc_by_type,
1497         .free_by_type           = intel_i810_free_by_type,
1498         .agp_alloc_page         = agp_generic_alloc_page,
1499         .agp_destroy_page       = agp_generic_destroy_page,
1500         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1501 };
1502
1503 static const struct agp_bridge_driver intel_820_driver = {
1504         .owner                  = THIS_MODULE,
1505         .aperture_sizes         = intel_8xx_sizes,
1506         .size_type              = U8_APER_SIZE,
1507         .num_aperture_sizes     = 7,
1508         .configure              = intel_820_configure,
1509         .fetch_size             = intel_8xx_fetch_size,
1510         .cleanup                = intel_820_cleanup,
1511         .tlb_flush              = intel_820_tlbflush,
1512         .mask_memory            = agp_generic_mask_memory,
1513         .masks                  = intel_generic_masks,
1514         .agp_enable             = agp_generic_enable,
1515         .cache_flush            = global_cache_flush,
1516         .create_gatt_table      = agp_generic_create_gatt_table,
1517         .free_gatt_table        = agp_generic_free_gatt_table,
1518         .insert_memory          = agp_generic_insert_memory,
1519         .remove_memory          = agp_generic_remove_memory,
1520         .alloc_by_type          = agp_generic_alloc_by_type,
1521         .free_by_type           = agp_generic_free_by_type,
1522         .agp_alloc_page         = agp_generic_alloc_page,
1523         .agp_destroy_page       = agp_generic_destroy_page,
1524         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1525 };
1526
1527 static const struct agp_bridge_driver intel_830mp_driver = {
1528         .owner                  = THIS_MODULE,
1529         .aperture_sizes         = intel_830mp_sizes,
1530         .size_type              = U8_APER_SIZE,
1531         .num_aperture_sizes     = 4,
1532         .configure              = intel_830mp_configure,
1533         .fetch_size             = intel_8xx_fetch_size,
1534         .cleanup                = intel_8xx_cleanup,
1535         .tlb_flush              = intel_8xx_tlbflush,
1536         .mask_memory            = agp_generic_mask_memory,
1537         .masks                  = intel_generic_masks,
1538         .agp_enable             = agp_generic_enable,
1539         .cache_flush            = global_cache_flush,
1540         .create_gatt_table      = agp_generic_create_gatt_table,
1541         .free_gatt_table        = agp_generic_free_gatt_table,
1542         .insert_memory          = agp_generic_insert_memory,
1543         .remove_memory          = agp_generic_remove_memory,
1544         .alloc_by_type          = agp_generic_alloc_by_type,
1545         .free_by_type           = agp_generic_free_by_type,
1546         .agp_alloc_page         = agp_generic_alloc_page,
1547         .agp_destroy_page       = agp_generic_destroy_page,
1548         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1549 };
1550
1551 static const struct agp_bridge_driver intel_840_driver = {
1552         .owner                  = THIS_MODULE,
1553         .aperture_sizes         = intel_8xx_sizes,
1554         .size_type              = U8_APER_SIZE,
1555         .num_aperture_sizes     = 7,
1556         .configure              = intel_840_configure,
1557         .fetch_size             = intel_8xx_fetch_size,
1558         .cleanup                = intel_8xx_cleanup,
1559         .tlb_flush              = intel_8xx_tlbflush,
1560         .mask_memory            = agp_generic_mask_memory,
1561         .masks                  = intel_generic_masks,
1562         .agp_enable             = agp_generic_enable,
1563         .cache_flush            = global_cache_flush,
1564         .create_gatt_table      = agp_generic_create_gatt_table,
1565         .free_gatt_table        = agp_generic_free_gatt_table,
1566         .insert_memory          = agp_generic_insert_memory,
1567         .remove_memory          = agp_generic_remove_memory,
1568         .alloc_by_type          = agp_generic_alloc_by_type,
1569         .free_by_type           = agp_generic_free_by_type,
1570         .agp_alloc_page         = agp_generic_alloc_page,
1571         .agp_destroy_page       = agp_generic_destroy_page,
1572         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1573 };
1574
1575 static const struct agp_bridge_driver intel_845_driver = {
1576         .owner                  = THIS_MODULE,
1577         .aperture_sizes         = intel_8xx_sizes,
1578         .size_type              = U8_APER_SIZE,
1579         .num_aperture_sizes     = 7,
1580         .configure              = intel_845_configure,
1581         .fetch_size             = intel_8xx_fetch_size,
1582         .cleanup                = intel_8xx_cleanup,
1583         .tlb_flush              = intel_8xx_tlbflush,
1584         .mask_memory            = agp_generic_mask_memory,
1585         .masks                  = intel_generic_masks,
1586         .agp_enable             = agp_generic_enable,
1587         .cache_flush            = global_cache_flush,
1588         .create_gatt_table      = agp_generic_create_gatt_table,
1589         .free_gatt_table        = agp_generic_free_gatt_table,
1590         .insert_memory          = agp_generic_insert_memory,
1591         .remove_memory          = agp_generic_remove_memory,
1592         .alloc_by_type          = agp_generic_alloc_by_type,
1593         .free_by_type           = agp_generic_free_by_type,
1594         .agp_alloc_page         = agp_generic_alloc_page,
1595         .agp_destroy_page       = agp_generic_destroy_page,
1596         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1597 };
1598
1599 static const struct agp_bridge_driver intel_850_driver = {
1600         .owner                  = THIS_MODULE,
1601         .aperture_sizes         = intel_8xx_sizes,
1602         .size_type              = U8_APER_SIZE,
1603         .num_aperture_sizes     = 7,
1604         .configure              = intel_850_configure,
1605         .fetch_size             = intel_8xx_fetch_size,
1606         .cleanup                = intel_8xx_cleanup,
1607         .tlb_flush              = intel_8xx_tlbflush,
1608         .mask_memory            = agp_generic_mask_memory,
1609         .masks                  = intel_generic_masks,
1610         .agp_enable             = agp_generic_enable,
1611         .cache_flush            = global_cache_flush,
1612         .create_gatt_table      = agp_generic_create_gatt_table,
1613         .free_gatt_table        = agp_generic_free_gatt_table,
1614         .insert_memory          = agp_generic_insert_memory,
1615         .remove_memory          = agp_generic_remove_memory,
1616         .alloc_by_type          = agp_generic_alloc_by_type,
1617         .free_by_type           = agp_generic_free_by_type,
1618         .agp_alloc_page         = agp_generic_alloc_page,
1619         .agp_destroy_page       = agp_generic_destroy_page,
1620         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1621 };
1622
1623 static const struct agp_bridge_driver intel_860_driver = {
1624         .owner                  = THIS_MODULE,
1625         .aperture_sizes         = intel_8xx_sizes,
1626         .size_type              = U8_APER_SIZE,
1627         .num_aperture_sizes     = 7,
1628         .configure              = intel_860_configure,
1629         .fetch_size             = intel_8xx_fetch_size,
1630         .cleanup                = intel_8xx_cleanup,
1631         .tlb_flush              = intel_8xx_tlbflush,
1632         .mask_memory            = agp_generic_mask_memory,
1633         .masks                  = intel_generic_masks,
1634         .agp_enable             = agp_generic_enable,
1635         .cache_flush            = global_cache_flush,
1636         .create_gatt_table      = agp_generic_create_gatt_table,
1637         .free_gatt_table        = agp_generic_free_gatt_table,
1638         .insert_memory          = agp_generic_insert_memory,
1639         .remove_memory          = agp_generic_remove_memory,
1640         .alloc_by_type          = agp_generic_alloc_by_type,
1641         .free_by_type           = agp_generic_free_by_type,
1642         .agp_alloc_page         = agp_generic_alloc_page,
1643         .agp_destroy_page       = agp_generic_destroy_page,
1644         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1645 };
1646
1647 static const struct agp_bridge_driver intel_915_driver = {
1648         .owner                  = THIS_MODULE,
1649         .aperture_sizes         = intel_i830_sizes,
1650         .size_type              = FIXED_APER_SIZE,
1651         .num_aperture_sizes     = 4,
1652         .needs_scratch_page     = TRUE,
1653         .configure              = intel_i915_configure,
1654         .fetch_size             = intel_i9xx_fetch_size,
1655         .cleanup                = intel_i915_cleanup,
1656         .tlb_flush              = intel_i810_tlbflush,
1657         .mask_memory            = intel_i810_mask_memory,
1658         .masks                  = intel_i810_masks,
1659         .agp_enable             = intel_i810_agp_enable,
1660         .cache_flush            = global_cache_flush,
1661         .create_gatt_table      = intel_i915_create_gatt_table,
1662         .free_gatt_table        = intel_i830_free_gatt_table,
1663         .insert_memory          = intel_i915_insert_entries,
1664         .remove_memory          = intel_i915_remove_entries,
1665         .alloc_by_type          = intel_i830_alloc_by_type,
1666         .free_by_type           = intel_i810_free_by_type,
1667         .agp_alloc_page         = agp_generic_alloc_page,
1668         .agp_destroy_page       = agp_generic_destroy_page,
1669         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1670 };
1671
1672 static const struct agp_bridge_driver intel_i965_driver = {
1673        .owner                  = THIS_MODULE,
1674        .aperture_sizes         = intel_i830_sizes,
1675        .size_type              = FIXED_APER_SIZE,
1676        .num_aperture_sizes     = 4,
1677        .needs_scratch_page     = TRUE,
1678        .configure              = intel_i915_configure,
1679        .fetch_size             = intel_i9xx_fetch_size,
1680        .cleanup                = intel_i915_cleanup,
1681        .tlb_flush              = intel_i810_tlbflush,
1682        .mask_memory            = intel_i965_mask_memory,
1683        .masks                  = intel_i810_masks,
1684        .agp_enable             = intel_i810_agp_enable,
1685        .cache_flush            = global_cache_flush,
1686        .create_gatt_table      = intel_i965_create_gatt_table,
1687        .free_gatt_table        = intel_i830_free_gatt_table,
1688        .insert_memory          = intel_i915_insert_entries,
1689        .remove_memory          = intel_i915_remove_entries,
1690        .alloc_by_type          = intel_i830_alloc_by_type,
1691        .free_by_type           = intel_i810_free_by_type,
1692        .agp_alloc_page         = agp_generic_alloc_page,
1693        .agp_destroy_page       = agp_generic_destroy_page,
1694        .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1695 };
1696
1697 static const struct agp_bridge_driver intel_7505_driver = {
1698         .owner                  = THIS_MODULE,
1699         .aperture_sizes         = intel_8xx_sizes,
1700         .size_type              = U8_APER_SIZE,
1701         .num_aperture_sizes     = 7,
1702         .configure              = intel_7505_configure,
1703         .fetch_size             = intel_8xx_fetch_size,
1704         .cleanup                = intel_8xx_cleanup,
1705         .tlb_flush              = intel_8xx_tlbflush,
1706         .mask_memory            = agp_generic_mask_memory,
1707         .masks                  = intel_generic_masks,
1708         .agp_enable             = agp_generic_enable,
1709         .cache_flush            = global_cache_flush,
1710         .create_gatt_table      = agp_generic_create_gatt_table,
1711         .free_gatt_table        = agp_generic_free_gatt_table,
1712         .insert_memory          = agp_generic_insert_memory,
1713         .remove_memory          = agp_generic_remove_memory,
1714         .alloc_by_type          = agp_generic_alloc_by_type,
1715         .free_by_type           = agp_generic_free_by_type,
1716         .agp_alloc_page         = agp_generic_alloc_page,
1717         .agp_destroy_page       = agp_generic_destroy_page,
1718         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1719 };
1720
1721
1722 static int find_gmch(u16 device)
1723 {
1724         struct pci_dev *gmch_device;
1725
1726         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1727         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1728                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1729                                 device, gmch_device);
1730         }
1731
1732         if (!gmch_device)
1733                 return 0;
1734
1735         intel_private.pcidev = gmch_device;
1736         return 1;
1737 }
1738
1739 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
1740  * driver and gmch_driver must be non-null, and find_gmch will determine
1741  * which one should be used if a gmch_chip_id is present.
1742  */
1743 static const struct intel_driver_description {
1744         unsigned int chip_id;
1745         unsigned int gmch_chip_id;
1746         char *name;
1747         const struct agp_bridge_driver *driver;
1748         const struct agp_bridge_driver *gmch_driver;
1749 } intel_agp_chipsets[] = {
1750         { PCI_DEVICE_ID_INTEL_82443LX_0, 0, "440LX", &intel_generic_driver, NULL },
1751         { PCI_DEVICE_ID_INTEL_82443BX_0, 0, "440BX", &intel_generic_driver, NULL },
1752         { PCI_DEVICE_ID_INTEL_82443GX_0, 0, "440GX", &intel_generic_driver, NULL },
1753         { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, "i810",
1754                 NULL, &intel_810_driver },
1755         { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, "i810",
1756                 NULL, &intel_810_driver },
1757         { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, "i810",
1758                 NULL, &intel_810_driver },
1759         { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, "i815",
1760                 &intel_810_driver, &intel_815_driver },
1761         { PCI_DEVICE_ID_INTEL_82820_HB, 0, "i820", &intel_820_driver, NULL },
1762         { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, "i820", &intel_820_driver, NULL },
1763         { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1764                 &intel_830mp_driver, &intel_830_driver },
1765         { PCI_DEVICE_ID_INTEL_82840_HB, 0, "i840", &intel_840_driver, NULL },
1766         { PCI_DEVICE_ID_INTEL_82845_HB, 0, "845G", &intel_845_driver, NULL },
1767         { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, "830M",
1768                 &intel_845_driver, &intel_830_driver },
1769         { PCI_DEVICE_ID_INTEL_82850_HB, 0, "i850", &intel_850_driver, NULL },
1770         { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, "855PM", &intel_845_driver, NULL },
1771         { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1772                 &intel_845_driver, &intel_830_driver },
1773         { PCI_DEVICE_ID_INTEL_82860_HB, 0, "i860", &intel_860_driver, NULL },
1774         { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, "865",
1775                 &intel_845_driver, &intel_830_driver },
1776         { PCI_DEVICE_ID_INTEL_82875_HB, 0, "i875", &intel_845_driver, NULL },
1777         { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1778                 &intel_845_driver, &intel_915_driver },
1779         { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1780                 &intel_845_driver, &intel_915_driver },
1781         { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1782                 &intel_845_driver, &intel_915_driver },
1783         { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1784                 &intel_845_driver, &intel_915_driver },
1785         { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1786                 &intel_845_driver, &intel_i965_driver },
1787         { PCI_DEVICE_ID_INTEL_82965G_1_HB, PCI_DEVICE_ID_INTEL_82965G_1_IG, "965G",
1788                 &intel_845_driver, &intel_i965_driver },
1789         { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1790                 &intel_845_driver, &intel_i965_driver },
1791         { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1792                 &intel_845_driver, &intel_i965_driver },
1793         { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1794                 &intel_845_driver, &intel_i965_driver },
1795         { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1796                 &intel_845_driver, &intel_i965_driver },
1797         { PCI_DEVICE_ID_INTEL_7505_0, 0, "E7505", &intel_7505_driver, NULL },
1798         { PCI_DEVICE_ID_INTEL_7205_0, 0, "E7205", &intel_7505_driver, NULL },
1799         { 0, 0, NULL, NULL, NULL }
1800 };
1801
1802 static int __devinit agp_intel_probe(struct pci_dev *pdev,
1803                                      const struct pci_device_id *ent)
1804 {
1805         struct agp_bridge_data *bridge;
1806         u8 cap_ptr = 0;
1807         struct resource *r;
1808         int i;
1809
1810         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
1811
1812         bridge = agp_alloc_bridge();
1813         if (!bridge)
1814                 return -ENOMEM;
1815
1816         for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
1817                 /* In case that multiple models of gfx chip may
1818                    stand on same host bridge type, this can be
1819                    sure we detect the right IGD. */
1820                 if ((pdev->device == intel_agp_chipsets[i].chip_id) &&
1821                         ((intel_agp_chipsets[i].gmch_chip_id == 0) ||
1822                                 find_gmch(intel_agp_chipsets[i].gmch_chip_id)))
1823                         break;
1824         }
1825
1826         if (intel_agp_chipsets[i].name == NULL) {
1827                 if (cap_ptr)
1828                         printk(KERN_WARNING PFX "Unsupported Intel chipset"
1829                                "(device id: %04x)\n", pdev->device);
1830                 agp_put_bridge(bridge);
1831                 return -ENODEV;
1832         }
1833
1834         if (intel_agp_chipsets[i].gmch_chip_id != 0)
1835             bridge->driver = intel_agp_chipsets[i].gmch_driver;
1836         else
1837             bridge->driver = intel_agp_chipsets[i].driver;
1838
1839         if (bridge->driver == NULL) {
1840                 printk(KERN_WARNING PFX "Failed to find bridge device "
1841                         "(chip_id: %04x)\n", intel_agp_chipsets[i].gmch_chip_id);
1842                 agp_put_bridge(bridge);
1843                 return -ENODEV;
1844         }
1845
1846         bridge->dev = pdev;
1847         bridge->capndx = cap_ptr;
1848         bridge->dev_private_data = &intel_private;
1849
1850         printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n",
1851                 intel_agp_chipsets[i].name);
1852
1853         /*
1854         * The following fixes the case where the BIOS has "forgotten" to
1855         * provide an address range for the GART.
1856         * 20030610 - hamish@zot.org
1857         */
1858         r = &pdev->resource[0];
1859         if (!r->start && r->end) {
1860                 if (pci_assign_resource(pdev, 0)) {
1861                         printk(KERN_ERR PFX "could not assign resource 0\n");
1862                         agp_put_bridge(bridge);
1863                         return -ENODEV;
1864                 }
1865         }
1866
1867         /*
1868         * If the device has not been properly setup, the following will catch
1869         * the problem and should stop the system from crashing.
1870         * 20030610 - hamish@zot.org
1871         */
1872         if (pci_enable_device(pdev)) {
1873                 printk(KERN_ERR PFX "Unable to Enable PCI device\n");
1874                 agp_put_bridge(bridge);
1875                 return -ENODEV;
1876         }
1877
1878         /* Fill in the mode register */
1879         if (cap_ptr) {
1880                 pci_read_config_dword(pdev,
1881                                 bridge->capndx+PCI_AGP_STATUS,
1882                                 &bridge->mode);
1883         }
1884
1885         pci_set_drvdata(pdev, bridge);
1886         return agp_add_bridge(bridge);
1887 }
1888
1889 static void __devexit agp_intel_remove(struct pci_dev *pdev)
1890 {
1891         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
1892
1893         agp_remove_bridge(bridge);
1894
1895         if (intel_private.pcidev)
1896                 pci_dev_put(intel_private.pcidev);
1897
1898         agp_put_bridge(bridge);
1899 }
1900
1901 #ifdef CONFIG_PM
1902 static int agp_intel_resume(struct pci_dev *pdev)
1903 {
1904         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
1905
1906         pci_restore_state(pdev);
1907
1908         /* We should restore our graphics device's config space,
1909          * as host bridge (00:00) resumes before graphics device (02:00),
1910          * then our access to its pci space can work right.
1911          */
1912         if (intel_private.pcidev)
1913                 pci_restore_state(intel_private.pcidev);
1914
1915         if (bridge->driver == &intel_generic_driver)
1916                 intel_configure();
1917         else if (bridge->driver == &intel_850_driver)
1918                 intel_850_configure();
1919         else if (bridge->driver == &intel_845_driver)
1920                 intel_845_configure();
1921         else if (bridge->driver == &intel_830mp_driver)
1922                 intel_830mp_configure();
1923         else if (bridge->driver == &intel_915_driver)
1924                 intel_i915_configure();
1925         else if (bridge->driver == &intel_830_driver)
1926                 intel_i830_configure();
1927         else if (bridge->driver == &intel_810_driver)
1928                 intel_i810_configure();
1929         else if (bridge->driver == &intel_i965_driver)
1930                 intel_i915_configure();
1931
1932         return 0;
1933 }
1934 #endif
1935
1936 static struct pci_device_id agp_intel_pci_table[] = {
1937 #define ID(x)                                           \
1938         {                                               \
1939         .class          = (PCI_CLASS_BRIDGE_HOST << 8), \
1940         .class_mask     = ~0,                           \
1941         .vendor         = PCI_VENDOR_ID_INTEL,          \
1942         .device         = x,                            \
1943         .subvendor      = PCI_ANY_ID,                   \
1944         .subdevice      = PCI_ANY_ID,                   \
1945         }
1946         ID(PCI_DEVICE_ID_INTEL_82443LX_0),
1947         ID(PCI_DEVICE_ID_INTEL_82443BX_0),
1948         ID(PCI_DEVICE_ID_INTEL_82443GX_0),
1949         ID(PCI_DEVICE_ID_INTEL_82810_MC1),
1950         ID(PCI_DEVICE_ID_INTEL_82810_MC3),
1951         ID(PCI_DEVICE_ID_INTEL_82810E_MC),
1952         ID(PCI_DEVICE_ID_INTEL_82815_MC),
1953         ID(PCI_DEVICE_ID_INTEL_82820_HB),
1954         ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
1955         ID(PCI_DEVICE_ID_INTEL_82830_HB),
1956         ID(PCI_DEVICE_ID_INTEL_82840_HB),
1957         ID(PCI_DEVICE_ID_INTEL_82845_HB),
1958         ID(PCI_DEVICE_ID_INTEL_82845G_HB),
1959         ID(PCI_DEVICE_ID_INTEL_82850_HB),
1960         ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
1961         ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
1962         ID(PCI_DEVICE_ID_INTEL_82860_HB),
1963         ID(PCI_DEVICE_ID_INTEL_82865_HB),
1964         ID(PCI_DEVICE_ID_INTEL_82875_HB),
1965         ID(PCI_DEVICE_ID_INTEL_7505_0),
1966         ID(PCI_DEVICE_ID_INTEL_7205_0),
1967         ID(PCI_DEVICE_ID_INTEL_82915G_HB),
1968         ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
1969         ID(PCI_DEVICE_ID_INTEL_82945G_HB),
1970         ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
1971         ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
1972         ID(PCI_DEVICE_ID_INTEL_82965G_1_HB),
1973         ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
1974         ID(PCI_DEVICE_ID_INTEL_82965G_HB),
1975         ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
1976         { }
1977 };
1978
1979 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
1980
1981 static struct pci_driver agp_intel_pci_driver = {
1982         .name           = "agpgart-intel",
1983         .id_table       = agp_intel_pci_table,
1984         .probe          = agp_intel_probe,
1985         .remove         = __devexit_p(agp_intel_remove),
1986 #ifdef CONFIG_PM
1987         .resume         = agp_intel_resume,
1988 #endif
1989 };
1990
1991 static int __init agp_intel_init(void)
1992 {
1993         if (agp_off)
1994                 return -EINVAL;
1995         return pci_register_driver(&agp_intel_pci_driver);
1996 }
1997
1998 static void __exit agp_intel_cleanup(void)
1999 {
2000         pci_unregister_driver(&agp_intel_pci_driver);
2001 }
2002
2003 module_init(agp_intel_init);
2004 module_exit(agp_intel_cleanup);
2005
2006 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
2007 MODULE_LICENSE("GPL and additional rights");